ADP1974-EVALZ [ADI]
Bidirectional, Synchronous PWM Controller for Battery Test and Formation;
| 型号： | ADP1974-EVALZ |
| 厂家： | 
ADI |
| 描述： | Bidirectional, Synchronous PWM Controller for Battery Test and Formation 电池 |
| 文件： | 总19页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Bidirectional, Synchronous PWM Controller
for Battery Test and Formation
Data Sheet
ADP1974
FEATURES
GENERAL DESCRIPTION
Input voltage range: 6 V to 60 V
On-board 5 V linear regulator
Buck/charge or boost/discharge mode
The ADP1974 is a constant frequency, voltage mode, synchronous,
pulse-width modulation (PWM) controller for bidirectional dc-to-
dc applications. The ADP1974 is designed for use in battery testing,
High PWM linearity with internal 4 V p-p PWM ramp voltage
FAULT and COMP input compatible with AD8450/AD8451
Programmable dead time control
Adjustable frequency from 50 kHz to 300 kHz
Synchronization output or input with adjustable phase shift
Programmable maximum duty cycle
Programmable soft start
Peak hiccup current-limit protection
Pin-compatible with ADP1972 (asynchronous version)
TSD protection
formation, and conditioning applications with an external, high
voltage field effect transistor (FET) half bridge driver, and an
external control device such as the AD8450/AD8451. The device
operates as a buck converter in battery charge mode and as a boost
converter in discharge mode to recycle energy to the input bus.
The ADP1974 high voltage VIN supply pin can withstand a
maximum operating voltage of 60 V and reduces the need for
additional system supply voltages. The ADP1974 has integrated
features such as precision enable, internal and external
synchronization control with programmable phase shift,
programmable maximum duty cycle, dead time control, and peak
hiccup current-limit protection. Additional protection features
include soft start to limit input inrush current during startup,
precision enable, and thermal shutdown (TSD). The ADP1974
also has a COMP pin to provide external control of the PWM
duty cycle and a FAULT pin that can disable the DH and DL
outputs. These functions are compatible with the AD8450/AD8451
analog front-end (AFE) error amplifiers.
16-lead TSSOP
APPLICATIONS
Single and multicell battery formation and testing
High efficiency battery test systems with recycle capability
Battery conditioning (charging and discharging) systems
Compatible with AD8450/AD8451 constant voltage (CV) and
constant current (CC) analog front end error amplifier
The ADP1974 is available in a 16-lead TSSOP package and is
pin-compatible with the ADP1972.
TYPICAL APPLICATION CIRCUIT
VIN
+24V
SYNC
SCFG
BATTERY CHARGER SYSTEM CONTROL
+24V RECYLCING DC BUS
VREG
CHARGE/
DISCHARGE
VOLTAGE
SETPOINT
CURRENT
SETPOINT
ON/OFF
DH
EN
HV
MOSFET
DRIVER
ADP1974
MODE
DL
ADuM7223
COMP
FAULT
ISET MODE
VSET
VCTRL
FAULT
CL
DT
SS
AD8450
FREQ
DMAX
LOOP
COMPENSATION
GND
BVP0 BVN0 ISVN ISVP
+
–
–
+
NOTES
1. THE AD8450 AND ADuM7223 ARE SIMPLIFIED REPRESENTATIONS.
Figure 1.
Rev. 0
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ADP1974
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
External COMP Control ........................................................... 12
Peak Current-Limit Hiccup Implementation......................... 12
Negative Current-Limit Detection (Buck Mode) .................. 13
PWM Frequency Control.......................................................... 13
Maximum Duty Cycle ............................................................... 13
External Fault Signaling ............................................................ 13
Thermal Shutdown (TSD) ........................................................ 13
Applications Information.............................................................. 14
Buck or Boost Selection............................................................. 14
Selecting RS to Set the Current Limit....................................... 14
Adjusting the Operating Frequency ........................................ 14
Programming the Maximum Duty Cycle ............................... 16
Adjusting the Soft Start Period................................................. 16
PCB Layout Guidelines.................................................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Operating Ranges......................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Supply Pins .................................................................................. 10
EN/Shutdown.............................................................................. 11
Undervoltage Lockout (UVLO) ............................................... 11
Soft Start ...................................................................................... 11
Operating Modes........................................................................ 11
PWM Drive Signals.................................................................... 12
REVISION HISTORY
9/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 19
Data Sheet
ADP1974
SPECIFICATIONS
VIN = 24 V and specifications valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. All limits at
temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
INPUT VOLTAGE (VIN)
Voltage Range
VIN Supply Current
VIN
IVIN
6
60
2.5
V
mA
RFREQ = 100 kΩ, VSS = 0 V, SYNC floating,
FAULT = low, EN = high
1.5
VIN Shutdown Current
UVLO Threshold Rising
UVLO Threshold Falling
SOFT START (SS)
SS Pin Current
SS Threshold Rising
ISHDN
VEN = 0 V
VIN rising
VIN falling
15
5.71
5.34
70
6
μA
V
V
5.1
4
ISS
VSS = 0 V
5
6
0.65
μA
V
V
Switching enable threshold
Switching disable threshold
Asynchronous to synchronous threshold
0.52
0.5
4.5
SS Threshold Falling
End of Soft Start
0.4
4.4
4.6
V
PWM CONTROL
FREQ
Frequency Range
Oscillator Frequency
FREQ Pin Voltage
fSET
fOSC
VFREQ
RFREQ = 33.2 kΩ to 200 kΩ
RFREQ = 100 kΩ
RFREQ = 100 kΩ
50
90
1.2
300
110
1.252 1.3
kHz
kHz
V
100
SYNC Output (Internal Frequency Control)
Internal SYNC Range
SYNC Output Clock Duty Cycle
SYNC Sink Resistance
SYNC Input (External Frequency Control)
External SYNC Range
SYNC Pull-Down Resistor
Maximum SYNC Pin Voltage
SYNC Threshold Rising
SYNC Threshold Falling
Minimum Pulse Width
SCFG
VSCFG ≥ 4.53 V or SCFG pin floating
For SYNC output
VSCFG = VVREG, RFREQ = 100 kΩ
VSCFG = 5 V, ISYNC = 10 mA
VSCFG < 4.25 V
fSET
50
40
300
60
20
kHz
%
Ω
50
10
RSYNC
fSYNC
VSYNC
For SYNC input clock
50
0.5
300
1.5
5.5
1.5
kHz
MΩ
V
V
V
1
1.2
1.05
100
0.7
ns
VSCFG
SCFG High Threshold Rising
SCFG High Threshold Falling
SCFG Low Threshold Rising
SCFG Low Threshold Falling
SCFG Pin Current
SYNC set to input
SYNC set to output
Programmable phase shift above threshold
No phase shift
RFREQ = 100 kΩ, VSCFG = GND
4.53
4.25 4.51
0.52
4.7
V
V
V
V
0.65
12.5
0.4
9.5
0.5
11
IISCFG
μA
DMAX
Maximum Internal Duty Cycle
DMAX Setting Current
DMAX and SCFG Current Matching1
COMP
COMP Pin Input Voltage Range
Internal Peak-to-Peak Ramp Voltage
Maximum Internal Ramp Voltage
Minimum Internal Ramp Voltage
DT
VCOMP, VDMAX, VSS, and VSCFG = 5 V
VDMAX = 0 V, RFREQ = 100 kΩ
97
11
%
μA
%
IDMAX
9.5
0
12.5
10
VCOMP
V p-p
5.0
V
V p-p
V
V
4
4.5
0.45 0.5
0.55
DT Pin Current
Maximum DT Programming Voltage
IDT
VDT
RFREQ = 100 kΩ, VDT = GND
20
22
3.5
μA
V
Rev. 0 | Page 3 of 19
ADP1974
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
PRECISION ENABLE LOGIC (EN)
Maximum EN Pin Voltage
EN Threshold Rising
EN Threshold Falling
EN Pin Current
60
1.4
V
V
V
μA
1.25
1.22
0.32
1.1
VEN = 5 V, internal pull down
2
MODE LOGIC
Maximum MODE Pin Voltage
MODE Threshold Rising
MODE Threshold Falling
CURRENT LIMIT (CL)
Set Current
5.5
1.5
V
V
V
1.20
1.05
0.7
ICL
VCL = 0 V
18
20
21
μA
Buck CL Threshold
Buck Negative Current Threshold
Boost CL Threshold
Hiccup Detect Time
Hiccup Off Time
VCL (BUCK)
VNC (BUCK)
VCL (BOOST)
250
400
450
300
450
500
5.2
5.2
350
500
550
mV
mV
mV
ms
ms
RFREQ = 100 kΩ, 500 consecutive clock pulses
RFREQ = 100 kΩ, 500 consecutive clock pulses
EN = high
VREG
LDO Regulator Output Voltage
Guaranteed Output Current
Load Regulation
VVREG
IOUT (MAX)
VIN = 6 V to 60 V, no external load
VIN = 6 V, external load
VIN = 6 V, IOUT = 0 mA to 5 mA
4.9
4.9
5
5
5.1
5
5.1
V
mA
V
FAULT
Maximum FAULT Pin Voltage
FAULT Threshold Rising
FAULT Threshold Falling
FAULT Pin Current
VFAULT
60
1.5
V
V
V
μA
1.2
1.05
0.49
0.7
0.5
VFAULT = 5 V, internal 8.5 MΩ pull-down resistor
2
PWM DRIVE LOGIC SIGNALS (DH/DL)
DL Drive Voltage
DH Drive Voltage
DL and DH Sink Resistance
DL and DH Source Resistance
DL and DH Pull-Down Resistor
THERMAL SHUTDOWN (TSD)
TSD Threshold Rising
TSD Threshold Falling
VDL
VDH
No load
No load
IDL = 10 mA
IDL = 10 mA
VREG
VREG
1.2
1.4
1
V
V
Ω
Ω
2.4
2.6
1.5
MΩ
150
135
°C
°C
1 The DMAX and SCFG current matching specification is calculated by taking the absolute value of the difference between the measured ISCFG and IDMAX currents, dividing
them by the 11 μA typical value, and multiplying this answer by 100.
ISCFG I
DMAX
DMAX and SCFG Current Matching (%)
100
11μA
Rev. 0 | Page 4 of 19
Data Sheet
ADP1974
ABSOLUTE MAXIMUM RATINGS
In applications with high power dissipation and poor printed
Table 2.
circuit board (PCB) thermal resistance, the maximum ambient
temperature may need to be derated. In applications with
moderate power dissipation and low PCB thermal resistance,
the maximum ambient temperature can exceed the maximum
limit when the junction temperature is within specification
limits.
Parameter
Rating
VIN, EN, FAULT to GND
SYNC, COMP, MODE, VREG to GND
−0.3 V to +61 V
−0.3 V to +5.5 V
DH, DL, SS, DMAX, SCFG, CL, DT,
FREQ to GND
−0.3 V to VREG + 0.3 V
Operating Ambient Temperature Range −40°C to +85°C
Junction Temperature
Storage Temperature Range
125°C
−65°C to +150°C
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction to ambient thermal resistance of the
package (θJA). Use the following equation to calculate the
maximum junction temperature (TJ) from the ambient
temperature (TA) and power dissipation (PD):
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TJ = TA + (PD × θJA)
(1)
For additional information on thermal resistance, refer to
Application Note AN-000, Thermal Characteristics of IC
Assembly.
Absolute maximum ratings apply individually only, not in
combination.
ESD CAUTION
THERMAL OPERATING RANGES
The ADP1974 can be damaged when the junction temperature
limits are exceeded. The maximum operating junction
temperature (TJ MAX) takes precedence over the maximum
operating ambient temperature (TA MAX). Monitoring ambient
temperature does not guarantee that the junction temperature
(TJ) is within the specified temperature limits.
Rev. 0 | Page 5 of 19
ADP1974
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DL
DH
CL
GND
DT
VREG
VIN
ADP1974
SCFG
FREQ
DMAX
SS
TOP VIEW
EN
(Not to Scale)
MODE
SYNC
FAULT
COMP
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
DL
DH
VREG
Logic Drive Output for the External Low-Side MOSFET Driver.
Logic Drive Output for the External High-Side MOSFET Driver.
Internal Voltage Regulator Output and Internal Bias Supply. A bypass capacitance of 1 μF or greater from this pin
to ground is required.
4
5
6
VIN
EN
MODE
High Input Voltage Supply Pin (6 V to 60 V). Bypass this pin with a 4.7 μF capacitor to ground.
Logic Enable Input. Drive EN logic low to shut down the device. Drive EN logic high to turn on the device.
Mode Select. Drive MODE logic low to place the device in boost (recycle) mode. Drive MODE logic high to place
the device in buck (charge) mode of operation. The MODE status is sampled at EN rising or FAULT falling (see the
Operating Modes section).
7
8
SYNC
Synchronization Pin. This pin is configured as an input (slave mode) with SCFG < 4.51 V to synchronize the ADP1974
to an external clock. This pin is an open-collector driver output with SCFG > 4.53 V (or SCFG connected to VREG).
When configured as an output, SYNC is used to synchronize with other channels; a 10 kΩ resistor to VREG can be
used as a pull-up.
Fault Input Pin. Drive FAULT low to disable the DL and DH drivers in the event of a fault. Drive FAULT high to enable
the DL and DH drivers. FAULT can also reset the mode of operation as described in the Operating Modes section.
This pin was designed to interface with the overcurrent protection (OCP) or overvoltage protection (OVP) fault
condition on the AD8450/AD8451.
FAULT
9
COMP
SS
PWM Modulator Input. This pin interfaces with an error amplifier output signal from the AD8450/AD8451. The
signal on this pin is compared internally to the linear ramp to produce the PWM signal. Do not leave this pin
floating; see the External COMP Control section for additional details.
Soft Start Control Pin. A capacitor connected from SS to ground sets the soft start ramp time. Soft start controls the
DL and DL duty cycle during power-up to reduce the inrush current. Drive SS below 0.5 V to disable switching of DL
and DH. During soft start, the ADP1974 operates in pseudosynchronous mode (see the Soft Start section).
Maximum Duty Cycle Input. Connect an external resistor to ground to set the maximum duty cycle. If the 97%
internal maximum duty cycle is sufficient for the application, tie this pin to VREG. If DMAX is left floating, this pin
is internally pulled up to VREG.
Frequency Set Pin. Connect an external resistor between this pin and ground to set the frequency between 50 kHz
and 300 kHz. When the ADP1974 is synchronized to an external clock (slave mode), set the slave frequency to 90%
of the master frequency by multiplying the master RFREQ value times 1.11.
10
11
12
13
DMAX
FREQ
SCFG
Synchronization Configuration Input. Drive VSCFG ≥ 4.53 V (typical) to configure SYNC as an output clock signal.
Drive VSCFG < 4.51 V (typical) to configure SYNC as an input. Connect a resistor to ground with 0.52 V < VSCFG < 4.53 V
(typical) to introduce a phase shift to the synchronized clock. Drive VSCFG ≤ 0.5 V (typical) to configure SYNC as an
input with no phase shift. If SCFG is left floating, the SYNC pin is internally tied to VREG, and SYNC is configured as
an output.
14
DT
Dead Time Programming Pin. Connect an external resistor between this pin and ground to set the dead time.
Do not leave this pin floating.
15
16
GND
CL
Power and Analog Ground Pin.
Current-Limit Programming Pin. Connect a current sense resistor in series with the low-side FET source to measure
the peak current in the inductor. The current-limit thresholds can operate with a 20 kΩ resistor as described in the
Peak Current-Limit Hiccup Implementation section.
Rev. 0 | Page 6 of 19
Data Sheet
ADP1974
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VEN = VFAULT = 24 V, VMODE = VCL = VSS = VCOMP = 0 V, TA = 25°C, unless otherwise noted.
0.45
0.40
0.35
0.30
0.25
0.20
0.15
5.8
5.7
5.6
5.5
5.4
5.3
5.2
RISING
FALLING
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
6
15
24
33
42
51
60
–40
–5
30
65
100
EN PIN VOLTAGE (V)
TEMPERATURE (°C)
Figure 3. Input Voltage (VIN) UVLO Threshold vs. Temperature,
VFAULT = 0 V
Figure 6. EN Pin Current vs. EN Pin Voltage, VEN = 5 V and VFAULT = 0 V
30
1.25
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
RISING
25
20
15
10
5
1.24
1.23
1.22
FALLING
1.21
1.20
0
6
15
24
33
42
51
60
–40
–5
30
65
100
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 4. Shutdown Current vs. Input Voltage, VEN = 0 V and VFAULT = 0 V
Figure 7. EN Pin Threshold vs. Temperature, VFAULT = 0 V
1.9
5.00
4.98
4.96
4.94
4.92
4.90
4.88
V
V
V
= 6V
T
T
T
T
= +125°C
= +85°C
= +25°C
= –40°C
IN
IN
IN
A
A
A
A
= 24V
= 60V
1.8
1.7
1.6
1.5
1.4
1.3
6
15
24
33
42
51
60
–40
0
40
80
120
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 5. Nonswitching Quiescent Current vs. Input Voltage (SYNC = Floating)
Figure 8. SS Pin Current vs. Temperature
Rev. 0 | Page 7 of 19
ADP1974
Data Sheet
210
190
170
150
130
110
90
97.8
97.7
97.6
97.5
97.4
97.3
70
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
50
97.2
6
30
15
24
33
42
51
60
50
100
150
200
(kHz)
250
300
INPUT VOLTAGE (V)
f
SET
Figure 9. Maximum Internal Duty Cycle vs. Input Voltage,
RFREQ = 100 kΩ, VCOMP = 5 V, and No Load on DL, DH, or DMAX
Figure 12. RFREQ (MASTER) vs. Switching Frequency (fSET
)
450
400
350
300
250
200
150
100
50
5.020
5.015
5.010
5.005
5.000
4.995
4.990
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
T
= +125°C
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
A
0
0
20
40
60
80
100
6
15
24
33
42
51
60
DUTY CYCLE (%)
INPUT VOLTAGE (V)
Figure 10. RDMAX vs. Duty Cycle, RFREQ = 100 kΩ, VCOMP = 5 V, and
No Load on DL or DH
Figure 13. VREG vs. Input Voltage, No Load
100
5.020
5.015
5.010
5.005
5.000
4.995
4.990
4.985
4.980
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
80
60
40
20
0
T
T
T
T
= +125°C
= +85°C
= +25°C
= –40°C
A
A
A
A
0.5
1.0
1.5
2.0
2.5
V
3.0
(V)
3.5
4.0
4.5
5.0
0
1
2
3
4
5
LOAD CURRENT (mA)
COMP
Figure 11. Duty Cycle vs. VCOMP, RFREQ = 100 kΩ, and
No Load on DL, DH, or DMAX
Figure 14. VREG vs. Load Current
Rev. 0 | Page 8 of 19
Data Sheet
ADP1974
175
T
EN
1
150
125
100
75
VREG
2
V
V
NO C
= 24V
IN
= 2.5V
COMP
SS
SYNC
3
50
DL
4
25
0
CH1 10.0V CH2 5.0V 100µs
5.0GS/s
CH1
7.00V
0
100
200
300
400
500
600
700
CH3 5.0V CH4 5.0V
10M POINTS
14.42%
T
tDEAD (ns)
Figure 15. Startup
Figure 18. DT Pin Resistance (RDT) vs. Dead Time (tDEAD)
450
400
350
300
250
200
150
100
50
EN
SS
1
2
V
V
C
= 24V
IN
= 2.5V
COMP
SS = 0.1µF
DH
DL
3
4
0
B
50.0ns/pt
CH1 5.0V
CH3 5.0V
CH2 2.0V
CH4 5.0V
W:20.0M
A
CH1
2.6V
0
1.5
3.0
4.5
6.0
7.5
25.0ms/div 20.0MS/s
tDELAY (µs)
Figure 19. RSCFG vs. Phase Time Delay (tDELAY
)
Figure 16. Buck Soft Start
EN
SS
1
2
V
V
C
= 24V
IN
COMP
= 2.5V
SS = 0.1µF
DH
DL
3
4
B
50.0ns/pt
CH1 5.0V
CH3 5.0V
CH2 2.0V
CH4 5.0V
W:20.0M
A
CH1
2.6V
25.0ms/div 20.0MS/s
Figure 17. Boost Soft Start
Rev. 0 | Page 9 of 19
ADP1974
Data Sheet
THEORY OF OPERATION
VIN
C
C
4.7µF
VREG
1µF
IN
VIN
VREG
MODE
24V
MODE
SELECT
15V
5V
EN
VREG
TSD
M1
M2
DH
DL
VREG = 5V
1Mꢀ
1Mꢀ
L
EXTERNAL
DRIVER
VOUT
DRIVE
LOGIC
C
OUT
BAND GAP
= 1.252V
UVLO
V
BG
FAULT
SYNC
MODE
SELECT
AD8450
VREG
8.5Mꢀ
1Mꢀ
500mV
I
CL
SYNC
DETECT
20µA
R
CL
20kꢀ
CL
R
S
GND
FREQ
300mV
OSCILLATOR
VREG
I
FREQ
VREG
I
R
FREQ
FREQ
CONFIG
AGND PGND
VREG
SCFG
DMAX
DETECT
I
FREQ
4V
VREG
450mV
I
10µA
DT
20µA
C
DMAX
VREG
R
DMAX
DT
R
DT
C
DT
COMP
1.64pF
AD8450
VREG
I
SS
5µA
SS
C
SS
SS DISCHARGE
1kꢀ
ADP1974
Figure 20. Internal Block Diagram
The ADP1974 is a constant frequency, voltage mode, synchronous,
PWM controller for bidirectional dc-to-dc applications. The
ADP1974 is designed to be used with an external, high voltage
FET half bridge driver, such as the ADuM7223, and an external
error amplifier AFE device, such as the AD8450/AD8451, to
implement a battery testing, charging, and discharging system.
The ADP1974 has a high input voltage range, multiple externally
programmed control pins, and integrated safety features. In
buck mode, the device charges a battery and delivers energy
from the input power source to the output. In boost mode, the
device discharges a battery and delivers energy from the battery
to the input. In both modes, the ADP1974 operates as a
synchronous controller for maximum efficiency.
SUPPLY PINS
The ADP1974 has two voltage supply pins, VIN and VREG.
The VIN pin operates from an external supply that ranges from
6 V to 60 V and is the supply voltage for the internal linear
regulator of the ADP1974. Bypass the VIN pin to ground with a
4.7 ꢀF or greater ceramic capacitor.
The VREG pin is the output of the internal linear regulator. The
internal regulator generates the 5 V (typical) rail that is used
internally to bias the control circuitry and can be used externally
as a pull-up voltage for the MODE, SYNC, DMAX, and FAULT
pins. Bypass the VREG pin to ground with a 1 ꢀF ceramic
capacitor. VREG is disabled when EN is low and is active as
long as VIN is above the internal UVLO (5.71 V typical) and
EN is high.
Rev. 0 | Page 10 of 19
Data Sheet
ADP1974
When operating with an input voltage above 50 V, additional
input filtering is recommended. Figure 21 shows the
recommended filter configuration.
When the device shuts down or a fault is detected, an active
internal 1 kΩ pull-down resistor on the SS pin discharges CSS.
tREG
VOUT
ADP1974
R
VIN
SUPPLY > 50V
VREG
4.5V
4.7µF
C
V
SS
SYNCHRONOUS
OPERATION
Figure 21. Recommended Filter Configuration for
Input Voltages Greater than 50 V
0.52V
0V
EN/SHUTDOWN
ENABLE
ADP1974
BEGIN
REGULATION
The EN input turns the ADP1974 on or off and can operate
from voltages up to 60 V. The EN pin is designed with precision
enable control. When the EN voltage is less than 1.22 V (typical),
the ADP1974 shuts down, VREG is disabled, and both DL and
DH are driven low. When the ADP1974 shuts down, the VIN
supply current is 15 ꢀA (typical). When the EN voltage is greater
than 1.25 V (typical), the ADP1974 is enabled, and VREG ramps
to 5 V.
Figure 22. Soft Start Diagram
The MODE pin controls the ADP1974 duty cycle generator and
affects the DL and DH signals during soft start. In buck mode,
a DH pulse initiates the on time (or Phase 1). In boost mode, a
DL pulse initiates the on time. For more information about
buck vs. boost operation, see the Operating Modes section.
During soft start, the ADP1974 operates in asynchronous mode,
and the synchronous FET is not driven. During the off cycle, the
diode in parallel to the low-side FET (buck mode) or the high-
side FET (boost mode) conducts the current until it reaches zero
or the next cycle begins. After the soft start period is completed
(SS > 4.5 V), the ADP1974 switches to full synchronous mode.
In addition to the EN pin, the device can be disabled via a fault
condition indicated by an internal TSD event, a UVLO condition
on VIN, or an external fault condition signaled via the FAULT pin.
It is necessary to disable the device to change the operating
mode from buck to boost.
OPERATING MODES
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP1974 operates as a synchronous buck or boost controller.
When the MODE pin is driven high, above the 1.20 V (typical)
threshold, the ADP1974 operates in a buck configuration for
battery charging. If the MODE pin is driven low, below the
1.05 V (typical) threshold, the ADP1974 operates in a boost
configuration. A boost configuration is ideal for discharging
in battery formation applications. See Figure 23 and Figure 24
for the ADP1974 behavior in each mode. When the ADP1974
is enabled, the internal regulator connected to the VREG pin also
powers up. On the rising edge of VREG, the state of the MODE pin
is latched, preventing the mode of operation from being changed
while the device is enabled. To change between boost and buck
modes of operation, shut down or disable the ADP1974, adjust the
MODE pin to change the operating mode, and restart the system.
The UVLO function prevents the IC from turning on when the
input voltage is below the specified operating range to avoid an
undesired operating mode. When VIN rises, the UVLO does
not allow the ADP1974 to turn on unless VIN is greater than
5.71 V (typical). The UVLO disables the device when VIN
drops below 5.34 V (typical). The UVLO levels have ~370 mV
of hysteresis to prevent the system from turning on and off
repeatedly when there is a slow voltage ramp on the VIN pin.
SOFT START
The ADP1974 has a programmable soft start that prevents
output voltage overshoot during startup. When the ADP1974 is
enabled with the EN pin, the VREG voltage begins rising to 5 V.
When VREG reaches 90% of its 5 V (typical) value, the 5 ꢀA
(typical) internal soft start current (ISS) begins charging the soft
start capacitor (CSS), causing the voltage on the SS pin (VSS) to rise.
The operating mode can be changed when the EN pin is driven
low, the FAULT pin is driven low, or the ADP1974 is disabled
via a TSD event or UVLO condition. On the rising edge of the
FAULT control signal, the state of the MODE pin is latched,
preventing the mode of operation from being changed while
the device is enabled.
While VSS is less than 0.52 V (typical), the ADP1974 switching
control remains disabled. When VSS reaches 0.52 V (typical),
switching is enabled. As CSS continues to charge and VSS rises, the
PWM duty cycle gradually increases, allowing the output
voltage to rise linearly. CSS continues to charge, and VSS rises to
the internal VREG voltage (5 V typical). When the system duty
cycle set by COMP is less than the soft start duty cycle, the external
control loop takes control of the ADP1974. See Figure 22 for a
soft start diagram.
Rev. 0 | Page 11 of 19
ADP1974
Data Sheet
BOOST MODE CONFIGURATION
error signal increases or decreases. The internal PWM comparator
determines the appropriate duty cycle drive signal by monitoring
the error signal at the COMP pin and the internal 4 V p-p ramp
signal. The internal PWM comparator subsequently drives the
external gate driver at the determined duty cycle through the DH
and DL signals.
MODE ≤ 1.05V (TYPICAL)
V
≥ 4.53V (TYPICAL)
SCFG
4.5V
2.5V
COMP
INTERNAL RAMP
(4V p-p)
0.5V
0V
VREG (5V TYPICAL)
The functional voltage range of the COMP pin is from 0 V to
5.0 V. If VCOMP is between 0.5 V and 4.5 V, the ADP1974 regulates
the DH and DL outputs accordingly. If VCOMP is greater than
4.5 V, the ADP1974 operates the DH and DL outputs at the
maximum programmed duty cycle (or 97% whichever is the
lowest). If VCOMP is less than 0.45 V, the ADP1974 operates the
DH or DL output at a 0% duty cycle, according to the operating
mode, while the complementary DL or DH output is driven at a
100% duty cycle. The input to the COMP pin must never
exceed the 5.5 V absolute maximum rating.
DH
0V
VREG (5V TYPICAL)
DL
0V
Figure 23. Drive Signal Diagram for Boost Configuration
BUCK MODE CONFIGURATION
MODE ≥ 1.20V (TYPICAL)
V
≥ 4.53V (TYPICAL)
SCFG
4.5V
2.5V
COMP
The DL and DH signals swing from VREG (5 V typical) to
ground. The external FET driver used must have input control
pins compatible with a 5 V logic signal.
INTERNAL RAMP
(4V p-p)
0.5V
0V
VREG (5V TYPICAL)
PEAK CURRENT-LIMIT HICCUP IMPLEMENTATION
DH
DL
The ADP1974 features a peak hiccup current-limit implementation
measured on the low-side FET across a sense resistor. When the
peak inductor current exceeds the programmed current limit
for more than 500 consecutive clock cycles, 5.2 ms (typical) for
a 100 kHz programmed frequency, the peak hiccup current-
limit condition occurs. If the overcurrent exist for less than
500 consecutive cycles, the counter is reset to zero. When the
overcurrent condition occurs, the SS pin is discharged through
a 1 kꢁ resistor, and the drive signals, DL and DH, are disabled
for the next 500 clock cycles to allow the FETs to cool down (hiccup
mode). When the 500 clock cycles expire, the ADP1974 restarts
through a new soft start cycle.
0V
VREG (5V TYPICAL)
0V
Figure 24. Drive Signal Diagram for Buck Configuration
PWM DRIVE SIGNALS
The ADP1974 has two 5 V logic level output drive signals, DH
and DL that are compatible with drivers similar to the ADuM7223.
The DH and DL drive signals synchronously turn on and off the
high-side and low-side switches driven from the external driver.
The ADP1974 provides resistor programmable dead time to
prevent the DH and DL pins from transitioning at the same
time, as shown in Figure 25. Connect a resistor to ground on
the DT pin to program the dead time.
Figure 26 shows the current-limit block diagram for peak current-
limit protection.
M2
MODE
VREG
SELECT
500mV
L
I
H = BUCK
L = BOOST
CL
20µA
R
20kꢀ
CL
DH
DL
H
L
CL
R
S
t
DEAD
t
DEAD
H
300mV
Figure 25. Dead Time (tDEAD) Between DH and DL Transitions
Figure 26. Current-Limit Block Diagram for Peak Current-Limit Protection
When driving capacitive loads with the DH and DL pins, a 20 Ω
resistor must be placed in series with the capacitive load to reduce
ground noise and ensure signal integrity.
The current-limit threshold is set internally based on the mode
selected. It is designed to trigger when the voltage on RS reaches
100 mV in either buck or boost mode when using RCL = 20 kΩ
with 400 mV across it due to the 20 ꢀA current source. More
information on how to set the current limit is available in the
Applications Information section.
EXTERNAL COMP CONTROL
The ADP1974 COMP pin is the input to the PWM modulator
comparator. The ADP1974 uses a voltage mode control that
compares an error signal, applied to the COMP pin by an
external error amplifier, such as the AD8450/AD8451, to an
internal 4 V p-p triangle waveform. As the load changes, the
Rev. 0 | Page 12 of 19
Data Sheet
ADP1974
switching regulators or devices in the system. When operating
the ADP1974 with an external clock, select RFREQ to provide a
frequency that approximates but is not equal to the external
clock frequency, which is further explained in the Applications
Information section.
NEGATIVE CURRENT-LIMIT DETECTION (BUCK
MODE)
The ADP1974 detects negative current in the inductor in buck
mode with a comparator on the CL pin set to 450 mV, as shown in
Figure 27. When the current in the low-side FET drops below the
limit (negative 50 mV on RS), the DL driver immediately disables,
which is used as a negative current limit in buck mode, detecting the
equivalent of ½ the positive peak current.
Operating Frequency Phase Shift
When the voltage applied to the SCFG pin is 0.65 V < VSCFG
<
4.25 V, the SYNC pin is configured as an input, and the ADP1974
synchronizes to a phase shifted version of the external clock
applied to the SYNC pin. To adjust the phase shift, place a resistor
(RSCFG) from SCFG to ground. The phase shift reduces the input
supply ripple for systems containing multiple switching power
supplies.
M2
MODE
SELECT
VREG
H = BUCK
L = BOOST
I
CL
L
20µA
R
CL
20kꢀ
H
CL
MAXIMUM DUTY CYCLE
R
S
The maximum duty cycle of the ADP1974 can be externally
programmed to any value between 0% and 97% via an external
resistor on the DMAX pin connected from DMAX to ground.
The maximum duty cycle defaults to 97% if DMAX is left floating,
if DMAX is tied to VREG, or if DMAX is programmed to a
value greater than 97%.
450mV
Figure 27. Block Diagram for Negative Current-Limit Protection
PWM FREQUENCY CONTROL
The FREQ, SYNC, and SCFG pins determine the source,
frequency, and synchronization of the clock signal that operates
the PWM control of the ADP1974.
EXTERNAL FAULT SIGNALING
The ADP1974 is equipped with a FAULT pin that signals the
ADP1974 when an external fault condition occurs. The external
fault signal stops PWM operation of the system to avoid damage
to the application and components. When a voltage less than
1.05 V (typical) is applied to the FAULT pin, the ADP1974 is
disabled. In this state, the DL and DH PWM drive signals are
both driven low to prevent switching, and the soft start capacitor
(CSS) is discharged with a 1 kΩ resistance. When a voltage greater
than 1.2 V (typical) is applied to the FAULT pin, the ADP1974
begins switching. A voltage ranging from 0 V to 60 V can be
applied to the FAULT pin of the ADP1974.
Internal Frequency Control
The ADP1974 frequency can be programmed with an external
resistor connected between FREQ and ground. The frequency
range can be set from a minimum of 50 kHz to a maximum of
300 kHz. If the SCFG pin is tied to VREG, forcing VSCFG ≥ 4.53 V
(typical), or if the SCFG pin is left floating, the SYNC pin is
configured as an output, and the ADP1974 operates at the
frequency set by RFREQ, which outputs from the SYNC pin through
the open-drain device. The output clock of the SYNC pin operates
with a 50% (typical) duty cycle. In this configuration, the SYNC pin
can synchronize other switching regulators in the system to the
ADP1974. When the SYNC pin is configured as an output, an
external pull-up resistor is needed from the SYNC pin to an
external supply. The VREG pin of the ADP1974 can be used as
the external supply rail for the pull-up resistor.
THERMAL SHUTDOWN (TSD)
The ADP1974 has a TSD protection circuit. The thermal shutdown
triggers and disables switching when the junction temperature
of the ADP1974 reaches 150°C (typical). While in TSD, the DL
and DH signals are driven low, the CSS capacitor discharges to
ground, and VREG remains high. When the junction temperature
decreases to 135°C (typical), the ADP1974 restarts the application
control loop.
External Frequency Control
When VSCFG ≤ 0.5 V (typical), the SYNC pin is configured as an
input, the ADP1974 synchronizes to the external clock applied
to the SYNC pin, and the ADP1974 operates as a slave device.
This synchronization allows the ADP1974 to operate at the
same switching frequency with the same phase as other
Rev. 0 | Page 13 of 19
ADP1974
Data Sheet
APPLICATIONS INFORMATION
The ADP1974 has many programmable features that are
optimized and controlled for a given application. The ADP1974
provides pins for selecting the operating mode, controlling the
current limit, selecting an internal or external clock, setting the
operating frequency, phase shifting the operating frequency,
programming the dead time, programming the maximum duty
cycle, and adjusting the soft start.
ADJUSTING THE OPERATING FREQUENCY
If the SCFG pin is tied to VREG, forcing VSCFG ≥ 4.53 V, or if
SCFG is left floating and internally tied to VREG, the ADP1974
operates at the frequency set by RFREQ, and the SYNC pin outputs
a clock at the programmed frequency. When VSCFG ≥ 4.53 V, the
output clock on the SYNC pin can be used as a master clock in
applications that require synchronization.
BUCK OR BOOST SELECTION
If VSCFG is ≤ 0.5 V, the SYNC pin is configured as an input, and
the ADP1974 operates as a slave device. As a slave device, the
ADP1974 synchronizes to the external clock applied to the SYNC
To operate the ADP1974 in boost (recycle) mode, apply a
voltage less than 1.05 V (typical) to the MODE pin. To operate
the ADP1974 in buck (discharge) mode, drive the MODE pin
high, greater than 1.20 V (typical). The state of the MODE pin
can change only when the ADP1974 is shut down via the EN pin,
or is disabled via an external fault condition signaled on the
FAULT pin, there is a TSD event, or there is a UVLO condition.
pin. If the voltage applied to the SCFG pin is 0.65 V < VSCFG
<
4.25 V, and a resistor is connected between SCFG and ground,
the SYNC pin is configured as an input, and the ADP1974
synchronizes to a phase shifted version of the external clock
applied to the SYNC pin.
SELECTING RS TO SET THE CURRENT LIMIT
Whether operating the ADP1974 as a master or as a slave
device, carefully select RFREQ using the equations in the
following sections.
See Figure 26 for the current-limit block diagram for peak current-
limit control. To set the current limit, use the following equation:
Selecting RFREQ for a Master Device
I
PK (mA) = 100 mV/RS
where:
PK is the desired peak current limit in mA.
RS is the sense resistor used to set the peak current limit in Ω.
(2)
When VSCFG is ≥ 4.53 V, the ADP1974 operates as a master device.
When functioning as a master device, the ADP1974 operates at
the frequency set by the external RFREQ resistor connected
between FREQ and ground, and the ADP1974 outputs a clock
at the programmed frequency on the SYNC pin.
I
When the ADP1974 is configured to operate in buck (charge)
mode, the internal current-limit threshold is set to 300 mV
(typical) and the negative valley current-limit threshold is set to
450 mV (typical). When the ADP1974 is configured to operate
in boost (recycle) mode, the internal current-limit threshold is
set to 500 mV (typical). The external resistor (RCL) offsets the
current properly to detect the peak in both buck and boost
operation. Set the RCL value to 20 kΩ. In operation, the
equations for setting the peak currents follow.
Figure 28 shows the relationship between the RFREQ (MASTER) value
and the programmed switching frequency.
210
190
170
150
130
110
90
For buck (charge) mode, use the following:
V
V
CL (BUCK) = (ICL) × (RCL) − (IPK) × (RS)
NC (BUCK) = (ICL) × (RCL) + (IVL (NEG)) × (RS)
(3)
(4)
For boost (recycle) mode, use the following:
70
V
CL (BOOST) = (ICL) × (RCL) + (IPK) × (RS)
(5)
50
where:
30
50
100
150
200
250
300
V
I
R
I
V
I
V
CL (BUCK) = 300 mV typical.
CL = 20 ꢀA typical.
CL = 20 kΩ.
PK is the peak inductor current.
NC (BUCK) = 450 mV typical.
VL (NEG) is the valley inductor current.
CL (BOOST) = 500 mV typical.
fSET (kHz)
Figure 28. RFREQ (MASTER) vs. Switching Frequency (fSET
)
To calculate the RFREQ (MASTER) value for a desired master clock
synchronization frequency, use the following equation:
104
RFREQ (MASTER)
kꢁ
(5)
f
SET (kHz)
The ADP1974 is designed so that the peak current limit is the
same in both the buck mode and the boost mode of operation. A
1% or better tolerance for the RCL and RS resistors is recommended.
where:
FREQ (MASTER) is the resistor in kꢁ to set the frequency for master
devices.
SET is the switching frequency in kHz.
R
f
Rev. 0 | Page 14 of 19
Data Sheet
ADP1974
Next, calculate the period of the slave clock.
1
Selecting RFREQ for a Slave Device
To configure the ADP1974 as a slave device, drive VSCFG < 4.53 V.
When functioning as a slave device, the ADP1974 operates at
the frequency of the external clock applied to the SYNC pin. To
ensure proper synchronization, select RFREQ to set the frequency
to a value slightly slower than that of the master clock by using
the following equation:
tSLAVE
μs
103
(8)
f
SLAVE (kHz)
where:
SLAVE is the period of the slave clock in ꢀs.
SLAVE is the frequency of the slave clock in kHz.
t
f
Next, determine the phase time delay (tDELAY) for the desired
phase shift (φSHIFT) using the following equation:
R
FREQ (SLAVE) = 1.11 × RFREQ (MASTER)
where:
FREQ (SLAVE) is the resistor value that appropriately scales the
(6)
SHIFT tSLAVE
μs
R
tDELAY
μs
(9)
360
frequency for the slave device, and 1.11 is the RFREQ slave to
master ratio for synchronization.
FREQ (MASTER) is the resistor value that corresponds to the
where:
DELAY is the phase time delay in ꢀs.
SHIFT is the desired phase shift.
Lastly, use the following equation to calculate tDELAY
SCFG (kΩ) = 0.45 × RFREQ (SLAVE) (kΩ) + 50 × tDELAY (ꢀs)
where:
SCFG is the corresponding resistor for the desired phase shift
in kHz. See Figure 19 for the RSCFG vs. tDELAY graph.
When using the phase shift feature, connect a capacitor of 47 pF
or greater in parallel with RSCFG
R
t
φ
frequency of the master clock applied to the SYNC pin.
The frequency of the slave device is set to a frequency slightly
lower than that of the master device to allow the digital
synchronization loop of the ADP1974 to synchronize to the
master clock period. The slave device can synchronize to a
master clock frequency running between 2% to 20% higher
than the slave clock frequency. Setting RFREQ (SLAVE) to 1.11× larger
than RFREQ (MASTER) runs the synchronization loop in approximately
the center of the adjustment range.
:
R
(10)
R
.
Programming the External Clock Phase Shift
Alternatively, the SCFG pin can be controlled with a voltage source.
When using an independent voltage source, ensure VSCFG ≤ VREG
under all conditions. When the ADP1974 is disabled via the
EN pin or UVLO, VREG = 0 V, and the voltage source must be
adjusted accordingly to ensure VSCFG ≤ VREG.
If a phase shift is not required for slave devices, connect the
SCFG pin of each slave device to ground. For devices that
require a phase shifted version of the synchronization clock that
is applied to the SYNC pin of the slave devices, connect a
resistor (RSCFG) from SCFG to ground to program the desired
phase shift. To determine the RSCFG for a desired phase shift
(φSHIFT), start by calculating the frequency of the slave clock
(fSLAVE).
Figure 29 shows the internal voltage ramp of the ADP1974. The
voltage ramp is a well controlled 4 V p-p.
T
4.5V
104
RFREQ (SLAVE)
f
SLAVE(kHz)
(7)
0.5V
0.01T
0.99T
Figure 29. Internal Voltage Ramp
Rev. 0 | Page 15 of 19
ADP1974
Data Sheet
Programming the Dead Time
The DMAX current source is equivalent to the programmed
current of the FREQ pin:
To adjust the dead time on the synchronous DH and DL
outputs, connect a resistor (RDT) from DT to GND and bypass
with a 47 pF capacitor. Select RDT for a given dead time using
Figure 30 or calculate RDT using the following equations. To
reach a single equation for RDT, combine the equations for VDT
and RDT.
VFREQ
RFREQ
IDMAX IFREQ
(15)
where IDMAX = IFREQ is the current programmed on the
FREQ pin.
450
I
DT
tDEAD
ns
28.51
T = +25°C
A
VDT
V
(11)
3.76
400
350
300
250
200
150
100
50
VDT
IDT
RDT
(12)
where:
DT is the DT pin programming voltage.
DT is the 20 ꢀA (typical) internal current source.
DEAD is the desired dead time in ns.
DT is the resistor value in kΩ for the desired dead time.
To calculate RDT for a given tDEAD, the resulting equation used is
V
I
t
R
tDEAD ns 28.51
0
RDT
kꢁ
(13)
0
20
40
60
80
100
3.76
DUTY CYCLE (%)
175
150
125
100
75
Figure 31. RDMAX vs. Duty Cycle, RFREQ = 100 kΩ, VCOMP = 5 V
The maximum duty cycle of the ADP1974 is 97% (typical). If
the resistor on DMAX sets a maximum duty cycle larger than
97%, the ADP1974 defaults to its internal maximum. If the 97%
internal maximum duty cycle is sufficient for the application, tie
the DMAX pin to VREG or leave it floating.
The CDMAX capacitor connected from the DMAX pin to the
ground plane must be 47 pF or greater.
50
ADJUSTING THE SOFT START PERIOD
25
The ADP1974 has a programmable soft start feature that
prevents output voltage overshoot during startup. Refer to
Figure 22 for a soft start diagram. To calculate the delay time
before switching is enabled (tREG), use the following equation:
0
0
100
200
300
400
500
600
700
t
(ns)
DEAD
Figure 30. DT Pin Resistance (RDT) vs. Dead Time (tDEAD
)
PROGRAMMING THE MAXIMUM DUTY CYCLE
0.52
ISS
tREG
CSS
(16)
The ADP1974 is designed with a 97% (typical) maximum
internal duty cycle. By connecting a resistor from DMAX to
ground, the maximum duty cycle can be programmed at any
value from 0% to 97%, by using the following equation:
where:
ISS = 5 ꢀA, typical.
CSS is the soft start capacitor value.
21.5VFREQ RDMAX
The output voltage rising ramp is then proportional to the ramp
on SS and the input voltage of the ADP1974.
(14)
DMAX
%
10.5
RFREQ
where:
4
ISS
tRAMP
CSS
DMAX is the programmed maximum duty cycle.
FREQ = 1.252 V (typical).
V
VOUT
Time(s) tRAMP
VIN
R
DMAX is the value of the resistance used to program the
maximum duty cycle.
FREQ is the frequency set resistor used in the application.
RAMP_RATE
(V/s)
R
Rev. 0 | Page 16 of 19
Data Sheet
ADP1974
As an example, a design with a 20 V input and a 10 nF capacitor
creates a delay of 1 ms and a 2.5 V/ms ramp rate.
capacitor is not used, there is no soft start control internal to the
ADP1974, and the system can produce a large output overshoot,
and a large peak inductor spike during startup. When a CSS
capacitor is not used, ensure that the output overshoot is not
large enough to trip the hiccup current limit during startup.
A CSS capacitor is not required for the ADP1974. When the CSS
capacitor is not used, the internal 5 ꢀA (typical) current source
immediately pulls the SS pin voltage to VREG. When a CSS
Rev. 0 | Page 17 of 19
ADP1974
Data Sheet
PCB LAYOUT GUIDELINES
When building a system with a master and multiple slave
devices, minimize the capacitance of the trace attached to
the SYNC pin by considering the following items:
For high efficiency, good regulation, and stability, a well designed
PCB layout is required.
Use the following guidelines when designing the PCB (see
Figure 20 for the block diagram and Figure 2 for the pin
configuration):
For small systems with only a few slave devices, a
resistor connected in series between the master SYNC
signal and the slave SYNC input pins limits the
capacitance of the trace and reduces the fast ground
currents that can inject noise into the master device.
For larger applications, the series resistance is not
enough to isolate the master SYNC clock. In larger
systems, use an external buffer to reduce the
capacitance of the trace. The external buffer has the
drive capability to support a large number of slave
devices.
Keep the low effective series resistance (ESR) input supply
capacitor (CIN) for VIN as close as possible to the VIN and
GND pins to minimize noise injected into the device from
board parasitic inductance.
Keep the low ESR input supply capacitor (CVREG) for VREG as
close as possible to the VREG and GND pins to minimize the
noise injected into the device from board parasitic inductance.
Place the components for the SCFG, FREQ, DMAX, and SS
pins close to the corresponding pins. Tie these components
collectively to an analog ground plane that makes a Kelvin
connection to the GND pin.
NMOS
POWER
FET
SOURCE
R
CL
20kꢀ
Keep the trace from the COMP pin to the accompanying
device (for example, the AD8450) as short as possible. Avoid
routing this trace near switching signals, and shield the trace,
if possible.
Place any trace or components for the SYNC pin away from
sensitive analog nodes. When using an external pull-up
resistor, it is best to use a local 0.1 ꢀF bypass capacitor from
the supply of the pull-up resistor to GND.
Keep the traces from the DH and DL pins to the external
components as short as possible to minimize parasitic
inductance and capacitance, which affect the control
signal. The DH and DL pins are switching nodes; do not
route them near any sensitive analog circuitry.
Keep high current traces as short and as wide as possible.
Connect the ground connection of the ADP1974 directly
to the ground connection of the current sense resistor (RS).
Connect CL through a 20 kΩ resistor directly to RS.
From the ground connection shown in Figure 32, connect
the following:
CL
R
S
GND
GROUND
BUS
Figure 32. Recommended RS Kelvin Ground Connection
The GND pin to the ground point for RS
The system power ground bus to the ground point of RS
Rev. 0 | Page 18 of 19
Data Sheet
ADP1974
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package Ordering
Model1
Package Description
Option
RU-16
RU-16
Quantity
ADP1974ARUZ-R7
ADP1974ARUZ-RL
ADP1974-EVALZ
−40°C to +125°C
−40°C to +125°C
16-Lead Thin Shrink Small Outline Package [TSSOP], 7”Tape and Reel
16-Lead Thin Shrink Small Outline Package [TSSOP], 13”Tape and Reel
Evaluation Board
1000
2500
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D12699-0-9/15(0)
Rev. 0 | Page 19 of 19
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