ADP2311ACPZ-3-R7 [ADI]
Dual 1 A, 18 V, Synchronous Step-Down Regulator with Fail-Safe Voltage Monitoring;
| 型号： | ADP2311ACPZ-3-R7 |
| 厂家： | 
ADI |
| 描述： | Dual 1 A, 18 V, Synchronous Step-Down Regulator with Fail-Safe Voltage Monitoring 监控 |
| 文件： | 总20页 (文件大小：688K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 1 A, 18 V, Synchronous Step-Down
Regulator with Fail-Safe Voltage Monitoring
Data Sheet
ADP2311
FEATURES
TYPICAL APPLICATION CIRCUIT
Input voltage: 4.5 V to 18 V
1.0% output accuracy
PFO POR WDI
EN
PVIN1
RSTO
PVIN2
V
IN
V
IN
Integrated MOSFET: 110 mΩ/60 mΩ typical
Continuous output current: 1 A/1 A
Power fail comparator generates warning
Power-on reset with programmable delay timer
Adjustable voltage monitor for power-down (Channel 2)
Watchdog refresh input
Dual phase with 180° out-of-phase operation
Fixed switching frequency: 300 kHz
Internal compensation and soft start
Stable with low ESR output ceramic capacitors
Precision enable input
R
R
R
PFI_TOP
VM2_TOP
C
IN1
C
PFI
VM2
IN2
R
PFI_BOT
VM2_BOT
BST1
ADP2311 BST2
C1
C2
BST
L1
BST
V
V
L2
OUT2
C
OUT1
SW1
PGND1
SW2
PGND2
R
OUT2
R
C
TOP1
BOT1
TOP2
OUT1
FB1
FB2
R
R
TIMER
BOT2
GND VREG
C
C
TIMER
VREG
Figure 1.
100
95
90
85
80
75
70
65
60
55
50
V
V
= 3.3V
= 5V
OUT
OUT
Power feedback during power-off
UVLO, OCP, OVP, and thermal shutdown protection
APPLICATIONS
Industrial and instrumentation
Healthcare and medical
DC-to-DC point of load applications
0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current at VIN = 12 V, fSW = 300 kHz
GENERAL DESCRIPTION
An on-chip watchdog timer can reset the microprocessor if it
fails to strobe within a preset timeout period. Accurate voltage
monitoring circuitry and a power fail comparator provide a
controlled power-up and power-down sequence to enhance
system reliability.
The ADP2311 is a fully integrated, dual output, synchronous
step-down dc-to-dc regulator. The regulator operates from input
voltages of 4.5 V to 18 V, and the output can regulate down to
0.6 V. Each channel can provide up to 1 A of continuous output
current.
The ADP2311 also includes undervoltage lockout (UVLO),
overvoltage protection (OVP), overcurrent protection (OCP),
and thermal shutdown (TSD).
The ADP2311 integrates the high-side and low-side MOSFETs
to provide a very high efficiency, compact solution. Both channels
of the regulator run at 180° out of phase to reduce the input ripple
current and the input capacitor size, thereby helping to lower
system electromagnetic interference (EMI). The ADP2311 also
integrates internal compensation and soft start circuitry to simplify
the design.
The ADP2311 operates over the −40°C to +125°C junction
temperature range and is available in a 24-lead LFCSP package.
Rev. B
Document Feedback
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Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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ADP2311
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Peak Current-Limit and Short-Circuit Protection ................ 13
Power-On Reset (POR) ............................................................. 13
TIMER Pin Configuration........................................................ 14
Power Fail Comparator.............................................................. 15
Voltage Monitor Comparator (VM2) ...................................... 15
Watchdog Timer......................................................................... 15
Power-Up and Power-Down Sequence ................................... 15
Overvoltage Protection (OVP)................................................. 15
Undervoltage Lockout (UVLO) ............................................... 15
Thermal Shutdown .................................................................... 16
Applications Information .............................................................. 17
Input Capacitor Selection.......................................................... 17
Output Voltage Setting .............................................................. 17
Inductor Selection...................................................................... 17
Output Capacitor Selection....................................................... 18
Application Circuit......................................................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 13
Control Scheme .......................................................................... 13
Precision Enable/Shutdown ...................................................... 13
Internal Regulator (VREG)....................................................... 13
Bootstrap Circuitry .................................................................... 13
Soft Start ...................................................................................... 13
REVISION HISTORY
8/2017—Rev. A to Rev. B
Updated Outline Dimensions....................................................... 20
Changes to Ordering Guide .......................................................... 20
3/2014—Revision A: Initial Version
Rev. B | Page 2 of 20
Data Sheet
ADP2311
FUNCTIONAL BLOCK DIAGRAM
UVLO
PVIN1
ADP2311
ACS1
HICCUP
MODE
OCP
BOOST
REGULATOR
I1
MAX
SLOPE RAMP1
SOFT
BST1
SW1
+
START
DRIVER
CMP1
AMP1
0.6V
+
–
FB1
CONTROL
0.7V
OVP
LOGIC
AND
–
VREG
DRIVER
MOSFET
DRIVER
WITH
ANTI-CROSS
PROTECTION
+
–
+
POR1
CLK1
PGND1
0.579V
LOW-SIDE
CURRENT
SENSE
–
+
I
TIMER
TIMER
POR
RSTO
POR1
POR2
PVIN1
POR
CONTROL
LOGIC
DELAY
TIMER
5V
VREG
GND
PFI
REGULATOR
CLK1
FB1
–
+
SLOPE RAMP1
CLK2
OSC
48mV
FB2
–
+
SLOPE RAMP2
0.6V
0.6V
+
–
POWER-UP
AND
PFO
POWER-DOWN
SEQUENCE
CONTROL
–
+
1.2V
4µA
EN
POR1
1µA
–
+
VM2
WDI
RSTO
RESET
GENERATOR
POR2
UVLO
PVIN2
ACS2
HICCUP
MODE
OCP
BOOST
REGULATOR
I2
MAX
SLOPE RAMP2
SOFT
BST2
SW2
+
START
DRIVER
CMP2
AMP2
0.6V
+
–
FB2
CONTROL
0.7V
OVP
LOGIC
AND
–
VREG
DRIVER
MOSFET
DRIVER
WITH
ANTI-CROSS
PROTECTION
+
–
+
POR2
CLK2
PGND2
0.579V
LOW-SIDE
CURRENT
SENSE
+
Figure 3.
Rev. B | Page 3 of 20
ADP2311
Data Sheet
SPECIFICATIONS
PVIN1 = PVIN2 = 12 V, TJ = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER INPUT
PVIN1, PVIN2 pins
Power Input Voltage Range
Quiescent Current (PVIN1 + PVIN2)
Shutdown Current (PVIN1 + PVIN2)
PVINx Undervoltage Lockout Threshold
PVINx Rising
VPVIN
IQ
ISHDN
4.5
18
1.5
20
V
mA
µA
No switching, FB1 = FB2 = 0.65 V
EN = GND
1.2
10
4.2
3.7
4.5
V
V
PVINx Falling
3.5
FEEDBACK
FB1, FB2 pins
FBx Regulation Voltage
VFB
IFB
TJ = 0°C to +85°C
TJ = −40°C to +125°C
0.594
0.591
0.6
0.6
0.01
0.606
0.609
0.1
V
V
µA
FBx Bias Current
INTERNAL REGULATOR
VREG Voltage
Dropout Voltage
Regulator Current Limit
MOSFET ON RESISTANCE
High-Side On Resistance
Low-Side On Resistance
CURRENT LIMIT
VREG pin
4.7
30
5
300
50
5.3
70
V
mV
mA
IVREG = 5 mA
RDSON
Pin to pin measurements
VBST to VSW = 5 V
VREG = 5 V
110
60
158
90
mΩ
mΩ
High-Side Peak Current Limit
Low-Side Source Current Limit
Low-Side Sink Current Limit
Hiccup Time
1.6
1.9
0.5
2
2.6
1
2.4
3.1
A
A
A
4096
Cycles
SWITCH NODE
SW1, SW2 pins
ISW = 0.5 A
SWx Minimum On Time
SWx Minimum Off Time
PWM SWITCHING FREQUENCY
SOFT START TIME
tMIN_ON
tMIN_OFF
fSW
100
165
300
512
ns
ns
250
1.02
93.5
350
kHz
Cycles
tSS
ENABLE
EN pin
EN Rising Threshold
EN Falling Threshold
EN Source Current
1.2
1.1
5
1.28
V
V
µA
µA
EN voltage below falling threshold
EN voltage above rising threshold
POR pin
1
POWER-ON RESET
Power-On Reset Threshold
Power-On Reset Hysteresis
Power-On Reset Default Deglitch Time
POR Leakage Current
POR Output Low Voltage
POWER FAIL INPUT AND OUTPUT
Power Fail Input Threshold
Power Fail Input Hysteresis
Power Fail Deglitch Time
PFI Leakage Current
Falling threshold (VFB1 and VFB2
)
95
96.5
%
1.5
1.7
0.1
65
%
ms
µA
mV
VPOR = 5 V
IPOR = 1 mA
1
90
PFI and PFO pins
Rising threshold
VPFI
VPFI_HYST
0.591
0.6
25
8
10
0.1
65
0.609
33
V
mV
Cycles
nA
µA
mV
VPFI = 1.2 V
VPFO = 5 V
IPFO = 1 mA
50
1
90
PFO Leakage Current
PFO Output Low Voltage
Rev. B | Page 4 of 20
Data Sheet
ADP2311
Parameter
Symbol
Test Conditions/Comments
VM2 pin
Falling threshold
Min
Typ
Max
Unit
VOLTAGE MONITOR COMPARATOR
VM2 Input Threshold
VM2 Input Hysteresis
VM2 Leakage Current
POR TIMER
0.585
0.6
50
10
0.615
65
50
V
mV
nA
TIMER pin
TIMER Pin Pull-Up Current
WATCHDOG
3
µA
WDI and RSTO pins
Senses VFB2
Reset Threshold Voltage
Reset Threshold Hysteresis
Reset Timeout Period
Watchdog Timeout Period
Option 1
Option 2
Option 3
Option 4
WDI Pulse Width
93.5
95
1.5
1
96.5
1.17
%
%
ms
tRP
tWD
0.883
See the Ordering Guide
83
41
125
167
80
100
50
150
200
117
58
175
233
ms
ms
ms
ms
ns
WDI Input High Voltage
WDI Input Low Voltage
RSTO Output Low Voltage
1.2
V
V
mV
0.4
90
IRSTO = 1 mA
VRSTO = 5 V
65
RSTO Leakage Current
0.1
1
µA
THERMAL
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
15
°C
°C
Rev. B | Page 5 of 20
ADP2311
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. θJA is
measured using natural convection on a JEDEC 4-layer board
with the exposed pad soldered to the printed circuit board
(PCB) and with thermal vias.
Parameter
Rating
PVIN1, PVIN2, EN
SW1, SW2
BST1, BST2
FB1, FB2, WDI, RSTO, VM2, TIMER,
POR, PFO, PFI
VREG
PGNDx to GND
Operating Temperature Range
(Junction)
−0.3 V to +20 V
−1 V to +20 V
VSW + 6 V
−0.3 V to +6 V
Table 3. Thermal Resistance
−0.3 V to +6 V
−0.3 V to +0.3 V
−40°C to +125°C
Package Type
θJA
θJC
Unit
24-Lead LFCSP_WQ
36.8
1.64
°C/W
Storage Temperature Range
Soldering Conditions
−65°C to +150°C
JEDEC J-STD-020
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 6 of 20
Data Sheet
ADP2311
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
18 PGND1
GND
VREG
TIMER
PFI
PGND1
BST1
17
16
15
ADP2311
TOP VIEW
BST2
PFO
14 PGND2
13 PGND2
POR
NOTES
1. SOLDER THE EXPOSED PAD TO AN
EXTERNAL GND PLANE.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
GND
VREG
Analog Ground. Connect this pin to the ground plane.
Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 µF ceramic
capacitor between VREG and GND.
3
4
TIMER
PFI
POR Sequence Selection and Delay Time Setting. This pin is used to set the POR sequence and delay time (see
the TIMER Pin Configuration section).
Power Fail Comparator Input. Connect an external resistor divider from PVIN2 to PFI to monitor the input voltage.
When the PFI voltage falls below the threshold voltage, the PFO pin is pulled low.
5
6
7
PFO
POR
FB2
Power Fail Output (Open Drain).
Power-On Reset Output (Open Drain).
Feedback Voltage Sense Input for Channel 2. Connect this pin to a resistor divider from the Channel 2 output
voltage, VOUT2
.
8
9
RSTO
WDI
Watchdog Output (Open Drain). The RSTO pin goes low if the internal watchdog timer times out because of
inactivity on the WDI input.
Watchdog Input. If WDI remains high or low for longer than the watchdog timeout period, the watchdog output,
RSTO, goes low. The timer is reset with each transition at the WDI input; a high to low or low to high transition
clears the counter.
10
PVIN2
Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor between
this pin and PGND2.
11, 12
13, 14
15
SW2
PGND2
BST2
BST1
PGND1
SW1
Switch Node for Channel 2.
Power Ground for Channel 2.
Supply Rail for the Gate Drive of Channel 2. Place a 0.1 µF capacitor between SW2 and BST2.
Supply Rail for the Gate Drive of Channel 1. Place a 0.1 µF capacitor between SW1 and BST1.
Power Ground for Channel 1.
16
17, 18
19, 20
21
Switch Node for Channel 1.
PVIN1
Power Input for Channel 1. Connect PVIN1 to the input power source, and connect a bypass capacitor between
this pin and PGND1.
22
23
EN
Precision Enable Input. An external resistor divider can be used to set the turn-on threshold. If the enable pin is
not used, connect EN to PVINx.
Voltage Monitor Comparator Input. Connect an external resistor divider from PVIN2 to VM2 to monitor the
input voltage. During the power-down sequence, Channel 2 turns off when the VM2 voltage falls below the
threshold voltage.
VM2
24
FB1
EP
Feedback Voltage Sense Input for Channel 1. Connect this pin to a resistor divider from the Channel 1 output
voltage, VOUT1
.
Exposed Pad. Solder the exposed pad to an external GND plane.
Rev. B | Page 7 of 20
ADP2311
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12 V, VOUT = 3.3 V, L = 22 µH, COUT = 47 µF/X7R/6.3 V, fSW = 300 kHz, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
V
V
V
V
V
V
V
= 1V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
= 5V
V
V
V
V
V
V
= 1V
OUT
OUT
OUT
OUT
OUT
OUT
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
INDUCTOR: XAL6060-223ME
0.2 0.4
OUTPUT CURRENT (A)
INDUCTOR: XAL6060-103ME
0.2 0.4
OUTPUT CURRENT (A)
0
0.6
0.8
1.0
0
0.6
0.8
1.0
Figure 5. Efficiency vs. Output Current at VIN = 12 V
Figure 8. Efficiency vs. Output Current at VIN = 5 V
1.30
1.25
1.20
1.15
1.10
1.05
1.00
15
14
13
12
11
10
9
T
T
T
= –40°C
= +25°C
= +125°C
T
T
T
= –40°C
= +25°C
= +125°C
J
J
J
J
J
J
8
7
6
5
4
6
8
10
12
14
16
18
4
6
8
10
12
14
16
18
V
(V)
IN
V
(V)
IN
Figure 6. Shutdown Current vs. VIN
Figure 9. Quiescent Current vs. VIN
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
1.30
1.25
1.20
1.15
1.10
1.05
1.00
RISING
RISING
FALLING
FALLING
–40
–20
0
20
40
60
80
100 120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. UVLO Threshold vs. Temperature
Figure 10. Enable Threshold vs. Temperature
Rev. B | Page 8 of 20
Data Sheet
ADP2311
5.4
5.2
5.0
4.8
4.6
4.4
4.2
1.20
1.16
1.12
1.08
1.04
1.00
0.96
0.92
0.88
0.84
0.80
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. EN Source Current vs. Temperature at VEN = 1 V
Figure 14. EN Source Current vs. Temperature at VEN = 1.5 V
606
588
584
580
576
572
568
564
560
604
602
600
598
596
594
RISING
FALLING
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Feedback Voltage vs. Temperature
Figure 15. POR Threshold vs. Temperature
612
608
604
600
596
592
588
584
580
576
572
568
564
560
670
660
650
640
630
620
610
600
590
580
RISING
RISING
FALLING
FALLING
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. PFI Threshold vs. Temperature
Figure 16. VM2 Threshold vs. Temperature
Rev. B | Page 9 of 20
ADP2311
Data Sheet
588
584
580
576
572
568
564
560
350
340
330
320
310
300
290
280
270
260
250
RISING
FALLING
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Frequency vs. Temperature
Figure 20. Watchdog Reset Threshold vs. Temperature
1.16
1.12
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
1.14
1.12
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Watchdog Reset Timeout Period vs. Temperature
Figure 21. Normalized Watchdog Timeout Period vs. Temperature
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. TIMER Pin Source Current vs. Temperature
Figure 22. Peak Current Limit Threshold vs. Temperature
Rev. B | Page 10 of 20
Data Sheet
ADP2311
160
150
140
130
120
110
100
90
90
85
80
75
70
65
60
55
50
45
40
80
70
60
50
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. High-Side MOSFET RDSON vs. Temperature
Figure 26. Low-Side MOSFET RDSON vs. Temperature
V
(AC)
OUT1
1
2
3
EN
SW1
1
V
OUT1
OUT2
2
3
V
(AC)
OUT2
V
SW2
POR
4
4
B
B
B
W
B
B
CH1 5V
CH3 2V
CH2 2V
CH4 2V
M1ms
T
A CH1
3V
CH1 20mV
CH3 20mV
CH2 20V
CH4 20V
M4µs
T
A CH4
7.2V
W
W
W
W
20.40%
50.40%
Figure 24. Working Mode Waveform
Figure 27. Soft Start with Full Load
V
IN
V
(AC)
OUT
1
SW
1
2
3
I
OUT
V
(AC)
OUT
4
B
CH1 100mV
M200µs
20.2%
A CH4
720mA
W
B
B
B
W
CH1 5V
CH3 20mV
CH2 10V
M1ms
T
A CH1
10.7V
W
W
CH4 500mA Ω B
T
W
20.40%
Figure 25. Load Transient Response, 0.25 A to 0.75 A
Figure 28. Line Transient Response, VIN from 8 V to 14 V, IOUT = 1 A
Rev. B | Page 11 of 20
ADP2311
Data Sheet
V
V
OUT
OUT
1
2
1
2
4
SW
SW
I
L
I
L
4
B
B
B
B
CH1 2V
CH2 10V
CH4 2A
M10ms
20.2%
A CH1
2.04V
CH1 2V
CH2 10V
CH4 2A Ω B
M10ms
A CH1
2.04V
W
W
W
W
W
Ω B
T
T
70.40%
W
Figure 30. Output Short Recovery
Figure 29. Output Short
Rev. B | Page 12 of 20
Data Sheet
ADP2311
THEORY OF OPERATION
The ADP2311 is a fully integrated, dual output, step-down dc-to-dc
regulator. The ADP2311 can operate with an input voltage from
4.5 V to 18 V and can regulate the output voltage down to 0.6 V.
The ADP2311 also integrates power-up and power-down sequence
circuitry and a watchdog timer to enhance system reliability.
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2311 has a peak current-limit protection circuit to
prevent current runaway. The high-side MOSFET peak current
is limited to 2 A typical. When the peak inductor current reaches
the current-limit threshold, the high-side MOSFET turns off,
the low-side MOSFET turns on, and the overcurrent counter
increments.
CONTROL SCHEME
The ADP2311 features a fixed frequency, current mode pulse-
width modulation (PWM) control architecture. At the start of
each oscillator cycle, the high-side MOSFET turns on, placing a
positive voltage across the inductor. The inductor current increases
until the current sense signal crosses the peak inductor current
threshold, which turns off the high-side MOSFET and turns on
the low-side MOSFET. This places a negative voltage across the
inductor, reducing the inductor current. The low-side MOSFET
stays on for the remainder of the cycle.
When the low-side MOSFET is turned on, the internal circuit
continues to monitor the current going through the low-side
MOSFET. At the end of every clock cycle, if the low-side MOSFET
source current is greater than the low-side source current limit
threshold (2.6 A typical), the high-side MOSFET stays off, the
low-side MOSFET stays on for the next cycle, and the over-
current counter increments. The high-side MOSFET turns on
again when the low-side source current is below the low-side
source current limit at the start of a cycle.
PRECISION ENABLE/SHUTDOWN
The ADP2311 has a precision enable pin for both channels.
The EN pin has an internal pull-down current source of 5 µA
that provides a default turn-off when the EN pin is open.
If the high-side MOSFET peak current does not exceed the peak
current limit in one cycle, the overcurrent counter is reset. If the
overcurrent counter reaches 10, the device enters hiccup mode.
During hiccup mode, the high-side and low-side MOSFETs are
both turned off. The device remains in hiccup mode for 4096
clock cycles and then attempts a soft start. If the current-limit
fault is cleared, the device resumes normal operation; if the
current-limit fault is still active, the device reenters hiccup mode.
When the voltage on the EN pin exceeds 1.2 V typical, Channel 1
and Channel 2 are enabled, and the internal pull-down current
source at the EN pin is reduced to 1 µA, which allows the user to
program the input voltage UVLO.
When the voltage on the EN pin falls below 1.1 V typical,
Channel 1, Channel 2, and all internal circuits are turned off,
and the device enters shutdown mode.
The low-side MOSFET can also sink current from the load. If
the low-side sink current limit is exceeded, both the low-side and
high-side MOSFETs are turned off until the next cycle starts.
INTERNAL REGULATOR (VREG)
The internal regulator provides a stable voltage supply for the
internal control circuits and bias voltage for the low-side gate
drivers. It is recommended that a 1 µF ceramic capacitor be
placed between VREG and GND. The internal regulator also
includes a current-limit circuit for protection.
POWER-ON RESET (POR)
The POR pin is an active high, open-drain output that requires
a resistor to pull it up to a voltage.
The POR threshold is referenced to the FBx pin voltage (VFB)
and is specified as a percentage of VFB. The POR falling threshold
is 95% typical, 93.5% minimum, and 96.5% maximum, which
covers the full temperature range. Therefore, the typical POR
falling threshold is 95% of the typical VFB value, the minimum
POR falling threshold is 93.5% of the minimum VFB value, and
the maximum POR falling threshold is 96.5% of the maximum
The PVIN1 pin provides the power supply for the internal
regulator shared by both channels.
BOOTSTRAP CIRCUITRY
The ADP2311 integrates boot regulators to provide the gate drive
voltage for the high-side MOSFETs. The regulators generate 5 V
bootstrap voltages between the BSTx pin and the SWx pin.
V
FB value.
If VFB is at the minimum value of 0.591 V, the minimum voltage
of the POR falling threshold is 0.591 V × 93.5% = 0.553 V.
It is recommended that an X7R or X5R, 0.1 µF ceramic capacitor
be placed between the BSTx and the SWx pins.
If VFB is at the maximum value of 0.609 V, the maximum voltage
of the POR falling threshold is 0.609 V × 96.5% = 0.588 V.
SOFT START
The ADP2311 has integrated soft start circuitry to limit the
output voltage rise time and to reduce inrush current at startup.
The soft start time is fixed at 512 clock cycles (1.7 ms).
Therefore, the worst-case POR falling threshold voltage range is
0.553 V to 0.588 V.
The typical POR falling threshold voltage is 0.6 V × 95% = 0.57 V.
Rev. B | Page 13 of 20
ADP2311
Data Sheet
The POR function has hysteresis of 1.5% between the falling and
rising thresholds. The POR rising threshold is 96.5% typical,
95% minimum, and 98% maximum. Therefore, the typical POR
rising trigger voltage is 0.6 V × 96.5% = 0.579 V. The POR rising
threshold voltage is always higher than the POR falling threshold
voltage.
POR
ADP2311
RSTO
TIMER
TIMER
C
TIMER PIN CONFIGURATION
Figure 31. Capacitor Connected Between TIMER and GND
The POR sequence timing and delay time depend on the config-
uration of the TIMER pin.
Figure 31 shows the first configuration of the TIMER pin.
Figure 34 shows the power-on reset timing for this configuration.
As shown in Figure 31, a capacitor is connected between the
TIMER pin and GND. The POR pin is pulled high when both
POR
ADP2311
RSTO
TIMER
VOUT1 and VOUT2 are above 96.5% of the VOUTx nominal value
R
SEQ
after a delay time. The POR pin is pulled low when either VOUT1
or VOUT2 falls below 95% of the VOUTx nominal voltage.
C
TIMER
R
= 10kΩ
SEQ
Figure 32. Resistor and Capacitor Connected Between TIMER and GND
The POR delay time is determined by the maximum value
between the internal default delay of 1.7 ms and an external
delay time calculated by the following equation:
POR
0.6 V CTIMER
tDELAY
ADP2311
ITIMER
RSTO
TIMER
where:
CTIMER is the capacitor between the TIMER pin and GND
(1 nF to 68 nF).
Figure 33. TIMER Pin Floating
ITIMER is the pull-up current of the TIMER pin (3 μA).
96.5% × V
OUT1
Figure 32 shows the second configuration of the TIMER pin.
Figure 35 shows the power-on reset timing for this configuration.
As shown in Figure 32, a resistor and capacitor are connected
between the TIMER pin and GND. The POR pin is pulled high
when both VOUT1 and VOUT2 are above 96.5% of the VOUTx nominal
value after a delay time. The POR pin is pulled low when VOUT1
or VOUT2 falls below 95% of the VOUTx nominal voltage or when
V
OUT1
95% × V
OUT2
96.5% × V
OUT2
V
OUT2
POR
tDELAY
RSTO
WDI
tRP
RSTO
the watchdog timer times out (the
to low).
pin is taken from high
tWD
Figure 34. Power-On Reset Timing for Figure 31
The POR delay time is determined by the maximum value
between the internal default delay of 1.7 ms and an external
delay time calculated by the following equation:
96.5% × V
OUT1
CTIMER
ITIMER
V
V
OUT1
OUT2
POR
tDELAY
0.6 V ITIMER RSEQ
95% × V
OUT2
96.5% × V
OUT2
where:
SEQ is a resistor in the range of 8 kΩ to 12 kΩ. Typically,
a 10 kΩ resistor is chosen for RSEQ
TIMER is a capacitor in the range of 1 nF to 68 nF.
tDELAY
tDELAY
R
.
RSTO
tRP
C
tWD
WDI
Figure 33 shows the third configuration of the TIMER pin.
Figure 35 shows the power-on reset timing for this configuration.
In this configuration, the TIMER pin is floating. The POR delay
time is fixed at 1.7 ms.
Figure 35. Power-On Reset Timing for Figure 32 and Figure 33
Rev. B | Page 14 of 20
Data Sheet
ADP2311
The watchdog timeout (tWD) is set by the factory to one of four
possible values: 50 ms, 100 ms, 150 ms, and 200 ms (see the
Ordering Guide).
POWER FAIL COMPARATOR
The ADP2311 integrates a power fail comparator that can
generate a warning when the input voltage falls below the
designated voltage. When the PFI input voltage falls below
0.575 V, the PFO pin is pulled low. When the PFI input voltage
rises above 0.6 V, the PFO pin is pulled high. The low leakage
current of the PFI pin allows the use of a large value external
resistor to reduce system current consumption.
POWER-UP AND POWER-DOWN SEQUENCE
The ADP2311 has a controlled power-up and power-down
sequence. During power-up, Channel 1 is powered up before
Channel 2. During power-down, Channel 2 is powered down
before Channel 1.
The PFO pin can be used to send a warning signal to the pro-
cessor in case of an abnormal input voltage condition so that
the processor can prepare to power down the system before
power is lost.
Channel 1 does not power up until all of the following
conditions are met followed by a 128 cycle delay:
•
•
•
The PFI voltage exceeds 0.6 V.
The voltage on the EN pin exceeds 1.2 V.
Both the FB1 and FB2 voltages are less than 48 mV.
VOLTAGE MONITOR COMPARATOR (VM2)
The VM2 pin connects to an accurate comparator. When the
VM2 voltage falls below 0.6 V, Channel 2 is turned off. When
the VM2 voltage rises above 0.65 V, Channel 2 is allowed to
power up if the EN pin is high and PFI is above 0.6 V.
When VOUT1 reaches 96.5% of its normal voltage, Channel 2 is
powered up after a delay of 256 cycles.
During power-down, when the VM2 voltage falls below 0.6 V,
Channel 2 is turned off and power feedback occurs. Channel 2
energy is fed back to the input voltage to speed up the discharge
time of Channel 2. When the FB2 output voltage falls below
48 mV, Channel 1 is allowed to turn off, and power feedback
occurs to speed up the discharge time of Channel 1.
WATCHDOG TIMER
The watchdog timer circuit is used to monitor the activity of the
processor. During power-up, the watchdog timer circuit does not
acknowledge pulses from the WDI pin until the voltage at FB2 is
above the reset threshold and the reset timeout period (tRP) has
The power feedback feature allows the Channel 1 and Channel 2
output voltage fall time (100% to 10%) to be within 10 ms.
RSTO
elapsed. During the power-up sequence, the
pin is pulled
low and remains low until the watchdog timer circuit is activated.
The watchdog timer circuit can be initialized only by a low to
high transition on the WDI pin both after power up and after a
watchdog timeout (see Figure 36).
OVERVOLTAGE PROTECTION (OVP)
The ADP2311 provides an OVP feature to protect the system
against output shorts to a higher voltage supply or when a
strong load disconnect transient occurs.
96.5%
V
OUT2
If the feedback voltage increases to 0.7 V, the high-side MOSFET
turns off and the low-side MOSFET turns on until the negative
current limit threshold is triggered. After the negative current
limit threshold is triggered, both MOSFETs are held in the off
state until the FBx pin voltage falls to 0.63 V, at which point the
ADP2311 resumes normal operation.
RSTO
tWD
tRP
tRP
WDI
Figure 36. Watchdog Timing Diagram
UNDERVOLTAGE LOCKOUT (UVLO)
After the watchdog timer circuit is active, it is cleared with every
low to high or high to low logic transition on the WDI pin, which
can detect pulse widths as short as 80 ns. If the WDI pin remains
high or low for longer than the watchdog timeout period (tWD),
The UVLO threshold is 4.2 V with hysteresis of 0.5 V to prevent
power-on glitches on the device. When the PVIN1 or PVIN2
voltage rises above 4.2 V, Channel 1 or Channel 2 is enabled, and
the soft start period begins. When PVIN1 or PVIN2 falls below
3.7 V, Channel 1 or Channel 2 is turned off.
RSTO
a reset is asserted, and the
pin is pulled low. The processor
is required to toggle the WDI pin within the timeout period;
therefore, it indicates a code execution error, and the generated
reset pulse (tRP) restarts the microprocessor in a known state.
The watchdog timer can also be cleared by a reset assertion due
to an undervoltage condition on VOUT2. When the FB2 voltage is
below the reset threshold, a reset is asserted; the watchdog timer
is cleared and does not begin counting again until reset is
deasserted.
Rev. B | Page 15 of 20
ADP2311
Data Sheet
A 15°C hysteresis is included so that the ADP2311 does not
THERMAL SHUTDOWN
recover from thermal shutdown until the on-chip temperature
falls below 135°C. Upon recovery, a soft start is initiated before
normal operation. Figure 37 shows the power sequence during
thermal protection based on the circuit shown in Figure 38.
If the ADP2311 junction temperature exceeds 150°C, the PFO
pin is immediately pulled low, and Channel 2 enters power feed-
back mode. When VOUT2 falls below 95% of its nominal voltage,
RSTO
the POR and
pins are pulled low. When the FB2 voltage falls
below 48 mV, Channel 1 turns off and enters discharge mode.
WHEN THE JUNCTION TEMPERATURE IS
HIGHER THAN 150°C, PFO IS IMMEDIATELY
PULLED LOW, AND CHANNEL 2 ENTERS
POWER FEEDBACK MODE.
WHEN FB2 FALLS TO 95% OF ITS NOMINAL
VALUE, POR AND RSTO ARE PULLED LOW.
WHEN FB2 DISCHARGES TO 48mV,
CHANNEL 1 TURNS OFF.
WHEN THE JUNCTION
TEMPERATURE IS LOWER
THAN 135°C, THE PART
POWERS UP AGAIN USING THE
NORMAL START-UP ROUTINE.
THERMAL
SHUTDOWN
V
IN
PWM1
POWER
FEEDBACK MODE
PWM2
FB1
48mV
FB2
95%
48mV
PFO
POR
RSTO
(INT)
WDI
(FROM
PROCESSOR)
Figure 37. Power Sequence During Thermal Protection Based on the Circuit Shown in Figure 38
Rev. B | Page 16 of 20
Data Sheet
ADP2311
APPLICATIONS INFORMATION
As a guideline, the inductor ripple current, ΔIL, is typically set
to one-third of the maximum load current. The inductor value
is calculated using the following equation:
INPUT CAPACITOR SELECTION
The input capacitor reduces the input voltage ripple caused by
the switch current on PVINx. Place the input capacitor as close
as possible to the PVINx pin. A ceramic capacitor in the 10 μF
to 47 μF range is recommended. The loop composed of the input
capacitor, the high-side MOSFET, and the low-side MOSFET
must be kept as small as possible.
(VIN −VOUT ) × D
L =
∆IL × fSW
where:
VIN is the input voltage.
The voltage rating of the input capacitor must be greater than
the maximum input voltage. Ensure that the rms current rating
of the input capacitor is larger than the value calculated from
the following equation:
V
OUT is the output voltage.
D is the duty cycle (D = VOUT/VIN).
ΔIL is the inductor current ripple.
fSW is the switching frequency.
The peak inductor current is calculated by
I
CIN_RMS = IOUT
×
D ×(1− D)
∆IL
2
IPEAK = IOUT +
where D is the duty cycle (D = VOUT/VIN).
OUTPUT VOLTAGE SETTING
The saturation current of the inductor must be larger than the
peak inductor current. For ferrite core inductors with a quick
saturation characteristic, the saturation current rating of the
inductor must be higher than the current-limit threshold of the
switch to prevent the inductor from reaching saturation.
The output voltage of the ADP2311 can be set by an external
resistor divider using the following equation:
RTOP
RBOT
V
OUT = 0.6 × 1 +
The rms current of the inductor is calculated using the follow-
ing equation:
To limit the output voltage accuracy degradation due to the FB
bias current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT < 30 kΩ.
2
∆IL
12
2
IRMS
=
IOUT
+
Table 5 lists the recommended resistor divider values for various
output voltages.
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 6 lists some recommended inductors.
Table 5. Resistor Divider Values for Various Output Voltages
Table 6. Recommended Inductors
VOUT (V)
RTOP 1% (kΩ)
RBOT 1% (kΩ)
Value
(µH)
DCR
ISAT (A) IRMS (A) (mΩ)
1.0
1.2
1.5
1.8
2.5
3.3
5.0
10
10
15
20
47.5
10
22
15
10
10
10
15
2.21
3
Vendor Part No.
Sumida CDRH8D58/
10
15
22
2.2
1.9
1.4
4.5
3.6
3.3
20.5
LDNP-100NC
CDRH8D58/
LDNP-150NC
CDRH8D58/
LDNP-220NC
29
36.2
Coilcraft XAL6060-103ME
XAL6060-153ME
10
15
22
7.6
5.8
5.6
7
6
5
27
39.7
55.1
INDUCTOR SELECTION
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor value leads to a faster transient response, but
degrades efficiency due to a larger inductor ripple current. Using
a large inductor value leads to smaller ripple current and better
efficiency, but results in a slower transient response.
XAL6060-223ME
Rev. B | Page 17 of 20
ADP2311
Data Sheet
Table 8 lists the recommended external inductors and output
capacitors for typical applications with the ADP2311.
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the regulator. The ADP2311 is
designed to operate with small ceramic capacitors that have low
equivalent series resistance (ESR) and low equivalent series
inductance (ESL) and can, therefore, easily meet the output
voltage ripple specifications.
Table 8. Recommended External Components for Typical
Applications
R
TOP (kΩ), RBOT (kΩ),
1% 1%
15
VIN (V) VOUT (V) L (µH) COUT (µF)
12
12
12
12
12
12
12
5
1.0
1.2
1.5
1.8
2.5
3.3
5.0
1.0
1.2
1.5
1.8
2.5
3.3
10
10
15
15
22
22
33
10
10
10
10
10
10
2 × 47
2 × 47
2 × 47
47
47
22
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
10
10
10
15
2.21
3
15
10
10
10
15
2.21
When the regulator operates in continuous conduction mode, the
overall output voltage ripple is the sum of the voltage spike caused
by the output capacitor ESR plus the voltage ripple caused by the
charging and discharging of the output capacitor.
1
22
∆VRIPPLE = ∆IL ×
+ ESRC
OUT
2 × 47
2 × 47
47
8× fSW ×COUT
5
5
Capacitors with lower ESR are preferable to guarantee low output
voltage ripple, as shown in the following equation:
5
47
5
22
∆VRIPPLE
∆IL
ESRC
≤
OUT
5
22
Ceramic capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied voltage.
X5R or X7R dielectrics are recommended for best performance
due to their low ESR and small temperature coefficients.
Table 7 lists recommended output capacitors for VOUT ≤ 5.0 V.
Table 7. Recommended Output Capacitors for VOUT ≤ 5.0 V
Vendor
Part No.
Value
Murata
GRM31CR60J226KE19
GRM32ER60J476ME20
C3216X5R0J226M160AA
C3216X5R0J336M130AC
C3216X5R0J476M160AC
22 μF, 6.3 V, X5R
47 μF, 6.3 V, X5R
22 μF, 6.3 V, X5R
33 μF, 6.3 V, X5R
47 μF, 6.3 V, X5R
TDK
Rev. B | Page 18 of 20
Data Sheet
ADP2311
APPLICATION CIRCUIT
BST1
SW1
C3
0.1µF
L1
15µH
EN
V
V
OUT1
IN
PVIN1
1.1V/0.6A
15.5V
C1
10µF/25V
C5
C6
47µF/6.3V/X7R
47µF/6.3V/X7R
PGND1
FB1
R1
11.5kΩ
R2
13.7kΩ
BST2
C4
0.1µF
L2
22µH
V
PVIN2
OUT2
SW2
2.5V/0.4A
C2
10µF/25V
C7
PGND2
47µF/6.3V/X7R
R3
47.5kΩ
ADP2311
R7
500kΩ
R9
500kΩ
FB2
R4
15kΩ
V
REG
R5
R6
R11
PFI
100kΩ 100kΩ 100kΩ
VM2
R8
21.8kΩ
R10
66.5kΩ
POR
PFO
WDI
POR
PFO
WDI
V
REG
RSTO
RSTO
VREG
GND
C8
1µF
TIMER
C9
15nF
Figure 38. Typical Application Circuit (Input Power Fail Voltage Programmed at 14.4 V/13.8 V; Channel 2 Turned Off at 5.1 V)
14.4V
13.8V
5.5V
5.1V
V
IN
0.575V
0.6V
PFI
PFO
0.65V
0.6V
VM2
OUT1
96.5%
V
96.5%
95%
0.2V
V
OUT2
POR
853µs
RSTO
WDI
(FROM PROCESSOR)
Figure 39. Power-Up and Power-Down Sequence Based on the Circuit Shown in Figure 38
Rev. B | Page 19 of 20
ADP2311
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8
Figure 40. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm x 4 mm Body and 0.75 mm Package Height
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Watchdog Timeout Period
tWD = 100 ms
tWD = 50 ms
tWD = 150 ms
tWD = 200 ms
Package Description
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
Package Option
CP-24-15
CP-24-15
CP-24-15
CP-24-15
ADP2311ACPZ-1-R7
ADP2311ACPZ-2-R7
ADP2311ACPZ-3-R7
ADP2311ACPZ-4-R7
ADP2311-1-EVALZ
Evaluation Board
1 Z = RoHS Compliant Part.
©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11036-0-8/17(B)
Rev. B | Page 20 of 20
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SI9137LG
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SI9122E
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