ADP2441-EVALZ [ADI]
36 V,1 A, Synchronous, Step-Down DC-to-DC Regulator; 36 V ， 1 A，同步，降压的DC- DC稳压器
| 型号： | ADP2441-EVALZ |
| 厂家： | 
ADI |
| 描述： | 36 V,1 A, Synchronous, Step-Down DC-to-DC Regulator |
| 文件： | 总32页 (文件大小：1912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
36 V,1 A, Synchronous,
Step-Down DC-to-DC Regulator
ADP2441
Data Sheet
FEATURES
TYPICAL CIRCUIT CONFIGURATION
C3
Wide input voltage range of 4.5 V to 36 V
Low minimum on time of 50 ns
Maximum load current of 1 A
C
C4
BST
V
OUT
High efficiency of up to 94%
R
TOP
Adjustable output down to 0.6 V
1% output voltage accuracy
Adjustable switching frequency of 300 kHz to 1 MHz
Pulse skip mode at light load for power saving
Precision enable input pin
V
IN
FB
VIN
R
V
BOTTOM
OUT
COMP ADP2441
SW
C
C
OUT
IN
V
IN
EN
R
PGND
COMP
Open-drain power good
C
COMP
External soft start with tracking
Overcurrent-limit protection
R
FREQ
Shutdown current of less than 15 μA
UVLO and thermal shutdown
Figure 1.
100
90
80
70
60
50
40
30
20
10
0
12-lead, 3 mm × 3 mm LFCSP package
V
= 5V
OUT
V
= 12V
OUT
APPLICATIONS
Point of load applications
Distributed power systems
Industrial control supplies
Standard rail conversion to 24 V/12 V/5 V/3.3 V
V
= 3.3V
OUT
V
= 24V
IN
GENERAL DESCRIPTION
fSW = 300kHz
The ADP2441 is a constant frequency, current mode control,
synchronous, step-down dc-to-dc regulator that is capable of
driving loads up to 1 A with excellent line and load regulation
characteristics. The ADP2441 operates with a wide input voltage
range of 4.5 V to 36 V, which makes it ideal for regulating power
from a wide variety of sources. In addition, the ADP2441 has
very low minimum on time (50 ns) and is, therefore, suitable for
applications requiring a very high step-down ratio.
0.02
0.2
LOAD (A)
1
Figure 2. Efficiency vs. Load Current, VIN = 24 V
The output voltage can be adjusted from 0.6 V to 0.9 V × VIN.
High efficiency is obtained with integrated low resistance
N-channel MOSFETs for both high-side and low-side devices.
The ADP2441 uses hiccup mode to protect the IC from short
circuits or from overcurrent conditions on the output. The external
programmable soft start limits inrush current during startup for
a wide variety of load capacitances. Other key features include
tracking, input undervoltage lockout (UVLO), thermal shutdown
(TSD), and precision enable (EN), which can also be used as a
logic level shutdown input.
The switching frequency is adjustable from 300 kHz to 1 MHz with
an external resistor. The ADP2441 also has an accurate power-good
(PGOOD) open-drain output signal.
At light load conditions, the regulator operates in pulse skip
mode by skipping pulses and reducing switching losses to improve
energy efficiency. In addition, at medium to heavy load conditions,
the regulator operates in fixed frequency pulse-width modulation
(PWM) mode to reduce electromagnetic interference (EMI).
The ADP2441 is available in a 3 mm × 3 mm, 12-lead LFCSP
package and is rated for a junction temperature range of −40°C
to +125°C.
Rev. A
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Technical Support
©2012 Analog Devices, Inc. All rights reserved.
www.analog.com
ADP2441
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information.............................................................. 18
Selecting the Output Voltage .................................................... 18
Setting the Switching Frequency.............................................. 18
Soft Start ...................................................................................... 19
External Components Selection............................................... 19
Boost Capacitor .......................................................................... 21
VCC Capacitor............................................................................ 21
Loop Compensation .................................................................. 21
Large Signal Analysis of the Loop Compensation................. 21
Design Example.............................................................................. 23
Configuration and Components Selection............................. 23
System Configuration................................................................ 24
Typical Application Circuits ......................................................... 25
Design Example.......................................................................... 25
Other Typical Circuit Configurations ..................................... 26
Power Dissipation and Thermal Considerations ....................... 29
Power Dissipation....................................................................... 29
Thermal Considerations............................................................ 29
Evaluation Board Thermal Performance .................................... 30
Circuit Board Layout Recommendations ................................... 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Circuit Configuration......................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Internal Block Diagram ................................................................. 14
Theory of Operation ...................................................................... 15
Control Architecure ................................................................... 15
Adjustable Frequency................................................................. 16
Power Good................................................................................. 16
Soft Start ...................................................................................... 16
Tracking ....................................................................................... 16
Undervoltage Lockout (UVLO) ............................................... 17
Precision Enable/Shutdown...................................................... 17
Current-Limit and Short-Circuit Protection.......................... 17
Thermal Shutdown..................................................................... 17
REVISION HISTORY
11/12—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changed IVIN Maximum Parameter from 2.2 mA to2 mA.......... 3
Changes to Pin 3 and Pin 5 Descriptions...................................... 6
Changes to Boost Capacitor Section............................................ 21
Changes to Figure 66...................................................................... 31
Changes to Ordering Guide .......................................................... 32
6/12—Revision 0: Initial Version
Rev. A | Page 2 of 32
Data Sheet
ADP2441
SPECIFICATIONS
VIN = 4.5 V to 36 V, TJ = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Input Voltage Range
Supply Current
Shutdown Current
UVLO
VIN
IVIN
ISHDN
4.5
36
2
15
V
mA
μA
VEN = 1.5 V not switching
VEN = AGND
1.7
10
Threshold
Hysteresis
VUVLO
VIN falling
3.8
4
200
4.2
5.5
V
mV
INTERNAL REGULATOR
Regulator Output Voltage
OUTPUT
VCC
VIN = 5 V to 36 V
5
V
Output Voltage Range
Maximum Output Current
Feedback Regulation Voltage
VOUT
IOUT
VFB
0.6
1
0.594
0.591
0.9 × VIN
V
A
V
V
TJ = −40°C to +85°C
TJ = −40°C to +125°C
0.6
0.6
0.606
0.609
Line Regulation
Load Regulation
0.005
0.05
%/V
%/A
ERROR AMPLIFIER
Feedback Bias Current
Transconductance
Open-Loop Voltage Gain1
MOSFETS
IFB_BIAS
gm
AVOL
VFB = 0.6 V
50
250
65
200
300
nA
μA/V
dB
ICOMP
=
20 μA
200
High-Side Switch On Resistance2
Low-Side Switch On Resistance2
Leakage Current
Minimum On Time3
Minimum Off Time4
CURRENT SENSE
RDS_H(ON)
RDS_L(ON)
ILKG
tON_MIN
tOFF_MIN
BST − SW = 5 V
VCC = 5 V
VEN = AGND
170
120
1
50
165
270
180
25
65
175
mΩ
mΩ
ꢀA
ns
All switching frequencies
ns
Current Sense Amplifier Gain
Hiccup Time
Number Of Cumulative Current-Limit Cycles
to Go into Hiccup Mode
Peak Current Limit
FREQUENCY
GCS
1.6
1.4
2
6
8
2.4
A/V
ms
Events
fSW = 300 kHz to1 MHz
ICL
1.6
1.8
A
Switching Frequency Range
Frequency Set Accuracy
fSW
300
270
900
1000
330
1100
kHz
kHz
kHz
FREQ pin = 308 kΩ
FREQ pin = 92.5 kΩ
300
1000
SOFT START
Soft Start Current
PRECISION ENABLE
Input Threshold
Hysteresis
Leakage Current
Thermal Shutdown
Rising
ISS
VSS = 0 V
0.9
1
1.2
1.25
1
μA
VEN(RISING)
VEN(HYST)
IIEN_LEAK
1.15
1.20
100
0.1
V
mV
μA
VIN = VEN
TSD
TSD(HYST)
150
25
°C
°C
Hysteresis
Rev. A | Page 3 of 32
ADP2441
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER GOOD
PGOOD High, FB Rising Threshold5
PGOOD Low, FB Rising Threshold5
PGOOD High, FB Falling Threshold5
PGOOD Low, FB Falling Threshold5
PGOOD
89
92
95
%
%
%
%
111
106
83
115
109
86
118
112
89
Delay
tPGOOD
50
1
0.5
μs
μA
kΩ
High Leakage Current
Pull-Down Resistor
TRK
IPGOOD(SRC) VPGOOD = VCC
IPGOOD(SNK) FB = 0 V
10
0.7
TRK Input Voltage Range
TRK to FB Offset Voltage
0
600
mV
mV
TRK = 0 mV to 500 mV
10
1 Guaranteed by design.
2 Measured between VIN and SW pins—includes bond wires and pin resistance.
3 Based on bench characterization. Measured with VIN = 12 V, VOUT = 1.2 V, load = 1 A, fSW = 1 MHz, and the output in regulation. Measurement does not include dead time.
4 Based on bench characterization. Measured with VIN = 15 V, VOUT = 12 V, load = 1 A, fSW = 600 kHz, and the output in regulation. Measurement does not include dead time.
5 This threshold is expressed as a percentage of the nominal output voltage.
Rev. A | Page 4 of 32
Data Sheet
ADP2441
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
VIN to PGND
EN to AGND
SW to PGND
BST to PGND
VCC to AGND
BST to SW
Rating
−0.3 V to +40 V
−0.3 V to +40 V
−0.3 V to +40 V
−0.3 V to +45 V
−0.3 V to +6 V
−0.3 V to +6 V
FREQ, PGOOD, SS/TRK, COMP, FB to AGND −0.3 V to +6 V
THERMAL RESISTANCE
PGND to AGND
0.3 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages, and is
based on a 4-layer standard JEDEC board.
Operating Junction Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
−40°C to +125°C
−65°C to +150°C
260°C
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
12-Lead LFCSP
40
2.4
°C/W
ESD CAUTION
Rev. A | Page 5 of 32
ADP2441
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FB
COMP
EN
1
2
3
9 VIN
SW
ADP2441
TOP
VIEW
8
7 PGND
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO THE SYSTEM AGND PLANE AND PGND PLANE.
Figure 3. Pin Configuration, Top View
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
FB
COMP
EN
Feedback Regulation Voltage is 0.6 V. Connect this pin to a resistor divider from the output of the dc-to-dc regulator.
Error Amplifier Compensation. Connect a resistor and capacitor in series to ground.
Precision Enable. This features offers ±±5 accuracy when using a 1.2± V reference voltage. Pull this pin high to
enable the regulator and low to disable the regulator. Do not leave the EN pin floating.
4
±
PGOOD
FREQ
Active High Power-Good Output. This pin is pulled low when the output is out of regulation.
Switching Frequency. A resistor to AGND sets the switching frequency (see the Setting the Switching Frequency
section). Do not leave the FREQ pin floating.
6
SS/TRK
PGND
SW
Soft Start/Tracking Input. A capacitor to ground is required to program the soft start time, which gradually ramps
up the output. A resistive divider to an external reference is required on this pin to track an external voltage.
Power Ground. Connect a decoupling ceramic capacitor as close as possible between the VIN pin and this pin.
Connect this pin directly to the exposed pad.
Switch. The midpoint for the drain of the low-side N-channel power MOSFET switch and the source for the high-side
N-channel power MOSFET switch.
7
8
9
VIN
Power Supply Input. Connect this pin to the input power source, and connect a bypass ceramic capacitor directly
from this pin to PGND, as close as possible to the IC. The operation voltage is 4.± V to 36 V.
10
BST
Boost. Connect a 10 nF ceramic capacitor between the BST and SW pins as close to the IC as possible to form a
floating supply for the high-side N-Channel power MOSFET driver. This capacitor is needed to drive the gate of the
N-channel power MOSFET above the supply voltage.
11
12
VCC
Output of the Internal Low Dropout Regulator. This pin supplies power for the internal controller and driver circuitry.
Connect a 1 μF ceramic capacitor between VCC and AGND and a 1 μF ceramic capacitor between VCC and PGND.
The VCC output is active when the EN pin voltage is more than 0.7 V.
Analog Ground. This pin is the internal ground for the control functions. Connect this pin directly to the exposed pad.
Exposed Thermal Pad. The exposed pad should be connected to AGND and PGND.
AGND
EP
Rev. A | Page 6 of 32
Data Sheet
ADP2441
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
90
80
70
60
50
40
30
20
10
0
V
= 5V
IN
V
= 5V
90
80
70
60
50
40
30
20
10
0
IN
V
= 12V
IN
V
= 12V
IN
V
= 24V
IN
V
= 24V
IN
V
= 3.3V
V
= 3.3V
OUT
OUT
fSW = 300kHz
COILCRAFT MSS1038
fSW = 700kHz
COILCRAFT MSS1038
0.01
0.1
LOAD (A)
1
1
1
0.01
0.1
LOAD (A)
1
Figure 4. Efficiency vs. Load Current,
VOUT = 3.3 V, fSW = 300 kHz
Figure 7. Efficiency vs. Load Current,
VOUT = 3.3 V, fSW = 700 kHz
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 12V
IN
V
= 12V
IN
V
= 24V
IN
V
= 24V
V
= 36V
IN
IN
V
= 36V
IN
V
= 5V
V
= 5V
OUT
OUT
fSW = 300kHz
COILCRAFT MSS1038
fSW = 700kHz
COILCRAFT MSS1038
0.01
0.1
LOAD (A)
0.01
0.1
LOAD (A)
1
Figure 5. Efficiency vs. Load Current,
VOUT = 5 V, fSW = 300 kHz
Figure 8. Efficiency vs. Load Current,
VOUT = 5 V, fSW = 700 kHz
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 24V
IN
V
= 24V
IN
V
= 36V
IN
V
= 36V
IN
V
= 12V
V
= 12V
OUT
OUT
fSW = 300kHz
COILCRAFT MSS1038
fSW = 600kHz
COILCRAFT MSS1038
0.01
0.1
0.01
0.1
1
LOAD (A)
LOAD (A)
Figure 6. Efficiency vs. Load Current,
VOUT = 12 V, fSW = 300 kHz
Figure 9. Efficiency vs. Load Current,
VOUT = 12 V, fSW = 600 kHz
Rev. A | Page 7 of 32
ADP2441
Data Sheet
0.5
0.4
0.3
0.2
0.1
0
400
350
300
250
200
150
100
50
V
V
V
= 12V
= 24V
= 36V
IN
IN
IN
fSW = 300kHz
fSW = 700kHz
–0.1
V
= 5V
OUT
fSW = 700kHz
–0.2
–0.3
–0.4
–0.5
V
= 3.3V
15
OUT
0
0
0.2
0.4
0.6
0.8
1.0
5
10
20
25
30
35
40
LOAD (A)
V
(V)
IN
Figure 10. Load Regulation for Different Supplies
Figure 13. Pulse Skip Threshold, VOUT = 3.3 V
1.0
0.8
300
250
200
150
100
50
fSW = 300kHz
0.6
0.4
T
= +25°C
A
T
= –40°C
0.2
A
fSW = 700kHz
0
–0.2
–0.4
–0.6
–0.8
–1.0
T
= +125°C
A
V
V
= 24V
= 5V
IN
OUT
fSW = 700kHz
V
= 5V
OUT
0
0
0.2
0.4
0.6
0.8
1.0
10
15
20
25
(V)
30
35
40
LOAD (A)
V
IN
Figure 11. Load Regulation for Different Temperatures
Figure 14. Pulse Skip Threshold, VOUT = 5 V
0.5
0.4
300
250
200
150
100
50
0.3
fSW = 300kHz
0.2
LOAD = 500mA
0.1
0
fSW = 600kHz
–0.1
–0.2
–0.3
–0.4
–0.5
LOAD = 1A
V
V
= 24V
IN
= 5V
OUT
fSW = 700kHz
V
= 12V
20
OUT
0
15
7
12
17
22
(V)
27
32
37
25
30
35
40
V
V
(V)
IN
IN
Figure 12. Line Regulation, VOUT = 5 V for Different Loads
Figure 15. Pulse Skip Threshold, VOUT = 12 V
Rev. A | Page 8 of 32
Data Sheet
ADP2441
12
2.25
2.05
1.85
1.65
1.45
1.25
1.05
0.85
0.65
0.45
0.25
0.05
V
= 36V
IN
10
8
V
= 4.5V
= 12V
= 24V
= 36V
IN
6
V
V
V
IN
IN
IN
4
V
= 4.5V
IN
2
0
–50
–50 –30 –10
10
30
50
70
90
110 130 150
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Shutdown Current vs. Temperature
Figure 19. Supply Current vs. Temperature
4.5
4.4
4.3
4.2
4.1
4.0
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
ENABLE RISING THRESHOLD
UVLO, RISING V
IN
ENABLE FALLING THRESHOLD
UVLO, FALLING V
IN
3.9
–50
–50 –30 –10
10
30
50
70
90
110 130 150
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. UVLO Threshold vs. Temperature
Figure 20. Enable Threshold vs. Temperature
130
120
110
100
90
0.7
0.6
0.5
0.4
0.3
0.2
0.1
80
P
P
P
P
FALL, FB INCREASING
RISE, FB DECREASING
RISE, FB INCREASING
FALL, FB DECREASING
GOOD
GOOD
GOOD
GOOD
70
60
0
–50 –30 –10
10
30
50
70
90
110 130 150
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
TRACK (V)
TEMPERATURE (°C)
Figure 21. PGOOD Threshold vs. Temperature
Figure 18. Tracking Range
Rev. A | Page 9 of 32
ADP2441
Data Sheet
1200
1100
1000
900
800
700
600
500
400
300
200
1200
1000
800
fSW = 1MHz
fSW = 1MHz
fSW = 700kHz
fSW = 700kHz
600
400
fSW = 300kHz
200
fSW = 300kHz
0
0
–50 –30 –10
10
30
50
70
90
110 130 150
5
10
15
20
(V)
25
30
35
40
TEMPERATURE (°C)
V
IN
Figure 22. Switching Frequency vs. Supply
Figure 25. Switching Frequency vs. Temperature
1.80
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
1.58
1.56
1.54
1.52
1.50
200
175
150
125
100
75
MINIMUM OFF
V
V
= 36V
IN
= 4.5V
IN
MINIMUM ON
50
25
0
–50
0
50
TEMPERATURE (°C)
100
150
–50 –30 –10
10
30
50
70
90
110 130 150
TEMPERATURE (°C)
Figure 26. Current Limit vs. Temperature
Figure 23. Minimum On Time and Minimum Off Time vs. Temperature
260
240
220
200
180
160
140
120
100
180
160
140
120
100
80
60
40
20
0
–50
–25
0
25
50
75
100
125
150
–50 –30 –10
10
30
50
70
90
110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. Low-Side RDS(ON) vs. Temperature
Figure 24. High-Side RDS(ON) vs. Temperature
Rev. A | Page 10 of 32
Data Sheet
ADP2441
V
V
OUT
OUT
1
1
V
V
f
= 24V
IN
OUT
SW
= 3.3V
= 500kHz
LOAD = 100mA
INDUCTOR CURRENT
INDUCTOR CURRENT
4
4
V
V
= 24V
= 3.3V
= 500kHz
IN
OUT
SW
F
SW
SW
2
2
B
B
W
CH1 20.0mV
CH2 10.0V
CH4 200mA Ω
M4.00µs A CH4 120mA
T 41.40%
CH1 20.0mV
CH2 10.0V
CH4 500mA Ω
M4.00µs A CH4 120mA
T 41.40%
W
Figure 28. Pulse Skip Mode,
IN = 24 V, VOUT = 3.3 V, fSW = 500 kHz, No Load
Figure 31. Pulse Skip Mode,
VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz, Load = 100 mA
V
V
V
OUT
OUT
1
1
INDUCTOR CURRENT
INDUCTOR CURRENT
V
V
f
= 24V
IN
OUT
SW
= 3.3V
4
= 500kHz
LOAD = 1A
4
2
SW
SW
2
B
B
W
CH1 20.0mV
CH2 10.0V
CH4 500mA Ω
M1.00µs
T 41.40%
A CH2 9.80V
CH1 200mV
CH2 10.0V
CH4 1.00A Ω
M2.00ms A CH1 60.0mV
T 49.40%
W
Figure 29. PWM Mode,
VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz, Load = 1 A
Figure 32. Hiccup Mode,
VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz, Output Short to PGND
V
V
= 24V fSW = 700kHz
OUT
V
IN
OUT
1
= 5V LOAD STEP = 300mA
V
OUT
V
V
f
= 24V
IN
1
= 5V
OUT
= 700kHz
LOAD STEP = 500mA
SW
LOAD
SW
LOAD
SW
4
2
4
2
B
B
CH1 100mV
CH2 10V
CH4 500mA Ω
M200µs A CH4 690mA
T 79.80%
CH1 50.0mV
CH2 10.0V
W
CH4 200mA Ω
M200µs A CH4 604mA
W
Figure 30. Load Transient Response,
Figure 33. Load Transient Response,
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load Step = 500 mA
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load Step = 300 mA
Rev. A | Page 11 of 32
ADP2441
Data Sheet
V
OUT
1
V
OUT
V
V
f
= 12V
IN
1
= 5V
OUT
= 300kHz
LOAD STEP = 500mA
SW
LOAD
SW
LOAD
SW
V
V
f
= 24V
= 12V
= 600kHz
IN
OUT
SW
LOAD STEP = 500mA
4
2
4
2
B
B
CH1 100mV
CH2 5.00V
M200µs A CH4 690mA
CH1 200mV
CH2 10.0V
M200µs A CH4 600mA
W
W
CH4 500mA Ω
CH4 500mA Ω
Figure 34. Load Transient Response,
Figure 37. Load Transient Response,
VIN = 12 V, VOUT = 5 V, fSW = 300 kHz, Load Step = 500 mA
VIN = 24 V, VOUT = 12 V, fSW = 600 kHz, Load Step = 500 mA
ENABLE
V
OUT
1
V
3
OUT
PGOOD
LOAD
SW
V
V
f
= 24V
= 12V
= 300kHz
IN
OUT
SW
LOAD STEP = 500mA
1
4
4
2
V
V
f
= 24V
IN
= 5V
OUT
= 700kHz
SW
B
B
CH1 200mV
CH2 10.0V
CH4 500mA Ω
M200µs A CH4 550mA
CH1 2.00V
CH3 5.00V
M 200µs
A CH3 1.60V
W
W
CH4 2.00V
Figure 35. Load Transient Response,
IN = 24 V, VOUT = 12 V, fSW = 300 kHz, Load Step = 500 mA
Figure 38. Power-Good Shutdown,
V
V
IN = 24 V, VOUT = 5 V, fSW = 700 kHz
V
ENABLE
IN
V
V
f
= 24V
IN
= 5V
OUT
= 700kHz
SW
V
OUT
V
V
= 36V
IN
3
1
3
1
= 5V
OUT
f
SW
= 700kHz
V
OUT
SW
PGOOD
4
2
B
CH2 10.0V
B
B
CH1 2.00V
CH3 2.00V
M1.00ms
A CH3 1.64V
CH1 2.00V
CH3 10.0V
W
M4.00ms
A CH3 5.00V
W
W
CH4 2.00V
Figure 36. Power Good Startup,
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz
Figure 39. Startup with VIN
VIN = 36 V, VOUT = 5 V, fSW = 700 kHz, No Load
,
Rev. A | Page 12 of 32
Data Sheet
ADP2441
ENABLE
V
IN
V
V
f
= 36V
IN
= 5V
OUT
= 700kHz
LOAD = 5Ω
SW
3
1
V
V
f
= 24V
IN
V
OUT
= 5V
OUT
V
OUT
= 700kHz
SW
3
1
SS
SW
4
2
SW
2
B
B
CH2 10.0V
B
CH2 10.0V
CH4 2.00V
CH1 2.00V
CH3 10.0V
W
M4.00ms
A CH3 9.00V
CH1 2.00V
CH3 5.00V
M1.00ms
A CH3 1.40V
W
W
Figure 40. Startup with VIN
IN = 36 V, VOUT = 5 V, fSW = 700 kHz, Load = 5 Ω
,
Figure 43. Soft Start Startup with Precision Enable,
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, No Load, Internal SS
V
110
90
200
160
120
80
ENABLE
70
3
V
OUT
V
V
f
= 24V
IN
50
= 5V
OUT
= 700kHz
LOAD = 5Ω
SW
30
40
SS
10
0
SW
1
4
–10
–30
–50
–70
–90
–40
–80
–120
–160
–200
CROSSOVER = 58kHz: 1/12fSW
PHASE MARGIN = 55°
V
V
f
= 24V
IN
= 5V
OUT
= 700kHz
LOAD = 1A
SW
2
B
CH2 10.0V
CH4 2.00V
CH1 2.00V
CH3 5.00V
M200µs
A CH3 2.20V
W
1
10
FREQUENCY (kHz)
100
Figure 44. Magnitude and Phase vs. Frequency
Figure 41. Shutdown with Precision Enable,
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load = 5 Ω
ENABLE
3
V
OUT
V
V
f
= 24V
IN
= 5V
OUT
1
4
SS
= 700kHz
LOAD = 5Ω
SW
SS = 10nF
SW
2
B
CH2 10.0V
CH1 2.00V
CH3 5.00V
M2.00ms
A CH3 2.20V
W
CH4 500mV
Figure 42. Startup with Precision Enable,
VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load = 5 Ω, SS = 10 nF
Rev. A | Page 13 of 32
ADP2441
Data Sheet
INTERNAL BLOCK DIAGRAM
AGND
VIN
VCC
INTERNAL LDO
BST
EN
UVLO
+
1.25V
BAND GAP
REFERENCE
OSC
FREQ
COMP
ENABLE
CLOCK
POWER STAGE
I
SS
+
PULSE SKIP
ENABLE
NMOS
FB
–
+
STATE MACHINE GATE
CONTROL LOGIC
COMP
THRESHOLD
SS/TRK
1V
SW
+
V
CC
+
PWM
V
= 0.6V
REF
NMOS
–
PWM
COMPARATOR
PGND
HICCUP
HICCUP
TIMER
–
+
SLOPE
COMPENSATION/
RAMP
GENERATOR
CURRENT SENSE
AMPLIFIER
PGOOD
115% OF
FEEDBACK
CURRENT-LIMIT
COMPARATOR
REFERENCE
CURRENT
V
FB
86%OF
FEEDBACK
Figure 45. Block Diagram
Rev. A | Page 14 of 32
Data Sheet
ADP2441
THEORY OF OPERATION
V
IN
The ADP2441 is a fixed frequency, current mode control, step-
down, synchronous switching regulator that is capable of
driving 1 A loads. The device operates with a wide input voltage
range from 4.5 V to 36 V, and its output is adjustable from 0.6 V
to 0.9 V × VIN. The integrated high-side N-channel power
MOSFET and the low-side N-channel power MOSFET yield
high efficiency with medium to heavy loads. Pulse skip mode is
available to improve efficiency at light loads.
CLOCK
VC
S
R
Q
V
OUT
COMP
PWM DRIVER
QB
I
L
COMPARATOR
R
× I
L
SWL
REF
RAMP
EMULATION
BLOCK
V
RAMP
gm
V
FB
SENSE_
OUT
G
The ADP2441 includes programmable features, such as soft
start, output voltage, switching frequency, and power good.
These features are programmed externally via tiny resistors and
capacitors. The ADP2441 also includes protection features, such
as UVLO with hysteresis, output short-circuit protection, and
thermal shutdown.
CS
Figure 46. Control Architecture Block Diagram
Pulse Skip Mode
The ADP2441 has built-in pulse skip circuitry that turns on
during light loads, switching only as necessary so that the
output voltage remains within regulation. This allows the
regulator to maintain high efficiency during operation with
light loads by reducing switching losses. The pulse skip circuitry
includes a comparator, which compares the COMP voltage to a
fixed pulse skip threshold.
CONTROL ARCHITECURE
The ADP2441 is based on the emulated peak current mode
control architecture.
Fixed Frequency Mode
A basic block diagram of the control architecture is shown in
Figure 46. With medium to heavy loads, the ADP2441 operates
in the fixed switching frequency PWM mode. The output
voltage, VOUT, is sensed on the feedback pin, FB. An error
amplifier integrates the error between the feedback voltage and
the reference voltage (VREF = 0.6 V) to generate an error voltage
at the COMP pin. A current sense amplifier senses the valley
inductor current (IL) during the off period when the low-side
power MOSFET is on and the high-side power MOSFET is off.
An internal oscillator initiates a PWM pulse to turn off the low-
side power MOSFET and turn on the high-side power MOSFET
at a fixed switching frequency. When the high-side N-channel
power MOSFET is enabled, the valley inductor current
information is added to an emulated ramp signal, and then the
PWM comparator compares this value to the error voltage on
the COMP pin. The output of the PWM comparator modulates
the duty cycle by adjusting the trailing edge of the PWM pulse
that turns off the high-side power MOSFET and turns on the
low-side power MOSFET.
COMP
CONTROL
LOGIC
PULSE SKIP
THRESHOLD
ADP2441
DC
1V
Figure 47. Pulse Skip Comparator
With light loads, the output voltage discharges at a very slow
rate (load dependent). When the output voltage is within
regulation, the device enters sleep mode and draws a very small
quiescent current. As the output voltage drops below the
regulation voltage, the COMP voltage rises above the pulse skip
threshold. The device wakes up and starts switching until the
output voltage is within regulation.
As the load increases, the settling value of the COMP voltage
increases. At a particular load, COMP settles above the pulse skip
threshold, and the part enters the fixed frequency PWM mode.
Therefore, the load current at which COMP exceeds the pulse
skip threshold is defined as the pulse skip current threshold; the
value varies with the duty cycle and the inductor ripple current.
Slope compensation is programmed internally into the
emulated ramp signal and is automatically selected, depending
on the input voltage, output voltage, and switching frequency.
This prevents subharmonic oscillations for near or greater than
50% duty cycle operation. The one restriction of this feature is
that the inductor ripple current must be set between 0.2 A and
0.5 A to provide sufficient current information to the loop.
The measured value of pulse skip threshold over VIN is given in
Figure 13, Figure 14, and Figure 15.
Rev. A | Page 15 of 32
ADP2441
Data Sheet
establishing a voltage ramp slope at the SS pin, as shown in
ADJUSTABLE FREQUENCY
Figure 49. The soft start period ends when the soft start ramp
voltage exceeds the internal reference of 0.6 V. The ADP2441
also features an internal default soft start time of 2 ms. For more
information, see the Applications Information section.
The ADP2441 features a programmable oscillator frequency with
a resistor connected between the FREQ and AGND pins.
At power-up, the FREQ pin is forced to 1.2 V and current flows
from the FREQ pin to AGND; the current value is based on the
resistor value on the FREQ pin. Then, the same current is
replicated in the oscillator to set the switching frequency. Note
that the resistor connected to the FREQ pin should be placed as
close as possible to the FREQ pin (see the Applications
Information section for more information).
ENABLE
3
V
OUT
POWER GOOD
SS
V
V
f
= 24V
1
2
IN
The PGOOD pin is an open-drain output that indicates the
status of the output voltage. When the voltage of the FB pin is
between 92% and 109% of the internal reference voltage, the
PGOOD output is pulled high, provided there is a pull-up
resistor connected to the pin. When the voltage of the FB pin is
not within this range, the PGOOD output is pulled low to
AGND. The PGOOD threshold is shown in Figure 48.
= 5V
OUT
= 700kHz
LOAD = 1A
SW
EXTERNAL SS = 10nF
B
CH2 1.00V
CH1 2.00V
CH3 5.00V
M10.0ms
A CH1 2.52V
W
Figure 49. External Soft Start
Likewise, the PGOOD pin is pulled low to AGND when the
input voltage is below the internal UVLO threshold, when the
EN pin is low, or when a thermal shutdown event has occurred.
TRACKING
The ADP2441 has a tracking feature that allows the output
voltage to track an external voltage. This feature is especially
useful in a system where power supply sequencing and tracking
is required.
V
FALLING
V
RISING
OUT
OUT
116
110
100
The ADP2441 SS/TRK pin is connected to the internal error
amplifier. The internal error amplifier includes three inputs: the
internal reference voltage, the SS/TRK voltage, and the feedback
voltage. The error amplifier regulates the feedback voltage to
the lower of the other two voltages. To track a master voltage,
tie the SS/TRK pin to a resistor divider from the master voltage
as shown in Figure 50.
100
90
84
UNDERVOLTAGE
POWER
GOOD
OVERVOLAGE POWER
GOOD
UNDERVOLTAGE
PGOOD
V
OUT
COMP
SW
MASTER
VOLTAGE
Figure 48. PGOOD Threshold
In a typical application, a pull-up resistor connected between the
PGOOD pin and an external supply is used to generate a logic
signal. This pull-up resistor should range in value from 30 kΩ
to 100 kΩ, and the external supply should be less than 5.5 V.
R
R
R
TOP
TRK_TOP
SS/TRK
FB
R
TRK_BOT
BOTTOM
ADP2441
Figure 50. Tracking Feature Block Diagram
SOFT START
The ratio of the slave output voltage to the master voltage is a
function of the two dividers as follows:
The ADP2441 soft start feature allows the output voltage to ramp
up in a controlled manner, limiting the inrush current during
startup. An external capacitor connected between the SS/TRK
and AGND pins is required to program the soft start time.
RTOP
RBOTTOM
1
1
VOUT
VMASTER
(1)
The programmable soft start feature is useful when a load
requires a controlled voltage slew rate at startup. When the
regulator powers up and soft start is enabled, the internal
1 μA current source charges the external soft start capacitor,
RTRK _TOP
RTRK _ BOT
Rev. A | Page 16 of 32
Data Sheet
ADP2441
Coincident Tracking
itself to using a resistor divider from the VIN pin (or another
external supply) to program a desired UVLO threshold that is
higher than the fixed internal UVLO of 4.2 V. The hysteresis is
100 mV.
The most common mode of tracking is coincident tracking. In this
method, the slope of the slave voltage matches that of the master
voltage, as shown in Figure 51. As the master voltage rises, the
slave voltage rises identically. Eventually, the slave voltage reaches
its regulation voltage, at which point the internal reference takes
over the regulation while the SS/TRK input continues to increase,
thus preventing itself from influencing the output voltage.
If a resistor divider is not used, a logic signal can be applied. A
logic high enables the part, and a logic low forces the part into
shutdown mode.
V
VIN
BST
IN
MASTER VOLTAGE
SLAVE VOLTAGE
V
OUT
SW
FB
ADP2441
R1
R2
EN
FREQ AGND COMP
TIME
Figure 51. Coincident Tracking
Figure 53. Precision Enable Used as a Programmable UVLO
For coincident tracking, select resistor values such that RTRK_TOP
= RTOP and RTRK_BOT = RBOTTOM in Equation 1.
CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
Ratiometric Tracking
The ADP2441 has a current-limit comparator that compares
the current sensed across the low-side power MOSFET to the
internally set reference current. If the sensed current exceeds
the reference current, the high-side power MOSFET is not
turned on in the next cycle and the low-side power MOSFET
stays on until the inductor current ramps down below the
current-limit level.
In the ratiometric tracking scheme, the master and the slave
voltages rise with different slopes.
MASTER VOLTAGE
SLAVE VOLTAGE
If the output is overloaded and the peak inductor current exceeds
the preset current limit for more than eight consecutive clock
cycles, the hiccup mode current-limit condition occurs. The
output goes to sleep for 6 ms, during which time the output is
discharged, the average power dissipation is reduced, and the
part wakes up with a soft start period. If the current-limit condition
is triggered again, the output goes to sleep and wakes up after 6 ms.
Figure 32 shows the current-limit hiccup mode when the output
is shorted to PGND.
TIME
Figure 52. Ratiometric Tracking
For ratiometric tracking in which the master voltage rises faster
than the slave voltage (as shown in Figure 52), select RTRK_TOP
RTOP and RTRK_BOT = RBOTTOM in Equation 1.
≥
UNDERVOLTAGE LOCKOUT (UVLO)
THERMAL SHUTDOWN
The UVLO function prevents the IC from turning on while the
input voltage is below the specified operating range to avoid an
undesired operating mode. If the input voltage drops below the
specified range, the UVLO function shuts off the device. The
rising input voltage threshold for the UVLO function is 4.2 V
with 200 mV hysteresis. The 200 mV of hysteresis prevents the
regulator from turning on and off repeatedly with slow voltage
ramp on the VIN pin.
If the ADP2441 junction temperature rises above 150°C, the
thermal shutdown circuit turns off the switching regulator. Extreme
junction temperatures can be the result of high current operation,
poor circuit board design, or high ambient temperature. A 25°C
hysteresis is included so that when a thermal shutdown occurs,
the ADP2441 does not return to normal operation until the
junction temperature drops below 125°C. Soft start is active
upon each restart cycle.
PRECISION ENABLE/SHUTDOWN
The ADP2441 features a precision enable pin (EN) that can be used
to enable or shut down the device. The 5% accuracy lends
Rev. A | Page 17 of 32
ADP2441
Data Sheet
APPLICATIONS INFORMATION
due to the requirement of minimum on time and minimum off
time for current sensing and robust operation. However, the
choice is also influenced by whether there is a need for small
external components. For example, for small, area limited
power solutions, higher switching frequencies are required.
100
SELECTING THE OUTPUT VOLTAGE
The output voltage is set using a resistor divider connected between
the output voltage and the FB pin (see Figure 54). The resistor
divider divides down the output voltage to the 0.6 V FB regulation
voltage. The output voltage can be set to as low as 0.6 V and as
high as 90% of the power input voltage.
90
D
MAX
The ratio of the resistive voltage divider sets the output voltage,
and the absolute value of the resistors sets the divider string
current. For lower divider string currents, the small 50 nA
(0.1 μA maximum) FB bias current should be taken into
account when calculating the resistor values. The FB bias
current can be ignored for a higher divider string current;
however, using small feedback resistors degrades efficiency at
very light loads.
80
70
60
50
40
30
20
10
0
To limit degradation of the output voltage accuracy due to FB
bias current to less than 0.005% (0.5% maximum), ensure that
the divider string current is greater than 20 μA. To calculate the
desired resistor values, first determine the value of the bottom
resistor, RBOTTOM, as follows:
D
MIN
0
200
400
600
800
1000
1200
FREQUENCY (kHz)
Figure 55. Duty Cycle vs. Switching Frequency
VREF
ISTRING
Calculate the value of the frequency resistor using the following
equation:
RBOTTOM
(2)
(3)
where:
92,500
fSW
RFREQ
(4)
VREF is the internal reference and equals 0.6 V.
ISTRING is the resistor divider string current.
where RFREQ is in kΩ, and fSW is in kHz.
Then calculate the value of the top resistor, RTOP, as follows:
Table 6 and Figure 56 provide examples of frequency resistor
values, which are based on the switching frequency.
VOUT VREF
RTOP RBOTTOM
VREF
Table 6. Frequency Resistor Selection
V
OUT
RFREQ (kΩ)
Frequency
300 kHz
700 kHz
1 MHz
ADP2441
308
132
92.5
R
TOP
FB
R
BOTTOM
PGOOD
R
FREQ SS/TRK
1200
1100
1000
900
800
700
600
500
400
300
200
C
FREQ
SS
EXTERNAL
SUPPLY
Figure 54. Voltage Divider
Table 5. Output Voltage Selection
Voltage (V)
RTOP (kΩ)
190
73
RBOTTOM (kΩ)
12
5
3.3
1.2
10
10
10
10
45
10
50
100
150
200
250
300
350
SETTING THE SWITCHING FREQUENCY
RESISTANCE (kΩ)
The choice of the switching frequency depends on the required
dc-to-dc conversion ratio and is limited by the minimum and
maximum controllable duty cycle, as shown in Figure 55. This is
Figure 56. Frequency vs. Resistance
Rev. A | Page 18 of 32
Data Sheet
ADP2441
due to their poor temperature and dc bias characteristics. Table 10
shows a list of recommended MLCC capacitors from Murata
and Taiyo Yuden.
SOFT START
The soft start function limits the input inrush current and
prevents output overshoot at startup. The soft start time is
programmed by connecting a small ceramic capacitor between
the SS/TRK and AGND pins, with the value of this capacitor
defining the soft start time, tSS, as follows:
For large step load transients, add more bulk capacitance by, for
example, using electrolytic or polymer capacitors. Make sure
that the ripple current rating of the bulk capacitor exceeds the
minimum input ripple current of a particular design.
VREF
tSS
ISS
CSS
(5)
Inductor Selection
The high switching frequency of the ADP2441 allows for
minimal output voltage ripple even when small inductors are used.
Selecting the size of the inductor involves considering the trade-off
between efficiency and transient response. A smaller inductor
results in larger inductor current ripple, which provides excellent
transient response but degrades efficiency. Due to the high
switching frequency of the ADP2441, using shielded ferrite core
inductors is recommended because of their low core losses and
low EMI.
where:
REF is the internal reference voltage and equals 0.6 V.
ISS is the soft start current and equals 1 μA.
CSS is the soft start capacitor value.
V
Table 7. Soft Start Time Selection
Soft Start Capacitor (nF)
Soft Start Time (ms)
5
3
10
20
6
12
The inductor ripple current also affects the stability of the loop
because the ADP2441 uses the emulated peak current mode
architecture. In the traditional approach of slope compensation,
the user sets the inductor ripple current and then sets the slope
compensation using an external ramp resistor. In most cases, the
inductor ripple current is typically set to be 1/3 of the maximum
load current for optimal transient response and efficiency. The
ADP2441 has internal slope compensation, which assumes that
the inductor ripple current is set to 0.3 A (30% of the maximum
load of 1 A), eliminating the need for an external ramp resistor.
Alternatively, the user can float the SS/TRK pin and use the
internal soft start time of 2 ms.
EXTERNAL COMPONENTS SELECTION
Input Capacitor Selection
The input current to a buck regulator is pulsating in nature. The
current is zero when the high-side switch is off and is approxi-
mately equal to the load current when the switch is on. Because
switching occurs at reasonably high frequencies (300 kHz to
1 MHz), the input bypass capacitor usually supplies most of
the high frequency current (ripple current), allowing the input
power source to supply only the average (dc) current. The input
capacitor needs a sufficient ripple current rating to handle the
input ripple and needs an ESR that is low enough to mitigate the
input voltage ripple. In many cases, different types of capacitors
are placed in parallel to minimize the effective ESR and ESL.
For the ADP2441, choose an inductor such that the peak-to-
peak ripple current of the inductor is between 0.2 A and 0.5 A
for stable operation.
Therefore, calculate the inductor value as follows:
VOUT (VIN VOUT
VIN fSW L
)
IL
(8)
(9)
0.2 A ≤ ΔIL ≤ 0.5 A
The minimum input capacitance required for a particular load is
2VOUT (VIN VOUT
VIN fSW
)
5VOUT (VIN VOUT
VIN fSW
)
L
I
OUT D (1 D)
CIN _ MIN
(6)
(VPP IOUT D RESR ) fSW
3.3VOUT (VIN VOUT
)
L
IDEAL
where:
VPP is the desired input ripple voltage.
ESR is the equivalent series resistance of the capacitor.
OUT is the maximum load current.
VIN fSW
where:
R
I
VIN is the input voltage.
OUT is the desired output voltage.
SW is the regulator switching frequency.
V
f
It is recommended to use a ceramic bypass capacitor because
the ESR associated with this type of capacitor is near zero,
simplifying the equation to
For applications with a wide input (VIN) range, choose the
inductor based on the geometric mean of the input voltage
extremes.
I
OUT D (1 D)
CIN _ MIN
(7)
V
PP fSW
VIN(GEOMETRIC) VIN _ MAX VIN _ MIN
In addition, it is recommended to use a ceramic capacitor with a
voltage rating that is 1.5 times the input voltage with X5R and X7R
dielectrics. Using Y5V and Z5U dielectrics is not recommended
where:
V
IN_MAX is the maximum input voltage.
V
IN_MIN is the minimum input voltage.
Rev. A | Page 19 of 32
ADP2441
Data Sheet
The inductor value is based on VIN(GEOMETRIC) as follows:
Output Capacitor Selection
3.3VOUT (VIN(GEOMETRIC) VOUT
VIN(GEOMETRIC) fSW
)
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the regulator. The ADP2441 is
designed to operate with small ceramic output capacitors that
have low ESR and ESL; therefore, the device can easily meet
tight output voltage ripple specifications. For best performance,
use X5R or X7R dielectric capacitors with a voltage rating that is
1.5 times the output voltage and avoid using Y5V and Z5U
dielectric capacitors, which have poor temperature and dc bias
characteristics. Table 10 lists some recommended capacitor
from Murata and Taiyo Yuden.
LIDEAL
Table 8. Inductor Values for Various VIN, VOUT, and fSW
Combinations
Inductor Value
fSW (kHz)
300
VIN (V)
12
12
24
24
24
36
36
36
12
12
24
24
24
36
36
12
24
24
36
VOUT (V)
3.3
5
3.3
5
12
3.3
5
12
3.3
5
3.3
5
12
3.3
5
Min (μH)
22
27
27
39
56
27
39
68
12
15
15
18
27
15
22
6.8
10
Max (μH)
27
33
33
47
68
33
47
82
15
18
18
22
33
18
27
10
300
300
300
300
300
300
300
600
600
600
600
600
600
600
1000
1000
1000
1000
For acceptable maximum output voltage ripple, determine the
minimum output capacitance, COUT(MIN), as follows:
1
VRIPPLE IL ESR
(11)
8 fSW COUT(MIN)
Therefore,
COUT(MIN)
where:
IL
(12)
8 fSW (VRIPPLE IL ESR)
ΔVRIPPLE is the allowable peak-to-peak output voltage ripple.
ΔIL is the inductor ripple current.
ESR is the equivalent series resistance of the capacitor.
fSW is the switching frequency of the regulator.
5
5
12
5
12
22
15
18
12
If there is a step load requirement, choose the output capacitor
value based on the value of the step load. For the maximum accep-
table output voltage droop/overshoot caused by the step load,
To avoid inductor saturation and ensure proper operation, choose
the inductor value so that neither the saturation current nor
the maximum temperature rated current ratings are exceeded.
Inductor manufacturers specify both of these ratings in data
sheets, or the rating can be calculated as follows:
3
COUT(MIN) IOUT(STEP)
(13)
fSW VDROOP
where:
ΔIOUT(STEP) is the load step.
SW is the switching frequency of the regulator.
IL
2
f
IL _ PEAK ILOAD(MAX)
(10)
ΔVDROOP is the maximum allowable output voltage droop/overshoot.
where:
LOAD(MAX) is the maximum dc load current.
ΔIL is the peak-to-peak inductor ripple current.
Select the largest output capacitance given by Equation 12 and
Equation 13. When choosing the type of ceramic capacitor for the
output filter of the regulator, select one with a nominal capacitance
that is 20% to 30% larger than the calculated value because the
effective capacitance degrades with dc voltage and temperature.
Figure 57 shows the capacitance loss due to the output voltage
dc bias for three X7R MLCC capacitors from Murata.
I
Table 9. Recommended Inductors
Small Size Inductors
Value (μH) (<10 mm × 10 mm)
Large Size Inductors
(>10 mm × 10 mm)
10
18
33
15
XAL4040-103ME
LPS6235-183ML
LPS6235-33ML
XAL4040-153ME
MSS1260
MSS1260
MSS1260
MSS1260
Rev. A | Page 20 of 32
Data Sheet
ADP2441
30.0
LOOP COMPENSATION
The ADP2441 uses peak current mode control architecture for
excellent load and line transient response. This control architecture
has two loops: an external voltage loop and an inner current loop.
24.6
19.2
13.8
8.40
The inner current loop senses the current in the low-side switch
and controls the duty cycle to maintain the average inductor
current. Slope compensation is added to the inner current loop
to ensure stable operation when the duty cycle is above 50%.
22µF/25V
10µF/25V
The external voltage loop senses the output voltage and adjusts
the duty cycle to regulate the output voltage to the desired
value. A transconductance amplifier with an external series RC
network connected to the COMP pin compensates the external
voltage loop.
3.00
0
5
10
15
20
25
DC BIAS VOLTAGE (V)
Figure 57. Capacitance vs. DC Bias Voltage
ADP2441
For example, to attain 20 μF of output capacitance with an output
voltage of 5 V while providing some margin for temperature
variation, use a 22 μF capacitor with a voltage rating of 25 V
and a 10 μF capacitor with a voltage rating of 25 V in parallel.
This configuration ensures that the output capacitance is
sufficient under all conditions and, therefore, that the device
exhibits stable behavior.
COMP
VFB
R
C
COMP
gm
0.6V
COMP
AGND
Table 10. Recommended Output Capacitors for ADP2441
Vendor
Figure 58. RC Compensation Network
Capacitor
10 μF/25 V
22 μF/25 V
47 μF/6.3 V
4.7 μF/50 V
Murata
Taiyo Yuden
LARGE SIGNAL ANALYSIS OF THE LOOP
COMPENSATION
GRM32DR71E106KA12L
GRM32ER71E226KE15L
GCM32ER70J476KE19L
GRM31CR71H475KA12L
TMK325B7106KN-TR
TMK325B7226MM-TR
JMK325B7476MM-TR
UMK325B7475MMT
The control loop can be broken down into the following three
sections:
VOUT to VCOMP
VCOMP to IL
IL to VOUT
BOOST CAPACITOR
The boost pin (BST) is used to power up the internal driver for the
high-side power MOSFET. In the ADP2441, the high-side power
MOSFET is an N-channel device to achieve high efficiency in
mid and high duty cycle applications. To power up the high-side
driver, a capacitor is required between the BST and SW pins.
The size of this boost capacitor is critical because it affects the
light load functionality and efficiency of the device. Therefore,
choose a boost ceramic capacitor with a value between 10 nF to
22 nF with a voltage rating of 50 V and place the capacitor as
close as possible to the IC. It is recommended to use a boost
capacitor within this range because a capacitor beyond 22 nF
can cause the LDO to reach the current-limit threshold.
V
IN
INDUCTOR
CURRENT
SENSE
PULSE-WIDTH
MODULATOR
I
L
V
OUT
C
OUT
R
LOAD
V
COMP
g
G
m
VCC CAPACITOR
V
= 0.6V
REF
ADP2441
The ADP2441 has an internal regulator to power up the internal
controller and the low-side driver. The VCC pin is the output of
the internal regulator. The internal regulator provides the pulse
current when the low-side driver turns on. Therefore, it is recom-
mended that a 1 ꢀF ceramic capacitor be placed between the VCC
and PGND pins as close as possible to the IC and that a 1 ꢀF
ceramic capacitor be placed between the VCC and AGND pins.
R
C
COMP
COMP
Figure 59. Large Signal Model
Rev. A | Page 21 of 32
ADP2441
Data Sheet
Correspondingly, there are three transfer functions:
At the crossover frequency, the gain of the open-loop transfer
function is unity.
V
V
COMP (s) VREF
OUT (s) VOUT
gm ZCOMP (s)
(14)
(15)
(16)
H(fCROSSOVER) = 1
(20)
This yields Equation 21 for the RC compensation network
impedance at the crossover frequency.
IL (s)
COMP (s)
GCS
V
2 fCROSSOVER COUT VOUT
Z
COMP ( fCROSSOVER)
(21)
(22)
V
IL (s)
OUT (s)
g
m GCS
VREF
ZFILT (s)
Placing s = fCROSSOVER in Equation 17,
where:
1 2 fCROSSOVER RCOMP CCOMP
Z
COMP ( fCROSSOVER)
gm is the transconductance of the error amplifier and equals
250 ꢀA/V.
2 fCROSSOVER CCOMP
GCS is the current sense gain and equals 2 A/V.
To ensure that there is sufficient phase margin at the crossover
frequency, place the compensator zero at 1/8 of the crossover
frequency, as shown in the following equation:
V
V
OUT is the output voltage of the regulator.
REF is the internal reference voltage and equals 0.6 V.
ZCOMP(s) is the impedance of the RC compensation network that
1
fCROSSOVER
fZERO
(23)
forms a pole at the origin and a zero as expressed in Equation 17.
2 RCOMP CCOMP
8
1 sRCOMP CCOMP
Z
COMP (s)
(17)
Solving Equation 21, Equation 22, and Equation 23 yields the
value for the resistor and capacitor in the RC compensation
network, as shown in Equation 24 and Equation 25.
sCCOMP
ZFILT(s) is the impedance of the output filter and is expressed as
RLOAD
1 sRLOAD COUT
2 fCROSSOVER
C
OUT VOUT
VREF
Z
FILT (s)
(18)
RCOMP 0.9
(24)
(25)
g
m GCS
where s is the angular frequency, which can be written as s = 2πf.
1
CCOMP
The overall loop gain, H(s), is obtained by multiplying the three
transfer functions previously mentioned as follows:
2 fZERO RCOMP
Using these equations allows calculating the compensations for
the voltage loop.
VREF
VOUT
H(s) gm GCS
ZCOMP (s) ZFILT (s)
(19)
When the switching frequency (fSW), output voltage (VOUT),
output inductor (L), and output capacitor (COUT) values are
selected, the unity crossover frequency can be set to 1/12 of the
switching frequency.
Rev. A | Page 22 of 32
Data Sheet
ADP2441
DESIGN EXAMPLE
Consider an application with the following specifications:
Soft Start Capacitor
For a given soft start time, the soft start capacitor can be calculated
using Equation 5,
VIN =24 V 10%
VOUT = 5 V 1%
Switching frequency = 700 kHz
Load = 800 mA typical
Maximum load current = 1 A
Soft start time = 6 ms
VREF
tSS
ISS
CSS
I
SS tSS
VREF
CSS
CSS
Overshoot ≤ 2% under all load transient conditions
1μA 6 ms
CONFIGURATION AND COMPONENTS SELECTION
Resistor Divider
10 nF
0.6 V
Inductor Selection
Select the inductor by using Equation 9.
The first step in selecting the external components is to
calculate the resistance of the resistor divider that sets the
output voltage.
3.3VOUT (VIN VOUT
VIN fSW
)
LIDEAL
Using Equation 2 and Equation 3,
VREF
ISTRING 60 μA
0.6
3.35 V(24 5) V
24 V700 kHz
RBOTTOM
10 kꢁ
L
IDEAL
18.66μH 18.3μH
VOUT VREF
In Equation 9, VIN = 24 V, VOUT = 5 V, ILOAD(MAX) = 1 A, and fSW
=
RTOP RBOTTOM
VREF
700 kHz, which results in L = 18.66 ꢀH. When L = 18 μH (the
closest standard value) in Equation 8, ΔIL = 0.314 A. Although
the maximum output current required is 1 A, the maximum
peak current is 1.6 A. Therefore, the inductor should be rated
for higher than 1.6 A current.
5 V 0.6 V
RTOP 10 kꢁ
73.3 kꢁ
0.6 V
Switching Frequency
Input Capacitor Selection
Choosing the switching frequency involves considering the
trade-off between efficiency and component size. Low
frequency improves the efficiency by reducing the gate losses
but requires a large inductor. The choice of high frequency is
limited by the minimum and maximum duty cycle.
The input filter consists of a small 0.1 ꢀF ceramic capacitor
placed as close as possible to the IC.
The minimum input capacitance required for a particular load is
I
OUT D (1 D)
CIN _ MIN
Table 11. Duty Cycle
VPP fSW
VIN
Duty Cycle
where:
VPP = 50 mV.
OUT = 1 A.
D = 0.23.
SW = 700 kHz.
Therefore,
24 V (Nominal)
26 V (10% Above Nominal)
22 V (10% Less than Nominal)
DNOMINAL = 20.8%
DMIN = 19%
DMAX = 23%
I
f
Based on the estimated duty cycle range, choose the switching
frequency according to the minimum and maximum duty cycle
limitations, as shown in Figure 55. For example, a 700 kHz,
frequency is well within the maximum and minimum duty
cycle limitations.
1 A 0.22(1 0.22)
0.05 V 700 kHz
CIN _ MIN
4.9 μF
Choosing an input capacitor of 10 ꢀF with a voltage rating of
50 V ensures sufficient capacitance over voltage and temperature.
Using Equation 4,
92,500
RFREQ
fSW
FREQ = 132 kΩ
R
Rev. A | Page 23 of 32
ADP2441
Data Sheet
Output Capacitor Selection
Selecting the crossover frequency to be 1/12 of the switching
frequency and placing the zero frequency at 1/8 of the crossover
frequency ensures that there is enough phase margin in the system.
Select the output capacitor by using Equation 12 and Equation 13:
IL
COUT(MIN)
Table 13. Calculated Parameter Value
8 fSW (VRIPPLE IL ESR)
Parameter
fCROSSOVER
fZERO
VREF
gm
Test Conditions/Comments
Value
Equation 12 is based on the output voltage ripple (ΔVRIPPLE),
which is 1% of the output voltage.
1/12 of fSW
1/8 of fCROSSOVER
Fixed reference
Transconductance of error
amplifier
58.3 kHz
7.3 kHz
0.6 V
3
COUT(MIN) IOUT(STEP)
250 μA/V
fSW VDROOP
Equation 13 calculates the capacitor selection based on the
transient load performance requirement of 2%. Perform these
calculations, and then use the equation that yields the larger
capacitor size to select a capacitor.
GCS
COUT
VOUT
Current sense gain
Output capacitor
Output voltage
2 A/V
22 μF
5 V
In this example, the values listed in Table 12 are substituted for
the variables in Equation 12 and Equation 13.
Based on the values listed in Table 13, calculate the compen-
sation value:
2 58.3 225
Table 12. Requirements
RCOMP 0.9
121 k
2502
0.6
Parameter
Test Conditions/Comments
Value
Ripple Current
Voltage Ripple
Voltage Droop Due
to Load Transient
Fixed at 0.3 A for the ADP2441 0.3 A
The closest standard resistor value is 118 kΩ. Therefore,
1% of VOUT
2% of VOUT
50 mV
100 mV
1
CCOMP
185 pF 180 pF
2 7.3118
ESR
fSW
5 mΩ
700 kHz
SYSTEM CONFIGURATION
Configure the system as follows:
1. Connect a capacitor of 1 ꢀF between the VCC and PGND
pins and another capacitor of 1 ꢀF between the VCC and
AGND pins. For best performance, use ceramic X5R or
X7R capacitors with a 25 V voltage rating.
2. Connect a ceramic capacitor of 10 nF with a 50 V voltage
rating between the BST and SW pins.
3. Connect a resistor between the FREQ and AGND pins as
close as possible to the IC.
4. If using the power-good feature, connect a pull-up resistor
of 50 kΩ to an external supply of 5 V.
The calculation based on the output voltage ripple (see
Equation 12) dictates that the minimum output capacitance is
0.3 A
COUT(MIN)
1.1μF
8700 kHz(50 mV 0.3 A5 mꢁ)
whereas the calculation based on the transient load (see
Equation 13) dictates that the minimum output capacitance is
3
COUT(MIN) 0.5
22 F
700 kHz0.1 V
5. Connect a capacitor of 10 nF between the SS and AGND pins.
If the tracking feature is needed, connect a resistor divider
between the TRK pin and another supply, as shown in
Figure 50.
To meet both requirements, use the value determined by the
latter equation. As shown in Figure 57, capacitance degrades
with dc bias; therefore, choose a capacitor that is 1.5 times the
calculated value.
See Figure 60 for a schematic of this design example and Table 14
for the calculated component values.
C
OUT = 1.5 × 22 ꢀF = 32 ꢀF
Compensation Selection
Calculate the compensation component values for the feedback
loop by using the following equations:
2 fCROSSOVER
C
OUT VOUT
VREF
RCOMP 0.9
g
m GCS
1
CCOMP
2 fZERO RCOMP
Rev. A | Page 24 of 32
Data Sheet
ADP2441
TYPICAL APPLICATION CIRCUITS
DESIGN EXAMPLE
VIN = 24 V 10%, VOUT = 5 V, fSW = 700 kHz.
C3
1µF/25V
V
24V
IN
C5
10nF/50V
C4
1µF/25V
C2
4.7µF/
50V
C1
4.7µF/
50V
FB
VIN
L1
V
OUT
R5
118kꢀ
18µH
R3
10kꢀ
5V, 1A
ADP2441
COMP
EN
SW
C10
180pF
C6
0.1µF
C7
22µF
C8
10µF
PGND
EXT
R2
73.3kꢀ
R7
50kꢀ
C11
10nF
PGOOD
TRK
R9
132kꢀ
Figure 60. ADP2441 Typical Application Circuit, VIN = 24 V 10%, VOUT = 5 V, fSW = 700 kHz
Table 14. Calculated Component Values for Figure 60
Qty.
Ref
C1, C2
C3, C4
C5, C11
C7
C8
L1
C6
C10
R9
Value
4.7 μF
1 μF
10 nF
22 μF
Description
Part Number
2
2
2
1
1
1
1
1
1
1
1
1
Capacitor ceramic, X7R, 50 V
Capacitor ceramic, 1 μF, 25 V, X7R, 10%, 0603
Capacitor ceramic, 10,000 pF, 50 V, 10%, X7R, 603 ECJ-1VB1H103K
Capacitor ceramic, 22 μF, 25 V, X7R, 1210
Capacitor ceramic, 10 μF, 25 V, X7R, 1210
Inductor, 18.3 μH
Capacitor ceramic, 0.1 μF, 50 V, X7R, 0805
Capacitor ceramic, 50 V
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
GRM31CR71H475KA12L
GRM188R71E105KA12D
GRM32ER71E226K
10 μF
GRM32DR71E106KA12L
CoilCraft MSS1260T-183NLB
ECJ-2FB1H104K
18.3 μH
0.1 μF
185 pF
132 kΩ
118 kΩ
74 kΩ
10 kΩ
50 kΩ
Vishay, Panasonic
R5
R2
R3
R7
1
Rev. A | Page 25 of 32
ADP2441
Data Sheet
OTHER TYPICAL CIRCUIT CONFIGURATIONS
VIN = 24 V 10%, VOUT = 12 V, fSW = 600 kHz.
C3
1µF/25V
V
IN
C4
1µF/25V
C5
10nF/50V
24V
C2
4.7µF/
50V
C1
4.7µF/
50V
FB
COMP
VIN
L1
33.3µH
V
OUT
R5
121kꢀ
R3
10kꢀ
12V, 1A
ADP2441
SW
C10
220pF
C6
0.1µF
C7
22µF/
25V
EN
PGND
EXT
R2
191kꢀ
F
SW
600kHz
R7
50kꢀ
C11
10nF
PGOOD
TRK
R9
154kꢀ
Figure 61. ADP2441 Typical Application Circuit, VIN = 24 V 10%, VOUT = 12 V, fSW = 600 kHz
Table 15. Calculated Component Values for Figure 61
Qty.
Ref
C1, C2
C3, C4
C5, C11
C7
L1
C6
C10
R9
R5
Value
4.7 μF
1 μF
10 nF
22 μF
33.3 μH
0.1 μF
220 pF
154 kΩ
121 kΩ
191 kΩ
10 kΩ
50 kΩ
Description
Part Number
2
2
2
1
1
1
1
1
1
1
1
1
Capacitor ceramic, X7R, 50 V
Capacitor ceramic, 1 μF, 25 V, X7R, 10%, 0603
Capacitor ceramic, 10000 pF, 50 V, 10%, X7R, 0603 ECJ-1VB1H103K
Capacitor ceramic, 22 μF, 25 V, X7R, 1210
Inductor, 33.3 μH
Capacitor ceramic, 0.1 μF, 50 V, X7R, 0805
Capacitor ceramic, 50 V
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
GRM31CR71H475KA12L
GRM188R71E105KA12D
GRM32ER71E226K
CoilCraft MSS1038-333ML
ECJ-2FB1H104K
Vishay, Panasonic
R2
R3
R7
Rev. A | Page 26 of 32
Data Sheet
ADP2441
VIN = 12 V 10%, VOUT = 5 V, fSW = 500 kHz.
C3
1µF/25V
V
IN
C4
1µF/25V
C5
10nF/50V
12V
C2
4.7µF/
50V
C1
4.7µF/
50V
FB
VIN
L1
V
OUT
R5
118kꢀ
18µH
R3
10kꢀ
5V, 1A
ADP2441
COMP
EN
SW
C10
270pF
C6
0.1µF
C7
22µF
C8
22µF
PGND
EXT
R2
73.3kꢀ
F
SW
500kHz
R7
50kꢀ
C11
10nF
PGOOD
TRK
R9
185kꢀ
Figure 62. ADP2441 Typical Application Circuit, VIN = 12 V 10%, VOUT = 5 V, fSW = 500 kHz
Table 16. Calculated Component Values for Figure 62
Qty.
Ref
C1, C2
C3, C4
C5, C11
C7
C8
L1
C6
C10
R9
Value
4.7 μF
1 μF
10 nF
22 μF
Description
Part Number
2
2
2
1
1
1
1
1
1
1
1
1
Capacitor ceramic, X7R, 50 V
GRM31CR71H475KA12L
GRM188R71E105KA12D
ECJ-1VB1H103K
Capacitor ceramic, 1 μF, 25 V, X7R, 10%, 0603
Capacitor ceramic, 10,000 pF, 50 V, 10%, X7R, 0603
Capacitor ceramic, 22 μF, 25 V, X7R, 1210
Capacitor ceramic, 22 μF, 25 V, X7R, 1210
Inductor, 18.3 μH
GRM32ER71E226K
22 μF
18.3 μH
0.1 μF
270 pF
185 kΩ
118 kΩ
74 kΩ
10 kΩ
50 kΩ
CoilCraft MSS1038-183ML
ECJ-2FB1H104K
Vishay, Panasonic
Capacitor ceramic, 0.1 μF, 50 V, X7R, 0805
Capacitor ceramic, 50 V
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
R5
R2
R3
R7
1
Rev. A | Page 27 of 32
ADP2441
Data Sheet
VIN = 36 V 10%, VOUT = 3.3 V, fSW = 300 kHz.
C3
1µF/25V
V
IN
C4
1µF/25V
C5
10nF/50V
36V
C2
4.7µF/
50V
C1
4.7µF/
50V
FB
VIN
L1
V
OUT
R5
91kꢀ
33.3µH
R3
10kꢀ
3.3V, 1A
ADP2441
COMP
EN
SW
C10
560pF
C6
0.1µF
C7
47µF
C8
47µF
PGND
EXT
R2
45kꢀ
F
SW
300kHz
R7
50kꢀ
C11
10nF
PGOOD
TRK
R9
300kꢀ
Figure 63. ADP2441 Typical Application Circuit, VIN = 36 V 10%, VOUT = 3.3 V, fSW = 300 kHz
Table 17. Calculated Component Values for Figure 63
Qty.
Ref
C1, C2
C3, C4
C5, C11
C7
C8
L1
C6
C10
R9
Value
4.7 μF
1 μF
Description
Part Number
2
2
2
1
1
1
1
1
1
1
1
1
Capacitor ceramic, X7R, 50 V
GRM31CR71H475KA12L
GRM188R71E105KA12D
ECJ-1VB1H103K
GRM32ER70J476KE20L
GRM32ER70J476KE20L
CoilCraft MSS1038T-333ML
ECJ-2FB1H104K
Capacitor ceramic, 1 μF, 25 V, X7R, 10%, 0603
Capacitor ceramic, 10,000 pF, 50 V, 10%, X7R, 0603
Capacitor ceramic, 47 μF, 6.3 V, X7R, 1210
Capacitor ceramic, 47 μF, 6.3 V, X7R, 1210
Inductor, 33.3 μH
10 nF
47 μF
47 μF
33.3 μH
0.1 μF
560 pF
300 kΩ
91 kΩ
45 kΩ
10 kΩ
50 kΩ
Capacitor ceramic, 0.1 μF, 50 V, X7R, 0805
Capacitor ceramic, 50 V
Vishay, Panasonic
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
Resistor, 1/10 W, 1%, 0603, SMD
R5
R2
R3
R7
1
Rev. A | Page 28 of 32
Data Sheet
ADP2441
POWER DISSIPATION AND THERMAL CONSIDERATIONS
Transition Losses
POWER DISSIPATION
The efficiency of a dc-to-dc regulator is
POUT
Transition losses occur because the N-channel MOSFET power
switch cannot turn on or off instantaneously. During a switch
node transition, the power switch provides all of the inductor
current, and the source-to-drain voltage of the power switch is
half the input, resulting in power loss. Transition losses increase
as the load current and input voltage increase, and these losses
occur twice for each switching cycle.
Efficiency
100%
(26)
PIN
where:
PIN is the input power.
OUT is the output power.
The power loss of a dc-to-dc regulator is
LOSS = PIN − POUT
There are four main sources of power loss in a dc-to-dc regulator:
P
The transition losses can be calculated as follows:
P
VIN
2
PTRANS
IOUT (tON tOFF ) fSW
(30)
where tON and tOFF are the rise time and fall time of the switch
node and are each approximately 10 ns for a 24 V input.
Inductor losses
Power switch conduction losses
Switching losses
THERMAL CONSIDERATIONS
Transition losses
The power dissipated by the regulator increases the die junction
temperature, TJ, above the ambient temperature, TA, as follows:
Inductor Losses
TJ = TA + TR
(31)
Inductor conduction losses are caused by the flow of current
through the inductor DCR (internal resistance).
where the temperature rise, TR, is proportional to the power
dissipation, PD, in the package.
The inductor power loss (excluding core loss) is
PL = IOUT2 × DCRL
The proportionality coefficient is defined as the thermal
resistance from the junction temperature of the die to the
ambient temperature as follows:
(27)
Power Switch Conduction Losses
Power switch conductive losses are due to the output current, IOUT
flowing through the N-channel MOSFET power switches that
have internal resistance, RDS(ON). The amount of power loss can
be approximated as follows:
,
TR = θJA + PD
(32)
where θJA is the junction-to-ambient thermal resistance and
equals 40°C/W for the JEDEC board (see Table 3).
2
When designing an application for a particular ambient tempera-
ture range, calculate the expected ADP2441 power dissipation (PD)
due to the conduction, switching, and transition losses using
Equation 28, Equation 29, and Equation 30, and then estimate
the temperature rise using Equation 31 and Equation 32. Improved
thermal performance can be achieved by implementing good
board layout. For example, on the ADP2441 evaluation board
(ADP2441-EVALZ), the measured θJA is <30°/W. Thermal perfor-
mance of the ADP2441 evaluation board is shown in the Figure 64
and Figure 65.
P
COND = [RDS(ON) –High Side × D + RDS(ON) – Low Side×(1 – D)] × IOUT (28)
Switching Losses
Switching losses are associated with the current drawn by the
driver to turn the power devices on and off at the switching
frequency. Each time a power device gate is turned on and off,
the driver transfers a charge (ꢂQ) from the input supply to the
gate and then from the gate to ground.
The amount of switching loss can by calculated as follows:
PSW = QG_TOTAL × VIN × fSW
where:
G_TOTAL is the total gate charge of both the high-side and low-
side devices and is approximately 28 nC.
SW is the switching frequency.
(29)
Q
f
Rev. A | Page 29 of 32
ADP2441
Data Sheet
EVALUATION BOARD THERMAL PERFORMANCE
55
145
125
105
85
T
= 25°C
A
50
45
40
35
30
25
65
45
25
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
IC POWER DISSIPIATION (W)
IC POWER DISSIPIATION (W)
Figure 64. Junction Temperature vs. Power Dissipation Based on
ADP2441-EVALZ
Figure 65. Maximum Ambient Temperature vs. Power Dissipation Based on
ADP2441-EVALZ
Rev. A | Page 30 of 32
Data Sheet
ADP2441
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential for obtaining optimum
performance. Poor circuit board layout degrades the output
voltage ripple; the load, line, and feedback regulation; and the
EMI and electromagnetic compatibility performance. For
optimum layout, refer to the following guidelines:
The placement and routing of the compensation components
are critical for optimum performance of ADP2441. Place
the compensation components as close as possible to the
COMP pin. Use 0402 sized compensation components to
allow closer placement, which in turn reduces parasitic noise.
Surround the compensation components with AGND to
prevent noise pickup.
The FREQ pin is sensitive to noise; therefore, the frequency
resistor should be located as close as possible to the FREQ pin
and should be routed with minimal trace length. The small
signal components should be grounded to the analog
ground path.
Use separate analog and power ground planes. Connect the
ground reference of sensitive analog circuitry, such as the
output voltage divider component and the compensation
and frequency resistor, to analog ground. In addition,
connect the ground references of power components, such
as input and output capacitors, to power ground. Connect
both ground planes to the exposed pad of the ADP2441.
Place one end of the input capacitor as close as possible to
the VIN pin, and connect the other end to the closest
power ground plane.
C3
C5
C4
V
OUT
Place a high frequency filter capacitor between the VIN
and PGND pins, as close as possible to the PGND pin.
VCC is the internal regulator output. Place a 1 ꢀF capacitor
between the VCC and AGND pins and another 1 ꢀF
capacitor between the VCC and PGND pins. Place the
capacitors as close as possible to the pins.
R2
V
IN
FB
VIN
SW
V
R3
OUT
COMP ADP2441
C6
C7
V
IN
EN
PGND
R5
Ensure that the high current loop traces are as short and wide
as possible. Make the high current path from CIN through
L, COUT, and the power ground plane back to CIN as short as
possible. To accomplish this, ensure that the input and output
capacitors share a common power ground plane. In addition,
make the high current path from the PGND pin through
L and COUT back to the power ground plane as short as
possible. To do this, ensure that the PGND pin is tied to
the PGND plane as close as possible to the input and output
capacitors (see Figure 66).
C10
R9
NOTES
1. THICK LINE INDICATES HIGH CURRENT TRACE.
Figure 66. High Current Trace
C
BST
Connect the ADP2441 exposed pad to a large copper plane
to maximize its power dissipation capability.
VCC
AGND
FB
C
V
IN
Place the feedback resistor divider network as close as possible
to the FB pin to prevent noise pickup. The length of the trace
connecting the top of the feedback resistor divider to the
output must be as short as possible while being kept away
from the high current traces and switch node to avoid noise
pickup. Place an analog ground plane on either side of the
FB trace to further reduce noise pickup.
IN
COMP
V
OUT
FREQ
PGND
C
OUT
Figure 67. PCB Top Layer Placement
Rev. A | Page 31 of 32
ADP2441
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
10
12
0.50
BSC
1
3
9
7
EXPOSED
PAD
1.70
1.60 SQ
1.50
0.20 MIN
6
4
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4.
Figure 68. 12-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-12-6)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model1
Output Voltage Temperature Range Package Description
Option
12-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-12-6
12-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-12-6
Evaluation Board Preset to 5 V
Branding
LK4
LK4
ADP2441ACPZ-R7 Adjustable
ADP2441ACPZ-R2 Adjustable
ADP2441-EVALZ
−40°C to +125°C
−40°C to +125°C
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10581-0-11/12(A)
Rev. A | Page 32 of 32
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