ADP2504ACPZ-4.2-R71 [ADI]
600 mA/1000 mA, 2.5 MHz Buck-Boost DC-to-DC Converter; 600毫安/ 1000毫安， 2.5 MHz降压 - 升压型DC - DC转换器
| 型号： | ADP2504ACPZ-4.2-R71 |
| 厂家： | 
ADI |
| 描述： | 600 mA/1000 mA, 2.5 MHz Buck-Boost DC-to-DC Converter |
| 文件： | 总16页 (文件大小：1663K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
600 mA/1000 mA, 2.5 MHz Buck-Boost
DC-to-DC Converter
Preliminary Technical Data
ADP2503/ADP2504
FEATURES
GENERAL DESCRIPTION
1 mm height profile
Compact PCB footprint
Seamless transition between modes
38 μA typical quiescent current
2.5 MHz operation enables 1 ꢀH inductor
Input voltage: 2.3 V to 5.5 V
The ADP2503/ADP2504 are high efficiency, low quiescent
current step-up/step-down dc-to-dc converters that can operate
at input voltages above, below, or equal to the regulated output
voltage. The power switches and synchronous rectifiers are
internal to minimize external part count. At high load currents,
the ADP2503/ADP2504 use a current-mode, fixed frequency
PWM control scheme for optimal stability and transient response.
Fixed output voltage: 2.8 V to 5.0 V
600 mA (ADP2503) and 1000 mA (ADP2504) output options
Boost converter configuration with load disconnect
Sync pin with three different modes:
Power save mode (PSM) for improved light load efficiency
Forced fixed frequency operation mode
Synchronization with external clock
Internal compensation
Soft start
Enable/shutdown logic input
Overtemperature protection
Short-circuit protection
To ensure the longest battery life in portable applications, the
ADP2503/ADP2504 have an optional power save mode that
reduces the switching frequency under light load conditions.
For wireless and other low noise applications where variable
frequency power save mode may cause interference, the logic
control input sync forces fixed frequency PWM operation
under all load conditions.
The ADP2503/ADP2504 can run from input voltages between
2.3 V and 5.5 V, allowing single lithium or lithium polymer cell,
multiple alkaline or NiMH cells, PCMCIA, USB, and other
standard power sources. The ADP2503/ADP2504 have fixed
output options ranging from 2.8 V to 5 V. Compensation is
internal to minimize the number of external components.
Undervoltage lockout protection
Small 10-lead 3 mm × 3 mm LFCSP/QFN package
APPLICATIONS
During logic-controlled shutdown, the input is disconnected
from the output and draws less than 1 μA from the input source.
Operating as a boost converter, the ADP2503/ADP2504 feature
a true load disconnect function that isolates the load from the
power source. Other key features include under voltage lockout
to prevent deep battery discharge and soft start to prevent input
current overshoot at startup.
Wireless handsets
Digital cameras/portable audio players
Miniature hard disk power supplies
USB powered devices
TYPICAL APPLICATION CIRCUIT
1.0µH
SW1
SW2
ADP2503
V
V
OUT
2.8V TO 5V
IN
2.3V TO 5.5V
PVIN
VOUT
VIN
FB
10µF
22µF
SYNC
EN
AGND PGND
ON
OFF
Figure 1. Application Circuit
Rev. PrB
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Fax: 781.461.3113
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©2008 Analog Devices, Inc. All rights reserved.
ADP2503/ADP2504
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Reverse Current Limit ............................................................... 10
Power save Mode........................................................................ 10
Soft Start ...................................................................................... 10
Enable........................................................................................... 11
Undervoltage Lockout ............................................................... 11
Thermal Shutdown .................................................................... 11
Short Circuit Protection ............................................................ 11
Applications Information.............................................................. 12
Inductor Selection...................................................................... 12
PCB Layout Guidelines.................................................................. 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Description .............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 10
REVISION HISTORY
8/08—Revision PrB
Rev. PrB | Page 2 of 16
Preliminary Technical Data
SPECIFICATIONS
ADP2503/ADP2504
VIN = 3.6 V, VOUT = 3.3 V, @ TA = TJ = −40°C to +125°C for minimum/maximum specifications and TA = +25°C for typical specifications,
unless otherwise noted.1
Table 1.
Parameters
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Voltage Range
Undervoltage Lockout Threshold VIN rising
Undervoltage Lockout Threshold VIN falling
OUTPUT CHARACTERISTICS
2.3
2.2
2.13
5.5
2.3
2.23
V
V
V
2.25
2.18
Output Voltage Range
2.8
5.0
V
Feedback Voltage
0.495
0.5
0.55
V
Feedback Impedance
Output Voltage Initial Accuracy
(PWM Mode, No Load)
450
kΩ
%
ADP2503/ADP2504 (PWM operation, no load)
−2
+2
Load and Line Regulation
VIN = 2.3 V to 3.6 V, ILOAD = 0mA to 500mA, forced PWM mode
VIN = 2.3 V to 5.5 V, ILOAD = 0mA to 500mA, forced PWM mode
0.5
0.6
%
%
CURRENT CHARACTERISTICS
Quiescent Current (VIN)
Shutdown Current
IOUT = 0 mA, V mode = EN = VIN = 3.6 V, device not switching
TA = TJ = −40°C to +85°C
38
0.2
50
1
μA
μA
SWITCH CHARACTERISTICS
N-Channel Switches (LFCSP)
P-Channel Switches (LFCSP)
P-Channel Leakage
VIN = 3.6 V
VIN = VOUT = 3.6 V
TJ = −40°C to +85°C
150
150
mΩ
mΩ
μA
1
Switch Current Limit
ADP2504
ADP2503
Reverse Current Limit
1.3
1.0
2.0
1.4
1.1
A
A
A
OSCILLATOR AND STARTUP
Oscillator Frequency
On Time PMOS1 (Buck Mode)
On Time NMOS2 (Boost Mode)
Sync Clock Frequency
VIN = 2.3 V to 5.5 V
Minimum duty cycle = 30%
Maximum duty cycle = 50% (×2)
2.2
130
2.5
2.8
MHz
ns
ns
MHz
ns
μs
200
2.8
2.2
160
Sync Clock Minimum Off Time
Soft Start Period
200
LOGIC LEVEL CHARACTERISTICS
EN, SYNC Input High Threshold
EN, SYNC Input Low Threshold
EN, SYNC Leakage Current
THERMAL CHARACTERISTICS
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1.2
−1
V
V
μA
0.4
+1
+0.1
150
25
°C
°C
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Rev. PrB | Page 3 of 16
ADP2503/ADP2504
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 1.
θJA is specified for device soldered JEDEC2S2P PCB. For a
typical printed circuit board of a handset, the total thermal
resistance is higher. For correct operation up to 85°C ambient
temperature the total thermal resistance must not exceed
100 K/W.
Parameter
Rating
PVIN, VIN, SW1, SW2, VOUT, SYNC, −0.3 V to +6 V
EN, FB
PGND to AGND
Operating Ambient Temperature
Operating Junction Temperature
Storage Temperature
Lead Temperature
−0.3 V to 0.3 V
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
Table 2.
Package Type
Unit
θJA
10-Lead LFCSP (QFN)
84
°C/W
Soldering (10 sec)
300°C
215°C
220°C
1000 V
500 V
100 V
Vapor Phase (60 sec)
Infrared (15 sec)
ESD CAUTION
ESD Human Body Model
ESD Charged Device Model
ESD Machine Model
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
Rev. PrB | Page 4 of 16
Preliminary Technical Data
ADP2503/ADP2504
PIN CONFIGURATION AND FUNCTION DESCRIPTION
VOUT 1
SW2 2
PGND 3
SW1 4
PVIN 5
10 FB
ADP2503/
ADP2504
9
8
7
6
AGND
VIN
TOP VIEW
SYNC
EN
(Not to scale)
*CONNECT PADDLETO GND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
VOUT
SW2
The output of the ADP2503/ADP2504. Connect the output capacitor between VOUT and PGND.
Power Switch 2 Connection. This is the internal connection to the input PMOS and NMOS switches.
Connect SW2 to the inductor with a short, wide track.
3
4
PGND
SW1
Power GND. Connect the input and output capacitors and PGND pin to a PGND plane.
Power Switch 1 Connection. This is the internal connection to the output PMOS and NMOS switches.
Connect SW1 to the inductor with a short, wide track.
5
6
7
PVIN
EN
Power Input. This the input to the buck-boost power switches. Place a 10 ꢀF capacitor between PVIN and
PGND as close as possible to the ADP2503/ADP2504.
Enable. Drive EN high to turn on the ADP2503/ADP2504. Bring EN low to put the part into shutdown
mode.
The SYNC pin permits the ADP2503/ADP2504 to operate in three different modes.
Normal operation: with SYNC driven low, the ADP2503/ADP2504 operates at 2.5 MHz PWM mode for
heavy and medium loads, and moves to power save mode (PSM) mode for light loads.
Forced PWM operation: with SYNC driven high, the ADP2503/ADP2504 operates at fixed 2.5 MHz PWM
mode for all load conditions.
SYNC
SYNC mode: to synchronize the ADP2503/ADP2504 switching to an external signal, drive this pin with a
clock between 2.2 MHz and 2.8 MHz. The SYNC signal must have on and off times greater than 160 ns.
8
9
10
EP
VIN
AGND
FB
Analog Power Supply. This is the supply for the ADP2503/ADP2504 internal circuitry.
Analog Ground.
Output Feedback. This is an input to the internal error amplifier.
Connect the paddle to PGND.
Paddle
Rev. PrB | Page 5 of 16
ADP2503/ADP2504
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
V
V
V
V
= 5.5V
= 4.2V
= 3.6V
= 2.3V
V
V
V
V
= 5.5V
= 4.2V
= 3.6V
= 2.3V
IN
IN
IN
IN
IN
IN
IN
IN
20
10
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
I
(A)
I
(A)
OUT
OUT
Figure 3. Efficiency vs. Output Current, PWM Mode (VOUT = 5.0 V)
Figure 6. Efficiency vs. Output Current, PSM and PWM Mode (VOUT = 3.3 V)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
V
V
V
V
= 5.5V
= 4.2V
= 3.6V
= 2.3V
V
V
V
V
= 5.5V
= 4.2V
= 3.6V
= 2.3V
IN
IN
IN
IN
IN
IN
IN
IN
20
10
20
10
0
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
I
(A)
I
(A)
OUT
OUT
Figure 4. Efficiency vs. Output Current, PSM and PWM Mode (VOUT = 5.0 V)
Figure 7. Efficiency vs. Output Current, PWM Mode (VOUT = 2.8 V)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
V
V
V
V
= 5.5V
= 4.2V
= 3.6V
= 2.3V
V
V
V
V
= 5.5V
= 4.2V
= 3.6V
= 2.3V
IN
IN
IN
IN
IN
IN
IN
IN
20
10
20
10
0
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
I
(A)
I
(A)
OUT
OUT
Figure 5. Efficiency vs. Output Current, PWM Mode (VOUT = 3.3 V)
Figure 8. Efficiency vs. Output Current, PSM and PWM Mode (VOUT = 2.8 V)
Rev. PrB | Page 6 of 16
Preliminary Technical Data
ADP2503/ADP2504
100
90
80
70
60
50
40
30
50
45
40
35
30
25
20
15
10
5
I
I
I
= 500mA
= 100mA
= 10mA
OUT
OUT
OUT
20
10
0
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
2.3
2.7
3.1
3.5
3.9
(V)
4.3
4.7
5.1
5.5
V
(V)
V
IN
IN
Figure 12. Quiescent Current vs. Input Voltage (VOUT = 3.3 V)
Figure 9. Efficiency vs. Input Voltage (VOUT = 3.3 V)
3.35
3.33
3.31
3.29
3.27
3.25
V
V
= 3.0V TO 3.6V
IN
= 5.0V
OUT
V
IN
SW1
SW2
4
2
3
V
OUT
1
B
B
B
CH1 50.0mV
CH2 1.00V
CH4 5.00V
M40.0µs
A CH2 3.40mV
W
W
W
0
0.1
0.2
0.3
0.4
0.5
(A)
0.6
0.7
0.8
0.9
1.0
B
T
18.20%
CH3 5.00V
W
I
OUT
Figure 13. Line Transient, PWM Mode (VIN = 3.0 V to 3.6 V, VOUT = 5.0 V)
Figure 10. Load Regulation (VIN = 3.6 V, VOUT = 3.3 V)
2.8
V
V
= 3.0V TO 3.6V
IN
= 3.3V
OUT
V
IN
2.7
2.6
2.5
2.4
2.3
2.2
–40°C
+25°C
SW1
SW2
4
2
3
+85°C
V
OUT
1
B
B
B
CH1 50.0mV
M40.0µs A CH2 3.40V
CH2 1.00V
CH4 5.00V
W
W
W
2.3
2.7
3.1
3.5
3.9
(V)
4.3
4.7
5.1
5.5
B
T
18.20%
CH3 5.00V
W
V
IN
Figure 11. Frequency vs. Input Voltage Over Temperature (VOUT = 3.3 V)
Figure 14. Line Transient, PWM Mode (VIN = 3.0 V to 3.6 V, VOUT = 3.3 V)
Rev. PrB | Page 7 of 16
ADP2503/ADP2504
Preliminary Technical Data
V
V
= 3.0V TO 3.6V
IN
SW1
= 2.8V
OUT
V
IN
SW1
SW2
4
4
I
OUT
2
3
2
1
V
V
= 3.6V
= 3.3V
V
IN
OUT
OUT
V
OUT
1
B
B
B
B
CH1 100mV
W
CH1 50.0mV
CH4 1.00V
CH4 5.00V
M40.0µs
A CH2 3.40mVꢀꢀ
CH2 500mA Ωꢀ M100µs
A
CH2
–115mA
W
W
W
B
B
T
18.20%ꢀꢀ
T
45.40%
CH3 5.00V
CH4 2.00V
W
W
Figure 15. Line Transient, PWM Mode (VIN = 3.0 V to 3.6 V, VOUT = 2.8 V)
Figure 18. Mode Change by Load Transients, Load Rise (VOUT = 3.3 V)
V
V
= 3.6V
= 3.3V
IN
OUT
SW1
V
OUT
1
I
OUT
4ꢀꢀ
2ꢀꢀ
I
OUT
SW1
SW2
2ꢀꢀ
4
3
V
V
= 3.6V
= 3.3V
IN
OUT
V
OUT
1
B
CH1 100mV
CH3 5.00V
CH2 250mA Ωꢀ M100µs
A CH2 60.0mA
W
B
W
CH1 100mV
CH2 500mA Ωꢀ M100µs
A
CH2
410mA
B
B
T
W
25.80%
CH4 5.00V
W
B
T
45.40%
CH4 2.00V
W
Figure 16. Load Transient (VIN = 3.6 V VOUT = 3.3 V, IOUT = 100 mA to 350 mA)
Figure 19. Mode Change by Load Transients, Load Fall (VOUT = 3.3 V)
V
V
= 3.6V
= 3.3V
V
V
= 4.0V
IN
OUT
IN
= 3.3V
OUT
SW2
SW1
V
OUT
1
2
3
4
I
OUT
SW1
SW2
I
SW
2
1
4
3
V
OUT
B
CH1 100mV
CH2 250mA Ωꢀ M100µs
A CH2 60.0mA
W
B
CH1 50.0mV
CH3 5.00V
CH2 250mA Ωꢀ M 400ns
A
CH3
2.40V
W
B
B
T
23.00%
CH3 5.00V
CH4 5.00V
W
W
B
B
T
50.00%
CH4 5.00V
W
W
Figure 17. Load Transient (VIN = 3.6 V VOUT = 3.3 V, IOUT = 10 mA to 300 mA)
Figure 20. Typical PWM Switching Waveform, Buck Operation (VOUT = 3.3 V)
Rev. PrB | Page 8 of 16
Preliminary Technical Data
ADP2503/ADP2504
V
V
= 3.0V
IN
= 3.3V
OUT
SW2
SW1
4
3
4
SW1
V
= 3.3V
OUT
V
OUT
1
2
I
I
SW
SW
2
1
EN
V
OUT
3
B
B
B
CH2 500mAΩꢀ
W
CH1 20.0mV
CH3 5.00V
CH2 250mA Ωꢀ M 400ns
A
CH4
2.40V
CH1 2.00V
CH3 5.00V
M 100µs
A CH3 2.40V
W
W
B
B
B
B
T
50.80%
T
9.400%
CH4 5.00V
CH4 5.00V
W
W
W
W
Figure 21. Typical PWM Switching Waveform, Boost Operation (VOUT = 3.3 V)
Figure 24. Startup into PWM Mode (VOUT = 3.3 V, IOUT = 300 mA)
V
V
= 3.0Vꢀꢀ
IN
= 3.3Vꢀꢀ
OUT
SW2
SW1
SW1
4
3
4
V
OUT
V
= 3.3V
OUT
1
2
I
I
SW
SW
2
1
EN
V
OUT
3
B
B
B
CH2 500mAΩꢀ
W
CH1 20.0mV
CH3 5.00V
CH2 250mA Ωꢀ M 400ns
A
CH4
2.40V
CH1 2.00V
CH3 5.00V
M 100µs
A CH3 2.40V
W
W
B
B
B
B
T
50.00%
T
9.400%
CH4 5.00V
CH4 5.00V
W
W
W
W
Figure 22. Typical PWM Switching Waveform, Buck-Boost Operation
(VOUT = 3.3 V)
Figure 25. Startup into PWM Mode (VOUT = 3.3 V, IOUT = 10 mA)
V
V
= 3.0Vꢀꢀ
= 3.3Vꢀꢀ
IN
OUT
SW1
SW2
SW1
4
3
V
= 3.3V
OUT
V
OUT
4ꢀꢀ
1ꢀꢀ
I
SW
2
I
SW
2
1
ENꢀꢀ
V
OUTꢀꢀ
3
B
B
B
CH2 500mAΩꢀ
W
CH1 100mV
CH3 5.00V
CH2 1.00A Ωꢀ
M 4.00µs
15.20%
A
CH2
820mA
CH1 2.00V
CH3 5.00V
M 100µs
A CH3 2.40V
W
W
B
B
B
B
T
T
9.400%
CH4 5.00V
CH4 5.00V
W
W
W
W
Figure 23. Typical PSM Switching Waveform, Buck-Boost Operation
(VOUT = 3.3 V)
Figure 26. Startup into PSM Mode (VOUT = 3.3 V, IOUT = 10 mA)
Rev. PrB | Page 9 of 16
ADP2503/ADP2504
Preliminary Technical Data
THEORY OF OPERATION
1.0µH
SW1
SW2
4
2
ADP2503/ADP2504
VIN
8
ADP2503/ADP2504
BIASING
VBAT = 2.3V
PMOS1
PMOS2
PVIN
VOUT
TO 5.5V
5
1
10µF
NMOS1
NMOS2
22µF
2.25V
SOFT START
UVLO
FB
10
BAND GAP
THERMAL
REFERENCE
PROTECTION
–0.5V
PWM CONTROL
EN
EN
CS
6
7
SYNC
PGND
OSCILLATOR
AGND
9
3
Figure 27. ADP2503/ADP2504 Block Diagram
The ADP2503/ADP2504 are synchronous average current-
mode switching buck-boost regulators designed to maintain a
fixed output voltage VOUT from an input supply VIN that can be
above, equal to, or below VOUT. When VIN is significantly greater
than VOUT, the device is in buck mode: PMOS2 is always active,
NMOS2 is always off and the switches PMOS1, NMOS1 consti-
POWER SAVE MODE
When the SYNC pin is low, the ADP2503/ADP2504 can operate
in power save mode (PSM). In this mode, when the load
current becomes lower than 75 mA nominally at VIN = 3.6 V,
the controller pulls up VOUT and then halts the switching regime
until VOUT goes back to a restart value. Then VOUT is pulled up
again for a new cycle. This minimizes the switching losses at
light load. When the load rises above 150 mA, the
ADP2503/ADP2504 revert back to fixed PWM mode. This
results in about 75 mA of hysteresis between PSM and fixed
PWM, preventing oscillations between these two modes.
tute a buck converter. When VIN is significantly lower than VOUT
the device is in boost mode: PMOS1 is always active, NMOS1 is
always off and the switches NMOS2, PMOS2 constitute a boost
converter. When VIN is in the range [VOUT − 10%; VOUT + 10%],
the ADP2503/ADP2504 automatically enter the buck-boost
mode. In buck-boost mode, the two operations buck (PMOS1
and NMOS1 switching in antiphase) and boost (NMOS2 and
PMOS2 switching in antiphase) take place at each period of the
clock. This is aimed at maintaining the regulation and keeping a
minimal current ripple in the inductor to guarantee good
transient performances.
,
SOFT START
When the ADP2503/ADP2504 are started, VOUT is ramped from
0 V to its final programmed value in 200 ꢀs (typ). This limits
the inrush current to less than 600 mA for a nominal output
capacitor of 20 ꢀF. Because the VOUT start-up slope is constant,
the inrush current becomes larger if the output capacitor is
made larger.
REVERSE CURRENT LIMIT
In case of a short circuit on VOUT to a value greater than
expected, the inductor current becomes negative (reverse
current). The negative peak value is limited to 1.1 A by
deactivating the switch PMOS2.
Rev. PrB | Page 10 of 16
Preliminary Technical Data
ADP2503/ADP2504
ENABLE
THERMAL SHUTDOWN
The device starts operation with soft start when the EN pin is
brought high. Pulling the EN pin low forces the device into
shutdown, with a typical shutdown current of 0.2 μA.
When the junction temperature, TJ, exceeds 150°C typical,
the device goes into thermal shutdown. In this mode, the power
switches are turned off. The device resumes operation when the
junction temperature again falls below 125°C typical.
In this mode, the PMOS power switches are turned off, the
NMOS power switches are turned on, and the control circuitry is
not enabled. For proper operation, the EN pin must be
terminated and must not be left floating.
SHORT CIRCUIT PROTECTION
When the nominal inductor peak current value of 1.5 A is
reached, the ADP2503/ADP2504 first switch off the NMOS2
transistor if it was active. If the current thereafter continues to
increase by an extra amount of 200 mA, the PMOS1 transistor
is also switched off. This operation is reversible when the short
circuit stops. It allows the inductor current ripple to be mini-
mized close to 1.5 A and, thus, the controller to restore VOUT
even if a high load current is maintained after the short circuit.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from oper-
ating incorrectly at low input voltages. It prevents the converter
from turning on the power switches under undefined conditions
and therefore, prevents deep discharge of the battery supply. VIN
must be greater than 2.25 V to enable the converter. During
operation, if VIN drops below 2.18 V, the ADP2503/ADP2504
are disabled until the supply exceeds the UVLO rising threshold.
Rev. PrB | Page 11 of 16
ADP2503/ADP2504
Preliminary Technical Data
APPLICATIONS INFORMATION
INDUCTOR SELECTION
Table 4. Sample of Recommended Inductors
Dimensions
L × W × H
(mm)
2.8 × 2.8 × 1.0
2.8 × 2.8 × 1.0
2.5 × 2 × 1.2
2.5 × 2 × 1
The high 2.5 MHz switching frequency of the ADP2503/
ADP2504 allows for minimal output voltage ripple, while
minimizing inductor size and cost. Careful inductor selection
also optimizes efficiency and reduces electromagnetic interfe-
rence (EMI). The selection of the inductor value determines the
inductor current ripple and loop dynamics.
Value
Vendor (ꢀH)
DCR
(mΩ) (A)
ISAT
Part No.
DE2810C
DE2810C
Toko
Toko
Toko
Murata
Murata
TDK
1.2
1.5
1
55
60
1.7
1.5
1.8
1.6
1.5
1.5
1.2
1.7
1.3
MDT2520-CN 100
1
LQM2HP-G0
LQM2HP-G0
CPL2512T
CPL2512T
LPS3010
55
70
90
120
85
VOUT ×ꢀ(VIN −ꢀVOUT
VIN ×ꢀfOSC ×ꢀL
)
1.5
1.0
1.5
2.5 × 2 × 1
ΔIL , peak (Buck) =ꢀ
2.5 × 1.5 × 1.2
2.5 × 1.5 × 1.2
3.0 × 3.0 × 0.9
3.0 × 3.0 × 0.9
TDK
(VOUT −ꢀVIN )
VIN
fOSC ×ꢀL
Coilcraft 1.0
Coilcraft 1.5
ΔIL , peak (Boost) =
×ꢀ
VOUT
LPS3010
120
where fOSC is the switching frequency (typically 2.5 MHz),
and L is the inductor value in henries.
Output Capacitor Selection
The output capacitor selection determines the output voltage
ripple, transient response and the loop dynamics of the
ADP2503/ADP2504. The output voltage ripple for a given
output capacitor is given by
A larger inductor value reduces the current ripple (and
therefore peak inductor current), but is physically larger in size
with increased dc resistance. Inductor values between 1 μH and
1.5 μH are usually suggested. The maximum inductor value to
ensure stability is 2.0 μH. For increased efficiency with the
ADP2504, it is suggested a 1.5 μH inductor be used.
VOUT ×ꢀ(VIN −ꢀVOUT
)
ΔVOUT, peak (Buck) =ꢀ
ΔVOUT, peak(Boost) =ꢀ
VIN ×ꢀ8 ×ꢀL × (ꢀfOSC
)
2 ×ꢀCOUT
The inductor peak current is at the maximum in boost mode.
To determine the actual maximum inductor current in boost
mode, the input dc current should be estimated.
I
LOAD×ꢀ(VOUT −ꢀVIN )
COUT ×VOUT ×ꢀfOSC
If the ADP2503/ADP2504 are operating in buck mode, the
worst-case voltage ripple occurs for the highest input voltage,
VIN. If the ADP2503/ADP2504 are operating in boost mode, the
worst-case voltage ripple occurs for the lowest input voltage, VIN.
⎛ꢀ
⎞ꢀ
VOUT
VIN
1
η
⎜ꢀ
⎜
⎟
IIN(MAX) =ꢀILOAD(MAX)
×
×ꢀꢀ
⎟
⎝ꢀ
⎠ꢀ
where η is efficiency (assume η ≈ 0.85 to 0.90).
The maximum voltage overshoot, or undershoot is inversely
proportional to the value of the output capacitor. To ensure
stability and excellent transient response, it is recommended to
use a minimum of 22 μF X5R 6.3 V or 2 × 10 μF X5R 6.3 V
capacitors at the output. The effective capacitance (includes
temperature, dc bias effects) needed for stability is 14 μF.
The saturation current rating of the inductor must be at least
IIN(MAX) + ΔILOAD/2.
Ceramic multilayer inductors can be used with lower current
designs for a reduced overall solution size and dc resistance (DCR).
These are available in low profile packages. Care must be taken as
these derate quickly as the inductor value is increased especially at
higher operating temperatures.
Ferrite core inductors have good core loss characteristics as well as
reasonable dc resistance. A shielded ferrite inductor reduces the
EMI generated by the inductor.
Table 5. Recommended Output Capacitors
Dimensions
L × W × H (mm)
Vendor
Murata
TDK
Murata
TDK
Value
Part No.
2 × 10 μF, 6.3 V
2 × 10 μF, 6.3 V
22 μF, 6.3 V
22 μF, 6.3 V
22 μF, 10 V
10 μF, 10 V
GRM188R60J106ME47
C1608JB0J106K
GRM21BR60J226ME39
C2012X5R0J226M
C3216X5R1A226K
GRM21BR71A106KE51L
1.6 × 0.8 × 0.8 (2)
1.6 × 0.8 × 0.8 (2)
2 × 1.25 × 1.25
2 × 1.25 × 1.25
2 × 1.25 × 1.25
2 × 1.25 × 1.25 (2)
TDK
Murata
Rev. PrB | Page 12 of 16
Preliminary Technical Data
ADP2503/ADP2504
Table 6. Recommended Input Capacitors
Input Capacitor Selection
Dimensions
L × W × H
(mm)
The ADP2503/ADP2504 require an input capacitor to filter
noise on the VIN pin, and provide the transient currents while
maintaining constant input and output voltage. A 10 μF X5R/
X7R ceramic capacitor rated for 6.3 V is the minimum recom-
mended input capacitor. Increased input capacitance reduces
the amplitude of the switching frequency ripple on the battery.
Because of the dc bias characteristics of ceramic capacitors, a
0603, 6.3 V X5R/X7R, 10 μF ceramic capacitor is preferable.
Vendor Value
Part No.
Murata 10 μF, 6.3 V GRM188R60J106ME47 1.6 × 0.8 × 0.8
TDK 10 μF, 6.3 V C1608JB0J106K 1.6 × 0.8 × 0.8
Rev. PrB | Page 13 of 16
ADP2503/ADP2504
Preliminary Technical Data
PCB LAYOUT GUIDELINES
Poor layout can affect ADP2503/ADP2504 performance,
causing electromagnetic interference (EMI) and electromagnetic
compatibility (EMC) performance, ground bounce, and voltage
losses. Poor layout can also affect regulation and stability. A
good layout is implemented using the following rules:
•ꢀꢀ Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
•ꢀꢀ Maximize the size of ground metal on the component side
to help with thermal dissipation.
•ꢀꢀ Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
•ꢀꢀ Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies and large tracks act like
antennas.
ADP2503/ADP2504 EVALUATION BOARD
10mm
L1
VIN
VOUT
J1
J3
C1
C2 C3
JP1
8mm
JP1
U1
C4
R3
PGND
J4
PGND
J2
TP2
TP1
R2
1
R1
1
J6
J5
EN
SYNC
Figure 28. ADP2503/ADP2504 Evaluation Board
Rev. PrB | Page 14 of 16
Preliminary Technical Data
OUTLINE DIMENSIONS
ADP2503/ADP2504
0.30
0.23
0.18
3.00
BSC SQ
0.50 BSC
10
6
5
PIN 1 INDEX
AREA
1.74
1.64
1.49
*
EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
1
PIN 1
INDICATOR
(R 0.20)
TOP VIEW
2.48
2.38
2.23
0.80 MAX
0.55 NOM
0.80
0.75
0.70
0.05 MAX
0.02 NOM
*
PADDLE CONNECTED TO GND.
SEATING
PLANE
0.20 REF
Figure 298. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Maximum Temperature
Voltage Current
Range
−40°C to +85°C
Package
Model
Package Description
Option
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
Branding
ADP2503ACPZ-2.8-R71
ADP2503ACPZ-3.3-R71
ADP2503ACPZ-3.5-R71
ADP2503ACPZ-4.2-R71
ADP2503ACPZ-4.5-R71
ADP2503ACPZ-5.0-R71
ADP2504ACPZ-2.8-R71
ADP2504ACPZ-3.3-R71
ADP2504ACPZ-3.5-R71
ADP2504ACPZ-4.2-R71
ADP2504ACPZ-4.5-R71
ADP2504ACPZ-5.0-R71
2.8 V
3.3 V
3.5 V
4.2 V
4.5 V
5.0 V
2.8 V
3.3 V
3.5 V
4.2 V
4.5 V
5.0 V
0.6 A
0.6 A
0.6 A
0.6 A
0.6 A
0.6 A
1 A
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
L9Y
L9Z
LAP
LA0
LA1
LA2
L9T
L85
LAN
L9U
L9V
L9W
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
1 A
1 A
1 A
1 A
1 A
1 Z = RoHS Compliant Part.
Rev. PrB | Page 15 of 16
ADP2503/ADP2504
NOTES
Preliminary Technical Data
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07475-0-8/08(PrB)
Rev. PrB | Page 16 of 16
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