ADP3188JRUZ-REEL [ADI]
6-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller; 6位可编程的双/三/四相位同步降压控制器
| 型号： | ADP3188JRUZ-REEL |
| 厂家： | 
ADI |
| 描述： | 6-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller |
| 文件： | 总28页 (文件大小：1190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6-Bit Programmable 2-/3-/4-Phase
Synchronous Buck Controller
ADP3188
FEATURES
Selectable 2-, 3- or 4-phase operation at up to
1 MHz per phase
±±9. ꢀV worst-case differential sensing error over
teꢀperature
FUNCTIONAL BLOCK DIAGRAM
VCC
RAMPADJ RT
28
14 13
ADP3188
UVLO
SHUTDOWN
AND BIAS
11
EN
OSCILLATOR
Logic-level PWM outputs for interface to external
high power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
6-bit digitally prograꢀꢀable 09837. V to 196 V output
SET
EN
GND 19
RESET
27 PWM1
CMP
CMP
CMP
CMP
DAC+150mV
CSREF
26
RESET
PWM2
2-/3-/4-PHASE
DRIVER LOGIC
CURRENT
BALANCING
CIRCUIT
RESET
25 PWM3
DAC-250mV
RESET
24
PWM4
Prograꢀꢀable short-circuit protection with
prograꢀꢀable latch-off delay
DELAY
10
PWRGD
ILIMIT
CROWBAR
CURRENT
LIMIT
SW1
SW2
SW3
SW4
23
22
21
20
APPLICATIONS
15
12
Desktop PC power supplies for
Next-generation Intel® processors
VRM ꢀodules
EN
CSSUM
17
CURRENT
LIMIT
CIRCUIT
DELAY
COMP
16
18
CSREF
GENERAL DESCRIPTION
SOFT
START
CSCOMP
The ADP3188 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. The part uses an internal 6-bit
DAC to read a voltage identification (VID) code directly from
the processor, which is used to set the output voltage between
0.8375 V and 1.6 V. It uses a multimode PWM architecture to
drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency.
The phase relationship of the output signals can be pro-
grammed to provide 2-, 3-, or 4-phase operation, allowing
the construction of up to four complementary buck
switching stages.
8
FB
9
PRECISION
REFERENCE
VID
DAC
7
1
2
3
4
5
6
FBRTN
VID4 VID3 VID2 VID1 VID0 VID5
Figure 1.
The ADP3188 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of
the load current, so it is always optimally positioned for a system
transient. The ADP3188 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a
delayed power good output that accommodates on-the-fly
output voltage changes requested by the CPU.
The ADP3188 is specified over the commercial tempera-
ture range of 0°C to 85°C and is available in 28-lead, TSSOP
and QSOP packages.
Rev9 A
Inforꢀation furnished by Analog Devices is believed to be accurate and reliable9
However, no responsibility is assuꢀed by Analog Devices for its use, nor for any
infringeꢀents of patents or other rights of third parties that ꢀay result froꢀ its use9
Specifications subject to change without notice9 No license is granted by iꢀplication
or otherwise under any patent or patent rights of Analog Devices9 Tradeꢀarks and
registered tradeꢀarks are the property of their respective owners9
One Technology Way, P9O9 Box ±106, Norwood, MA 02062-±106, U9S9A9
Tel: 781932±94700
Fax: 781946193113
www9analog9coꢀ
© 200. Analog Devices, Inc9 All rights reserved9
ADP3188
TABLE OF CONTENTS
Specifications..................................................................................... 3
Inductor Selection...................................................................... 15
Designing an Inductor............................................................... 16
Selecting a Standard Inductor .............................................. 16
Output Droop Resistance.......................................................... 16
Inductor DCR Temperature Correction ................................. 17
Output Offset.............................................................................. 17
COUT Selection ............................................................................. 18
Power MOSFETs......................................................................... 18
Ramp Resistor Selection............................................................ 20
COMP Pin Ramp ....................................................................... 20
Current-Limit Setpoint.............................................................. 20
Feedback Loop Compensation Design.................................... 20
CIN Selection and Input Current di/dt Reduction.................. 22
Tuning the ADP3188 ................................................................. 23
DC Loadline Setting .............................................................. 23
AC Loadline Setting............................................................... 24
Layout and Component Placement.............................................. 26
General Recommendations....................................................... 26
Power Circuitry Recommendations ........................................ 26
Signal Circuitry Recommendations......................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Test Circuits ....................................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function DescriptionS ............................ 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ........................................................................ 9
Start-Up Sequence........................................................................ 9
Master Clock Frequency.............................................................. 9
Output Voltage Differential Sensing.......................................... 9
Output Current Sensing .............................................................. 9
Active Impedance Control Mode............................................. 10
Current-Control Mode and Thermal Balance........................ 10
Voltage Control Mode................................................................ 10
Soft Start ...................................................................................... 10
Current-Limit, Short-Circuit, and Latch-Off Protection...... 11
Dynamic VID.............................................................................. 11
Power Good Monitoring ........................................................... 12
Output Crowbar ......................................................................... 13
Output Enable and UVLO ........................................................ 13
Application Information................................................................ 15
Setting the Clock Frequency..................................................... 15
Soft Start and Current-Limit Latch-Off Delay Times ........... 15
REVISION HISTORY
4/05—Rev. 0 to Rev. A
Changes to Figure 10.........................................................................14
Changes to Ordering Guide .............................................................27
4/04—Revision 0: Initial Version
Rev. A | Page 2 of 28
ADP3188
SPECIFICATIONS
VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1
Table 1.
Paraꢀeter
Syꢀbol
Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
Output Voltage Range2
Accuracy
VCOMP
VFB
0.7
−9.5
3.1
+9.5
V
mV
Relative to nominal DAC output,
referenced to FBRTN,
CSSUM = CSCOMP, Figure 2
Line Regulation
Input Bias Current
FBRTN Current
VCC = 10 V to 14 V
0.05
15.5
100
500
20
%
∆VFB
IFB
14
17
µA
µA
IFBRTN
IO(ERR)
GBW(ERR)
140
Output Current
Gain Bandwidth Product
Slew Rate
FB forced to VOUT – 3%
COMP = FB
CCOMP = 10 pF
µA
MHz
25
V/µs
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current, Input Voltage Low
Input Current, Input Voltage High
Pull-Up Resistance
VIL(VID)
VIH(VID)
IIL(VID)
IIH(VID)
RVID
0.4
V
V
0.8
VID(X) = 0 V
−25
5
−35
15
µA
µA
kΩ
V
ns
ns
VID(X) = 1.25 V
35
60
1.1
85
Internal Pull-Up Voltage
VID Transition Delay Time
No CPU Detection Turn-Off Delay
Time2
0.9
400
400
2
VID code change to FB change
VID code change to 11111 to PWM
going low
OSCILLATOR
2
Frequency Range
fOSC
fPHASE
0.25
155
4
245
MHz
kHz
kHz
kHz
V
Frequency Variation
200
400
600
2.0
TA = 25°C, RT = 250 kΩ, 4-phase
TA = 25°C, RT = 115 kΩ, 4-phase
TA = 25°C, RT = 75 kΩ, 4-phase
RT = 100 kΩ to GND
Output Voltage
VRT
1.9
−50
0
2.1
RAMPADJ Output Voltage
RAMPADJ Input Current Range
VRAMPADJ
IRAMPADJ
RAMPADJ – FB
+50
100
mV
µA
CURRENT-SENSE AMPLIFIER
Offset Voltage
VOS(CSA)
CSSUM – CSREF, Figure 3
TA = 25°C to 85°C, CSSUM – CSREF,
Figure 3
−1.75
−1.5
+1.75
+1.5
mV
mV
Input Bias Current
Gain Bandwidth Product
Slew Rate
IBIAS(CSSUM)
GBW(CSA)
−50
+50
nA
MHz
V/µs
V
mV
V
10
10
CCSCOMP = 10 pF
CSSUM and CSREF
Figure 4
Input Common-Mode Range
Positioning Accuracy
Output Voltage Range
Output Current
0
−77
0.05
2.7
−83
2.7
−80
500
∆VFB
ICSCOMP
µA
CURRENT-BALANCE CIRCUIT
Common-Mode Range
Input Resistance
VSW(X)CM
RSW(X)
ISW(X)
−600
20
+200
40
mV
kΩ
µA
%
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
30
7
Input Current
4
10
Input Current Matching
−5
+5
∆ISW(X)
Rev. A | Page 3 of 28
ADP3188
Paraꢀeter
Syꢀbol
Conditions
Min
Typ
Max
Unit
CURRENT-LIMIT COMPARATOR
Output Voltage
Normal Mode
VILIMIT(NM)
VILIMIT(SD)
IILIMIT(NM)
2.9
3
3.1
V
EN > 0.8 V, RILIMIT = 250 kΩ
EN < 0.4 V, IILIMIT = −100 µA
EN > 0.8 V, RILIMIT = 250 kΩ
Shutdown Mode
400
mV
Output Current, Normal Mode
12
µA
µA
mV
2
Maximum Output Current
60
Current-Limit Threshold Voltage
Current-Limit Setting Ratio
DELAY Normal Mode Voltage
DELAY Overcurrent Threshold
Latch-Off Delay Time
VCL
105
125
10.4
3
145
VCSREF – VCSCOMP, RILIMIT = 250 kΩ
VCL/IILIMIT
mV/µA
V
VDELAY(NM)
VDELAY(OC)
tDELAY
2.9
1.7
3.1
1.9
RDELAY = 250 kΩ
RDELAY = 250 kΩ
1.8
1.5
V
ms
RDELAY = 250 kΩ, CDELAY = 12 nF
SOFT START
Output Current, Soft-Start Mode
Soft-Start Delay Time
IDELAY(SS)
tDELAY(SS)
During startup, DELAY < 2.4 V
15
20
1
25
µA
ms
RDELAY = 250 kΩ, CDELAY = 12 nF,
VID code= 011111
ENABLE INPUT
Input Low Voltage
Input High Voltage
Input Current, Input Voltage Low
Input Current, Input Voltage High
VIL(EN)
VIH(EN)
IIL(EN)
0.4
V
V
0.8
−1
EN = 0 V
+1
25
µA
µA
IIH(EN)
EN = 1.25 V
10
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
Relative to nominal DAC output
Relative to nominal DAC output
IPWRGD(SINK) = 4 mA
−180
90
−250
150
225
−300
200
400
mV
mV
mV
Power Good Delay Time
During Soft Start2
1
ms
RDELAY = 250 kΩ, CDELAY = 12 nF,
VID code = 011111
VID Code Changing
VID Code Static
100
250
200
150
550
µs
ns
mV
mV
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
VCROWBAR
tCROWBAR
Relative to nominal DAC output
Relative to FBRTN
Overvoltage to PWM going low
90
450
200
650
100
250
400
µs
ns
PWM OUTPUTS
Output Low Voltage
Output High Voltage
VOL(PWM)
VOH(PWM)
160
5
500
mV
V
IPWM(SINK) = −400 µA
IPWM(SOURCE) = 400 µA
4.0
SUPPLY
DC Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
5
6.9
0.9
10
7.3
1.1
mA
V
V
VUVLO
VCC rising
6.5
0.7
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 Guaranteed by design or bench characterization, not tested in production.
Rev. A | Page 4 of 28
ADP3188
TEST CIRCUITS
ADP3188
ADP3188
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VCC
PWM1
PWM2
PWM3
PWM4
SW1
12V
VCC
+
1
µ
F
100nF
28
18
12V
2
VID3
3
VID2
CSCOMP
CSSUM
CSREF
6-BIT CODE
4
VID1
100nF
39kΩ
5
VID0
17
16
19
6
VID5
1kΩ
7
FBRTN
FB
SW2
8
SW3
1.0V
CSCOMP – 1V
GND
V
=
OS
40
9
COMP
PWRGD
EN
SW4
1kΩ
10
11
12
13
14
GND
Figure 3. Current-Sense Amplifier VOS
1.25V
CSCOMP
CSSUM
CSREF
ILIMIT
20kΩ
100nF
DELAY
RT
12nF
250kΩ
ADP3188
RAMPADJ
VCC
28
250kΩ
12V
FB
8
10kΩ
COMP
Figure 2. Closed-Loop Output Voltage Accuracy
9
CSCOMP
200kΩ
18
100nF
200kΩ
∆V
CSSUM
CSREF
GND
17
16
1.0V
19
∆V = FB
FB
– FB
∆V = 0mV
∆V = 80mV
Figure 4. Positioning Voltage
Rev. A | Page 5 of 28
ADP3188
ABSOLUTE MAXIMUM RATINGS
Table 2.
Paraꢀeter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.
VCC
FBRTN
−0.3 V to +15 V
−0.3 V to +0.3 V
VID0 to VID5, EN, DELAY, ILIMIT, CSCOMP, −0.3 V to +5.5 V
RT, PWM1 to PWM4, COMP
SW1 – SW4
All Other Inputs and Outputs
Storage Temperature
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA)
Lead Temperature
−5 V to +25 V
−0.3 V to VCC + 0.3 V
−65°C to +150°C
0°C to 85°C
125°C
100°C/W
Soldering (10 sec)
Infrared (15 sec)
300°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 28
ADP3188
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VCC
2
VID3
PWM1
PWM2
PWM3
PWM4
SW1
3
VID2
4
VID1
5
VID0
ADP3188
TOP VIEW
(Not to Scale)
6
VID5
7
FBRTN
FB
SW2
8
SW3
9
COMP
PWRGD
EN
SW4
10
11
12
13
14
GND
CSCOMP
CSSUM
CSREF
ILIMIT
DELAY
RT
RAMPADJ
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No9
Mneꢀonic
Description
1 to 6
VID4 to VID0, Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1 if
VID5
left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V
to 1.6 V (see Table 4). Leaving all the VID pins open results in the ADP3188 going into No CPU mode, shutting
off its PWM outputs and pulling the PWRGD output low.
7
8
FBRTN
FB
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no-load offset point.
9
COMP
Error Amplifier Output and Compensation Point.
10
PWRGD
Power Good Output. Open-drain output that signals when the output voltage is outside the proper
operating range.
11
12
EN
DELAY
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
Soft-Start Delay and Current-Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off delay time.
13
14
15
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Current-Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current-limit threshold
of the converter. This pin is actively pulled low when the ADP3188 EN input is low, or when VCC is below its
UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.
RAMPADJ
ILIMIT
16
CSREF
Current-Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-sense
amplifier and the power good and crowbar functions. This pin should be connected to the common point of
the output inductors.
17
18
CSSUM
Current-Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
Current-Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope of
the load line and the positioning loop response time.
CSCOMP
19
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23
SW4 to SW1
Current-Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
24 to 27
28
PWM4 to
PMW1
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the
ADP3188 to operate as a 2-, 3-, or 4-phase controller.
VCC
Supply Voltage for the Device.
Rev. A | Page 7 of 28
ADP3188
TYPICAL PERFORMANCE CHARACTERISTICS
4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
T
= 25°C
A
4-PHASE OPERATION
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
50
100
150
200
250
300
OSCILLATOR FREQUENCY (MHz)
R
VALUE (kΩ)
T
Figure 7. Supply Current vs. Oscillator Frequency
Figure 6. Master Clock Frequency vs. RT
Rev. A | Page 8 of 28
ADP3188
THEORY OF OPERATION
The ADP3188 combines a mulitmode, fixed frequency PWM
control with mulitphase logic outputs for use in 2-, 3-, and
4 - phase synchronous buck CPU core supply power converters.
The internal VID DAC is designed to interface with the Intel
6-bit VRD/VRM 10-and 10.1-compatible CPUs. Multiphase
operation is important for producing the high currents and low
voltages demanded by today’s microprocessors. Handling the
high currents in a single-phase converter places high thermal
demands on the components in the system, such as
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at the
same time for overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3188 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, divide the master clock by 3 for the fre-
quency of the remaining phases. If PWM3 and 4 are grounded,
divide by 2. If all phases are in use, divide by 4.
the inductors and MOSFETs.
The multimode control of the ADP3188 ensures a stable, high
performance topology for
•
•
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3188 combines differential sensing with a high accuracy
VID DAC and reference and a low offset error amplifier. This
maintains a worst-case specification of 9.5 mV differential
sensing error over its full operating output voltage and tem-
perature range. The output voltage is sensed between the
FB and FBRTN pins. FB should be connected through a resistor
to the regulation point, usually the remote sense pin of the
microprocessor. FBRTN should be connected directly to the
remote sense ground point. The internal VID DAC and
precision reference are referenced to FBRTN, which has a
minimal current of 100 µA to allow accurate remote sensing.
The internal error amplifier compares the output of the DAC
to the FB pin to regulate the output voltage.
•
Minimizing thermal switching losses due to lower
frequency operation
•
•
•
•
•
Tight load line regulation and accuracy
High current output for up to 4-phase operation
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
•
Flexibility in operation for tailoring design to low cost or
high performance
OUTPUT CURRENT SENSING
START-UP SEQUENCE
The ADP3188 provides a dedicated current-sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current-limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element, such as the low-side MOSFET.
This amplifier can be configured several ways depending on the
objectives of the system:
During start-up, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3188 operates
as a 4-phase PWM controller. Grounding the PWM4 pin pro-
grams 3-phase operation, and grounding the PWM3 and
PWM4 pins programs 2-phase operation.
When the ADP3188 is enabled, the controller outputs a voltage
on PWM3 and PWM4, which is approximately 675 mV. An
internal comparator checks each pin’s voltage vs. a threshold of
300 mV. If the pin is grounded, it is below the threshold, and the
phase is disabled. The output resistance of the PWM pin is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pin should not be
less than 25 kΩ to ensure proper operation. PWM1 and PWM2
are disabled during the phase detection interval, which occurs
during the first two clock cycles of the internal oscillator. After
this time, if the PWM output is not grounded, the 5 kΩ
resistance is removed, and it switches between 0 V and 5 V.
If the PWM output is grounded, it remains off.
•
•
•
Output inductor DCR sensing without a thermistor for
lowest cost
Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature
Sense resistors for highest accuracy measurements
Rev. A | Page 9 of 28
ADP3188
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor to set the load line required by the microprocessor. The
current information is then given as the difference of CSREF –
CSCOMP. This difference signal is used internally to offset the
VID DAC for voltage positioning and as a differential input for
the current-limit comparator.
External resistors can be placed in series with individual phases
to create, if desired, an intentional current imbalance such as
when one phase may have better cooling and can support higher
currents. Resistors RSW1 through RSW4 (see the typical appli-
cation circuit in Figure 10) can be used for adjusting thermal
balance. It is best to have the ability to add these resistors during
the initial design, so make sure that placeholders are provided in
the layout.
To increase the current in any given phase, make RSW for this
phase larger (make RSW = 0 for the hottest phase, and do not
change during balancing). Increasing RSW to only 500 Ω makes
a substantial increase in phase current. Increase each RSW value
by small amounts to achieve balance, starting with the coolest
phase first.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing
gain is determined by external resistors, so that it can be made
extremely accurate.
VOLTAGE CONTROL MODE
A high gain bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID logic according to the voltages
listed in Table 4. This voltage is also offset by the droop voltage
for active positioning of the output voltage as a function of
current, commonly known as active voltage positioning. The
output of the amplifier is the COMP pin, which sets the termi-
nation voltage for the internal PWM ramps.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output current
at the CSCOMP pin can be scaled to equal the droop impedance
of the regulator multiplied by the output current. This droop
voltage is then used to set the input control voltage to the
system. The droop voltage is subtracted from the DAC
The negative input (FB) is tied to the output sense location with
a resistor (RB) and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is negative with respect to
the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.
reference input voltage directly to tell the error amplifier where
the output voltage should be. This differs from previous imple-
mentations and allows enhanced feed-forward response.
CURRENT-CONTROL MODE AND
THERMAL BALANCE
The ADP3188 has individual inputs for each phase, which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system, which has been optimized for initial current
balance accuracy and dynamic thermal balancing during opera-
tion. This current-balance information is independent of the
average output current information used for positioning
described previously.
SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current-limit latch-
off time as explained in the following section. In UVLO, or
when EN is a logic low, the DELAY pin is held at ground. After
the UVLO threshold is reached and EN is a logic high, the
DELAY capacitor is charged with an internal 20 µA current
source. The output voltage follows the ramping voltage on the
DELAY pin, limiting the inrush current. The soft-start time
depends on the value of the VID DAC and CDLY, with a
secondary effect from RDLY. Refer to the Application
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the RAMPADJ
pin determines the slope of the internal PWM ramp. Detailed
information about programming the ramp is given in the
Application Information section.
Information section for detailed information on setting CDLY
.
If either EN is taken low, or VCC drops below UVLO, the
DELAY capacitor is reset to ground to be ready for another
soft-start cycle. Figure 8 shows a typical soft-start sequence
for the ADP3188.
Rev. A | Page 10 of 28
ADP3188
DELAY to VCC. This prevents the DELAY capacitor from
discharging, so the 1.8 V threshold is never reached. The resistor
has an impact on the soft-start time because the current through
it adds to the internal 20 µA current source.
During start-up when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
This secondary current limit controls the internal COMP
voltage to the PWM comparators to 2 V. This limits the
voltage drop across the low-side MOSFETs through the
current balance circuitry.
An inherent per phase current limit protects individual phases,
if one or more phases stops functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage.
Figure 8. Typical Start-Up Waveforms
Channel 1: PWRGD, Channel 2: CSREF,
Channel 3: DELAY, Channel 4: COMP
CURRENT-LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3188 compares a programmable current-limit setpoint
to the voltage from the output of the current-sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to give a current-limit threshold of 10.4 mV/µA. If the
difference in voltage between CSREF and CSCOMP rises above
the current-limit threshold, the internal current-limit ampli-
fier controls the internal COMP voltage to maintain the average
output current at the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current-limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V.
The Application Information section discusses the selection of
Figure 9. Overcurrent Latch-Off Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID
The ADP3188 has the ability to dynamically change the VID
input while the controller is running. This allows the output
voltage to change while the supply is running and supplying
current to the load. This is commonly referred to as VID on-
the-fly (OTF). A VID OTF can occur under either light or
heavy load conditions. The processor signals the controller by
changing the VID inputs in multiple steps from the start code
to the finish code. This change can be positive or negative.
CDLY and RDLY
.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has
caused the output voltage to drop below the PWRGD thresh-
old, a soft-start cycle is initiated.
When a VID input changes state, the ADP3188 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the six
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and crowbar blanking functions for a
minimum of 100 µs to prevent a false PWRGD or crowbar
event. Each VID change resets the internal timer.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3188, or by pulling the EN pin
low for a short time. To disable the short-circuit latch-off
function, the external resistor to ground should be left open,
and a high value (>1 MΩ) resistor should be connected from
Rev. A | Page 11 of 28
ADP3188
Table 4. VID Codes for the ADP3188
VID4 VID3 VID2 VID1 VID0 VID.
Output
No CPU
VID4 VID3 VID2 VID1 VID0 VID.
Output
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.2125 V
1.2250 V
1.2375 V
1.2500 V
1.2625 V
1.2750 V
1.2875 V
1.3000 V
1.3125 V
1.3250 V
1.3375 V
1.3500 V
1.3625 V
1.3750 V
1.3875 V
1.4000 V
1.4125 V
1.4250 V
1.4375 V
1.4500 V
1.4625 V
1.4750 V
1.4875 V
1.5000 V
1.5125 V
1.5250 V
1.5375 V
1.5500 V
1.5625 V
1.5750 V
1.5875 V
1.6000 V
No CPU
0.8375 V
0.8500 V
0.8625 V
0.8750 V
0.8875 V
0.9000 V
0.9125 V
0.9250 V
0.9375 V
0.9500 V
0.9625 V
0.9750 V
0.9875 V
1.0000 V
1.0125 V
1.0250 V
1.0375 V
1.0500 V
1.0625 V
1.0750 V
1.0875 V
1.1000 V
1.1125 V
1.1250 V
1.1375 V
1.1500 V
1.1625 V
1.1750 V
1.1875 V
1.2000 V
The PWRGD circuitry also incorporates an initial turn-on
delay time based on the DELAY ramp. The PWRGD pin is held
low until the DELAY pin reaches 2.6 V. The time between when
the PWRGD undervoltage threshold is reached and when the
DELAY pin reaches 2.6 V provides the turn-on delay time.
This time is incorporated into the soft-start ramp. To ensure a
1 ms delay time on PWRGD, the soft-start ramp must also be
>1 ms. Refer to the Application Information section for detailed
POWER GOOD MONITORING
The power good comparator monitors the output voltage via the
CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified in
Table 4. These limits are based on the VID voltage setting.
PWRGD goes low if the output voltage is outside of this
specified range, if all of the VID DAC inputs are high, or when-
ever the EN pin is pulled low. PWRGD is blanked during a VID
OTF event for a period of 250 µs to prevent false signals during
the time the output is changing.
information on setting CDLY
.
Rev. A | Page 12 of 28
ADP3188
OUTPUT CROWBAR
OUTPUT ENABLE AND UVLO
As part of the protection for the load and output components
of the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately 550 mV.
For the ADP3188 to begin switching, the input supply (VCC)
to the controller must be higher than the UVLO threshold, and
the EN pin must be higher than its logic threshold. If UVLO is
less than the threshold or the EN pin is a logic low, the ADP3188
is disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at ground.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over-
voltage is due to a short in the high-side MOSFET, this action
current-limits the input supply or blows its fuse, protecting the
microprocessor from being destroyed.
In the application circuit, the ILIMIT pin should be connected
to the
pins of the ADP3418 drivers. The ILIMIT being
OD
grounded disables the drivers such that both DRVH and DRVL
are grounded. This feature is important in preventing the dis-
charge of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated during output due to the high current discharge of
the output capacitors through the inductors.
Rev. A | Page 13 of 28
ADP3188
U P
C O M F R
*FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION.
Figure 10. Typical VR 10.1 Application Circuit
Rev. A | Page 14 of 28
ADP3188
APPLICATION INFORMATION
The design parameters for a typical Intel VRD 10.1-compliant
CPU application are as follows:
However, as long as RDLY is kept greater than 200 kΩ, this effect
is minor. The value for CDLY can be approximated using
•
•
•
•
•
•
Input voltage (VIN) = 12 V
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VVID
tSS
⎜
(2)
CDLY = 20 µA−
×
VID setting voltage (VVID) = 1.300 V
Duty cycle (D) = 0.108
2 × RDLY
VVID
where tSS is the desired soft-start time. Assuming an RDLY of
390 kΩ and a desired soft-start time of 3 ms, CDLY is 36 nF.
The closest standard value for CDLY is 39 nF. Once CDLY is
chosen, RDLY can be calculated for the current-limit latch-off
time using
Nominal output voltage at no load (VONL) = 1.281 V
Nominal output voltage at 101 A load (VOFL) = 1.180 V
Static output voltage drop based on a 1.0 mΩ load line (RO)
from no load to full load
1.96 ×tDELAY
(VD) = VONL − VOFL = 1.281 V − 1.180 V = 101 mV
RDLY
=
(3)
CDLY
•
•
•
•
Maximum output current (IO) = 119 A
Maximum output current step (∆IO) = 95 A
Number of phases (n) = 4
If the result for RDLY is less than 200 kΩ, a smaller soft-start time
should be considered by recalculating the equation for CDLY, or a
longer latch-off time should be used. RDLY should never be less
than 200 kΩ. In this example, a delay time of 9 ms results in
RDLY = 452 kΩ. The closest standard 5% value is 470 kΩ.
Switching frequency per phase (fSW) = 330 kHz
SETTING THE CLOCK FREQUENCY
The ADP3188 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and/or the input and output
capacitors. With n = 4 for four phases, a clock frequency of
1.32 MHz sets the switching frequency (fSW) of each phase to
330 kHz, which represents a practical trade-off between the
switching losses and the sizes of the output filter components.
Equation 1 shows that to achieve an 1.32 MHz oscillator fre-
quency, the correct value for RT is 137 kΩ. Alternatively, the
value for RT can be calculated using
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs, but allows using smaller inductors and,
for a specified peak-to-peak transient deviation, less total output
capacitance. Conversely, a higher inductance means lower ripple
current and reduced conduction losses, but requires larger
inductors and more output capacitance for the same peak-to-
peak transient deviation. In any multiphase converter, a practical
value for the peak-to-peak inductor ripple current is less than
50% of the maximum dc current in the same inductor. Equation 4
shows the relationship between the inductance, oscillator
frequency, and peak-to-peak ripple current in the inductor.
1
RT
=
− 27 kΩ
(1)
n × fSW × 4.7 pF
VVID
×
(
1− D
)
IR
=
(4)
where 4.7 pF and 27 kΩ are internal IC component values.
For good initial accuracy and frequency stability, a 1%
resistor is recommended.
fSW × L
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
SOFT START AND CURRENT-LIMIT LATCH-OFF
DELAY TIMES
VVID × RO ×
1−
n× D
L ≥
(5)
Because the soft start and current-limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set CDLY for the soft-start ramp. This
ramp is generated with a 20 µA internal current source. The
value of RDLY has a second-order impact on the soft-start time
because it sinks part of the current source to ground.
fSW ×VRIPPLE
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
1.3 V ×1.0 mΩ × 1− 0.432
(
)
= 224 nH
L ≥
330 kHz ×10 mV
If the resulting ripple voltage is less than it was designed for, make
the inductor smaller until the ripple value is met. This allows
optimal transient response and minimum output decoupling.
Rev. A | Page 15 of 28
ADP3188
•
•
•
Coiltronics
(561) 752-5000
www.coiltronics.com
The smallest possible inductor should be used to minimize the
number of output capacitors. For this example, choosing a
320 nH inductor is a good starting point and gives a calculated
ripple current of 11 A. The inductor should not saturate at the
peak current of 35.5 A and should be able to handle the sum of
the power dissipation caused by the average current of 30 A in
the winding and core loss.
Sumida Electric Company
(847) 545-6700
www.sumida.com
Vishay Intertechnology
(402) 563-6866
www.vishay.com
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
can cause excessive power losses, while too small a value can
lead to increased measurement error. A good rule is to have the
DCR be about 1 to 1½ times the droop resistance (RO). For this
design, an inductor with a DCR of 1.4 mΩ is used.
OUTPUT DROOP RESISTANCE
The design requires the regulator output voltage measured at
the CPU pins to drop when the output current increases. The
specified voltage drop corresponds to a dc output resistance (RO).
DESIGNING AN INDUCTOR
Once the inductance and DCR are known, the next step is to
either design an inductor, or to find a standard inductor that
comes as close as possible to meeting the overall design goals. It
is also important to have the inductance and DCR tolerance
specified to control the accuracy of the system. 15% inductance
and 8% DCR (at room temperature) are reasonable tolerances
that most manufacturers can meet.
The output current is measured by summing the voltage across
each inductor and passing the signal through a low-pass filter.
This summer filter is the CS amplifier configured with resistors
RPH(X) (summers), and RCS and CCS (filter). The output resistance
of the regulator is set by the following equations, where RL is the
DCR of the output inductors:
RCS
RPH
( )
x
RO
=
× RL
(6)
(7)
The first decision in designing the inductor is to choose the
core material. Several possibilities for providing low core loss at
high frequencies include the powder cores (for example, Kool-
Mµ® from Magnetics, Inc. or from Micrometals) and the gapped
soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low
frequency powdered iron cores should be avoided due to their
high core loss, especially when the inductor value is relatively
low, and the ripple current is high.
L
CCS
=
RL × RCS
The user has the flexibility of choosing either RCS or RPH(X). It is
best to select RCS equal to 100 kΩ, and then solve for RPH(X) by
rearranging Equation 6.
RL
The best choice for a core geometry is a closed-loop type such
as a potentiometer core, PQ, U, or E core or toroid. A good
compromise between price and performance is a core with a
toroidal shape.
RPH
=
× RCS
(
x
)
RO
1.4 mΩ
1.0 mΩ
RPH
=
×100 kΩ =140 kΩ
(
x
)
Many useful magnetics design references are available for
quickly designing a power inductor, such as
Next, use Equation 6 to solve for CCS.
•
Magnetic Designer Software
Intusoft (www.intusoft.com)
320 nH
CCS
=
= 2.28 nF
1.4 mΩ ×100 kΩ
•
Designing Magnetic Components for High-Frequency DC-
DC Converters, by William T. McLyman, K G Magnetics,
Inc., ISBN 1883107008
It is best to have a dual location for CCS in the layout, so that
standard values can be used in parallel to get as close to the
value desired. For accuracy, CCS should be a 5% or 10% NPO
capacitor. This example uses a 5% combination for CCS of 1.5 nF
and 560 pF in parallel. Recalculating RCS and RPH(X) using this
capacitor combination yields 110 kΩ and 154 kΩ. The closest
standard 1% value for RPH(X) is 158 kΩ.
Selecting a Standard Inductor
The following power inductor manufacturers can provide design
consultation and deliver power inductors optimized for high
power applications upon request:
•
Coilcraft
(847) 639-6400
www.coilcraft.com
Rev. A | Page 16 of 28
ADP3188
INDUCTOR DCR TEMPERATURE CORRECTION
4. Compute the relative values for RCS1, RCS2, and RTH using
With the inductor’s DCR being used as the sense element and
copper wire being the source of the DCR, compensation is
needed for temperature changes of the inductor’s winding.
Fortunately, copper has a well-known temperature coefficient
(TC) of 0.39%/°C.
A− B
)
× r1 × r2 − A×
(
1− B
(1− A
)
× r2 + B ×
× r2 −
1− A
)
× r1
rCS2
=
=
A× 1− B × r1 − B ×
(
)
)
(
A− B
)
1− A
)
rCS1
1
A
−
If RCS is designed to have an opposite and equal percentage
change in resistance to that of the wire, it cancels the tempera-
ture variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, resistors RCS1 and RCS2 are needed.
See Figure 11 to linearize the NTC and produce the desired
temperature tracking.
1− rCS2 r1 − rCS2
1
rTH
=
(8)
1
1
−
1− rCS2 rCS1
5. Calculate RTH = rTH × RCS, then select the closest value of
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
thermistor available. Also compute a scaling factor k based
on the ratio of the actual thermistor value used relative to
the computed one:
TO
SWITCH
NODES
TO
OR LOW-SIDE MOSFET
V
OUT
SENSE
R
TH
RTH
(
ACTUAL
)
(9)
k =
R
R
R
PH3
PH1
PH2
RTH
(CALCULATED
)
ADP3188
R
R
CS2
CS1
CSCOMP
6.
Calculate values for RCS1 and RCS2 using Equation 10:
18
RCS1 = RCS × k × rCS1
C
C
CS2
KEEP THIS PATH
CS1
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
CSSUM
CSREF
17
RCS2 = RCS
×
1− k
+
k × rCS2
(10)
16
For this example, RCS has been calculated to be 110 kΩ.
Start with a thermistor value of 100 kΩ. Next, look through
the available 0603-size thermistors, and find a Vishay
NTHS0603N01N1003JR NTC thermistor with A = 0.3602
Figure 11. Temperature Compensation Circuit Values
The following procedure and expressions yield values to use
for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a
given RCS value.
and B = 0.09174. From these, compute rCS1 = 0.3795, rCS2
=
0.7195, and rTH = 1.075. Solve for RTH, which yields118.28 kΩ.
Then, choose 100 kΩ, which makes k = 0.8455. Finally, RCS1
and RCS2 are 35.3 kΩ and 83.9 kΩ. Choose the closest 1%
resistor values, which yields a choice of 35.7 kΩ or 84.5 kΩ.
1. Select an NTC based on type and value. Because there isn’t
a value yet, start with a thermistor with a value close to RCS.
The NTC should also have an initial tolerance of better
than 5%.
OUTPUT OFFSET
The Intel specification requires that at no load the nominal
output voltage of the regulator be offset to a value lower than
the nominal voltage corresponding to the VID code. The offset
is set by a constant current source flowing out of the FB pin (IFB)
and flowing through RB. The value of RB can be found using
Equation 11:
2. Based on the type of NTC, find its relative resistance value
at two temperatures. The temperatures that work well are
50°C and 90°C. These resistance values are called
A (RTH(50°C)/RTH(25°C)) and B (RTH(90°C)/RTH(25°C)).
Note: the NTC’s relative value is always 1 at 25°C.
3. Find the relative values of RCS required for each of these
temperatures. This is based on the percentage change
needed, which in this example is initially 0.39%/°C.
The relative values are called r1 (1/(1 + TC × (T1 − 25)))
and r2 (1/(1 + TC × (T2 − 25))), where TC = 0.0039 for
copper. T1 = 50°C and T2 = 90°C are chosen. From this,
calculate that r1 = 0.9112 and r2 = 0.7978.
V
VID −VONL
RB
=
IFB
1.3 V−1.281V
RB
=
=1.22 kΩ
(11)
15.5 µA
The closest standard 1% resistor value is 1.21 kΩ.
Rev. A | Page 17 of 28
ADP3188
This example uses 18, 10 µF 1206 MLC capacitors (CZ = 180
µF). The VID on-the-fly step change is 450 mV in 230 µs with
a setting error of 2.5 mV. The maximum allowable load release
overshoot for this example is 50 mV, so solving for the bulk
capacitance yields
COUT SELECTION
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
Also, to determine what is required, use some simple design
guidelines. These guidelines are based on having both bulk
and ceramic capacitors in the system.
⎛
⎜
⎞
⎟
The first thing is to select the total amount of ceramic capaci-
tance. This is based on the number and type of capacitor to
be used. The best location for ceramic capacitors is inside the
socket, with 12 to 18 of size 1206 being the physical limit.
Others can be placed along the outer edge of the socket as well.
⎜
⎜
⎜
⎟
320 nH × 95 A
Cx
≤
)
−180 µF = 3.65 mF
⎟
(
MIN
⎛
⎞
50 mV
95 A
⎟
⎜
⎟
⎟
4 × 1.0 mΩ+
×1.3 V
⎜
⎝
⎜
⎝
⎟
⎠
⎠
320 nH × 450 mV
4 × 4.62 × 2 ×1.3 V
1.0 mΩ
Combined ceramic values of 200 µF to 300 µF are recom-
mended, usually made up of multiple 10 µF or 22 µF capacitors.
Select the number of ceramic capacitors and find the total
ceramic capacitance (CZ).
Cx
≤
)
×
(
MAX
(
)
⎛
⎜
⎞
2
⎟
⎛
⎞
230 µs ×1.3 V × 4 × 4.6 ×1.0 mΩ
450 mV × 320 nH
⎜
⎜
⎟
⎟
1+
−1 −180 µF
⎜
⎟
⎝
⎠
⎜
⎝
⎟
Next, there is an upper limit imposed on the total amount of
bulk capacitance (CX) when considering the VID on-the-fly
voltage stepping of the output (voltage step VV in time tV with
error of VERR). A lower limit is based on meeting the capaci-
tance for load release for a given maximum load step ∆IO and a
maximum allowable overshoot. The total amount of load
release voltage is given as ∆VO = ∆IO × RO + ∆Vrl, where ∆Vrl
is the maximum allowable overshoot voltage.
⎠
= 48.5 mF
where K = 4.6.
Using eight 560 µF Al-Poly capacitors with a typical ESR of
5 mΩ each yields CX = 4.48 mF with an RX = 0.63 mΩ.
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the high frequency
ringing during a load change. This is tested using
⎛
⎜
⎞
⎟
⎜
⎜
⎜
⎟
⎟
⎟
L × ꢀ IO
Cx
≥
)
−Cz
(12)
(
MIN
⎛
⎜
⎝
⎞
⎟
⎟
⎠
∆Vrl
+
⎜
n × RO
×VVID
2
L ≤ C × RO ×Q2
⎜
⎝
⎟
⎠
∆IO
x
z
(14)
Lx ≤180 µF×
(
1mΩ
2 ×2 = 360 pH
)
Cx
≤
MAX )
(
where Q is limited to the square root of 2 to ensure a critically
damped system. In this example, LX is approximately 350 pH
for the eight A1-Polys capacitors, which satisfies this limita-
tion. If the LX of the chosen bulk capacitor bank is too large, the
number of ceramic capacitors may need to be increased if
there is excessive ringing.
⎛
⎞
2
⎜
⎟
⎛
⎜
⎝
⎞
VV
VVID nKRO
L
⎜
⎟
⎟
⎠
×
×
1+ tv
×
−1 −C (13)
⎜
⎟
z
nK 2RO2
VVID
VV
L
⎜
⎝
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VERR
VV
where K =1n
Note for this multimode control technique, all ceramic designs
can be used as long as the conditions of Equations 11, 12, and
13 are satisfied.
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (RX) should be less
than two times the droop resistance (RO). If the CX(MIN) is larger
than CX(MAX), the system cannot meet the VID on-the-fly speci-
fication and may require the use of a smaller inductor or more
phases (and may need the switching frequency to increase to
keep the output ripple the same).
POWER MOSFETS
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive
voltage (the supply voltage to the ADP3418) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With VGATE ~10 V, logic-level threshold MOSFETs
(VGS(TH)°< 2.5 V) are recommended.
Rev. A | Page 18 of 28
ADP3188
The maximum output current (IO) determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. With
the ADP3188, currents are balanced between phases, thus the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (nSF). With conduction losses
being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and average total output current (IO):
Note that adding more main MOSFETs (nMF) does not really
help the switching loss per MOSFET because the additional gate
capacitance slows switching. The best way to reduce switching
loss is to use lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following, where RDS(MF) is the on resistance of the MOSFET:
2
2
⎡
⎤
n × I
⎞
R
⎛
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
IO
nMF
1
12
⎢⎜
⎟ ⎥
PC
= D ×
+
×
×RDS
(MF )
(17)
(
MF
)
⎜
⎟
⎥
⎠
⎦
2
2
nMF
⎢
⎡
⎤
⎞
⎝
⎛
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
n IR
nSF
IO
1
12
⎣
⎢⎜
⎟ ⎥
PSF
=
(1− D
)
×
+
×
×RDS
(15)
(
SF )
⎜
⎟
⎢ nSF
⎥
⎝
⎠
⎣
⎦
Typically, for main MOSFETs, the highest speed (low CISS
)
device is preferred, but these usually have higher on resistance.
Select a device that meets the total power dissipation (about
1.5 W for a single D-PAK) when combining the switching and
conduction losses.
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, it is possible to find
the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up
to an ambient temperature of 50°C, a safe limit for PSF is 1 W to
1.5 W at 120°C junction temperature. Thus, for this example
(119 A maximum), RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF)
is also at a junction temperature of about 120°C, so be certain to
account for this temperature when making this selection. This
example uses two lower-side MOSFETs at 4.8 mΩ each at 120°C.
For this example, an NTD40N03L was selected as the main
MOSFET (eight total; nMF = 8), with a CISS = 584 pF (max) and
RDS(MF) = 19 mΩ (max at TJ = 120°C), and an NTD110N02L was
selected as the synchronous MOSFET (eight total; nSF = 8), with
CISS = 2710 pF (max) and RDS(SF) = 4.8 mΩ (max at TJ = 120°C).
The synchronous MOSFET CISS is less than 3000 pF, satisfying
that requirement. Solving for the power dissipation per MOSFET
at IO = 119 A and IR = 11 A yields 958 mW for each synchronous
MOSFET and 872 mW for each main MOSFET. These numbers
comply with the guideline to limit the power dissipation to 1 W
per MOSFET.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of the
driver is approximately 2 Ω, and the typical MOSFET input gate
resistances are about 1 Ω to 2 Ω, so a total gate capacitance of
less than 6000 pF should be adhered to. Because there are two
MOSFETs in parallel, the input capacitance for each synchronous
MOSFET should be limited to 3000 pF.
One last thing to consider is the power dissipation in the driver
for each phase. This is best described in terms of the QG for the
MOSFETs and is given by the following equation, where QGMF is
the total gate charge for each main MOSFET, and QGSF is the
total gate charge for each synchronous MOSFET:
⎡
⎢
⎤
fSW
2 ×n
PDRV
=
×
(
n
MF ×QGMF +nSF ×QGSF
)
+ ICC ×V
(18)
⎥
CC
⎢
⎣
⎥
⎦
The high-side (main) MOSFET has to be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the switching
speed on the rise and fall time of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET,
where nMF is the total number of main MOSFETs:
Also shown is the standby dissipation factor (ICC × VCC) for the
driver. For the ADP3418, the maximum dissipation should be
less than 400 mW. In this example, with ICC = 7 mA, QGMF
=
5.8 nC, and QGSF = 48 nC, 297 mW is found in each driver,
which is below the 400 mW dissipation limit. See the ADP3418
data sheet for more details.
V
CC × IO
nMF
n
PS ) = 2 × fSW
×
× RG ×
×CISS
(16)
(
MF
nMF
where RG is the total gate resistance (2 Ω for the ADP3418 and
about 1 Ω for typical high speed switching MOSFETs, making
RG = 3 Ω), and CISS is the input capacitance of the main MOSFET.
Rev. A | Page 19 of 28
ADP3188
For values of RLIM greater than 500 kΩ, the current limit may be
lower than expected, so some adjustment of RLIM may be needed.
Here, ILIM is the average current limit for the output of the supply.
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:
In this example, choosing a peak current limit of 200 A for ILIM
results in RLIM = 156 kΩ, for which 150 kΩ is chosen as the
nearest 1% value.
,
The limit of the per-phase current limit described earlier is
determined by
AR × L
RR =
3× AD × RDS × CR
(19)
VCOMP
−VR −VBIAS
)
IR
(
MAX
(23)
)
IPHLIM
≅
+
AD × RDS
2
0.2 × 320 nH
3× 5 × 2.4 mΩ × 5 pF
(
MAX
)
RR =
= 356 kΩ
For the ADP3188, the maximum COMP voltage (VCOMP(MAX)
is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the
where AR is the internal ramp amplifier gain, AD is the current
balancing amplifier gain, RDS is the total low-side MOSFET on
resistance, and CR is the internal ramp capacitor value. The
closest standard 1% resistor value is 357 kΩ.
current-balancing amplifier gain (AD) is 5. Using VR of 0.49 V
and RDS(MAX) of 3 mΩ (low-side on resistance at 150°C), calculate
a per-phase peak current limit of 100 A. Although this number
may seem high, this current level can be reached only with an
absolute short at the output, and the current-limit latch-off func-
tion shuts down the regulator before overheating can occur.
The internal ramp voltage magnitude can be calculated by using
AR ×
RR × CR × fSW
(
1− D
)
×VVID
VR
=
This limit can be adjusted by changing the ramp voltage (VR),
but make sure not to set the per-phase limit lower than the
average per-phase current (ILIM/n).
(20)
0.2 ×
(
1− 0.108
)
×1.3V
VR
=
= 390 mV
357 kΩ × 5 pF × 330 kHz
The per-phase initial duty cycle limit is determined by
VCOMP
) −VBIAS
The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made
smaller, thermal balance improves at the sacrifice of transient
response and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
(
MAX
DMAX = D ×
(24)
VRT
In this example, the maximum duty cycle is 0.46.
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3188 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make the
regulator and output decoupling appear as an output impedance
that is entirely resistive over the widest possible frequency range,
including dc, and equal to the droop resistance (RO).
COMP PIN RAMP
A ramp signal on the COMP pin is due to the droop voltage
and output voltage ramps. This ramp amplitude adds to the
internal ramp to produce the following overall ramp signal
at the PWM input:
With the resistive output impedance, the output voltage droops
in proportion to the load current at any load current-slew rate.
This ensures the optimal positioning and allows the
minimization of the output decoupling.
VR
VRT
=
(21)
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2 ×
(
1−n × D
)
1−
n × fSW ×CX × RO
With the multimode feedback structure of the ADP3188, the
feedback compensation must be set to make the converter’s
output impedance, working in parallel with the output decoup-
ling, to meet this goal. Several poles and zeros created by the
output inductor and decoupling capacitors (output filter) need
to be compensated for.
In this example, the overall ramp signal is 0.49 V.
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, first find the resistor
value for RLIM. The current-limit threshold for the ADP3188
is set with a 3 V source (VLIM) across RLIM with a gain of
10.4 mV/µA (ALIM). RLIM can be found using
ALIM ×VLIM
RLIM
=
(22)
ILIM × RO
Rev. A | Page 20 of 28
ADP3188
A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. Equations 25 to 29
yield an optimal starting point for the design; some adjustments
may be necessary to account for PCB and component parasitic
effects (see the section).
The first step is to compute the time constants for all of the
poles and zeros in the system
RL ×VRT 2 × L ×
1− n × D
)
×VRT
RE = n × RO + AD × RDS
+
+
VVID
n × CX × RO ×VVID
1.4 mΩ × 0.49V 2 × 320 nH ×
1− 0.432
)
× 0.49 V
RE = 4 ×1 mΩ+ 5 × 2.4 mΩ+
+
= 24.2 mΩ
(25)
1.3 V
4 × 4.45 mF×1 mΩ ×1.3 V
′
LX RO − R
350 pH 1 mΩ− 0.65mΩ
′
TA = CX
×
(
RO − R
)
+
×
= 4.45 mF×
(
1 mΩ− 0.5 mΩ
)
+
×
= 2.50 µs
(26)
(27)
RO
RX
1 mΩ
10.63mΩ
′
TB =
(
RX + R − RO
)
×CX =
(
0.63mΩ+0.5mΩ−1mΩ
)
× 4.45mF= 580ns
⎛
⎞
⎟
⎟
⎠
⎛
⎞
AD × RDS
2 × fSW
5 × 2.4 mΩ
2 × 330 kHz
⎜
⎜
⎟
⎟
VRT × L −
0.49 V × 320 nH−
⎜
⎜
⎝
⎝
⎠
TC
TD
=
=
=
= 4.7 µs
(28)
VVID × RE
1.3 V × 24.2 mΩ
CX × CZ × RO2
RO − R' + CZ × RO 4.45 mF ×
2
4.45 mF ×180 µF ×
1 mΩ− 0.5mΩ
1 mΩ
=
= 333 ns
(29)
(32)
(33)
CX
×
(
)
(
)
+180 µF ×1 mΩ
where, for the ADP3188, R' is the PCB resistance from the
bulk capacitors to the ceramics and where RDS is the total low-
side MOSFET on resistance per phase. In this example, AD is 5,
VRT equals 0.49 V, R' is approximately 0.5 mΩ (assuming a
4-layer, 1 ounce motherboard), and LX is 350 pH for the eight
Al-Poly capacitors.
TB
580ns
CB
=
=
= 479 nF
= 24.3 pF
RB 1.21kΩ
TD
333ns
CFB
=
=
RA 13.7 kΩ
These are the starting values, prior to tuning the design, to
account for layout and other parasitic effects (see the section).
The final values selected after tuning are
The compensation values can then be solved using the following:
n × RO ×TA
RE × RB
CA
=
CA = 470 pF
RA =12.1kΩ
CB = 470pF
CFB = 22 pF
(30)
(31)
4×1mΩ × 2.50 µs
24.2mΩ ×1.21kΩ
CA =
= 342 pF
TC
4.7 µs
RA
=
=
=13.7 kΩ
CA 342 pF
Rev. A | Page 21 of 28
ADP3188
Figure 12 and Figure 13 show the typical transient response
using these compensation values.
CIN SELECTION AND
INPUT CURRENT DI/DT REDUCTION
In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude of one-nth the
maximum output current. To prevent large voltage transients,
a low ESR input capacitor, sized for the maximum rms current,
must be used. The maximum rms capacitor current is given by
1
ICRMS = D × IO
×
−1
N × D
(34)
1
ICRMS = 0.108 ×119A ×
−1 =14.7A
4 × 0.108
Figure 12. Typical Transient Response for Design Example
Load Step
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2,000 hours of life. This makes it advisable
to further derate the capacitor, or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
two 2,700 µF, 16 V aluminum electrolytic capacitors and eight
4.7 µF ceramic capacitors.
To reduce the input current di/dt to a level below the recom-
mended maximum of 0.1 A/µs, an additional small inductor
(L > 370 nH at 18 A) should be inserted between the converter
and the supply bus. That inductor also acts as a filter between
the converter and the primary power source.
100
80
60
40
20
Figure 13. Typical Transient Response for Design Example
Load Release
V
T
= 1.3 V
= 25°C
OUT
A
0
0
20
40
60
80
100
120
OUTPUT CURRENT (A)
Figure 14. Efficiency of the Circuit of Figure 10 vs. Output Current
Rev. A | Page 22 of 28
ADP3188
6. Measure the output voltage from no-load to full-load using
5 A steps. Compute the loadline slope for each change, and
then average to get the overall loadline slope (ROMEAS).
TUNING THE ADP3188
1. Build a circuit based on the compensation values
computed from the design spreadsheet.
7. If ROMEAS is off from RO by more than 0.05 mΩ, use the
following to adjust the RPH values:
2. Hook up the dc load to circuit, turn it on, and verify its
operation. Also, check for jitter at no load and full load.
DC Loadline Setting
ROMEAS
RO
RPH
) = RPH ×
(OLD)
(36)
(
NEW
3. Measure the output voltage at no load (VNL). Verify that it
is within tolerance.
8. Repeat Steps 6 and 7 to check the loadline, and repeat
adjustments if necessary.
4. Measure the output voltage at full load cold (VFLCOLD). Let
the board sit for ~10 minutes at full load, and then measure
the output (VFLHOT). If there is a change of more than a few
millivolts, adjust RCS1 and RCS2 using Equations 35 and 36.
9. Once dc loadline adjustment is complete, do not change
RPH, RCS1, RCS2, or RTH for remainder of procedure.
10. Measure the output ripple at no load and full load with
a scope, and make sure it is within specifications.
VNL −VFLCOLD
VNL −VFLHOT
RCS2
= RCS2
×
)
(35)
(
NEW
)
(
OLD
5. Repeat Step 4 until the cold and hot voltage measurements
remain the same.
(37)
1
RCS1
=
NEW )
(
RCS1 ) + RTH
(25°C)
1
(
OLD
−
RCS1 ) × RTH
+
(
RCS1 ) − RCS2
)
×
(
RCS1 ) − RTH
)
RTH
(25°C
(
OLD
(
25°C
)
(
OLD
(
NEW
)
(
OLD
(
25°C
)
)
Rev. A | Page 23 of 28
ADP3188
Initial Transient Setting
AC Loadline Setting
11. Remove the dc load from the circuit and hook up the
dynamic load.
19. With the dynamic load still set at the maximum step size,
expand the scope time scale to see 2 µs/div to 5 µs/div. The
waveform may have two overshoots and one minor under-
shoot (see Figure 16). Here, VDROOP is the final desired value.
12. Hook up the scope to the output voltage and set it to dc
coupling, with the time scale at 100 µs/div.
13. Set the dynamic load for a transient step of about 40 A at
1 kHz with a 50% duty cycle.
14. Measure the output waveform (if not visible, use dc offset
on scope to view). Try to use a vertical scale of 100 mV/div
or finer. This waveform should look similar to Figure 15.
V
DROOP
V
TRAN1
V
TRAN2
V
ACDRP
Figure 16. Transient Setting Waveform
V
DCDRP
20. If both overshoots are larger than desired, try making
these adjustments:
Note that if these adjustments do not change the response,
the output decoupling is the limiting factor. Check the
output response every time a change is made, or nodes
are switched, to make sure the response remains stable.
Figure 15. AC Loadline Waveform
15. Use the horizontal cursors to measure VACDRP and VDCDRP as
shown. Do not measure the undershoot or overshoot that
happens immediately after this step.
•
•
Make the ramp resistor larger by 25% (RRAMP).
For VTRAN1, increase CB, or increase the switching
frequency.
16. If VACDRP and VDCDRP are different by more than a few
millivolts, use Equation 38 to adjust CCS. It may be nec-
essary to parallel different values to get the correct one as
there are limited standard capacitor values available. It is a
good idea to have locations for two capacitors in the layout
for this.
•
For VTRAN2, increase RA, and decrease CA by 25%.
21. For load release (see Figure 17), if VTRANREL is larger
than VTRAN1 (see Figure 16), there is not enough output
capacitance. Either more capacitance is needed, or the
inductor values need to be smaller. (If inductors are
changed, start the design again using the spreadsheet
and this tuning procedure.)
VACDRP
VDCDRP
CCS
= CCS ×
(OLD)
(38)
(
NEW
)
17. Repeat Steps 11 to 13, and repeat the adjustments if
necessary. Once complete, do not change CCS for the
remainder of the procedure.
V
TRANREL
V
DROOP
18. Set the dynamic load step to maximum step size (do not
use a step size larger than needed) and verify that the
output waveform is square, which means that VACDRP and
VDCDRP are equal.
Figure 17. Transient Setting Waveform
Rev. A | Page 24 of 28
ADP3188
Because the ADP3188 turns off all of the phases (switches
inductors to ground), there is no ripple voltage present during
load release. Thus, headroom does not need to be added for
ripple, allowing load release VTRANREL to be larger than VTRAN1
by the amount of ripple, and still meet specifications.
If VTRAN1 and VTRANREL are less than the desired final droop, this
implies that capacitors can be removed. When removing capaci-
tors, also check the output ripple voltage to make sure it is still
within specifications.
Rev. A | Page 25 of 28
ADP3188
POWER CIRCUITRY RECOMMENDATIONS
LAYOUT AND COMPONENT PLACEMENT
The switching power path should be routed on the PCB to
encompass the shortest possible length in order to minimize
radiated switching noise energy (EMI) and conduction losses
in the board. Failure to take proper precautions often results in
EMI problems for the entire PC system as well as noise-related
operational problems in the power converter control circuitry.
The switching power path is the loop formed by the current path
through the input capacitors and the power MOSFETs, including
all interconnecting PCB traces and planes. Using short and wide
interconnection traces is especially critical in this path for two
reasons: it minimizes the inductance in the switching loop, which
can cause high energy ringing, and it accommodates the high
current demand with minimal voltage loss.
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
GENERAL RECOMMENDATIONS
For good results, a PCB with at least four layers is recommended.
This allows the needed versatility for control circuitry inter-
connections with optimal placement, power planes for ground,
input and output power, and wide interconnection traces in the
remainder of the power delivery current paths. Keep in mind
that each square unit of 1 ounce copper trace has a resistance of
~0.53 mΩ at room temperature.
Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths. Then, the resistance and inductance introduced by
these current paths is minimized, and the via current rating
is not exceeded.
Whenever a power dissipating component, for example, a
power MOSFET, is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately surround-
ing it, is recommended. This improves current rating through
the vias and also improves thermal performance from vias
extended to the opposite side of the PCB, where a plane can
more readily transfer the heat to the air. Make a mirror image of
any pad being used to heat-sink the MOSFETs on the opposite
side of the PCB to achieve the best thermal dissipation to the air
around the board. To further improve thermal performance, use
the largest possible pad area.
If critical signal lines (including the output voltage sense lines of
the ADP3188) must cross through power circuitry, it is best if a
signal ground plane can be interposed between those signal lines
and the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
making signal ground noisier.
An analog ground plane should be used around and under the
ADP3188 as a reference for the components associated with
the controller. This plane should be tied to the nearest output
decoupling capacitor ground and not tied to any other power
circuitry to prevent power currents from flowing in it.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.
The components around the ADP3188 should be located close
to the controller with short traces. The most important traces to
keep short, and away from other traces, are the FB and CSSUM
pins. The output capacitors should be connected as close as
possible to the load (or connector), for example, a micro-
processor core, that receives the power. If the load is distributed,
the capacitors should also be distributed and generally be in
proportion to where the load tends to be more dynamic.
SIGNAL CIRCUITRY RECOMMENDATIONS
The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connect to the signal ground at the
load. To avoid differential-mode noise pickup in the sensed
signal, the loop area should be small. Thus, the FB and FBRTN
traces should be routed adjacent to each other on top of the
power ground plane back to the controller.
Avoid crossing any signal lines over the switching power path
loop, as described next.
The feedback traces from the switch nodes should be con-
nected as close as possible to the inductor. The CSREF signal
should be connected to the output voltage at the nearest
inductor to the controller.
Rev. A | Page 26 of 28
ADP3188
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 18. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
0.390
BSC
28
1
15
14
0.154
BSC
0.236
BSC
PIN 1
0.069
0.053
0.065
0.049
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AF
Figure 19. 28-Lead Shrink Small Outline Package [QSOP]
(RQ-28)
Dimensions shown in inches
ORDERING GUIDE
Model
ADP3188JRUZ-REEL1
ADP3188JRQZ-REEL1
Teꢀperature Range
Package Description
Package Option
RU-28
Quantity per Reel
0°C to 85°C
0°C to 85°C
Thin Shrink Small Outline Package 13” Reel
Shrink Small Outline Package 13” Reel
2500
2500
RQ-28
1 Z = Pb-free part.
Rev. A | Page 27 of 28
ADP3188
NOTES
©
200. Analog Devices, Inc9 All rights reserved9 Tradeꢀarks
and registered tradeꢀarks are the property of their respective owners9
D0483.–0–4/0.(A)
Rev. A | Page 28 of 28
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