ADP3194 [ADI]
6-Bit, Programmable 2-/3-/4-Phase, Synchronous Buck Controller; 6位，可编程的双/三/四相，同步降压控制器
| 型号： | ADP3194 |
| 厂家： | 
ADI |
| 描述： | 6-Bit, Programmable 2-/3-/4-Phase, Synchronous Buck Controller |
| 文件： | 总32页 (文件大小：1118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.DataSheet4U.com
6-Bit, Programmable 2-/3-/4-Phase,
Synchronous Buck Controller
ADP3194
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCC
RAMPADJ RT
Selectable 2-, 3-, or 4-phase operation
Up to 1 MHz per phase
±±9. ꢀV worst-case differential sensing error
over teꢀperature
Logic-level PWM outputs for interface to external
high power drivers
PWM Flex-ModeTM architecture for excellent load
transient perforꢀance
Active current balancing between all output phases
Built-in power good/crowbar blanking supports OTF VID
code changes
6-bit digitally prograꢀꢀable 09837. V to 196 V output
Prograꢀꢀable short circuit protection with prograꢀꢀable
latch-off delay
28
14 13
ADP3194
SHUNT
REGULATOR
OSCILLATOR
UVLO
SHUTDOWN
AND BIAS
11
EN
SET
EN
RESET
27 PWM1
26 PWM2
CMP
CMP
CMP
CMP
GND 19
DAC + 150mV
RESET
CSREF
2-/3-/4-PHASE
DRIVER LOGIC
CURRENT-
BALANCING
CIRCUIT
RESET
25 PWM3
DAC – 250mV
RESET
24
PWM4
DELAY
10
PWRGD
ILIMIT
CROWBAR
CURRENT
LIMIT
SW1
SW2
SW3
SW4
23
22
21
20
15
12
EN
APPLICATIONS
CSSUM
17
CURRENT-
LIMIT
CIRCUIT
Desktop PC power supplies for
Next-generation Intel® processors
VRM ꢀodules
DELAY
COMP
16 CSREF
SOFT
START
18
CSCOMP
Gaꢀes consoles
8
FB
9
PRECISION
REFERENCE
VID
DAC
7
1
2
3
4
5
6
FBRTN
VID4 VID3 VID2 VID1 VID0 VID5
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The ADP31941 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
5 V or 12 V main supply into the core supply voltage required
by high performance Intel processors. It uses an internal 6-bit
DAC to read a voltage identification (VID) code directly from
the processor that is used to set the output voltage between
0.8375 V and 1.6 V. The device uses a multimode PWM archi-
tecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VR size and
efficiency. The phase relationship of the output signals can be
programmed to provide 2-, 3-, or 4-phase operation, allowing
for the construction of up to four complementary buck switch-
ing stages.
The ADP3194 also includes programmable, no-load offset,
and slope functions to adjust the output voltage as a function
of the load current, so it is always optimally positioned for a
system transient. The ADP3194 also provides accurate and
reliable short-circuit protection, adjustable current limiting,
and a delayed power good output that accommodates on-the-
fly (OTF) output voltage changes requested by the CPU.
The devices are specified over the commercial temperature
range of 0°C to +85°C and are available in a 28-lead TSSOP.
1 Protected by U. S. Patent Number 6,683,441; other patents pending.
Rev9 0
Inforꢀation furnished by Analog Devices is believed to be accurate and reliable9 However, no
responsibility is assuꢀed by Analog Devices for its use, nor for any infringeꢀents of patents or other
rights of third parties that ꢀay result froꢀ its use9 Specifications subject to change without notice9 No
license is granted by iꢀplication or otherwise under any patent or patent rights of Analog Devices9
Tradeꢀarks and registeredtradeꢀarks arethe property of their respective owners9
One Technology Way, P9O9 Box ±106, Norwood, MA 02062-±106, U9S9A9
Tel: 781932±94700
Fax: 781946193113
www9analog9coꢀ
©2006 Analog Devices, Inc9 All rights reserved9
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ADP3194
TABLE OF CONTENTS
Features .............................................................................................. 1
Designing an Inductor............................................................... 14
Sense Resistor.............................................................................. 14
Sense Resistor Selection ............................................................ 14
Output Droop Resistance–Sense Resistor............................... 14
Output Offset.............................................................................. 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristic and Test Circuits ................ 7
Theory of Operation ........................................................................ 8
Startup Sequence .......................................................................... 8
Master Clock Frequency.............................................................. 8
Output Voltage Differential Sensing.......................................... 8
Output Current Sensing .............................................................. 8
Active Impedance Control Mode............................................... 9
Current-Control Mode and Thermal Balance.......................... 9
Voltage Control Mode.................................................................. 9
Soft Start ........................................................................................ 9
Current-Limit, Short-Circuit, and Latch-Off Protection...... 10
Dynamic VID.............................................................................. 10
Power Good Monitoring ........................................................... 12
Output Crowbar ......................................................................... 12
Output Enable and UVLO ........................................................ 12
Application Information................................................................ 13
Setting the Clock Frequency..................................................... 13
Soft Start and Current-Limit Latch-Off Delay Times ........... 13
Inductor Selection ...................................................................... 13
Design Comparison Trade-Off Between DCR and Sense
Resistor ........................................................................................ 15
COUT Selection ............................................................................. 16
Ramp Resistor Selection............................................................ 17
COMP Pin Ramp ....................................................................... 17
Current-Limit Setpoint.............................................................. 17
Feedback Loop Compensation Design.................................... 17
CIN Selection and Input Current di/dt Reduction.................. 19
Tuning the ADP3194 ................................................................. 20
RAMPADJ Filter......................................................................... 22
Shunt Resistor Design................................................................ 22
Design Example Using DCR Method.......................................... 23
Inductor Selection Using DCR................................................. 23
Designing an Inductor Using DCR.......................................... 23
Inductor DCR Temperature Correction ................................. 23
Output Droop Resistance–DCR Method................................ 24
Power MOSFETs......................................................................... 24
Layout and Component Placement.............................................. 26
General Recommendations....................................................... 26
Power Circuitry Recommendations ........................................ 26
Signal Circuitry Recommendations......................................... 26
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
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ADP3194
SPECIFICATIONS
VCC = 5 V, FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted.1
Table 1.
Paraꢀeter
Syꢀbol Conditions
Min
Typ
Max Unit
ERROR AMPLIFIER
Output Voltage Range
Accuracy
VCOMP
VFB
0
−8.0
VCC
+8.0
V
mV
Relative to nominal DAC output, referenced
to FBRTN, CSSUM = CSCOMP; VOUT < 1 V
Accuracy
VFB
Relative to nominal DAC output, referenced
to FBRTN, CSSUM = CSCOMP; VOUT > 1 V
VCC = 4.75 V to 5.25 V
−9.5
14
+9.5
mV
Line Regulation
0.05
15.5
100
500
20
%
ΔVFB
IFB
IFBRTN
IO(ERR)
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
17
140
μA
μA
μA
MHz
V/μs
FB forced to VOUT – 3%
GBW(ERR) COMP = FB
CCOMP = 10 pF
25
VID INPUTS
Input Low Voltage
Input High Voltage
VIL(VID)
VIH(VID)
0.4
V
V
0.8
Input Current, Input Voltage Low
Input Current, Input Voltage High
Pull-Up Resistance
Internal Pull-Up Voltage
VID Transition Delay Time2
No CPU Detection Turn-Off Delay Time2
OSCILLATOR
IIL(VIDX)
IIH(VIDX)
RVID
VID(X) = 0 V
VID(X) = 1.25 V
–25
5
60
1.2
–35
15
85
μA
μA
kΩ
V
ns
ns
35
1.0
400
400
VID code change to FB change
VID code change to 11111 to PWM going low
Frequency Range2
Frequency Variation
fOSC
fPHASE
0.25
1.55
4.5
2.45
MHz
MHz
MHz
MHz
V
TA = +25°C, RT = 247 kΩ, 4-phase
TA = +25°C, RT = 138 kΩ, 4-phase
TA = +25°C, RT = 84 kΩ, 4-phase
RT = 100 kΩ to GND
2
3
4
2.0
Output Voltage
VRT
VRAMPADJ
IRAMPADJ
1.8
–50
0
2.3
+50
100
RAMPADJ Output Voltage
RAMPADJ Input Current Range
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common-Mode Range
Positioning Accuracy
Output Voltage Range
Output Current
RAMPADJ – FB
mV
μA
VOS(CSA)
IBIAS(CSSUM)
GBW(CSA)
CSSUM – CSREF
–1.5
–10
+1.5
+10
mV
nA
MHz
V/μs
V
mV
V
μA
10
10
CCSCOMP = 10 pF
CSSUM and CSREF
0
–77
0.05
3
–83
VCC
–80
500
ΔVFB
ICSCOMP
CURRENT BALANCE CIRCUIT
Common-Mode Range
Input Resistance
Input Current
Input Current Matching3
VSW(X)CM
RSW(X)
ISW(X)
–600
12
5
+200 mV
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
20
11
28
17
+5
kΩ
μA
%
–5
ΔISW(X)
Rev. 0 | Page 3 of 32
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ADP3194
Paraꢀeter
Syꢀbol Conditions
Min
Typ
Max Unit
CURRENT LIMIT COMPARATOR
Output Voltage
Normal Mode
VILIMIT(NM) EN > 0.8 V, RILIMIT = 250 kΩ
2.8
3
3.3
V
Shutdown Mode
VILIMIT(SD)
IILIMIT(NM)
EN < 0.4 V, IILIMIT = –100 μA
EN > 0.8 V, RILIMIT = 250 kΩ
400
mV
μA
μA
mV
mV/μA
V
Output Current, Normal Mode
Maximum Output Current2
Current Limit Threshold Voltage
Current Limit Setting Ratio
DELAY Normal Mode Voltage
DELAY Overcurrent Threshold
Latch-Off Delay Time
SOFT START
12
60
105
VCL
VCSREF – VCSCOMP, RILIMIT = 250 kΩ
VCL/IILIMIT
125
10.4
3
1.9
1.5
145
VDELAY(NM) RDELAY = 250 kΩ
VDELAY(OC) RDELAY = 250 kΩ
tDELAY
2.8
1.6
3.3
2.2
V
ms
RDELAY = 250 kΩ, CDELAY = 12 nF
Output Current, Soft Start Mode
Soft Start Delay Time
ENABLE INPUT
IDELAY(SS)
tDELAY(SS)
During startup, DELAY < 2.8 V
RDELAY = 250 kΩ, CDELAY = 12 nF, VID code = 011111
15
20
1
25
μA
ms
Input Low Voltage
Input High Voltage
Input Current
VIL(EN)
VIH(EN)
IIL(EN)
0.4
+1
V
V
μA
0.8
–1
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Power Good Delay Time
During Soft Start
VID Code Changing
VID Code Static
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
VPWRGD(UV) Relative to nominal DAC output
VPWRGD(OV) Relative to nominal DAC output
VOL(PWRGD) IPWRGD(SINK) = 4 mA
–180
90
–250
150
225
–300 mV
200
400
mV
mV
RDELAY = 250 kΩ, CDELAY = 12 nF, VID code = 011111
1
100
ms
μs
ns
250
200
150
550
VCROWBAR
tCROWBAR
Relative to nominal DAC output
Relative to FBRTN
Overvoltage to PWM going low
Blanking time
90
450
200
650
mV
mV
100
250
400
μs
ns
PWM OUTPUTS
Output Low Voltage
Output High Voltage
SUPPLY—ADP3194
VCC
DC Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
VOL(PWM)
VOH(PWM)
IPWM(SINK) = –400 μA
IPWM(SOURCE) = +400 μA
VSYSTEM = 12 V, RSHUNT = 300 Ω
160
5
500
mV
V
4.0
VCC
4.75
6.3
5
20
7
V
mA
V
30
8.0
VUVLO
VCC rising
0.9
V
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 Guaranteed by design, not production tested.
3 Relative current matching from each phase to the average of all four phases.
Rev. 0 | Page 4 of 32
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ADP3194
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Paraꢀeter
Rating
VCC
–0.3 V to +6 V
–0.3 V to +6 V
–0.3 V to +0.3 V
−5 V to +25 V
–0.3 V to VCC + 0.3 V
–65°C to +150°C
0°C to +85°C
125°C
VID4 to VID0, VID5
FBRTN
SW1 to SW4
All Other Inputs and Outputs
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA)
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages
are referenced to GND.
100°C/W
ESD CAUTION
300°C
215°C
220°C
Rev. 0 | Page 5 of 32
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ADP3194
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VCC
2
VID3
PWM1
PWM2
PWM3
PWM4
SW1
3
VID2
4
VID1
5
VID0
ADP3194
TOP VIEW
(Not to Scale)
6
VID5
7
FBRTN
FB
SW2
8
SW3
9
COMP
PWRGD
EN
SW4
10
11
12
13
14
GND
CSCOMP
CSSUM
CSREF
ILIMIT
DELAY
RT
RAMPADJ
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No9
Mneꢀonic
Description
1 to 6
VID4 to VID0, Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing Logic 1
VID5
is left open. When in normal operation mode, the DAC output programs the FB regulation voltage from
0.8375 V to 1.6 V (see Table 2). Leaving all the VID pins open results in ADP3194 going into a No CPU mode,
shutting off their PWM outputs and pulling the PWRGD output low.
7
8
FBRTN
FB
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no-load offset point.
9
COMP
Error Amplifier Output and Compensation Point.
10
PWRGD
Power Good Output. Open drain output that signals when the output voltage is outside of the proper oper-
ating range.
11
12
EN
DELAY
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
Soft Start Delay and Current-Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time.
13
14
15
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit thresh
old of the converter. This pin is actively pulled low when the ADP3194 EN input is low or when VCC is below
its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.
RAMPADJ
ILIMIT
16
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the power good and crowbar functions. This pin should be connected to the common point of
the output inductors.
17
18
CSSUM
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the slope of the
load line and the positioning loop response time.
CSCOMP
19
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23
SW4 to SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. Leave the SW pins of unused
phases open.
24 to 27
28
PWM4 to
PMW1
Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3120A. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the
ADP3194 to operate as a 2-, 3-, or 4-phase controller.
VCC
A 300 Ω resistor should be placed between the 12 V system supply and the VCC pin to ensure 5 V.
Rev. 0 | Page 6 of 32
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ADP3194
TYPICAL PERFORMANCE CHARACTERISTIC AND TEST CIRCUITS
7000
6000
5000
4000
3000
2000
1000
0
12V
ADP3194
300Ω
VCC
28
18
CSCOMP
CSSUM
CSREF
GND
100nF
39kΩ
17
16
19
1kΩ
1.0V
CSCOMP – 1V
V
=
OS
40
0
100
200
300
400
500
(kΩ)
600
700
800
900
R
T
Figure 3. Master Clock Frequency vs. RT (kΩ)
Figure 5. Current Sense Amplifier VOS
12V
ADP3194
300Ω
1
2
VCC 28
VID4
VID3
VID2
VID1
VID0
VID5
FBRTN
FB
+
1µF
100nF
27
26
PWM1
PWM2
3
6-BIT CODE
4
PWM3 25
5
24
23
22
21
20
19
PWM4
SW1
SW2
SW3
SW4
GND
12V
6
ADP3194
300Ω
7
VCC
28
18
8
1kΩ
CSCOMP
9
200kΩ
COMP
PWRGD
EN
10
11
12
13
100nF
200kΩ
ΔV
CSSUM
CSREF
GND
1.25V
CSCOMP 18
CSSUM 17
CSREF 16
17
16
19
20kΩ
100nF
DELAY
RT
250kΩ
12nF
1.0V
ILIMIT
14 RAMPADJ
15
250kΩ
ΔV = FB = 80mV – FB = 0mV
FB ΔV ΔV
Figure 4. Closed-Loop Output Voltage Accuracy
Figure 6. Positioning Voltage
Rev. 0 | Page 7 of 32
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ADP3194
THEORY OF OPERATION
After this time, if the PWM output is not grounded, the 5 kΩ
resistance is removed and it switches between 0 V and 5 V. If the
PWM output is grounded, it remains off. The PWM outputs are
logic-level devices intended for driving external gate drivers,
such as the ADP3120A. Because each phase is monitored inde-
pendently, operation approaching 100% duty cycle is possible.
Also, more than one output can be on at the same time for
overlapping phases.
The ADP3194 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal VID DAC is designed to interface with the Intel
6-bit VRD/VRM 10- and 10.1-compatible CPUs. Multiphase
operation is important for producing the high currents and
low voltages demanded by today’s microprocessors. Handling
the high currents in a single-phase converter places high thermal
demands on the components in the system, such as the inductors
and MOSFETs.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3194 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 3. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, divide the master clock by 3 for the fre-
quency of the remaining phases. If PWM3 and PWM4 are
grounded, divide by 2. If all phases are in use, divide by 4.
The multimode control of the ADP3194 ensures a stable, high
performance topology for
•
•
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
•
Minimizing thermal switching losses due to lower
frequency operation
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3194 differential sense compares a high accuracy VID
DAC and a precision reference to implement a low offset error
amplifier. This maintains a worst-case specification of 9.5 mV
differential sensing error over their full operating output voltage
and temperature range. The output voltage is sensed between
the FB pin and the FBRTN pin. Connect FB through a resistor
to the regulation point, usually the remote sense pin of the
microprocessor. Connect FBRTN directly to the remote sense
ground point. The internal VID DAC and precision reference
are referenced to FBRTN, which has a minimal current of 100 μA
to allow accurate remote sensing. The internal error amplifier
compares the output of the DAC to the FB pin to regulate the
output voltage.
•
•
•
•
•
Tight load line regulation and accuracy
High current output for up to 4-phase operation
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
•
Flexibility in operation for tailoring design to low cost or
high performance
STARTUP SEQUENCE
During startup, the number of operational phases and their phase
relationship is determined by the internal circuitry that monitors
the PWM outputs. Normally, the ADP3194 operate as a 4-phase
PWM controller. Grounding the PWM4 pin programs 3-phase
operation, and grounding the PWM3 pin and the PWM4 pin
programs 2-phase operation.
OUTPUT CURRENT SENSING
The ADP3194 provide a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current-limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element, such as the low-side MOSFET.
This amplifier can be configured several ways, depending on
the objectives of the system:
When the ADP3194 are enabled, the controller outputs a volt-
age on PWM3 and PWM4, which is approximately 675 mV.
An internal comparator checks each pin’s voltage vs. a threshold
of 300 mV. If the pin is grounded, it is below the threshold, and
the phase is disabled. The output resistance of the PWM pins is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pins should not be
less than 25 kΩ to ensure proper operation. PWM1 and PWM2
are disabled during the phase detection interval that occurs during
the first two clock cycles of the internal oscillator.
Output inductor DCR sensing without a thermistor for
lowest cost,
Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature,
Sense resistors for highest accuracy measurements.
Rev. 0 | Page 8 of 32
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ADP3194
The positive input of the CSA is connected to the CSREF pin,
External resistors can be placed in series with individual phases
to create, if desired, an intentional current imbalance such as
when one phase may have better cooling and can support higher
currents. Resistor RSW1 through Resistor RSW4 (see the typical
application circuit in Figure 19 and Figure 20) can be used for
adjusting thermal balance. It is best to have the ability to add
these resistors during the initial design, so make sure that place-
holders are provided in the layout.
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resis-
tor between CSCOMP and CSSUM sets the gain of the amplifier
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor to set the load line required by the microprocessor.
The current information is then given as the difference of
CSREF − CSCOMP. This difference signal is used internally to
offset the VID DAC for voltage positioning and as a differential
input for the current-limit comparator.
To increase the current in any given phase, make RSW for this
phase larger (make RSW = 0 for the hottest phase, and do not
change during balancing). Increasing RSW to only 500 Ω makes
a substantial increase in phase current. Increase each RSW value
by small amounts to achieve balance, starting with the coolest
phase first.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing
gain is determined by external resistors, so it can be made
extremely accurate.
VOLTAGE CONTROL MODE
A high gain bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID logic according to the voltages
listed in Table 4. This voltage is also offset by the droop voltage
for active positioning of the output voltage as a function of the
current, commonly known as active voltage positioning. The
output of the amplifier is the COMP pin, which sets the termi-
nation voltage for the internal PWM ramps.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output current
at the CSCOMP pin can be scaled to equal the droop imped-
ance of the regulator multiplied by the output current. This
droop voltage is then used to set the input control voltage to
the system. The droop voltage is subtracted from the DAC
reference input voltage directly to tell the error amplifier where
the output voltage should be. This differs from previous imple-
mentations and allows an enhanced feed-forward response.
The negative input (FB) is tied to the output sense location with
a resistor (RB) and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is negative with respect
to the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.
CURRENT-CONTROL MODE AND
THERMAL BALANCE
The ADP3194 has individual inputs for each phase, which are
used for monitoring the current in each phase. This informa-
tion is combined with an internal ramp to create a current
balancing feedback system, which has been optimized for
initial current balance accuracy and dynamic thermal bal-
ancing during operation. This current-balance information is
independent of the average output current information used
for positioning described previously.
SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current-limit latch-off
time. In UVLO, or when EN is logic low, the DELAY pin is held
at ground. After the UVLO threshold is reached and EN is logic
high, the DELAY capacitor is charged with an internal 20 μA
current source. The output voltage follows the ramping voltage
on the DELAY pin, limiting the inrush current. The soft start
time depends on the value of the VID DAC and CDLY, with a
secondary effect from RDLY. See the Application Information
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the RAMPADJ
pin determines the slope of the internal PWM ramp. Detailed
information about programming the ramp is given in the
Application Information section.
section for detailed information on setting CDLY
.
If EN is taken low or if VCC drops below UVLO, the DELAY
capacitor is reset to ground to be ready for another soft start
cycle. Figure 7 shows a typical soft start sequence for the ADP3194.
Rev. 0 | Page 9 of 32
www.DataSheet4U.com
ADP3194
This prevents the DELAY capacitor from discharging, so the
1.8 V threshold is never reached. The resistor has an impact on
the soft start time because the current through it adds to the
internal 20 μA current source.
During startup, when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This sec-
ondary current limit controls the internal COMP voltage to the
PWM comparators to 2 V. This limits the voltage drop across
the low-side MOSFETs through the current balance circuitry.
An inherent per phase current limit protects individual phases,
if one or more phases stops functioning because of a faulty com-
ponent. This limit is based on the maximum normal mode
COMP voltage.
Figure 7. Typical Start-Up Waveforms
Channel 1: PWRGD, Channel 2: CSREF,
Channel 3: DELAY, Channel 4: COMP
CURRENT-LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3194 compares a programmable current-limit setpoint
to the voltage from the output of the current sense amplifier. The
level of current limit is set with the resistor from the ILIMIT pin
to ground. During normal operation, the voltage on ILIMIT is
3 V. The current through the external resistor is internally scaled
to give a current-limit threshold of 10.4 mV/μA. If the difference in
voltage between CSREF and CSCOMP rises above the current-
limit threshold, the internal current-limit amplifier controls the
internal COMP voltage to maintain the average output current at
the limit.
Figure 8. Overcurrent Latch-Off Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: COMP, Channel 4: Phase 1 Switch Node
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops below
1.8 V. The current-limit latch-off delay time is, therefore, set by the
RC time constant discharging from 3 V to 1.8 V. The Application
DYNAMIC VID
The ADP3194 has the ability to dynamically change the VID
input while the controller is running. This allows the output
voltage to change while the supply is running and supplying
current to the load. This is commonly referred to as VID OTF.
A VID OTF can occur under either light or heavy load conditions.
The processor signals the controller by changing the VID inputs
in multiple steps from the start code to the finish code. This
change can be positive or negative.
Information section discusses the selection of CDLY and RDLY
.
Because the controller continues to cycle the phases during the
latch-off delay time, the controller returns to normal operation
if the short is removed before the 1.8 V threshold is reached.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has caused
the output voltage to drop below the PWRGD threshold, a soft
start cycle is initiated.
When a VID input changes state, the ADP3194 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the six
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and crowbar blanking functions for a
minimum of 100 μs to prevent a false PWRGD or crowbar
event. Each VID change resets the internal timer.
The latch-off function can be reset by either removing and reap-
plying VCC to the ADP3194 or by pulling the EN pin low for a
short time. To disable the short-circuit latch-off function, the
external resistor to ground should be left open, and a high value
(>1 MΩ) resistor should be connected from DELAY to VCC.
Rev. 0 | Page 10 of 32
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ADP3194
Table 4. VID Codes for the ADP3194
VID4
VID3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
VID2
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
VID1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
VID0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
VID.
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
No CPU
No CPU
0.8375 V
0.8500 V
0.8625 V
0.8750 V
0.8875 V
0.9000 V
0.9125 V
0.9250 V
0.9375 V
0.9500 V
0.9625 V
0.9750 V
0.9875 V
1.0000 V
1.0125 V
1.0250 V
1.0375 V
1.0500 V
1.0625 V
1.0750 V
1.0875 V
1.1000 V
1.1125 V
1.1250 V
1.1375 V
1.1500 V
1.1625 V
1.1750 V
1.1875 V
1.2000 V
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID2
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
VID1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VID.
Output
1.2125 V
1.2250 V
1.2375 V
1.2500 V
1.2625 V
1.2750 V
1.2875 V
1.3000 V
1.3125 V
1.3250 V
1.3375 V
1.3500 V
1.3625 V
1.3750 V
1.3875 V
1.4000 V
1.4125 V
1.4250 V
1.4375 V
1.4500 V
1.4625 V
1.4750 V
1.4875 V
1.5000 V
1.5125 V
1.5250 V
1.5375 V
1.5500 V
1.5625 V
1.5750 V
1.5875 V
1.6000 V
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 0 | Page 11 of 32
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ADP3194
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over-
voltage is due to a short in the high-side MOSFET, this action
current-limits the input supply or blows its fuse, protecting the
microprocessor from being destroyed.
POWER GOOD MONITORING
The power good comparator monitors the output voltage via the
CSREF pin. The PWRGD pin is an open-drain output whose high
level (when connected to a pull-up resistor) indicates that the
output voltage is within the nominal limits specified in Table 4.
These limits are based on the VID voltage setting. PWRGD
goes low if the output voltage is outside of this specified range,
if all of the VID DAC inputs are high, or whenever the EN pin
is pulled low. PWRGD is blanked during a VID OTF event for
a period of 250 μs to prevent false signals during the time the
output is changing.
OUTPUT ENABLE AND UVLO
For the ADP3194 to begin switching, the input supply (VCC)
to the controller must be higher than the UVLO threshold, and
the EN pin must be higher than its logic threshold. If UVLO is
less than the threshold or the EN pin is logic low, the ADP3194
is disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at ground.
The PWRGD circuitry also incorporates an initial turn-on delay
time based on the DELAY ramp. The PWRGD pin is held low
until the DELAY pin reaches 2.6 V. The time between when the
PWRGD undervoltage threshold is reached and when the DELAY
pin reaches 2.6 V provides the turn-on delay time. This time is
incorporated into the soft start ramp. To ensure a 1 ms delay
time on PWRGD, the soft start ramp must also be >1 ms. See
the Application Information section for detailed information on
In the application circuit, the ILIMIT pin should be connected
to the
pins of the ADP3120A drivers. Grounding ILIMIT
OD
disables the drivers so that both the DRVH and DRVL are also
grounded. This feature is important in preventing the discharge
of the output capacitors when the controller is shut off. If the
driver outputs were not disabled, a negative voltage could be
generated during output due to the high current discharge of
the output capacitors through the inductors.
setting CDLY
.
OUTPUT CROWBAR
As part of the protection for the load and output components
of the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately 550 mV.
Rev. 0 | Page 12 of 32
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ADP3194
APPLICATION INFORMATION
The design parameters for a typical Intel VRD 10.1-compliant
CPU application are as follows:
However, as long as RDLY is kept greater than 200 kΩ, this effect
is minor. The value for CDLY can be approximated by
•
•
•
•
•
•
Input voltage (VIN) = 12 V
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VVID
2 × RDLY
tSS
VVID
⎜
(2)
CDLY = 20 μA−
×
VID setting voltage (VVID) = 1.300 V
Duty cycle (D) = 0.108
where tSS is the desired soft start time.
Nominal output voltage at no load (VONL) = 1.281 V
Nominal output voltage at 101 A load (VOFL) = 1.159 V
Static output voltage drop based on a 1.2 mΩ load line
(RO) from no load to full load (VD) = VONL − VOFL
1.281 V − 1.159 V = 121.2 mV
Assuming an RDLY of 390 kΩ and a desired soft start time of 3 ms,
CDLY is 36 nF. The closest standard value for CDLY is 39 nF. Once
DLY is chosen, RDLY can be calculated for the current-limit latch-
C
off time by
=
1.96 ×tDELAY
RDLY
=
(3)
CDLY
•
•
•
•
Maximum output current (IO) = 120 A
Maximum output current step (ΔIO) = 85 A
Number of phases (n) = 4
If the result for RDLY is less than 200 kΩ, a smaller soft start time
should be considered by recalculating Equation 2, or a longer latch-
off time should be used. RDLY should never be less than 200 kΩ.
In this example, a delay time of 9 ms results in RDLY = 452 kΩ.
The closest standard 5% value is 470 kΩ.
Switching frequency per phase (fSW) = 1.125 MHz
SETTING THE CLOCK FREQUENCY
INDUCTOR SELECTION
The ADP3194 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and/or the input and output capaci-
tors. With n = 4 for four phases, a clock frequency of 4 MHz
sets the switching frequency (fSW) of each phase to 1 MHz,
which represents a practical trade-off between the switching
losses and the sizes of the output filter components. Figure 3
shows that to achieve
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs; but it allows using smaller inductors
and, for a specified peak-to-peak transient deviation, less total
output capacitance.
Conversely, a higher inductance means lower ripple current
and reduced conduction losses but requires larger inductors
and more output capacitance for the same peak-to-peak transient
deviation. In any multiphase converter, a practical value for the
peak-to-peak inductor ripple current is less than 50% of the
maximum dc current in the same inductor. Equation 4 shows
the relationship between the inductance, oscillator frequency,
and peak-to-peak ripple current in the inductor.
4 MHz oscillator frequency, the correct value for RT is 84 kΩ.
3 MHz oscillator frequency, the correct value for RT is 138 kΩ.
2 MHz oscillator frequency, the correct value for RT is 247 kΩ.
Alternatively, the value for RT can be calculated using
3
RT =
−79 kΩ
(1)
VVID
×
(
1− D
)
n × fSW × 4.6 pF
IR
=
(4)
fSW × L
where 4.6 pF and 79 kΩ are internal IC component values. For
good initial accuracy and frequency stability, a 1% resistor is
recommended.
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
VVID × RO ×
1−
n × D
SOFT START AND CURRENT-LIMIT LATCH-OFF
DELAY TIMES
L ≥
(5)
fSW ×VRIPPLE
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
1.3 V ×1.2 mꢀ × 1−0.108
Because the soft start and current-limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set CDLY for the soft start ramp. This
ramp is generated with a 20 μA internal current source. The value
of RDLY has a second-order impact on the soft start time because
it sinks part of the current source to ground.
(
)
L ≥
= 280 nH
1.125 MHz × 4.4 mV
If the resulting ripple voltage is less than it was designed for, make
the inductor smaller until the ripple value is met. This allows
optimal transient response and minimum output decoupling.
Rev. 0 | Page 13 of 32
www.DataSheet4U.com
ADP3194
The smallest possible inductor should be used to minimize the
number of output capacitors. For this example, choosing a 280 nH
inductor is a good starting point and gives a calculated ripple
current of 3.68 A. The inductor should not saturate at the peak
current of 31.84 A and should be able to handle the sum of the
power dissipation caused by the average current of 30 A in the
winding and core loss.
SENSE RESISTOR SELECTION
The resistance value of the sense resistor must be chosen to
minimize the conduction loss, but be large enough for accurate
current measurement. The lower the resistance, the lower the
signal to noise ratio that appears at the ADP3194 input. This
directly affects the current sense accuracy. A sense resistor of
1 mꢀ is chosen. The power loss in the resistor is calculated as:
DESIGNING AN INDUCTOR
PRS = I 2 × RSENSE
(6)
Once the inductance is known, the next step is either to design
an inductor or to find a standard inductor that comes as close as
possible to meeting the overall design goals.
If the design has 30 A per phase, then:
PRS = 30A × 30A ×1 mꢀ = 900 mW
The first decision in designing the inductor is to choose the core
material. Several possibilities for providing low core loss at high
frequencies include the powder cores (for example, Kool-Mμ®
from Magnetics, Inc. or from Micrometals) and the gapped soft
ferrite cores (for example, 3F3 or 3F4 from Philips). Avoid low
frequency powdered iron cores due to their high core loss, espe-
cially when the inductor value is relatively low and the ripple
current is high.
This results in a 900mW conduction loss through the sense
resistor in a 30 A per phase design. Therefore, a 1 mꢀ, 1 W sense
resistor is chosen. There is a parasitic inductance (LP) associated
with the sense resistor. This value can be found on the data sheet of
the sense resistor. A typical value is of the order of 2.2 nH.
OUTPUT DROOP RESISTANCE–SENSE RESISTOR
The design requires the regulator output voltage measured at
the CPU pins to drop when the output current increases. The
specified voltage drop corresponds to a dc output resistance (RO).
The best choice for a core geometry is a closed-loop type such
as a potentiometer core, PQ, U, or E core or toroid. A good
compromise between price and performance is a core with a
toroidal shape.
The output current is measured by summing the voltage across
each inductor and passing the signal through a low-pass filter.
This summer filter is the CS amplifier configured with resistors
Many useful magnetics design references are available for
quickly designing a power inductor, such as Magnetic Designer
Software™ by Intusoft and Designing Magnetic Components for
High-Frequency DC-DC Converters, by William T. McLyman,
KG Magnetics, Inc., ISBN 1883107008.
R
PH(X) (summers), and RCS and CCS (filter). The output resistance
of the regulator is set by the following equations:
RCS
RO =
× RSENSE
(7)
(8)
RPH
(X)
Selecting a Standard Inductor
LP
RSENSE × RCS
CCS
=
Power inductor manufacturers can provide design consulta-
tion and deliver power inductors optimized for high power
applications upon request. Such manufacturers include
Coilcraft, Coiltronics, Sumida Electric Company, and Vishay
Intertechnology.
where RSENSE is the resistance of the sense resistor.
The user has the flexibility of choosing either RCS or RPH(X). It is
best to select RCS equal to 100 kΩ, and then solve for RPH(X) by
rearranging Equation 6.
SENSE RESISTOR
RSENSE
RO
A dedicated sense resistor can be used for current sensing. An
advantage to this is the fact that there is much less temperature
variation than using the DCR method. Therefore, a thermistor
is not required. The trade-off is that a sense resistor is required
for each phase. So, one thermistor is saved, but four sense resistors
are needed in a four phase design. Also, there is extra power dissi-
pation due to the sense resistor in series with the power delivery.
(9)
RPH(X)
=
× RCS
1.0 mꢀ
1.2 mꢀ
RPH(X)
=
×100 kꢀ = 82.5 kꢀ
Next, use Equation 8 to solve for CCS.
2.2 nH
1.0 mꢀ ×100 kꢀ
CCS
=
= 220 pF
Therefore, set RCS equal to 100 kΩ, CCS equal to 220 pF, and RPH
equal to 82.5 kΩ.
Rev. 0 | Page 14 of 32
www.DataSheet4U.com
ADP3194
SENSE
1mΩ
1W
L2
280nH
560µF/4V × n
SANYO SEPC SERIES
V
CC (CORE)
+
+
V
CC (CORE) RTN
28
18
VCC
R
PH1
ADP3194
R
CB1
CSCOMP
CSSUM
CSREF
KEEP THIS PATH
C
C
CB1
CB2
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES.
17
16
Figure 9. Using a Sense Resistor
OUTPUT OFFSET
Table 5. Input Parameters
The Intel specification requires that at no load should the nomi-
nal output voltage of the regulator be offset to a value lower than
the nominal voltage corresponding to the VID code. The offset
is set by a constant current source flowing out of the FB pin (IFB)
and flowing through RB. The value of RB can be found using
Equation 10:
Design Inputs
Sense Resistor Method
DCR Method
Value
4
1.00 mΩ
1.00 mΩ
120.0 A
90.0 A
20%
5%
5%
70°C
26.6%
19.0 mV
8.0 mV
6.0 A
Paraꢀeter
N
DCR
Loadline
Imax
Istep
L error
C error
RSENSE error
Temp Rise
RSENSE vs. Temp
No-load Offset
Total Output Vripple
Inductor Iripple
Gain Factor for TC
Value
4
1.00 mΩ
1.00 mΩ
120.0 A
90.0 A
0%
5%
1%
70°C
0.0 %
19.0 mV
8.0 mV
6.0 A
12
VVID −VONL
(10)
RB =
IFB
1.3 V−1.281 V
RB =
= 1.22 kꢀ
15.5 ꢁA
The closest standard 1% resistor value is 1.21 kΩ.
DESIGN COMPARISON TRADE-OFF BETWEEN DCR
AND SENSE RESISTOR
Cost
12
The inductor DCR method requires a thermistor, which costs
about $0.03. The RSENSE method requires an extra sense resistors
for each phase. This costs about 4 × $0.07 = $0.28. If it can also
meet the Intel accuracy specification of 25mV across the full
load range, then it is the preferred method in VR applications.
30
ERROR FROM LOADLINE (± AMOUNT SHOWN)
THIS CHART IS ACTIVE.
28
26
24
22
20
18
16
14
VRD10.1 SPEC
Accuracy
Table 5 shows the accuracy results for a 4-phase VR10.1 applica-
tion, using DCR method and sense resistor method. As can be
seen, the sense resistor method improves the accuracy slightly.
However, since the DCR method meets the Intel specification,
it is the preferred solution, for cost reasons.
DCR METHOD
SENSE RESISTOR
METHOD
0
20
40
60
80
100
120
OUTPUT CURRENT (A)
Figure 10. Accuracy Comparison of DCR and Sense Resistor Methods
Rev. 0 | Page 15 of 32
www.DataSheet4U.com
ADP3194
larger than CX(MAX), the system cannot meet the VID OTF
specification and may require the use of a smaller inductor or
more phases (and may need the switching frequency to increase
to keep the out-put ripple the same).
COUT SELECTION
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
Also, to determine what is required, use some simple design
guidelines that are based on having both bulk and ceramic
capacitors in the system.
This example uses 18, 22 μF 1206 MLC capacitors (CZ = 396 μF).
The VID on-the-fly step change is 450 mV in 230 μs with a settling
error of 2.5 mV. The maximum allowable load release overshoot for
this example is 50 mV, so solving for the bulk capacitance yields
The first thing is to select the total amount of ceramic capaci-
tance. This is based on the number and type of capacitor to be
used. The best location for ceramic capacitors is inside the socket,
with 12 to 18 of Size 1206 being the physical limit. Additional
ceramic capacitors can be placed along the outer edge of the
socket as well.
⎛
⎜
⎞
⎟
⎜
⎜
⎜
⎟
280 nH ×85 A
⎟
CX(MIN)
≤
− 396 ꢁF = 2.16 mF
⎛
⎜
⎝
⎞
⎟
50 mV
⎜
⎟
⎟
⎠
4 × 1.2 mꢀ +
×1.3 V
⎜
⎜
⎟
⎟
85 A
⎝
⎠
Combined ceramic values of 200 μF to 400 μF are recommended,
usually made up of multiple 10 μF or 22 μF capacitors. Select
the number of ceramic capacitors, and find the total ceramic
capacitance (CZ).
280 nH × 450 mV
4 × 4.62 ×
1.2 mꢀ
2 ×1.3 V
CX(MAX)
≤
×
(
)
2
⎛
⎞
⎟
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎜
⎜
250 ꢁs ×1.3 V × 4 × 4.6×1.2 mꢀ
450 mV ×280 nH
Next, there is an upper limit imposed on the total amount of
bulk capacitance (CX) when considering the VID OTF voltage
stepping of the output (Voltage Step VV in Time tV with error
of VERR). A lower limit is based on meeting the capacitance for
load release for a given maximum load step, ∆IO, and a max-
imum allowable overshoot. The total amount of load release
voltage is given as
1+
−1 − 396 ꢁF = 40.5 mF
⎟
⎜
⎝
⎟
⎠
where K = 4.6.
Using four 560 μF Al-Poly capacitors with a typical ESR of
5 mΩ each yields CX = 2.24 mF with an RX = 1.25 mΩ.
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the high frequency
ringing during a load change. This is tested using
ΔVO = ΔIO × RO + ΔVrl
where ΔVrl is the maximum allowable overshoot voltage.
LX ≤CZ × RO2 ×Q2
⎛
⎜
⎞
⎟
(13)
LX ≤ 396ꢁF×
(
1.2 mꢀ 2
×2 =1.14 nH
)
⎜
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎟
⎠
L ×ꢂIO
ΔVrl
CX
≥
MIN )
− CZ
(11)
(
⎛
⎞
⎟
⎟
⎠
where Q is limited to the square root of 2 to ensure a critically
damped system.
⎜
n× RO +
×VVID
⎜
ΔIO
⎝
In this example, LX is approximately 175 pH for the four A1-Polys
capacitors, which satisfies this limitation. If the LX of the chosen
bulk capacitor bank is too large, the number of ceramic capaci-
tors may need to be increased if there is excessive ringing.
2
⎛
⎞
⎛
⎜
⎝
⎞
⎟
⎟
⎠
⎜
⎟
L
VV
VVID nKRO
⎜
CX(MAX)
=
×
×
1+ tV
×
−1 −C
⎜
⎜
⎝
⎟
Z
nK 2RO2 VVID
VV
L
⎟
⎠
(12)
For this multimode control technique, all ceramic designs can
be used as long as the conditions of Equation 11, Equation 12,
and Equation 13 are satisfied.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VERR
VV
where K = 1n
To meet the conditions of these equations and transient
response, the ESR of the bulk capacitor bank (RX) should be
less than two times the droop resistance (RO). If the CX(MIN) is
Rev. 0 | Page 16 of 32
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ADP3194
CURRENT-LIMIT SETPOINT
RAMP RESISTOR SELECTION
To select the current-limit setpoint, first find the resistor value
for RLIM. The current-limit threshold for the ADP3194 is set with a
3 V source (VLIM) across RLIM with a gain of 10.4 mV/μA (ALIM).
RLIM can be found using
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following equation is used for determining the
optimum value:
A
LIM ×VLIM
RLIM
=
(17)
I
LIM × RO
AR × L
RR =
3× AD × RDS ×CR
For values of RLIM greater than 500 kꢀ, the current limit can be
lower than expected, so some adjustment of RLIM may be needed.
Here, ILIM is the average current limit for the output of the supply.
In this example, choosing a peak current limit of 185 A for ILIM
results in RLIM = 140 kꢀ.
(14)
0.2 ×280 nH
RR =
=118 kΩ
3×5×6.33 mΩ ×5 pF
where:
The limit of the per-phase current-limit described earlier is
determined by
AR is the internal ramp amplifier gain
AD is the current balancing amplifier gain
RDS is the total low-side MOSFET on resistance
CR is the internal ramp capacitor value.
VCOMP
−VR −VBIAS
MAX )
IR
2
(
IPHLIM
≅
+
(18)
AD × RDS
(
MAX )
For the ADP3194, the maximum COMP voltage (VCOMP(MAX)) is
3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the current-
balancing amplifier gain (AD) is 5. Using VR of 0.35 V and RDS(MAX)
of 7 mꢀ, the per-phase peak current limit is calculated to be
51.8 A. Although this number may seem high, this current level
can be reached only with an absolute short at the output, and the
current-limit latch-off function shuts down the regulator before
overheating can occur.
The internal ramp voltage magnitude can be calculated by using
AR ×
RR × CR × fSW
(
1− D
) × VVID
VR =
(15)
0.2 ×
1− 0.108 ×1.3V
( )
VR =
= 350 mV
118 kΩ × 5 pF ×1.125 MHz
The size of the internal ramp can be made larger or smaller. If
it is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made smaller,
thermal balance improves at the sacrifice of transient response
and stability. The factor of 3 in the denominator of Equation 14
sets a ramp size that gives an optimal balance for good stability,
transient response, and thermal balance.
This limit can be adjusted by changing the ramp voltage (VR),
but make sure not to set the per-phase limit lower than the
average per-phase current (ILIM/n).
The per-phase initial duty cycle limit is determined by
VCOMP
) −VBIAS
(
MAX
DMAX = D ×
(19)
VRT
In this example, the maximum duty cycle is 0.46.
COMP PIN RAMP
A ramp signal on the COMP pin is due to the droop voltage
and output voltage ramps. This ramp amplitude adds to the
internal ramp to produce the following overall ramp signal at
the PWM input:
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3194 allows the best pos-
sible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output imped-
ance that is entirely resistive over the widest possible frequency
range, including dc, and equal to the droop resistance (RO).
VR
VRT
=
(16)
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2 ×
(
1−n× D
)
1−
n× fSW ×CX × RO
With the resistive output impedance, the output voltage droops
in proportion to the load current at any load current slew rate.
This ensures optimal positioning and allows minimization of
the output decoupling.
In this example, the overall ramp signal is 390 mV.
Rev. 0 | Page 17 of 32
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ADP3194
With the multimode feedback structure of the ADP3194, the
feedback compensation must be set to make the converter’s
output impedance, working in parallel with the output decoup-
ling, to meet this goal. Several poles and zeros created by the
output inductor and decoupling capacitors (output filter) need
to be compensated for.
CX ×C × R2
Z
O
TD =
(24)
CX ×
(
RO − R'
)
+ CZ × RO
where:
R' is the PCB resistance from the bulk capacitors to the ceramics
RDS is the total low-side MOSFET on resistance per phase.
A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. Equation 20 to
Equation 28 yield an optimal starting point for the design;
some adjustments may be necessary to account for PCB and
component parasitic effects (see the Layout and Component
Placement section).
In this example, AD is 5, VRT equals 0.39 V, R' is approximately
0.5 mΩ (assuming a 4-layer, 1 ounce motherboard), and LX is
175 pH for the four Al-Poly capacitors.
The compensation values can then be solved using the following
equations:
n× RO ×TA
The first step is to compute the time constants for all of the
poles and zeros in the system:
(25)
(26)
(27)
(28)
CA
=
RE × RB
TC
CA
RA =
CB =
R
SENSE ×VRT
RE = n× RO + AD × RDS
2× L × 1 − n× D ×VRT
+
+
VVID
TB
RB
(20)
(
)
n×CX × RO ×VVID
TD
RA
CFB
=
′
RO − R
RX
LX
RO
′
TA = CX ×
(
RO − R
)
+
×
(21)
(22)
These are the starting values, prior to tuning the design, to
account for layout and other parasitic effects (see the Layout
and Component Placement section).
′
TB =
RX + R −RO
×CX
⎛
⎞
⎟
⎟
⎠
The final values selected after tuning are
AD × RDS
2× fSW
⎜
VRT × L −
⎜
CA = 3.3 nF,
RA = 7.32 kꢀ,
CB = 1 nF,
⎝
TC =
(23)
V
VID × RE
CFB = 33 pF.
Rev. 0 | Page 18 of 32
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ADP3194
Figure 11 and Figure 12 show the typical transient response
using these compensation values.
CIN SELECTION AND INPUT CURRENT
di/dt REDUCTION
In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude of one-nth the
maximum output current. To prevent large voltage transients,
a low ESR input capacitor, sized for the maximum rms current,
must be used. The maximum rms capacitor current is given by
1
ICRMS = D × IO
×
−1
N × D
(29)
1
ICRMS = 0.108 ×119A ×
−1 =14.7A
4 × 0.108
Figure 11. Typical Transient Response
The capacitor manufacturer’s ripple current ratings are often
based on only 2000 hours of life. This makes it advisable to
further derate the capacitor or to choose a capacitor rated at
a higher temperature than required. Several capacitors can be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
two 2700 μF, 16 V aluminum electrolytic capacitors and eight
4.7 μF ceramic capacitors.
for Design Example Load Step
To reduce the input current di/dt to a level below the recom-
mended maximum of 0.1 A/μs, an additional small inductor
(L > 370 nH at 18 A) should be inserted between the converter
and the supply bus. This inductor also acts as a filter between
the converter and the primary power source.
Figure 12. Typical Transient Response
for Design Example Load Release
Figure 13. Efficiency of the Circuit of Figure 10 vs. Output Current
Rev. 0 | Page 19 of 32
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ADP3194
5. Repeat Step 4 until the cold and hot voltage measurements
remain the same.
TUNING THE ADP31±4
1. Build a circuit based on the compensation values
computed from the equations used in the example.
6. Measure the output voltage from no load to full load, using
5 Amps steps. Compute the load line slope for each change,
and then average to get the overall load line slope (ROMEAS).
2. Hook up the dc load to circuit, turn it on, and verify its
operation. Also, check for jitter at no load and full load.
7. If ROMEAS is off from RO by more than 0.05 mΩ, use the
following to adjust the RPH values:
DC Load Line Setting
3. Measure the output voltage at no load (VNL). Verify it is
within tolerance.
ROMEAS
RO
RPH
) = RPH ×
(OLD)
(31)
(
NEW
4. Measure the output voltage at full load cold (VFLCOLD). Let
the board sit for ~10 minutes at full load, and then measure
the output (VFLHOT). If there is a change of more than a few
millivolts, adjust RCS1 and RCS2, using Equation 30 and
Equation 31.
8. Repeat Step 6 and Step 7 to check the load line, and repeat
adjustments if necessary.
9. Once the dc load line adjustment is complete, do not
change RPH, RCS1, RCS2, or RTH for the remainder of the
procedure.
VNL −VFLCOLD
(30)
RCS2
= RCS2
×
OLD )
(
NEW
)
(
10. Measure the output ripple at no load and full load with a
scope, and make sure it is within specifications.
VNL −VFLHOT
1
(32)
RCS1
=
(
NEW )
RCS1
) + RTH
1
(
OLD
(
25°C
)
−
RCS1
) × RTH
+
×
RTH
(
25° C
(
OLD
(
25°C
)
)
(
RCS1
) − RCS2
)
(
RCS1
) − RTH
)
(
OLD
(
NEW )
(
OLD
(
25° C
)
Rev. 0 | Page 20 of 32
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ADP3194
AC Load Line Setting
Initial Transient Setting
11. Remove the dc load from the circuit and hook up the
dynamic load.
18. With the dynamic load still set at the maximum step size,
expand the scope time scale to see 2 μs/div to 5 μs/div. The
waveform may have two overshoots and one minor under-
shoot (see Figure 15). Here, VDROOP is the final desired value.
12. Hook up the scope to the output voltage and set it to dc
coupling, with the time scale at 100 μs/div.
13. Set the dynamic load for a transient step of about 40 A at
1 kHz with a 50% duty cycle.
14. Measure the output waveform (if not visible, use dc offset
on scope to view). Try to use a vertical scale of 100 mV/div
or finer. This waveform should look similar to Figure 14.
V
DROOP
V
TRAN1
V
TRAN2
V
ACDRP
Figure 15. Transient Setting Waveform
V
DCDRP
19. If both overshoots are larger than desired, try making the
following adjustments:
Make the ramp resistor larger by 25% (RRAMP).
For VTRAN1, increase CB, or increase the switching frequency.
For VTRAN2, increase RA, and decrease CA by 25%.
Figure 14. AC Load Line Waveform
15. Use the horizontal cursors to measure VACDRP and VDCDRP
,
If these adjustments do not change the response, the output
decoupling is the limiting factor. Check the output response
every time a change is made, or nodes are switched, to make
sure the response remains stable.
as shown in Figure 14. Do not measure the undershoot or
overshoot that happens immediately after this step.
If VACDRP and VDCDRP are different by more than a few milli-
volts, use Equation 38 to adjust CCS. It may be necessary to
parallel different values to get the correct one, because there
are limited standard capacitor values available. It is a good
idea to have locations for two capacitors in the layout for this.
20. For load release (see Figure 16), if VTRANREL is larger than
VTRAN1 (see Figure 15), there is not enough output capaci-
tance. Either more capacitance is needed or the inductor
values need to be smaller. If inductors are changed, start
the design again using the spreadsheet and this tuning
procedure.
VACDRP
VDCDRP
CCS
= CCS ×
(OLD)
(38)
(
NEW
)
16. Repeat Step 11 to Step 13, and repeat the adjustments,
if necessary. Once complete, do not change CCS for the
remainder of the procedure.
V
TRANREL
V
DROOP
17. Set the dynamic load step to maximum step size. Do not
use a step size larger than needed, and verify that the output
waveform is square, which means that VACDRP and VDCDRP
are equal.
Figure 16. Transient Setting Waveform
Rev. 0 | Page 21 of 32
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ADP3194
Because the ADP3194 turns off all of the phases (switches induc-
tors to ground), there is no ripple voltage present during load
release. Thus, headroom does not need to be added for ripple,
allowing load release (VTRANREL) to be larger than VTRAN1 by the
amount of ripple and still meet specifications.
The CECC standard specification for power rating in surface
mount resistors is ꢁ6ꢁ3 = ꢁ.1 W, ꢁ8ꢁ5 = ꢁ.125 W, 12ꢁ6 = ꢁ.25 W.
For example, UVLO voltage specification = 8 V.
From Figure 17, a shunt resistor value of 42ꢁ Ω is recommended.
From Figure 17, the power dissipation is 14ꢁ mW. The user can
choose any of the following:
If VTRAN1 and VTRANREL are less than the desired final droop, this
implies that capacitors can be removed. When removing capaci-
tors, also check the output ripple voltage to make sure it is still
within specifications.
Two 84ꢁ Ω, ꢁ6ꢁ3 resistors in parallel
Two 84ꢁ Ω, ꢁ8ꢁ5 resistors in parallel
One 42ꢁ Ω, 12ꢁ6 resistor.
RAMPADJ FILTER
9.5
9.0
8.5
8.0
7.5
7.0
6.5
0.40
0.35
0.30
0.25
0.20
0.15
0.10
It is recommended that a filter be placed on the RAMPADJ line.
On the ADP3194, the VCC is 5 V, but the RAMPADJ still needs
to be connected to the 12 V input supply. Therefore, the filter is
needed to remove noise from the 12 V input supply. A 1 kΩ resistor
and 1 μF cap are recommended for this filter.
R
SHUNT
SHUNT RESISTOR DESIGN
When replacing an existing ADP3181 design with the ADP3194,
the shunt resistor value needs to be determined. A trade-off can
be made between the power dissipated in the shunt resistor and
the UVLO threshold. Figure 17 shows the typical resistor value
needed to realize certain UVLO voltages. It also gives the maxi-
mum power dissipated in the shunt resistor for these UVLO
voltages. The maximum power dissipated is calculated using
Equation 33.
P
SHUNT
100
200
300
400
500
600
700
R
(Ω)
SHUNT
Figure 17. Typical Shunt Resistor Value and Power Dissipation
for Different UVLO Voltages
2
VIN
) − VCC
(MIN)
(
MAX
PMAX
=
(33)
RSHUNT
where:
IN(MAX) is the maximum voltage from the 12 V input supply.
(If the 12 V input supply is 12 V 5ꢀ, then VIN(MAX) = 12.6 V.
V
If the 12 V input supply is 12 V 1ꢁꢀ, then VIN(MAX) = 13.2 V.)
Figure 17 shows the power when VIN(MAX) = 12.6 V.
V
CC(MIN) is the minimum VCC voltage of the ADP3194. It is
specified as 4.75 V.
SHUNT is the shunt resistor value.
R
Rev. 0 | Page 22 of 32
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ADP3194
DESIGN EXAMPLE USING DCR METHOD
The following procedure and equations yield values to use for RCS1,
RCS2, and RTH (the thermistor value at 25°C) for a given RCS value.
The following are guidelines for designs that use an inductor
DCR method instead of sense resistor method.
Select an NTC based on type and value. Because there is not a
value yet, start with a thermistor with a value close to RCS. The
NTC should also have an initial tolerance of better than 5%.
INDUCTOR SELECTION USING DCR
Use the method and equations described in the Inductor
Selection section to calculate the inductor. An important factor
in the inductor design is the DCR, which is used for measuring
the phase currents. A large DCR can cause excessive power losses,
while too small a value can lead to increased measurement error.
A good rule is to have the DCR be about 1 to 1½ times the droop
resistance (RO). For this design, an inductor with a DCR of
1.4 mΩ is used.
Based on the type of NTC, find its relative resistance value at two
temperatures. The temperatures that work well are 50°C and 90°C.
These resistance values are called A (RTH(50°C)/RTH(25°C)) and B
(RTH(90°C)/RTH(25°C)). The NTC’s relative value is always 1 at 25°C.
Find the relative values of RCS required for each of these
temperatures. This is based on the percentage change needed,
which in this example is initially 0.39%/°C. These are called
r1 (1/(1 + TC × (T1 − 25))) and r2 (1/(1 + TC × (T2 − 25))),
where TC = 0.0039 for copper. T1 = 50°C and T2 = 90°C are
chosen. From this, calculate that r1 = 0.9112 and r2 = 0.7978.
DESIGNING AN INDUCTOR USING DCR
Once the inductance and DCR are known, the next step is either to
design an inductor or to find a standard inductor that comes as
close as possible to meeting the overall design goals. It is also
important to have the inductance and DCR tolerance specified
to control the accuracy of the system. 15% inductance and 8%
DCR (at room temperature) are reasonable tolerances most
manufacturers can meet.
Compute the relative values for RCS2, RCS1, and RTH using
(
A − B
)
×r ×r2 − A ×
(
1 − B
)
×r2 + B ×
(
1 − A
)
)
× r
1
1
RCS2
=
=
(34)
(35)
A ×
(1 − B
)
×r − B × 1 − A
(
)
×r2 − A − B
(
1
(
1− A
)
INDUCTOR DCR TEMPERATURE CORRECTION
RCS1
1
A
With the inductors DCR being used as the sense element and
copper wire being the source of the DCR, compensation is
needed for temperature changes of the inductor’s winding.
Fortunately, copper has a well-known temperature coefficient
(TC) of 0.39%/°C.
−
1− RCS2 r − R
1
CS2
1
RTH
=
(36)
1
1
−
1− RCS2 RCS1
If RCS is designed to have an opposite and equal percentage
change in resistance to that of the wire, it cancels the tempera-
ture variation of the inductor’s DCR. Due to the nonlinear nature
of NTC thermistors, Resistor RCS1 and Resistor RCS2 are needed.
See Figure 18 to linearize the NTC and produce the desired
temperature tracking.
Calculate RTH = RTH × RCS, then select the closest value of thermis-
tor available. Also, compute a scaling factor k based on the ratio
of the actual thermistor value used relative to the computed one:
RTH
(
ACTUAL
)
(37)
k =
RTH
(CALCULATED
)
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
OR LOW-SIDE MOSFET
Calculate values for RCS1 and RCS2 using Equation 38 and
Equation 39:
TO
SWITCH
NODES
TO
OUT
SENSE
V
R
TH
ADP3194
RCS1 = RCS × k × RCS1
(38)
(39)
R
R
R
PH3
PH1
PH2
RCS2 = RCS
×
1− k
)
+
k × RCS2
R
R
CS2
CS1
CSCOMP
CSSUM
CSREF
18
17
16
For this example, RCS has been calculated to be 110 kΩ. Start with a
thermistor value of 100 kΩ. Next, look through the available
0603-size thermistors, and find a Vishay NTHS0603N01N1003JR
NTC thermistor with A = 0.3602 and B = 0.09174. From these,
compute RCS1 = 0.3795, RCS2 = 0.7195, and RTH = 1.075. Solve for
RTH, which yields 118.28 kΩ. Then, choose 100 kΩ, which makes
k = 0.8455. Finally, RCS1 and RCS2 are 35.3 kΩ and 83.9 kΩ.
Choose the closest 1% resistor values, which yield a choice
of 35.7 kΩ or 84.5 kΩ.
C
C
KEEP THIS PATH
CS1
CS2
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
Figure 18. Temperature Compensation Circuit Values
Rev. 0 | Page 23 of 32
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ADP3194
being dominant, the following equation shows the total power
being dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and average total output current (IO):
OUTPUT DROOP RESISTANCE–DCR METHOD
The design requires the regulator output voltage measured at
the CPU pins to drop when the output current increases. The
specified voltage drop corresponds to a dc output resistance (RO).
2
2
⎡
⎤
⎞
⎛
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
n IR
nSF
IO
1
12
⎢⎜
⎟ ⎥
PSF
=
(1− D
)
×
+
×
×RDS
(43)
(
SF )
⎜
⎟
The output current is measured by summing the voltage across
each inductor and passing the signal through a low-pass filter.
This summer filter is the CS amplifier configured with RPH(X)
(summers), RCS, and CCS (filter). The output resistance of the
regulator is set by the following equations:
⎢ nSF
⎥
⎝
⎠
⎣
⎦
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, it is possible to find
the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up
to an ambient temperature of 50°C, a safe limit for PSF is 1 W to
1.5 W at 120°C junction temperature. Thus, for this example
(119 A maximum), RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF)
is also at a junction temperature of about 120°C, so be certain to
account for this temperature when making this selection. This
example uses two lower-side MOSFETs at 4.8 mΩ each at 120°C.
RCS
RO
=
× RL
(40)
RPH
(X )
L
CCS
=
(41)
RL × RCS
where RL is the DCR of the output inductors.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.
The user has the flexibility of choosing either RCS or RPH(X). It is
best to select RCS (equal to 100 kΩ) and then solve for RPH(X) by
rearranging Equation 6.
RL
RO
RPH
=
× RCS
(42)
(
X
)
Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3120A). The output impedance of the
driver is approximately 2 Ω,and the typical MOSFET input gate
resistances are about 1 Ωto 2 Ω, so a total gate capacitance of
less than 6000 pF should be adhered to. Because there are two
MOSFETs in parallel, the input capacitance for each synchronous
MOSFET should be limited to 3000 pF.
1.0 mꢀ
1.2 mꢀ
RPH
=
×100 kꢀ = 82.5 kꢀ
(
X
)
Next, use Equation 41 to solve for CCS.
280 nH
CCS
=
= 2.8 nF
1.0 mꢀ ×100 kꢀ
It is best to have a dual location for CCS in the layout, so that
The high-side (main) MOSFET has to be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it takes
for the main MOSFET to turn on and off and to the current and
the voltage that are being switched.
standard values can be used in parallel to get as close as possible
to the value desired. For accuracy, CCS should be a 5% or 10%
NPO capacitor. This example uses a 5% combination for CCS of
2.2 nF and 560 pF in parallel.
POWER MOSFETS
Basing the switching speed on the rise and fall time of the gate
driver impedance and MOSFET input capacitance, the follow-
ing equation provides an approximate value for the switching
loss per main MOSFET:
This section is only applicable if power MOSFETs need to be
selected.
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive
voltage (the supply voltage to the ADP3120A) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With VGATE ~10 V, logic-level threshold MOSFETs
(VGS(TH)°< 2.5 V) are recommended.
V
CC × IO
nMF
n
PS ) = 2 × fSW
×
× RG ×
×CISS
(44)
(
MF
nMF
where:
MF is the total number of main MOSFETs,
n
RG is the total gate resistance (2 Ω for the ADP3120A and about
1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω),
C
ISS is the input capacitance of the main MOSFET.
The maximum output current (IO) determine1s the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. With
the ADP3194, currents are balanced between phases, thus the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (nSF). With conduction losses
Adding more main MOSFETs (nMF) does not really help the
switching loss per MOSFET because the additional gate capaci-
tance slows switching. The best way to reduce switching loss is
to use lower gate capacitance devices.
Rev. 0 | Page 24 of 32
www.DataSheet4U.com
ADP3194
The conduction loss of the main MOSFET is given by the
following equation:
These numbers comply with the guideline to limit the power
dissipation to 1 W per MOSFET.
2
2
One last thing to consider is the power dissipation in the driver
for each phase. This is best described in terms of the QG for the
MOSFETs and is given by the following equation:
⎡
⎛
⎤
n × I
⎞
R
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
IO
nMF
1
12
⎢⎜
⎟ ⎥
×RDS
PC
= D ×
+
×
(45)
(
MF
)
(MF )
⎜
⎟
nMF
⎢
⎥
⎠
⎦
⎝
⎣
where RDS(MF) is the on resistance of the MOSFET.
Typically, for main MOSFETs, the highest speed (low CISS)
device is preferred, but these usually have higher on resistance.
Select a device that meets the total power dissipation (about
1.5 W for a single D-PAK) when combining the switching and
conduction losses.
⎡
⎢
⎤
fSW
2 ×n
PDRV
=
×
(
nMF ×QGMF +nSF ×QGSF
)
+ ICC ×V
(45)
⎥
CC
⎢
⎣
⎥
⎦
where:
Q
GMF is the total gate charge for each main MOSFET
Q
GSF is the total gate charge for each synchronous MOSFET
For this example, an NTD40N03L was selected as the main
MOSFET (eight total; nMF = 8), with a CISS = 584 pF (maximum)
and RDS(MF) = 19 mΩ (maximum at TJ = 120°C). An NTD110N02L
was selected as the synchronous MOSFET (eight total; nSF = 8),
with CISS = 2710 pF (maximum) and RDS(SF) = 4.8 mΩ (maximum
at TJ = 120°C). The synchronous MOSFET CISS is less than 3000 pF,
satisfying that requirement. Solving for the power dissipation per
MOSFET at IO = 119 A and IR = 11 A yields 958 mW for each
synchronous MOSFET and 872 mW for each main MOSFET.
The standby dissipation factor for the driver is ICC × VCC. For
the ADP3120A, the maximum dissipation should be less than
400 mW. In this example (with ICC = 7 mA, QGMF = 5.8 nC, and
Q
GSF = 48 nC) 297 mW is found in each driver, which is below
the 400 mW dissipation limit. See the ADP3120A data sheet for
more details.
Rev. 0 | Page 25 of 32
www.DataSheet4U.com
ADP3194
LAYOUT AND COMPONENT PLACEMENT
POWER CIRCUITRY RECOMMENDATIONS
The following guidelines are recommended for optimal per-
formance of a switching regulator in a PC system.
The switching power path should be routed on the PCB to encom-
pass the shortest possible length in order to minimize radiated
switching noise energy (that is, EMI) and conduction losses in
the board. Failure to take proper precautions often results in
EMI problems for the entire PC system as well as noise-related
operational problems in the power converter control circuitry.
The switching power path is the loop formed by the current path
through the input capacitors and the power MOSFETs, including
all interconnecting PCB traces and planes. Using short and wide
interconnection traces is especially critical in this path for two
reasons: it minimizes the inductance in the switching loop, which
can cause high energy ringing; and it accommodates the high
current demand with minimal voltage loss.
GENERAL RECOMMENDATIONS
For good results, a PCB with at least four layers is recom-
mended. This allows the needed versatility for control
circuitry interconnections with optimal placement; power
planes for ground, input, and output power; and wide inter-
connection traces in the remainder of the power delivery
current paths.
Each square unit of 1 ounce copper trace has a resistance of
~0.53 mΩ at room temperature.
Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths. Then, the resistance and inductance introduced by these
current paths is minimized, and the via current rating is not
exceeded.
Whenever a power dissipating component, (for example, a
power MOSFET), is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately surrounding
it, is recommended. This improves current rating through the
vias and also improves thermal performance from vias extended
to the opposite side of the PCB, where a plane can more readily
transfer the heat to the air. Make a mirror image of any pad
being used to heat-sink the MOSFETs on the opposite side
of the PCB to achieve the best thermal dissipation to the air
around the board. To further improve thermal performance,
use the largest possible pad area.
If critical signal lines, including the output voltage sense lines of
the ADP3194, must cross through power circuitry, it is best if a
signal ground plane can be interposed between those signal lines
and the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of making
the signal ground noisier.
Use an analog ground plane around and under the ADP3194 as
a reference for the components associated with the controller. This
plane should be tied to the nearest output decoupling capacitor
ground and not tied to any other power circuitry. This prevents
power currents from flowing in the ground plane.
The output power path should also be routed to encompass a short
distance. The output power path is formed by the current path
through the inductor, the output capacitors, and the load.
For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.
Locate the components around the ADP3194 close to the con-
troller with short traces. The most important traces to keep short,
and away from other traces, are the FB pin and the CSSUM pin.
Connect the output capacitors as close as possible to the load
(or connector), for example, a microprocessor core that receives
the power. If the load is distributed, the capacitors should also
be distributed and generally be in proportion to where the load
tends to be more dynamic.
SIGNAL CIRCUITRY RECOMMENDATIONS
The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connect to the signal ground at the
load. To avoid differential-mode noise pickup in the sensed signal,
the loop area should be small. Thus, the FB and FBRTN traces
should be routed adjacent to each other on top of the power
ground plane back to the controller.
Avoid crossing any signal lines over the switching power path
loop, as described in the Power Circuitry Recommendations
section.
The feedback traces from the switch nodes should be connected
as close as possible to the inductor. The CSREF signal should be
Kelvin connected through a 10 ꢀ resistor to the center point of
the copper bar, which is the VCORE common node for the inductors
of all the phases (see Figure 19 and Figure 20).
Rev. 0 | Page 26 of 32
www.DataSheet4U.com
ADP3194
+12V
+12V
NFET
3
2
1
2
3
4
5
6
14
DL1
DL2
DL3
DL4
DL5
DL6
RED
RED
RED
RED
RED
RED
1K
1K
1K
1K
1K
1K
Q6
RN1A
13
NFET
3
2
Q5
1
2
3
4
5
6
14
RN2A
13
RN2B
12
RN2C
11
RN2D
10
RN2E
RN1B
12
NFET
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
3
2
Q4
RN1C
11
NFET
3
2
Q3
RN1D
10
NFET
3
2
Q2
RN1E
9
NFET
3
2
Q1
RN1F
R40
R41
R42
R43
374 Ohm
DL7
9
PHASE_1_RDY
PHASE_2_RDY
PHASE_3_RDY
PHASE_4_RDY
GRN
GRN
GRN
GRN
RN2F
J2
374 Ohm
DL8
CPU_VID0
1
3
5
7
9
2
4
6
8
10
12
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
374 Ohm
DL9
11
374 Ohm
DL10
HEADER_6x2
VCCP
1
1
2
2
R1
0
VCCSocket
1
2
VCCSocket
R30
10
0
0
R2
R3
NI VCCSense
NI VSSSense
1
1
2
2
VCCSense
VSSSense
R31
10
0
R4
VSSSocket
1
2
GND
VSSSocket
1
R10
10
1
TP 2
VCCP
TP 1
VSSP
TP13
VCC
D1
1
MM SD414 8
SOD-123
1
1
2
2
+12V
VCC1
12VR
2
1
DL11
8
RN1G
GRN
NFET
2
7
3
C44
1000p
+
1K
C23
1uF/16V
X7R(0805 )
CE13
100uF/16V
5x11mm
Q23
D6
R
R
B
BZX84C5V1FSCT
SHUNT
C
B
8
7
7
1.21K
U1
221
3.9K
1.5K
1.5 nF
1%
TP20
VID4
VID3
VID2
VID1
VID0
VID5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
RN3G
8
VID4
VID3
VID2
VID1
VID0
VID5
FBRTN
FB
COMP
PWRGD
EN
DELAY
RT
RAMPADJ
VCC
27
PWM1
PWM2
PWM3
PWM4
PWM1
26
1
R32
470K
RN2G
PWM2
25
PWM1
PWM2
PWM3
TP 9
1
1
1
1
PWM3
24
PWM1
FB
C
FB
15 pF
PWM4
23
C
R
A
A
R34
R13
R14
R15
R16
715 Ohm
105 Ohm
619 Ohm
0
PHASE1
PHASE2
PHASE3
PHASE4
1
2
2
2
2
VTT_Pwrg
d
SW1
22
1 nF
X7 R
2
1
2
7.32K
1%
TP10
1
1
1
SW2
21
PWM2
SW3
20
0
1
1
TP 4
SW4
19
PWRGD
TP11
GND
18
PWM3
Gr ound PWM 4 f o r
3- Phase
oper at i on
CSCOMP
17
R44
R
R45
R
R46
R
R47
CSSUM
16
R
PWM4
TP12
CSREF
15
R33
220K
C43
39n
PWM4
ILIMIT
R
R
R
R
R
15K
15K
15K
15K
1%
2
T
PH1
1
R
X7R
154K
1%
CS_PH1
CS_PH2
CS_PH3
CS_PH4
R
118K
1%
ADP3194
C
R
DLY
470K
DLY
39n
TP 5
EN
SW1
1%
2
PH2
1
R
R
LIM
140K
1%
SC2
TP 3
C
C
SC2
DNI
R21
0
18.2K
1%
SC1
COMP
150 pF
NPO 5%
1%
2
R
0
PH3
1
CS1
NPO 5%
1%
1
1
OD#
C24
2
2
1%
2
PH4
1
1
TP18
JP3
1
AGND
TP 7
OD#
100p
NPO
2
1
JP1
SHORTPIN
C45
1uF
TP23
CSREF
1
R
TH
100KOhm
1
2
1
TP19
GND
THERMISTOR 5%
R35
1K
Not e:
Ther mi st or ( R
f or DCR met hod. Do not i nser t
f or met hod.
TP 8
1
2
12VR
GND
) used onl y
TH
C46
10nF
R11
10
CSCOMP
R
SENSE
VCC1
CSREF
VCCP
VCCP
CE1
CE3
CE5
CE7
CE9
C1
22uF/6.3V
X5 R
C3
22uF/6.3V
X5 R
C5
22uF/6.3V
X5R
C7
22uF/6.3V
X5R
C9
22uF/6.3V
X5 R
C11
22uF/6.3V
X5R
C13
22uF/6.3V
X5R
C15
22uF/6.3V
X5R
C17
22uF/6.3V
X5R
560uF/4V
5mOhm
560uF/4V
5mOhm
560uF/4V
5mOhm
560uF/4V
5mOhm
560uF/4V
5mOhm
+
+
+
+
+
+
+
+
+
+
C2
22uF/6.3V
X5R
C4
22uF/6.3V
X5 R
C6
22uF/6.3V
X5 R
C8
22uF/6.3V
X5R
C10
22uF/6.3V
X5R
C12
22uF/6.3V
X5R
C14
22uF/6.3V
X5R
C16
22uF/6.3V
X5R
C18
22uF/6.3V
X5R
CE2
560uF/4V
5mOhm
CE4
N/L
5mOhm
CE6
N/L
5mOhm
CE8
560uF/4V
5mOhm
CE10
560uF/4V
5mOhm
GND
GND
Figure 19. Typical Applications Schematic Part 1
Rev. 0 | Page 27 of 32
www.DataSheet4U.com
ADP3194
TP32
RS5
TP33
RS5
TP24
TP21
12VR
VSWS_1
+12V
TP22
GND
1
L1
Rsense5
0.37uH18A
GND
12VR
1
2
3
4
1
2
10 mOhm 1%
+
+
C30
4.7uF/16V
X5R(1206)
CE12
2700uF/16V
12.5x30mm
U2
C50
4.7uF/16V
JP4
2X2 HDR
CE11
2700uF/16V
12.5x30mm
Q24
NTD100N02
R28
OD#
0 Ohm
1
8
6
2
3
GND
VDD
Vin
SW2
2
3
1
TP34
+5V
1
Enable
PWM
Vsw
PWM1
1
2
R36
10K
GND
PHASE_1_RDY
4
5
PRDY
PGND
TP35
-5V
1
L2 280nH
30A/0.8mohm
iP2003A
TP25
VCCP
Rsense1
1m Ohm 1%
1
1
3
2
C29
1uF/16V
X5R(0805)
PHASE1
PHASE_1_RDY
CS_PH1
R_PH1
10
1
TP14
SW1
JP2
HEADER 2
TP26
Vcc2
C38
C51
4.7uF/16V
4.7uF/16V
X5R(1206)
VSWS_2
U3
VCCP
R27
0 Ohm
L4 280nH
30A/0.8mohm
8
6
1
VDD
Vin
+
CE15
Rsense2
1m Ohm 1%
OD#
PWM2
47uF/16V
5x11mm
2
3
1
3
2
Enable
PWM
Vsw
CS_PH2
PHASE_2_RDY
5
4
1
PRDY
PGND
PHASE2
1
GND
R_PH2
10
C37
iP2003A
1uF/16V
X5R(0805)
PT1
VOUT
TP27
TP15
SW2
1
2
4
3
VCCP
PHASE_2_RDY
CSREF
TP28
PT2
C52
4.7uF/16V
C34
4.7uF/16V
X5R(1206)
GND OUT
VSWS_3
1
2
4
3
GND
U4
R26
0 Ohm
1
8
6
VDD
Vin
L3 280nH
30A/0.8mohm
2
1
VCCP
OD#
PWM3
2
3
Rsense3 1m Ohm 1%
Enable
PWM
Vsw
3
CS_PH3
PHASE_3_RDY
4
5
PRDY
PGND
PHASE3
R_PH3
10
C33
1uF/16V
X5R(0805)
iP2003A
1
TP29
1
TP16
SW3
PHASE_3_RDY
C53
C42
4.7uF/16V
X5R(1206)
TP30
4.7uF/16V
VSWS_4
Remove R29for
3-Phase operation
VCCP
U7
L5 280nH
30A/0.8mohm
R29
0 Ohm
1
8
6
Rsense4 1m Ohm 1%
VDD
Vin
1
3
2
OD#
2
3
CS_PH4
Enable
PWM
Vsw
PWM4
PHASE4
R_PH4
10
C41
1uF/16V
X5R(0805)
1
PHASE_4_RDY
4
5
PRDY
PGND
TP17
SW4
iP2003A
TP31
1
PHASE_4_RDY
Figure 20. Typical Applications Schematic Part 2
Rev. 0 | Page 28 of 32
www.DataSheet4U.com
ADP3194
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 21. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3194JRUZ-RL1
Teꢀperature Range
0°C to +85°C
Package Description
Package Option
RU-28
Ordering Quantity
2500
28-Lead TSSOP 13”Reel
1 Z = Pb-free part.
Rev. 0 | Page 29 of 32
www.DataSheet4U.com
ADP3194
NOTES
Rev. 0 | Page 30 of 32
www.DataSheet4U.com
ADP3194
NOTES
Rev. 0 | Page 31 of 32
www.DataSheet4U.com
ADP3194
NOTES
©2006 Analog Devices, Inc9 All rights reserved9 Tradeꢀarks and
registered tradeꢀarks are the property of their respective owners9
D06022-0-10/06(0)
Rev. 0 | Page 32 of 32
相关型号：
ADP3198AJCPZ-RL
SWITCHING CONTROLLER, 4000kHz SWITCHING FREQ-MAX, QCC40, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
ONSEMI
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