ADP3197JCPZ-RL_技术文档

6-Bit Programmable 2-/3-Phase

Synchronous Buck Controller

ADP3197

FUNCTIONAL BLOCK DIAGRAM

FEATURES

VCC

24

RT

9

RAMPADJ

10

Selectable 2-phase and 3-phase operation at up to 1 MHz

per phase

SHUNT

REGULATOR

10 mV worst-case differential sensing error over

temperature

Logic-level PWM outputs for interface to external high

power drivers

Enhanced PWM flex mode for excellent load transient

performance

Active current balancing between all output phases

Built-in power good/crowbar blanking that supports

on-the-fly VID code changes

16

OSCILLATOR

OD

UVLO

SHUTDOWN

SET EN

15

1

GND

EN

+

CMP

–

+

800mV

CSREF

RESET

PWM1

23

+

CURRENT

BALANCING

CIRCUIT

RESET

2-/3-PHASE

22 PWM2

CMP

–

+

2.2V

–

DRIVER LOGIC

+

RESET

PWM3

21

CMP

+

–

DAC – 250mV

CURRENT

LIMIT

Digitally programmable 0.3750 V to 1.55 V output

Programmable short-circuit protection with

programmable latch-off delay

2

DELAY

PWRGD

CROWBAR

20

19

18

SW1

SW2

SW3

TTSENSE 31

THERMAL

THROTTLING

CONTROL

32

APPLICATIONS

VRHOT

Desktop PC power supplies for

Next-generation AMD processors

Voltage regulator modules (VRM)

14 CSCOMP

8

7

ILIMIT

CURRENT

MEASUREMENT

AND LIMIT

12

+

–

CSREF

DELAY

13

CSSUM

GENERAL DESCRIPTION

The ADP3197¹is a highly efficient multiphase synchronous buck

switching regulator controller optimized for converting a 12 V

main supply into the core supply voltage required by high perform-

ance, Advanced Micro Devices, AMD processors. It uses an

internal 6-bit digital-to-analog converter (DAC) to read a voltage

identification (VID) code directly from the processor, which is

used to set the output voltage between 0.3750 V and 1.55 V. It uses

a multimode pulse-width modulation (PWM) architecture to

drive the logic level outputs at a programmable switching

frequency that can be optimized for VR size and efficiency.

The phase relationship of the output signals can be programmed

to provide 2-phase or 3-phase operation, allowing for the

construction of up to three complementary buck switching stages.

IREF

17

5

–

+

4

FB

COMP

+

PRECISION

REFERENCE

11

LLSET

–

FBRTN

3

SOFT START

CONTROL

6

SS

VID DAC

28

ADP3197

25

26

27

29

30

VID5 VID4 VID3 VID2 VID1 VID0

Figure 1.

The ADP3197 supports a programmable slope function to adjust

the output voltage as a function of the load current so it is always

optimally positioned for a system transient. This can be disabled

by connecting the LLSET pin to the CSREF pin.

The ADP3197 has a built-in shunt regulator that allows the part

to be connected to the 12 V system supply through a series resistor.

The ADP3197 also provides accurate and reliable short-circuit

protection, adjustable current limiting, and a delayed power-

good output that accommodates on-the-fly output voltage

changes requested by the CPU.

The ADP3197 is specified over the extended commercial tempera-

ture range of 0°C to 85°C and is available in a 32-lead LFCSP.

¹Protected by U.S. Patent Number 6,683,441; other patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP3197

TABLE OF CONTENTS

Features .............................................................................................. 1

Power-Good Monitoring........................................................... 13

Output Crowbar ......................................................................... 14

Output Enable and UVLO ........................................................ 14

Thermal Monitoring.................................................................. 14

Typical Application Circuit....................................................... 16

Applications Information.............................................................. 17

Setting the Clock Frequency..................................................... 17

Soft Start Delay Time................................................................. 17

Current-Limit Latch-Off Delay Times .................................... 17

Inductor Selection...................................................................... 18

Current Sense Amplifier............................................................ 18

Inductor DCR Temperature Correction ................................. 19

Output Offset.............................................................................. 20

C_OUTSelection ............................................................................. 20

Power MOSFETs......................................................................... 21

Ramp Resistor Selection............................................................ 22

COMP Pin Ramp ....................................................................... 23

Current-Limit Setpoint.............................................................. 23

Feedback Loop Compensation Design.................................... 23

C_INSelection and Input Current di/dt Reduction.................. 25

Thermal Monitor Design .......................................................... 25

Shunt Resistor Design................................................................ 25

Tuning the ADP3197 ................................................................. 26

Layout and Component Placement ......................................... 27

Outline Dimensions....................................................................... 29

Ordering Guide .......................................................................... 29

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Test Circuits....................................................................................... 9

Theory of Operation ...................................................................... 10

Start-Up Sequence...................................................................... 10

Phase Detection Sequence......................................................... 10

Master Clock Frequency............................................................ 11

Output Voltage Differential Sensing........................................ 11

Output Current Sensing ............................................................ 11

Active Impedance Control Mode............................................. 11

Current Control Mode and Thermal Balance ........................ 11

Voltage Control Mode................................................................ 12

Current Reference ...................................................................... 12

Enhanced PWM Mode .............................................................. 12

Delay Timer................................................................................. 12

Soft Start ...................................................................................... 12

Current Limit, Short-Circuit, and Latch-Off Protection ...... 13

Dynamic VID.............................................................................. 13

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

ADP3197

SPECIFICATIONS

VCC = 5 V, FBRTN = GND, T_A= 0°C to 85°C, unless otherwise noted¹

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

REFERENCE CURRENT

Reference Bias Voltage

Reference Bias Current

V_IREF

I_IREF

1.5

14.25 15

V

15.75 μA

R_IREF= 100 kΩ

ERROR AMPLIFIER

Output Voltage Range²

Accuracy

V_COMP

V_FB

0.05

−10

4.4

10

V

mV

Relative to nominal DAC output, referenced to FBRTN,

LLSET = CSREF (see Figure 4)

Load Line Positioning Accuracy

Differential Nonlinearity

Input Bias Current

FBRTN Current

Output Current

Gain Bandwidth Product

Slew Rate

CSREF – LLSET = 80 mV

−78

−1

−9

−80

−82

+1

−6

mV

LSB

μA

I_FB

I_FB= 0.5 × I_IREF

−7.5

65

500

20

I_FBRTN

I_COMP

GBW_(ERR)

200

FB forced to V_OUT– 3%

COMP = FB

MHz

V/μs

25

LLSET Input Voltage Range

LLSET Input Bias Current

VID INPUTS

V_LLSET

I_LLSET

Relative to CSREF

−250

−10

+250 mV

+10

nA

Input Low Voltage

Input High Voltage

Input Current

V_IL(VID)

V_IH(VID)

I_IN(VID)

VIDx, VIDSEL

0.6

V

μA

ns

1.4

−10

VID Transition Delay Time²

VID code change to FB change

400

OSCILLATOR

Frequency Range²

Frequency Variation

f_OSC

f_PHASE

0.25

180

3

220

MHz

kHz

V

T_A= 25°C, R_T= 280 kΩ, 3-phase

T_A= 25°C, R_T= 130 kΩ, 3-phase

T_A= 25°C, R_T= 57.6 kΩ, 3-phase

R_T= 280 kΩ to GND

200

400

800

2.0

Output Voltage

V_RT

V_RAMPADJ

I_RAMPADJ

1.9

−50

1

2.1

+50

50

RAMPADJ Output Voltage

RAMPADJ Input Current Range

CURRENT SENSE AMPLIFIER

Offset Voltage

Input Bias Current

Gain Bandwidth Product

Slew Rate

Input Common-Mode Range

Output Voltage Range

Output Current

Current Limit Latch-off Delay Time

CURRENT BALANCE AMPLIFIER

Common-Mode Range

Input Resistance

RAMPADJ − FB, DAC=1.55 V

mV

μA

V_OS(CSA)

I_BIAS(CSSUM)

GBW_(CSA)CSSUM = CSCOMP

C_CSCOMP= 10 pF

CSSUM – CSREF (see Figure 5)

−1.0

−10

+1.0

+10

mV

nA

MHz

V/μs

V

μA

ms

10

CSSUM and CSREF

0

0.05

3.5

I_CSCOMP

t_OC(DELAY)

500

8

C_DELAY= 10 nF

V_SWxCM

R_SWx

I_SWx

−600

10

8

+200 mV

SWx = 0 V

17

12

26

20

+4

kΩ

μA

%

Input Current

Input Current Matching

−4

ΔI_SWx

CURRENT LIMIT COMPARATOR

ILIMIT Bias Current

ILIMIT Voltage

I_ILIMIT

V_ILIMIT

I_ILIMIT= 2/3 × I_IREF

R_ILIMIT= 121 kΩ (V_ILIMIT= I_ILIMIT× R_ILIMIT

9

1.09

10

1.21

11

1.33

μA

V

)

Rev. 0 | Page 3 of 32

ADP3197

Parameter

Symbol

Conditions

Min

3

80

Typ

Max

Unit

V

mV

Maximum Output Voltage

Current Limit Threshold Voltage

Current Limit Setting Ratio

DELAY TIMER

V_CL

V_CSREF− V_CSCOMP, R_ILIMIT= 121 kΩ

V_CL/I_ILIMIT

100

82.6

125

mV/V

Normal Mode Output Current

Output Current in Current Limit

Threshold Voltage

I_DELAY

I_DELAY(CL)

V_DELAY(TH)

I_DELAY= I_IREF

I_DELAY(CL)= 0.25 × I_IREF

12

3.0

1.6

15

3.75

1.7

18

4.5

1.8

μA

V

SOFT START

Output Current (Startup)

Output Current (DAC Code Change) I_SS(DAC)

ENABLE INPUT

I_SS(STARTUP)During startup, I_SS(STARTUP)= 0.25 × I_IREF

3

15

3.75

18.75 22.5

4.5

μA

DAC code change, I_SS(DAC)= 1.25 × I_IREF

Threshold Voltage

Hysteresis

Input Current

Delay Time

V_TH(EN)

V_HYS(EN)

I_IN(EN)

750

80

800

100

−1

2

850

125

mV

μA

t_DELAY(EN)

EN > 950 mV, C_DELAY= 10 nF

ms

OD

OUTPUT

Output Low Voltage

V_OL(

160

5

500

mV

V

)

OD

Output High Voltage

V_OH(

4

0

)

OD

60

kΩ

Pulldown Resistor

THERMAL THROTTLING CONTROL

TTSENSE Voltage Range

Internally limited

5

V

TTSENSE Bias Current

−135 −123 −111 μA

TTSENSE VRHOT Threshold

Voltage

665

710

755

mV

TTSENSE Hysteresis

50

mV

VRHOT Output Low Voltage

POWER-GOOD COMPARATOR

Overvoltage Threshold

V_OL(VRHOT)I_VRHOT(SINK)= −4 mA

150

300

mV

V_PWRGD(OV)Relative to nominal DAC output; DAC = 0.5 V to 1.55 V

200

250

300

310

mV

Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V 190

V_PWRGD(UV)Relative to nominal DAC output; DAC = 0.5 V to 1.55 V

Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V −310 −250 −190 mV

Undervoltage Threshold

−300 −250 −200 mV

Output Low Voltage

Power-Good Delay Time

During Soft Start²

VID Code Changing

VID Code Static

Crowbar Trip Point

Crowbar Reset Point

PWM OUTPUTS

V_OL(PWRGD)I_PWRGD(SINK)= −4 mA

150

300

mV

C_DELAY= 10 nF

2

ms

μs

ns

V

100

250

200

1.8

300

V_CROWBAR

Relative to FBRTN

1.75

1.85

500

mV

Output Low Voltage

Output High Voltage

SUPPLY

V_OL(PWM)

V_OH(PWM)

I_PWM(SINK)= −400 μA

I_PWM(SOURCE)= +400 μA

160

5

mV

V

4.0

V_SYSTEM= 12 V, R_SHUNT= 340 Ω (see Figure 4)

VCC

I_VCC

4.65

5

5.55

25

11

V

mA

DC Supply Current

UVLO Turn On Current

UVLO Threshold Voltage

6.5

4.1

V_UVLO

VCC rising

VCC falling

9

V

¹All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

²Guaranteed by design or bench characterization; not tested in production.

Rev. 0 | Page 4 of 32

ADP3197

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

VCC

FBRTN

PWM3, RAMPADJ

SW1 to SW3

<200 ns

All Other Inputs and Outputs

Storage Temperature Range

Operating Ambient Temperature Range

Operating Junction Temperature

Thermal Impedance (θ_JA)

Lead Temperature

Soldering (10 sec)

Infrared (15 sec)

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

−0.3 V to +6 V

−0.3 V to +0.3 V

−0.3 V to VCC + 0.3 V

−5 V to +25 V

−10 V to +25 V

−0.3 V to VCC + 0.3 V

−65°C to +150°C

0°C to 85°C

Absolute maximum ratings apply individually only, not in

combination. Unless otherwise specified, all other voltages are

referenced to GND.

125°C

100°C/W

ESD CAUTION

300°C

260°C

Rev. 0 | Page 5 of 32

ADP3197

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24

23

22

21

20

19

18

17

VCC

EN

PWRGD

FBRTN

FB

COMP

SS

1

2

3

4

5

6

7

8

PIN 1

INDICATOR

PWM1

PWM2

PWM3

SW1

SW2

SW3

ADP3197

TOP VIEW

(Not to Scale)

DELAY

ILIMIT

NOTES

1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN

ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND.

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

EN

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.

Power-Good Output. Open-drain output that signals when the output voltage is outside proper operating range.

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this

pin and the output voltage sets the no load offset point.

PWRGD

FBRTN

FB

5

6

COMP

SS

Error Amplifier Output and Compensation Point.

Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start

ramp-up time.

7

DELAY

ILIMIT

RT

Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent

latch-off delay time, EN delay time, and PWRGD delay time.

Current Limit Set Point. An external resistor from this pin to GND sets the current limit threshold of the

converter.

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.

8

9

10

11

RAMPADJ

LLSET

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.

Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to

the center point of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables

positioning.

12

CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense

amplifier and the power-good and crowbar functions. This pin should be connected to the common point of

the output inductors.

13

14

CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor

currents together to measure the total output current.

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of the

current sense amplifier and the positioning loop response time.

CSCOMP

15

16

GND

OD

Ground. All internal biasing and logic output signals of the device are referenced to this ground.

Output Disable Logic Output. This pin is actively pulled low when EN input is low or when VCC is below its UVLO

threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.

17

IREF

Current Reference Input. An external resistor from this pin to ground sets the reference current for I_FB, I_DELAY, I_SS,

I_ILIMIT, and I_TTSENSE

.

18 to 20

SW3 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SWx pins of unused phases

should be left open.

Rev. 0 | Page 6 of 32

ADP3197

Pin No.

Mnemonic

Description

21 to 23

PWM3 to

PMW1

Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the

ADP3120. Connecting the PWM3 output to VCC causes that phase to turn off, allowing the ADP3197 to operate

as a 2-phase or 3-phase controller.

24

VCC

A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator

maintains VCC = 5 V.

25 to 30

31

VID5 to VID0 Voltage Code DAC Inputs. These six pins are pulled down to GND, providing a Logic 0 if left open. When in normal

operation mode, the DAC output programs the FB regulation voltage from 0.3750 V and 1.55 V (see Table 4).

TTSENSE

VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense

the temperature at the desired thermal monitoring point.

32

VRHOT

Open-Drain Output. This output signals when the temperature at the monitoring point connected to TTSENSE

exceeds the maximum operating temperature. This can be connected to the PROCHOT# (a PC system signal)

output from the CPU.

Rev. 0 | Page 7 of 32

ADP3197

TYPICAL PERFORMANCE CHARACTERISTICS

7200

6400

5600

4800

4000

3200

2400

1600

800

0

100

200

300

400

500

600

700

800

900

RT (kΩ)

Figure 3. Master Clock Frequency vs. R_T

Rev. 0 | Page 8 of 32

ADP3197

TEST CIRCUITS

6-BIT CODE

12V

ADP3197

12V

32

680Ω

VCC

FB

24

4

680Ω

1

VCC

PWM1

PWM2

PWM3

SW1

1.25V

EN

+

1µF

100nF

PWRGD

FBRTN

FB

COMP

SS

10kΩ

FBRTN

LLSET

ADP3197

1kΩ

3

SW2

10nF

DELAY

SW3

–

+

11

10nF

IREF

ILIMIT

100kΩ

ΔV

CSREF

GND

121kΩ

VID

DAC

12

15

1V

20kΩ

V

= FB = 80mV – FB = 0mV

ΔV ΔV

100nF

FB

Figure 4. Closed-Loop Output Voltage Accuracy

Figure 6. Positioning Voltage

12V

ADP3197

680Ω

VCC

24

14

CSCOMP

100nF

39kΩ

CSSUM

13

1kΩ

CSREF

GND

12

15

1V

CSCOMP – 1V

V

=

OS

40

Figure 5. Current Sense Amplifier V_OS

Rev. 0 | Page 9 of 32

ADP3197

THEORY OF OPERATION

The ADP3197 combines a multimode, fixed frequency PWM

control with multiphase logic outputs for use in 2-phase and

3-phase synchronous buck CPU core supply power converters.

The internal VID DAC is designed to interface with the AMD

6-bit CPUs.

0.8V

ADP3197 EN

DELAY

V

Multiphase operation is important for producing the high

currents and low voltages demanded by today’s microprocessors.

Handling the high currents in a single-phase converter places

high thermal demands on the components in the system, such

as the inductors and MOSFETs.

DELAY(TH)

(1.7V)

V

VID

SS

The multimode control of the ADP3197 ensures a stable, high

performance topology for

VID

TD1

VCC_CORE

•

Balancing currents and thermals between phases

High speed response at the lowest possible switching

frequency and output decoupling

TD2

TD3

•

Minimizing thermal switching losses by utilizing lower

frequency operation

Tight load line regulation and accuracy, if load line is

selected

High current output from having up to 3-phase operation

Reduced output ripple due to multiphase cancellation

PC board layout noise immunity

Ease of use and design due to independent component

selection

VID INVALID

VID VALID

Figure 7. System Start-Up Sequence

PHASE DETECTION SEQUENCE

•

During startup, the number of operational phases and their phase

relationships are determined by the internal circuitry that monitors

the PWM outputs. Normally, the ADP3197 operates as a 3-phase

PWM controller. Connecting the PWM3 pin to the VCC pin

programs 2-phase operation.

•

Flexibility in operation for tailoring design to low cost or

high performance

While EN is low and prior to soft start, Pin PWM3 sinks approxi-

mately 100 μA. An internal comparator checks each pin voltage vs.

a threshold of 3 V. If the pin is tied to VCC, it is above the

threshold. Otherwise, an internal current sink pulls the pin to

GND, which is below the threshold. PWM1 and PWM2 are low

during the phase detection interval, which occurs during the

first four clock cycles of TD2. After this time, if the remaining

PWM outputs are not pulled to VCC, the 100 μA current sink

is removed and the outputs function as normal PWM outputs.

If they are pulled to VCC, the 100 μA current source is removed

and the outputs are put into a high impedance state.

START-UP SEQUENCE

The ADP3197 follows the start-up sequence shown in Figure 7.

After both the EN and UVLO conditions are met, the DELAY pin

goes through one cycle (TD1). The first four clock cycles of TD2

are blanked from the PWM outputs and used for phase detection,

as explained in the Phase Detection Sequence section. Then the

soft start ramp is enabled (TD2) and the output comes up to the

programmed DAC voltage.

After TD2 has been completed and the PWRGD masking time

(equal to VID on-the-fly masking) is finished, a second ramp

on the DELAY pin sets the PWRGD blanking (TD3).

The PWM outputs are logic-level devices intended for driving

external gate drivers, such as the ADP3120A. Because each

phase is monitored independently, operation approaching 100%

duty cycle is possible. In addition, more than one output can be

on at the same time to allow overlapping phases.

Rev. 0 | Page 10 of 32

ADP3197

The difference between CSREF and CSCOMP is then used as a

differential input for the current limit comparator. This allows

for the load line to be set independently of the current limit

threshold. In the event that the current limit threshold and load

line are not independent, the resistor divider between CSREF

and CSCOMP can be removed and the CSCOMP pin can be

directly connected to the LLSET pin. To disable voltage posi-

tioning entirely (that is, no load line), connect LLSET to CSREF.

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3197 is set with an external

resistor connected from the RT pin to ground. The frequency

follows the graph in Figure 3. To determine the frequency per

phase, the clock is divided by the number of phases in use. If all

phases are in use, divide by 3. If the PWM3 pin is tied to VCC,

then divide the master clock by 2 for the frequency of the

remaining phases.

To provide the best accuracy for sensing current, the CSA is

designed to have a low offset input voltage. In addition, the

sensing gain is determined by external resistors so it can be

made extremely accurate.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3197 combines differential sensing with a high accuracy

VID DAC and reference and a low offset error amplifier. This

maintains a worst-case specification of 10 mV differential

sensing error over its full operating output voltage and temperature

range. The output voltage is sensed between the FB pin and the

FBRTN pin. The FB pin should be connected through a resistor to

the regulation point, usually the remote sense pin of the micro-

processor. The FBRTN pin should be connected directly to the

remote sense ground point. The internal VID DAC and precision

reference are referenced to FBRTN, which has a minimal current

of 65 μA to allow accurate remote sensing. The internal error

amplifier compares the output of the DAC to the FB pin to

regulate the output voltage.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function

of output current, a signal proportional to the total output current

at the LLSET pin can be scaled to be equal to the droop impedance

of the regulator times the output current. This droop voltage is

then used to set the input control voltage to the system. The

droop voltage is subtracted from the DAC reference input

voltage directly to tell the error amplifier where the output

voltage should be. This allows enhanced feed-forward response.

CURRENT CONTROL MODE AND THERMAL

BALANCE

OUTPUT CURRENT SENSING

The ADP3197 provides a dedicated current sense amplifier

(CSA) to monitor the total output current for proper voltage

positioning vs. load current and for current limit detection.

Sensing the load current at the output gives the total average

current being delivered to the load, which is an inherently more

accurate method than peak current detection or sampling the

current across a sense element, such as the low-side MOSFET.

This amplifier can be configured in the following ways,

depending on the objectives of the system:

The ADP3197 has individual inputs (SW1 to SW3) for each

phase, which are used for monitoring the current in each phase.

This information is combined with an internal ramp to create

a current balancing feedback system that has been optimized

for initial current balance accuracy and dynamic thermal

balancing during operation. This current balance information is

independent of the average output current information used for

positioning, described in the Output Current Sensing section.

The magnitude of the internal ramp can be set to optimize the

transient response of the system. It also monitors the supply

voltage for feed-forward control for changes in the supply. A

resistor connected from the power input voltage to the RAMPADJ

pin determines the slope of the internal PWM ramp. External

resistors can be placed in series with individual phases to create

an intentional current imbalance, if desired, such as when one

phase may have better cooling and can support higher currents.

Resistor R_SW1through Resistor R_SW3can be used for adjusting

thermal balance (see the typical application circuit in Figure 10).

It is best to add these resistors during the initial design, so be

sure that placeholders are provided in the layout.

•

Output inductor DCR sensing without a thermistor for

lowest cost

Output inductor DCR sensing with a thermistor for

improved accuracy with tracking of inductor temperature

Sense resistors for highest accuracy measurements

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. The inputs to the

amplifier are summed together through resistors from the

sensing element (such as the switch node side of the output

inductors) to the inverting input, CSSUM. The feedback resistor

between CSCOMP and CSSUM sets the gain of the amplifier,

and a filter capacitor is placed in parallel with this resistor. The

gain of the amplifier is programmable by adjusting the feedback

resistor. If required, an additional resistor divider connected

between CSREF and CSCOMP, with the midpoint connected

to LLSET, can be used to set the load line required by the micro-

processor. The current information is then given as CSREF −

LLSET. This difference signal is used internally to offset the

VID DAC for voltage positioning.

To increase the current in any given phase, make R_SWxfor that

phase larger (make R_SWx= 0 for the hottest phase and do not change

during balancing). Increasing R_SWxto only 500 Ω makes a substan-

tial increase in phase current. Increase each R_SWxvalue by small

amounts to achieve balance, starting with the coolest phase first.

Rev. 0 | Page 11 of 32

ADP3197

The delay time is, therefore, set by the IREF current charging

a capacitor from 0 V to 1.7 V. This DELAY pin is used for two

delay timings (TD1 and TD3) during the start-up sequence. In

addition, DELAY is used for timing the current limit latch-off,

as explained in the Current Limit, Short-Circuit, and Latch-Off

Protection section.

VOLTAGE CONTROL MODE

A high gain, high bandwidth voltage mode error amplifier

is used for the voltage mode control loop. The control input

voltage to the positive input is set via the VID logic according

to the voltages listed in Figure 6 . If load line is selected, this

voltage is also offset by the droop voltage for active positioning

of the output voltage as a function of current, commonly known

as active voltage positioning. The output of the amplifier is the

COMP pin, which sets the termination voltage for the internal

PWM ramps.

SOFT START

The soft start ramp rates for the output voltage are set up with

a capacitor from the soft start (SS) pin to ground. During startup,

the SS pin sources a current of 3.75 μA. After startup, when

a DAC code change takes place, the SS pin sinks or sources an

18.75 μA current to control the rate at which the output voltage

can transition up or down.

The negative input (FBRTN) is tied to the output sense location

with Resistor R_Band is used for sensing and controlling the

output voltage at this point. A current source (equal to IREF/2)

flows through RB into the FB pin and is used for setting the no

load offset voltage from the VID voltage. The no load offset is

positive with respect to the VID DAC. The main loop compen-

sation is incorporated into the feedback network between FB

and COMP.

During startup (after TD1 and the phase detection cycle have been

completed), the SS time (TD2 in Figure 7) starts. The SS pin is

disconnected from GND, and the capacitor is charged up to the

programmed DAC voltage by the SS amplifier, which has an

output current equal to 1/4 IREF (normally 3.75 μA). The voltage

at the FB pin follows the ramping voltage on the SS pin, limiting

the inrush current during startup. The soft start time depends

on the value of the initial DAC voltage and C_SS. It is important

to note that the DAC code needs to be set before the ADP3197

is enabled.

CURRENT REFERENCE

The IREF pin is used to set an internal current reference. This

reference current sets I_FB, I_DELAY, I_SS, I_LIMIT, and I_TTSENSE. A resistor-to-

ground programs the current, based on the 1.5 V output.

1.5 V

IREF =

Once the SS voltage is within 50 mV of the programmed DAC

voltage, the power-good delay time (TD3) is started.

R_IREF

Typically, R_IREFis set to 100 kΩ to program IREF = 15 μA.

The following currents are then equal to:

Once TD2 has completed the SS current changes, it is changed

to 18.75 μA. If the programmed DAC code changes after

startup, then the SS pin sources or sinks a current of 18.75 μA to

or from the SS cap until the SS voltage is within 50 mV of the

newly programmed DAC voltage.

I

_FB= 1/2 × (IREF) = 7.5 μA

_DELAY= IREF = 15 μA

_SS(STARTUP)=1/4 × (IREF) = 3.75 μA

_SS(DAC)= 5/4 × (IREF) = 18.75 μA

_LIMIT= 2/3 × (IREF) = 10 μA

_TTSENSE= 8 × (IREF) = 120 μA

If EN is taken low or VCC drops below UVLO, DELAY and SS are

reset to ground in preparation for another soft start cycle.

Figure 8 shows typical start-up waveforms for the ADP3197.

T

ENHANCED PWM MODE

Enhanced PWM mode is intended to improve the transient

response of the ADP3197 to a load step-up. In previous genera-

tions of controllers, when a load step-up occurred, the controller

had to wait until the next turn on of the PWM signal to respond

to the load change. Enhanced PWM mode allows the controller

to respond immediately when a load step-up occurs. This allows

the phases to respond when the load increase transition takes place.

1

3

2

DELAY TIMER

The delay times for the start-up timing sequence are set with a

capacitor from the DELAY pin to ground. In UVLO or when EN

is logic low, the DELAY pin is held at ground. After the UVLO

and EN signals are asserted, the first delay time (TD1 in Figure 7)

4

CH1 1.00V

CH3 1.00V

CH2 500mV

CH4 10.0V

M2.00ms

A CH3

960mV

Figure 8. Typical Start-up Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: Power Good, Channel 4: Phase 1 Switch Node

is initiated. A current flows out of the DELAY pin to charge C_DLY

.

This current is equal to IREF, which is normally 15 μA. A

comparator monitors the DELAY voltage with a threshold of 1.7 V.

Rev. 0 | Page 12 of 32

ADP3197

T

CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH-

OFF PROTECTION

The ADP3197 compares a programmable current limit setpoint

to the voltage from the output of the current sense amplifier.

The level of current limit is set with the resistor from the ILIMIT

pin to ground. During operation, the current from ILIMIT is

equal to 2/3 IREF, giving 10 μA normally.

1

2

This current, through the external resistor, sets the ILIMIT

voltage, which is internally scaled to give a current limit threshold

of 82.6 mV/V. If the difference in voltage between CSREF and

CSCOMP rises above the current limit threshold, the internal

current limit amplifier controls the internal COMP voltage to

maintain the average output current at the limit.

3

4

CH1 1.00V

CH3 5.00V

CH2 2.00V

CH4 10.0V

M2.00ms

A CH1

660mV

Figure 9. Overcurrent Latch-Off Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node

If the limit is reached and TD3 has completed, a latch-off delay

time starts and the controller shuts down if the fault is not removed.

The current limit delay time shares the DELAY pin timing

capacitor with the start-up sequence timing. However, during

current limit, the DELAY pin current is reduced to IREF/4.

DYNAMIC VID

The ADP3197 has the ability to respond to dynamically

changing VID inputs while the controller is running. This

allows the output voltage to change while the supply is running

and supplying current to the load. This is commonly referred to

as VID on-the-fly (OTF). A VID OTF can occur under either

light or heavy load conditions. The processor signals the controller

by changing the VID inputs in multiple steps from the start

code to the finish code. This change can be positive or negative.

A comparator monitors the DELAY voltage and shuts off the

controller when the voltage reaches 1.7 V. The current limit latch-

off delay time is, therefore, set by the current of IREF/4, charging

the delay capacitor from 0 V to 1.7 V. This delay is four times

longer than the delay time during the start-up sequence. The

current limit delay time starts only after TD3 has completed.

If there is a current limit during startup, the ADP3197 goes

through TD1 to TD3 and then starts the latch-off time. Because

the controller continues to cycle the phases during the latch-off

delay time, if the short is removed before the 1.7 V threshold is

reached, the controller returns to normal operation and the DELAY

capacitor is reset to GND.

When a VID input changes state, the ADP3197 detects the

change and ignores the DAC inputs for a minimum of 400 ns.

This time prevents a false code due to logic skew while the six

VID inputs are changing. Additionally, the first VID change

initiates the power-good and crowbar blanking functions for

a minimum of 250 μs to prevent a false power-good or crowbar

event. Each VID change resets the internal timer.

The latch-off function can be reset either by removing and

reapplying the supply voltage to the ADP3197 or by toggling the

EN pin low for a short time. To disable the short-circuit latch-

off function, an external resistor should be placed in parallel

POWER-GOOD MONITORING

The power-good comparator monitors the output voltage via

the CSREF pin. The PWRGD pin is an open-drain output whose

high level (when connected to a pull-up resistor) indicates that

the output voltage is within the nominal limits defined in the

Power-Good Comparator section of the Specifications table,

based on the VID voltage setting. PWRGD goes low if the

output voltage is outside of this specified range.

with C_DLY

.

This prevents the DELAY capacitor from charging up to the 1.7 V

threshold. The addition of this resistor causes a slight increase

in the delay times.

During startup, when the output voltage is below 200 mV,

a secondary current limit is active. This is necessary because

the voltage swing of CSCOMP cannot go below ground. This

secondary current limit controls the internal COMP voltage to

the PWM comparators to 1.5 V. This limits the voltage drop

across the low-side MOSFETs through the current balance

circuitry.

The PWRGD circuitry also incorporates an initial turn-on

delay time (TD3) based on the DELAY timer. Prior to the SS

voltage reaching the programmed VID DAC voltage and the

PWRGD masking time finishing, the PWRGD pin is held low.

Once the SS pin is within 50 mV of the programmed DAC

voltage, the capacitor on the DELAY pin begins to charge up. A

comparator monitors the DELAY voltage and enables PWRGD

when the voltage reaches 1.7 V. The PWRGD delay time is,

therefore, set by a current of IREF charging a capacitor from 0

V to 1.7 V.

An inherent per phase current limit protects individual phases

if one or more phases stop functioning because of a faulty

component. This limit is based on the maximum normal mode

COMP voltage. Typical overcurrent latch-off waveforms are

shown in Figure 9.

Rev. 0 | Page 13 of 32

ADP3197

OUTPUT CROWBAR

THERMAL MONITORING

As part of the protection for the load and output components of

the supply, the PWM outputs are driven low (turning on the low-

side MOSFETs) when the output voltage exceeds the upper

crowbar threshold.

The ADP3197 includes a thermal monitoring circuit to detect

when a point on the VR has exceeded two different user-defined

temperatures. The thermal monitoring circuit requires an NTC

thermistor to be placed between TTSENSE and GND. A fixed

current of eight times IREF (normally giving 123 μA) is sourced

out of the TTSENSE pin and into the thermistor. The current

source is internally limited to 5 V. An internal circuit compares

the TTSENSE voltage to a 0.81 V threshold and outputs an

open-drain signal at the VRHOT outputs, respectively.

Turning on the low-side MOSFETs pulls down the output as the

reverse current builds up in the inductors. If the output over-

voltage is due to a short in the high-side MOSFET, this action

current limits the input supply or blows its fuse, protecting the

microprocessor from being destroyed.

The VRHOT open-drain output goes high once the voltage on

the TTSENSE pin goes below the VRHOT thresholds and signals

the system that an overtemperature event has occurred. Because

the TTSENSE voltage changes slowly with respect to time, 50 mV

of hysteresis is built into these comparators. The thermal moni-

toring circuitry does not depend on EN and is active when

UVLO is above its threshold. When UVLO is below its threshold,

VRHOT is forced low.

OUTPUT ENABLE AND UVLO

For the ADP3197 to begin switching, the input supply (VCC) to

the controller must be higher than the UVLO threshold, the EN

pin must be higher than its 0.85 V threshold, and the DAC code

must be valid. This initiates a system start-up sequence.

If either UVLO or EN is less than its respective threshold, the

ADP3197 is disabled. This holds the PWM outputs at ground,

shorts the DELAY capacitor to ground, and forces the PWRGD

OD

and

In the application circuit (see Figure 10), the

OD

signals low.

OD

pin should be

inputs of the ADP3120A drivers. Grounding

disables the drivers such that both DRVH and DRVL are

connected to the

OD

grounded. This feature is important in preventing the discharge

of the output capacitors when the controller is shut off. If the

driver outputs are not disabled, a negative voltage can be generated

during output due to the high current discharge of the output

capacitors through the inductors.

Rev. 0 | Page 14 of 32

ADP3197

Table 4. VID Codes

OUTPUT

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

0.900

0.875

0.850

0.825

0.800

0.775

0.7625

VID5

0

1

VID4

0

1

0

VID3

0

1

0

1

0

VID2

0

1

0

1

0

1

0

1

0

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OUTPUT

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

VID5

1

VID4

0

1

VID3

0

1

0

1

VID2

0

1

0

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Rev. 0 | Page 15 of 32

ADP3197

TYPICAL APPLICATION CIRCUIT

1 0 8 - 6 6 0 6

5 D I

4 D I

3 D I

2 D I

1 D I

0 D I

V

D O

D N G

P M O C S C

M U S S C

F E R S C

T E S L L

E S N E S T T

T O H R V

J D A P M A R

T R

Figure 10. Typical Application of 3-Phase VR

Rev. 0 | Page 16 of 32

ADP3197

APPLICATIONS INFORMATION

The design parameters for a typical AMD socket AM2 CPU

application are as follows:

SOFT START DELAY TIME

The value of C_SSsets the soft start time on initial power-up and,

additionally, whenever the output voltage is modified by a change

in the VID code. The ramp is generated with a 3.7± μA internal

current source during startup and by an 18.7± μA internal current

source during a VID code change. The value for C_SScan be

found using the following equations:

•

Input voltage (V_IN) = 12 V

VID setting voltage (V_VID) = 1.300 V

Duty cycle (D) = 0.108

Maximum static output voltage error (±V_SRER) = ±±0 mV

Maximum dynamic output voltage error (±V_DRER) = ±100 mV

Error voltage allowed for controller and ripple

(±V_RERR) = ±20 mV

During startup,

TD2

V_VID

C_SS= 3.7± μA ×

(2)

•

Maximum output current (I_O) = 110 A

Maximum output current step (ΔI_O) = 70 A

Static output droop resistance (R_O) based on

• No load output voltage set at upper output voltage limit

where:

TD2 is the desired soft start time.

_VIDis set by the VID inputs.

V

_ONL= V_VID+ V_SERR– V_RERR= 1.330 V

• Full load output voltage set at lower output voltage limit

_OFL= V_VID– V_SERR+ V_RERR= 1.270 V

The slew rate during a VID code change is five times faster than

the startup slew rate (because the internal current source is five

times larger).

V

• R_O= (V_ONL– V_OFL)/I_O= (1.33 V – 1.27 V)/110 A = 0.±4± mΩ

Dynamic output droop resistance (R_OD) based on

• Output current step to no load with output voltage set at

upper output dynamic voltage limit

•

TD

ΔV_VID

C_SS= 18.7± μA ×

The Advanced Micro Devices, AMD specification calls for

a minimum slew rate of 2 mV/μs for VID code changes. For

example, if the VID code changes from 1.0 V to 1.2 V, then TD

is 10 ms. This means C_SSequals 9.37± nF. The closest standard

capacitor value available is 10 nF.

V

_ONLD= V_VID+ V_DERR– V_RERR= 1.380 V

• Output voltage prior to load change (at I_OUT= ΔI_O)

_OL= V_ONL– (ΔI_O× R_O) = 1.292 V

V

• R_OD= (V_ONLD– V_OL)/ΔI_O= (1.380 V – 1.292 V)/70 A =

1.2± mΩ

CURRENT-LIMIT LATCH-OFF DELAY TIMES

•

Number of phases (n) = 3

Switching frequency per phase (f_SW) = 330 kHz

The start-up and current-limit delay times are determined by

the capacitor connected to the DELAY pin. The first step is to

set C_DLYfor the TD1 and TD3 delay times (see Figure 7). The

DELAY ramp (I_DELAY)is generated using a 1± μA internal

current source. The value for C_DLYcan be approximated using

SETTING THE CLOCK FREQUENCY

The ADP3197 uses a fixed frequency control architecture. The

frequency is set by an external timing resistor (R_T). The clock

frequency and the number of phases determine the switching

frequency per phase, which relates directly to switching losses

as well as the sizes of the inductors, the input capacitors, and

output capacitors. With n = 3 for three phases, a clock frequency

of 1.32 MHz sets the switching frequency (f_SW) of each phase to

330 kHz, which represents a practical trade-off between the

switching losses and the sizes of the output filter components.

Figure 3 shows that to achieve a 1.32 MHz oscillator frequency,

the correct value for R_Tis 130 kΩ.

TD(x)

V_{DELAY(TH )}

C_DLY= I_DELAY

×

(3)

where TD(x) is the desired delay time for TD1 and TD3.

The DELAY threshold voltage (V_DELAY(TH)) is given as 1.7 V. In

this example, 2 ms is chosen for all delay times, which meets the

AMD specifications (of not greater than 6 ms). Solving for C_DLY

gives a value of 17.6 nF. The closest standard value for C_DLYis 18 nF.

When the ADP3197 enters current limit, the internal current

source changes from 1± μA to 3.7± μA. This makes the latch-off

delay time four times longer than the start-up delay time. Longer

latch-off delay times can be achieved by placing a resistor in

Alternatively, the value for R_Tcan be calculated using

1

R_T=

(1)

n × f_SW× 6 pF

parallel with C_DLY

.

where 6 pF is the internal IC component value. For good initial

accuracy and frequency stability, a 1% resistor is recommended.

Rev. 0 | Page 17 of 32

ADP3197

The first decision in designing the inductor is choosing the

core material. Several possibilities for providing low core loss

at high frequencies include the powder cores (from

Micrometals, Inc., for example, or Kool Mu® from Magnetics)

and the gapped soft ferrite cores (for example, 3F3 or 3F4 from

Philips). Low frequency powdered iron cores should be avoided

due to their high core loss, especially when the inductor value is

relatively low and the ripple current is high.

INDUCTOR SELECTION

The choice of inductance for the inductor determines the ripple

current in the inductor. Less inductance leads to more ripple

current, which increases the output ripple voltage and conduction

losses in the MOSFETs. However, using smaller inductors allows

the converter to meet a specified peak-to-peak transient deviation

with less total output capacitance. Conversely, a higher inductance

means lower ripple current and reduced conduction losses, but

more output capacitance is required to meet the same peak-to-

peak transient deviation.

The best choice for a core geometry is a closed-loop type such

as a potentiometer core (PQ, U, or E core) or toroid. A good

compromise between price and performance is a core with

a toroidal shape.

In any multiphase converter, a practical value for the peak-to-

peak inductor ripple current is less than 50% of the maximum

dc current in the same inductor. Equation 4 shows the relationship

between the inductance, oscillator frequency, and peak-to-peak

ripple current in the inductor.

Many useful magnetics design references are available for

quickly designing a power inductor, such as

•

Intusoft Magnetic Designer Software

V_VID

×

(

1− D

)

Designing Magnetic Components for High Frequency Dc-Dc

Converters by William T. McLyman, Kg Magnetics, Inc.,

ISBN 1883107008

I_R

=

(4)

f_SW× L

Equation 5 can be used to determine the minimum inductance

based on a given output ripple voltage.

Selecting a Standard Inductor

The following power inductor manufacturers can provide design

consultation and deliver power inductors optimized for high

power applications upon request.

V_VID× R_OD

×

(

1 −

f_SW×V_RIPPLE

Solving Equation 5 for a 10 mV p-p output ripple voltage yields

1.3 V ×1.25 mꢀ × 1 − 0.324

(n × D)

)

L ≥

(5)

•

Coilcraft, Inc.

Coiltronics/Div of Cooper Bussmann

Sumida Corporation

(

)

L ≥

= 333 nH

330 kHz ×10 mV

If the resulting ripple voltage is less than what it is designed for,

the inductor can be made smaller until the ripple value is met.

This allows optimal transient response and minimum output

decoupling.

CURRENT SENSE AMPLIFIER

Most designs require the regulator output voltage, measured at

the CPU pins, to droop when the output current increases. The

specified voltage droop corresponds to a dc output resistance (R_O),

also referred to as a load line. The ADP3197 has the flexibility of

adjusting R_Oindependent of current-limit or compensation

components, and it can also support CPUs that do not require

a load line.

The smallest possible inductor should be used to minimize

the number of output capacitors. For this example, choosing a

400 nH inductor is a good starting point and gives a calculated

ripple current of 8.78 A. The inductor should not saturate at

the peak current of 41.06 A and should be able to handle the

sum of the power dissipation caused by the average current of

36.7 A in the winding and core loss.

For designs requiring a load line, the impedance gain of the

CS amplifier (R_CSA) must be greater than or equal to the load line.

All designs, whether they have a load line or not, should keep

R_CSA≥ 1 mΩ.

Another important factor in the inductor design is the dc resis-

tance (DCR), which is used for measuring the phase currents. A

large DCR may cause excessive power losses, though too small

a value may lead to increased measurement error. A good rule is

to have the DCR (R_L) be about 1 to 1½ times the droop resistance

(R_OD). This example uses an inductor with a DCR of 1.875 mΩ.

The output current is measured by summing the voltage across

each inductor and passing the signal through a low-pass filter.

This summer filter is the CS amplifier configured with Resistors

R_PH(x)(summers) and Resistor R_CSand Capacitor C_CS(filters).

The impedance gain of the regulator is set by the following

equations where R_Lis the DCR of the output inductors:

Designing an Inductor

Once the inductance and DCR are known, the next step is either

to design an inductor or find a standard inductor that comes as

close as possible to meeting the overall design goals. It is also

important to have the inductance and DCR tolerance specified

to control the accuracy of the system. Reasonable tolerances most

manufacturers can meet are 15% inductance and 7% DCR at

room temperature.

R_CS

R_CSA

=

× R_L

(6)

(7)

R_PH

x

( )

L

C_CS

=

R_L× R_CS

The user has the flexibility to choose either R_CSor R_PH(x)

.

Rev. 0 | Page 18 of 32

ADP3197

However, it is best to select R_CSequal to 100 kΩ, and then solve

for R_PH(x)by rearranging Equation 6. Here, R_CSA= 1 mΩ because

this is equal to the design load line.

2. Based on the type of NTC, find its relative resistance

value at two temperatures. The temperatures that work

well are 50°C and 90°C. These resistance values are called

A (R_TH(50°C))/R_TH(25°C)) and B (R_TH(90°C))/R_TH(25°C)). The relative

value of the NTC is always 1 at 25°C.

R_L

R_CSA

R_PH

=

× R_CS

(

x

)

3. Find the relative value of R_CSrequired for each of these

temperatures. The relative value of R_CSis based on the

percentage change needed, which in this example is initially

0.39%/°C. These temperatures are called r_1.

1.875 mꢀ

1.0 mꢀ

R_PH

=

×100 kꢀ =187.5 kꢀ

(

x

)

r₁= 1/(1 + TC × (T₁− 25°C))

and r₂

Next, use Equation 7 to solve for C_CS.

400 nH

C_CS

=

= 2 nF

1.875 mꢀ×100 kꢀ

r₂= 1/(1 + TC × (T₂− 25°C))

where:

TC = 0.0039 for copper.

T₁= 50°C.

T₂= 90°C.

It is best to have a dual location for C_CSin the layout so that

standard values can be used in parallel to get as close as possible

to the desired value. For best accuracy, C_CSshould be a 5% or

10% NPO capacitor. This example uses a 5% combination for

C_CSof two 1 nF capacitors in parallel. Recalculating R_CSand R_PH(X)

using this capacitor combination yields 110 kΩ and 140 kΩ.

The closest standard 1% value for R_PH(X)is 187 kΩ.

From this, r₁= 0.9112 and r₂= 0.7978.

4. Compute the relative values for R_CS1, R_CS2, and R_THusing

(

A − B

)

× r × r₂− A ×

(

1− B

(

)

× r₂+ B ×

× r₂−

(

1− A

)

× r

1

)

1

INDUCTOR DCR TEMPERATURE CORRECTION

R_CS2

R_CS1

=

(8)

A ×

(1− B

)

× r − B × 1− A

)

(

A − B

1

When the inductor DCR is used as the sense element and

copper wire is used as the source of the DCR, the user needs to

compensate for temperature changes of the inductor’s winding.

Fortunately, copper has a well-known temperature coefficient

(TC) of 0.39%/°C.

(

1− A

)

(9)

1

A

−

1− R_CS2r − R

1

CS2

1

R_TH

=

(10)

If R_CSis designed to have an opposite and equal percentage change

in resistance to that of the wire, it cancels the temperature

variation of the inductor DCR. Due to the nonlinear nature of

NTC thermistors, Resistor R_CS1and Resistor R_CS2are needed.

See Figure 11 to linearize the NTC and produce the desired

temperature tracking.

1

−

1− R_CS2R_CS1

Calculate R_TH= r_TH× R_CS, then select the closest value of

thermistor available. Also, compute a scaling factor (K)

based on the ratio of the actual thermistor value used

relative to the computed one.

PLACE AS CLOSE AS POSSIBLE

TO NEAREST INDUCTOR

TO

SWITCH

NODES

TO

OR LOW-SIDE MOSFET

R_TH

(

ACTUAL)

VOUT

SENSE

K =

(11)

R

TH

R_TH

(

CALCULATED

)

5. Calculate values for R_CS1and R_CS2using Equation 12 and

Equation 13.

R

PH3

PH1

PH2

ADP3197

R

CS2

R

_CS1= R_CS× K × R_CS1

(12)

(13)

CS1

CSCOMP

14

R_CS2= R_CS× ((1 − K) + (K × R_CS2))

C

CS2

KEEP THIS PATH

CS1

AS SHORT AS POSSIBLE

AND WELL AWAY FROM

SWITCH NODE LINES

CSSUM

CSREF

13

12

In this example, R_CSis calculated to be 114 kΩ. Look for an

available 100 kΩ thermistor, 0603 size. One such thermistor

is the Vishay NTHS0603N01N1003JR NTC thermistor with

A = 0.3602 and B = 0.09174. From these values, r_CS1= 0.3795,

r_CS2= 0.7195, and r_TH= 1.075.

Figure 11. Temperature Compensation Circuit Values

Solving for R_THyields 122.55 kΩ, so 100 kΩ is chosen, making

K = 0.816. Next, find R_CS1and R_CS2to be 35.3 kΩ and 87.9 kΩ.

Finally, choose the closest 1% resistor values, which yields

a choice of 35.7 kΩ and 88.7 kΩ.

The following procedure and equations yield values to use for

R_CS1, R_CS2, and R_TH(the thermistor value at 25°C) for a given

R_CSvalue:

1. Select an NTC based on type and value. Because the value

is unknown, use a thermistor with a value close to R_CS. The

NTC should also have an initial tolerance of greater than 5%.

Rev. 0 | Page 19 of 32

ADP3197

Load Line Setting

By combining Equation 16 with Equation 14 and selecting

minimum values for the resistors, the following equations result:

For load line values greater than 1 mΩ, R_CSAcan be set equal

to R_O, and the LLSET pin can be directly connected to the

CSCOMP pin. When the load line value needs to be less than

1 mΩ, two additional resistors are required. Figure 12 shows

the placement of these resistors.

I

_LIM×R_O

50μA

R_LL2

=

(17)

⎛

⎜

⎝

⎞

⎟

⎠

R_CSA

R_O

⎟

R_LL1

=

−1 ×R_LL2

(18)

ADP3197

Therefore, both R_LL1and R_LL2need to be in parallel and equal to

less than 8.33 kꢀ.

CSCOMP

14

Another useful feature for some VR applications is the ability to

select different load lines. Figure 12 shows an optional MOSFET

switch that allows this feature. Here, design for R_CSA= R_O(MAX)

(selected with Q_LLon) and then use Equation 14 to set R_O= R_O(MIN)

(selected with Q_LLoff).

CSSUM

13

CSREF

12

R

LL2

LL1

For this design, R_CSA= R_O= 1 mΩ. As a result, connect LLSET

directly to CSCOMP; the R_LL1and R_LL2resistors are not needed.

OPTIONAL LOAD LINE

SELECT SWITCH

LLSET

11

Q

LL

OUTPUT OFFSET

Figure 12. Load Line Setting Resistors

The Advanced Micro Devices, AMD specification requires that at

no load the nominal output voltage of the regulator be offset to a

value higher than the nominal voltage corresponding to the VID

code. The offset is set by a constant current source flowing into

the FB pin (I_FB) and flowing through R_B. The value of R_Bcan be

found using Equation 19.

The two resistors, R_LL1and R_LL2, set up a divider between the

CSCOMP pin and CSREF pin. This resistor divider is input into

the LLSET pin to set the load line slope R_Oof the VR according

to the following equation:

R_LL2

R_O=

× R_CSA

(14)

V_ONL− V_VID

R

_LL1+ R_LL2

The resistor values for R_LL1and R_LL2are limited by two factors.

R_B

=

I_FB

1.33 V− 1.3 V

•

The minimum value is based on the loading of the CSCOMP

pin. This pin’s drive capability is 500 ꢁA, and the majority

of this should be allocated to the CSA feedback. If the current

through R_LL1and R_LL2is limited to 10% of this (50 ꢁA), the

following limit can be placed for the minimum value for

(19)

R_B=

= 4.00 kꢀ

15 ꢁA

The closest standard 1% resistor value is 4.00 kΩ.

C_OUTSELECTION

The required output decoupling for the regulator is typically

R_LL1and R_LL2:

recommended by AMD for various processors and platforms.

Use simple design guidelines to determine the requirements.

These guidelines are based on having both bulk capacitors and

ceramic capacitors in the system.

I

_LIM×R_CSA

50×10⁻⁶

R

_LL1+ R_LL2≥

(15)

Here, I_LIMis the current-limit current, which is the

maximum signal level that the CSA responds to.

First, select the total amount of ceramic capacitance. This is based

on the number and type of capacitor used. The best location for

ceramic capacitors is inside the socket. Other capacitors can be

placed along the outer edge of the socket.

•

The maximum value is based on minimizing induced dc

offset errors based on the bias current of the LLSET pin.

To keep the induced dc error less than 1 mV, which makes

this error statistically negligible, place the following limit to

Combined ceramic values of 30 μF to 100 μF are recommended,

usually made up of multiple 10 μF or 22 μF capacitors. Select the

number of ceramics and find the total ceramic capacitance (Cz).

the parallel combination of R_LL1and R_LL2

:

1×10⁻³

R

_LL1× R_LL2

≤

= 8.33 kΩ

(16)

_LL1+ R_LL2120×10⁻⁹

Next, there is an upper limit imposed on the total amount of

bulk capacitance (C_X) when the user considers the VID on-the-

fly voltage stepping of the output (voltage step V_Vin time t_V

with an error of V_ERR).

When selecting the resistors, it is best to minimize their values

to reduce the noise and parasitic susceptibility of the feedback path.

Rev. 0 | Page 20 of 32

ADP3197

A lower limit is based on meeting the capacitance for load

release for a given maximum load step (ΔI_O) and a maximum

allowable overshoot. The total amount of load release voltage

is given as ΔV_O= ΔI_O× R_OD.

In this example, L_Xis approximately 240 pH for the 10 Al-Poly

capacitors, which satisfies this limitation. If the L_Xof the chosen

bulk capacitor bank is too large, the number of ceramic capacitors

needs to be increased, or lower ESL bulks must be used if there

is excessive undershoot during a load transient.

⎛

⎜

⎝

⎞

⎟

⎠

L × Δ I_O

C_X

≥

≤

− C_Z

(20)

(21)

For this multimode control technique, all ceramic designs can

be used providing the conditions of Equation 20 through

Equation 23 are satisfied.

(

MIN

)

n× R_OD×V_VID

MAX

)

POWER MOSFETS

2

⎛

⎞

⎟

⎛

⎜

⎝

⎞

⎟

⎠

L

V_V

⎜

V_VIDnKR_O

⎜

×

1+ t_V

×

− 1 −C_Z

For this example, the N-channel power MOSFETs have been

selected for one high-side switch and two low-side switches per

phase. The main selection parameters for the power MOSFETs

are V_GS(TH), Q_G, C_ISS, C_RSS, and R_DS(ON). The minimum gate drive

voltage (the supply voltage to the ADP3120A) dictates whether

standard threshold or logic-level threshold MOSFETs must be

used. With V_GATEequal to approximately 10 V, logic-level

threshold MOSFETs (V_GS(TH)< 2.5 V) are recommended.

⎜

⎝

⎟

nK²R_O²V_VID

V_V

L

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

V_ERR

V_V

where K = −1n

To meet the conditions of these equations and transient response,

the ESR of the bulk capacitor bank (R_X) should be less than two

times the dynamic input droop resistance (R_OD). If C_X(MIN)is

larger than C_X(MAX), the system cannot meet the VID on-the-fly

specification and may require the use of a smaller inductor or

more phases (and may have to increase the switching frequency

to keep the output ripple the same).

The maximum output current (I_O) determines the R_DS(ON)

requirement for the low-side (synchronous) MOSFETs. With

the ADP3197, currents are balanced between phases; thus, the

current in each low-side MOSFET is the output current divided

by the total number of MOSFETs (n_SF).

This example uses 18, 10 μF 1206 MLC capacitors (C_Z= 180 μF).

The VID on-the-fly step change is 1.3 V to 0.6 V (making V_V=

0.7 V) in 100 μs with a settling error of 2.5 mV. ≈

With conduction losses being dominant, Equation 24 shows the

total power that is dissipated in each synchronous MOSFET in

terms of the ripple current per phase (I_R) and average total

output current (I_O).

The maximum allowable load release overshoot for this example is

3%. Therefore, solving for the bulk capacitance yields

2

⎡

⎢

⎤

⎥

n I

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

I_O

1

12

R

⎛

⎜

⎝

⎞

400 nH × 70 A

3 ×1.25mΩ ×1.3 V

P_SF

=

(1− D

)

×

+

×

×R_DS

(24)

⎟

(

SF )

C_X

≤

MIN )

−180 ꢁF = 5.564 mF (22)

(

n_SF

⎢

⎣

⎥

⎦

⎟

⎠

Knowing the maximum output current being designed for and

the maximum allowed power dissipation, the user can find the

required R_DS(ON)for the MOSFET. For D-Pak MOSFETs up to an

ambient temperature of 50°C, a safe limit for P_SFis 1 W to 1.5 W

at 120°C junction temperature.

400 nH×700 mV

3×3.5²× ²×1.3 V

1.25 mꢀ

≤

MAX)

×

(

)

2

⎛

⎜

⎞

⎛

⎜

⎝

⎞

⎟

⎠

100 ꢁs ×1.3 V × 3 × 3.5 × 1.25 mꢀ

700 mV × 400 nH

⎟

1+

−1 −

⎜

⎟

⎜

⎟

⎠

Thus, for this example (100 A maximum), R_DS(SF)(per MOSFET)

is less than 7.5 mΩ. This R_DS(SF)is also at a junction temperature

of about 120°C. As a result, users need to account for these

conditions when selecting a low-side MOSFET. This example

uses two lower-side MOSFETs at 4.8 mΩ, each at 120°C.

⎝

180 μF = 19.23 mF

where K = 3.5.

Using 10, 560 μF Al-Poly capacitors with a typical ESR of 6 mΩ

each yields C_X= 5.6 mF with an R_X= 0.6 mΩ.

Another important factor for the synchronous MOSFET is the

input capacitance and feedback capacitance. The ratio of the

feedback to input needs to be small (less than 10% is recom-

mended) to prevent accidental turn-on of the synchronous

MOSFETs when the switch node goes high.

One last check should be made to ensure that the ESL of the bulk

capacitors (L_X) is low enough to limit high frequency ringing

during a load change.

This is tested using

L_X≤ C × R_O²× Q²

Also, the time to switch the synchronous MOSFETs off should

not exceed the nonoverlap dead time of the MOSFET driver

(40 ns typical for the ADP3110A). The output impedance of

the driver is approximately 2 Ω and the typical MOSFET input

gate resistances are about 1 Ω to 2 Ω. Therefore, a total gate

capacitance of less than 6000 pF should be adhered to.

Z

(23)

L_X≤180 ꢁF ×

(

1.25 mꢀ

)

²×2 = 562 pH

where Q²is limited to 2 to ensure a critically damped system.

Rev. 0 | Page 21 of 32

ADP3197

Because two MOSFETs are in parallel, the input capacitance for

each synchronous MOSFET should be limited to 3000 pF.

Finally, consider the power dissipation in the driver for each

phase. This is best expressed as Q_Gfor the MOSFETs and is

given by Equation 27, where Q_GMFis the total gate charge for

each main MOSFET and Q_GSFis the total gate charge for each

synchronous MOSFET.

The high-side (main) MOSFET must be able to handle two

main power dissipation components: conduction and switching

losses. The switching loss is related to the amount of time it

takes for the main MOSFET to turn on and off and to the

current and voltage being switched. Basing the switching speed

on the rise and fall time of the gate driver impedance and

MOSFET input capacitance, Equation 25 provides an approximate

value for the switching loss per main MOSFET, where n_MFis the

total number of main MOSFETs.

⎡

⎢

⎤

f_SW

2 ×n

P_DRV

=

×

(

n_MF×Q_GMF+ n_SF×Q_GSF

)

+ I_CC×V (27)

⎥

CC

⎢

⎥

⎦

⎣

Also shown is the standby dissipation factor (I_CC× V_CC) of the

driver. For the ADP3110A, the maximum dissipation should be

less than 400 mW. In this example, with I_CC= 7 mA, Q_GMF= 5.8 nC,

and Q_GSF= 48 nC, there is 297 mW in each driver, which is below

the 400 mW dissipation limit. See the ADP3110A data sheet for

more details.

V_CC× I_O

n_MF

n

P_S

= 2 × f_SW

MF )

×

× R_G×

×C_ISS

(25)

(

n_MF

where:

RAMP RESISTOR SELECTION

R_Gis the total gate resistance (2 Ω for the ADP3110A and about

1 Ω for typical high speed switching MOSFETs, making R_G= 3 Ω).

The ramp resistor (R_R) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the best

combination of thermal balance, stability, and transient response.

Equation 28 is used for determining the optimum value.

C_ISSis the input capacitance of the main MOSFET.

Adding more main MOSFETs (n_MF) does not help the switching

loss per MOSFET because the additional gate capacitance slows

switching. Use lower gate capacitance devices to reduce

switching loss.

A_R× L

R_R=

3× A_D× R_DS× C_R

(28)

The conduction loss of the main MOSFET is given by the

following, where R_DS(MF)is the on resistance of the MOSFET:

0.2 × 400 nH

3× 5 × 2.4 mΩ × 5 pF

R_R=

= 444 kΩ

2

⎛ n × I_R⎞²

⎡

⎢

⎤

I

⎛

⎜

⎝

⎞

⎟

⎠

O

1

12

⎜

⎝

⎟ ⎥

× R_DS

P_C

= D ×

+

×

(26)

(

MF

)

(MF )

⎟

where:

n_MF

⎠

⎢

⎥

⎣

⎦

A_Ris the internal ramp amplifier gain.

A_Dis the current balancing amplifier gain.

Typically, for main MOSFETs, the highest speed (low C_ISS)

device is preferred, but these usually have higher on resistance.

Select a device that meets the total power dissipation (about

1.5 W for a single D-Pak) when combining the switching and

conduction losses.

R

_DSis the total low-side MOSFET on resistance.

C_Ris the internal ramp capacitor value.

The internal ramp voltage magnitude can be calculated by using

A_R×

(

1− D

)

× V_VID

V_R=

For this example, an NTD40N03L is selected as the main MOSFET

R_R× C_R× f_SW

(29)

(six total; n_MF= 6), with C_ISS= 584 pF (maximum) and R_DS(MF)

=

19 mΩ (maximum at T_J= 120°C). An NTD110N02L is selected as

the synchronous MOSFET (six total; n_SF= 6), with C_ISS= 2710 pF

(maximum) and R_DS(SF)= 4.8 mΩ (maximum at T_J= 120°C). The

synchronous MOSFET C_ISSis less than 3000 pF, satisfying this

requirement.

0.2 ×

(

1− 0.108

)

×1.3V

V_R=

= 317 mV

444 kΩ × 5 pF × 330 kHz

The size of the internal ramp can be made larger or smaller.

If it is made larger, stability and noise rejection improve, but

transient degrades. Likewise, if the ramp is made smaller,

Solving for the power dissipation per MOSFET at I_O= 100 A and

I_R= 12.55 A yields 958 mW for each synchronous MOSFET and

872 mW for each main MOSFET. A guideline to follow is to limit

the MOSFET power dissipation to 1 W. The values calculated in

Equation 25 and Equation 26 comply with this guideline.

transient response improves at the sacrifice of noise rejection

and stability.

The factor of 3 in the denominator of Equation 28 sets a ramp

size that gives an optimal balance for good stability, transient

response, and thermal balance.

Rev. 0 | Page 22 of 32

ADP3197

For the ADP3197, the maximum COMP voltage (V_COMP(MAX)

)

is 4.0 V, and the COMP pin bias voltage (V_BIAS) is 1.1 V. In this

example, the maximum duty cycle is 0.61 and the peak current

is 62 A.

COMP PIN RAMP

A ramp signal on the COMP pin is due to the droop voltage

and output voltage ramps. This ramp amplitude adds to the

internal ramp to produce the following overall ramp signal

at the PWM input:

The limit of the peak per-phase current described previously

during the secondary current limit is determined by

V_R

(30)

V_RT

=

V_COMP

−V_BIAS

CLAMPED

)

(

⎛

⎜

⎝

⎞

⎟

⎠

2×

(

1− n× D

)

I_PHLIM

≅

(34)

1−

A_D× R_DS

(

MAX

)

n× f_SW×C_X× R_O

For the ADP3197, the current balancing amplifier gain (A_D) is 5

and the clamped COMP pin voltage is 2 V. Using an R_DS(MAX)of

2.8 mΩ (low-side on resistance at 150°C) results in a per-phase

peak current limit of 64 A. This current level can be reached only

with an absolute short at the output, and the current-limit latch-off

function shuts down the regulator before overheating can occur.

In this example, the overall ramp signal is 0.46 V. However,

if the ramp size is smaller than 0.5 V, increase the ramp size

to at least 0.5 V by decreasing the ramp resistor for noise immunity.

Because there is only 0.46 V initially, a ramp resistor value of

444 kΩ is chosen for this example, yielding an overall ramp

of 0.51 V.

FEEDBACK LOOP COMPENSATION DESIGN

CURRENT-LIMIT SETPOINT

Optimized compensation of the ADP3197 allows the best possible

response of the regulator output to a load change. The basis for

determining the optimum compensation is to make the regulator

and output decoupling appear as an output impedance that is

entirely resistive over the widest possible frequency range,

including dc, and equal to the static output droop resistance (R_O).

With the resistive output impedance, the output voltage droops

in proportion to the load current at any load current slew rate.

This ensures optimal positioning and minimizes the output

decoupling.

To select the current-limit setpoint, first find the resistor value

for R_LIM. The current-limit threshold for the ADP3197 is set

with a constant current source flowing out of the ILIMIT pin,

which sets up a voltage (V_LIM) across R_LIMwith a gain of

82.6 mV/V (A_LIM). Thus, increasing R_LIMnow increases the

current limit. R_LIMcan be found using

V_CL

I

_LIM×R_CSA

82.6 mV

R_LIM

=

×R_REF

(31)

A_LIM× I_ILIMIT

Here, I_LIMis the peak average current limit for the supply output.

The peak average current is the dc current limit plus the output

ripple current. In this example, choosing a dc current limit of

159 A and having a ripple current of 12.55 A gives an I_LIMof

171.55 A. This results in an R_LIM= 207.6 kΩ, for which 205 kΩ

is chosen as the nearest 1% value.

Because of the multimode feedback structure of the ADP3197,

the feedback compensation must be set to make the converter

output impedance work in parallel with the output decoupling

to make the load look entirely resistive. Compensation is needed

for several poles and zeros created by the output inductor and

the decoupling capacitors (output filter).

The per-phase initial duty cycle limit and peak current during a

load step are determined by

A type-three compensator on the voltage feedback is adequate

for proper compensation of the output filter. Equation 35 to

Equation 39 are intended to yield an optimal starting point for

the design; some adjustments may be necessary to account for

PCB and component parasitic effects (see the Tuning the

ADP3197 section).

V_COMP

−V_BIAS

MAX)

(

D_MAX= D ×

(32)

(33)

V_RT

D_MAX

f_SW

(

V_IN−V_VID

×

)

I_PHMAX

≅

L

Rev. 0 | Page 23 of 32

ADP3197

Computing the Time Constants

First, compute the time constants for all the poles and zeros in the system using Equation 35 to Equation 39.

R_L×V_RT2×L ×

(

1−n × D ×V_RT

)

R_E= n × R_O+ A_D× R_DS

+

V_VID

n × C_X× R_O×V_VID

1.4 mꢀ × 0.51V 2 × 320 nH ×

(

1−0.432

)

× 0.51 V

R_E= 4 ×1 mꢀ + 5 × 2.4 mꢀ +

+

= 22.9 mꢀ

(35)

1.3 V

4 × 5.6 mF ×1 mꢀ ×1.3 V

240 pH 1 mꢀ−0.5mꢀ

R_O− R'

R_X

L_X

R_O

T_A= C_X×

(

R_O−R'

)

+

×

=

= 5.6 mF ×

(

1 mꢀ−0.5 mꢀ

)

+

×

= 3.00 ꢁs

(36)

(37)

1 mꢀ

0.6mꢀ

T_B=

(

R_X+ R' − R_O

)

× C_X

(

0.6 mꢀ + 0.5 mꢀ −1 mꢀ

)

× 5.6 mF = 560 ns

⎛

⎞

⎟

⎠

⎛

⎞

⎟

⎠

A_D× R_DS

2 × f_SW

5 × 2.4 mꢀ

2 × 330 kHz

⎜

V_RT× L −

0.51 V × 320 nH−

⎜

⎝

T_C=

T_D=

=

= 5.17 ꢁs

(38)

(39)

V_VID× R_E

1.3 V × 22.9 mꢀ

2

C_X×C × R²

5.6 mF×180 ꢁF ×

+ C_Z× R_O5.6 mF× 1mꢀ − 0.5mꢀ

(

1mꢀ

)

Z

O

=

= 338 ns

C_X×

(

R_O− R'

)

(

)

+180 ꢁF×1mꢀ

where:

R' is the PCB resistance from the bulk capacitors to the ceramics.

_DSis the total low-side MOSFET on resistance per phase.

A_D= 5.

_RT= 0.51 V.

R

V

R' ≈ 0.5 mΩ (assuming a 4-layer, 1 oz motherboard).

L_X= 240 pH for the 10 Al-Poly capacitors.

The compensation values can then be solved using

n × R_O×T_A4×1 mꢀ × 3.00 ꢁs

C_A=

R_A=

C_B=

=

= 524 pF

(40)

(41)

R_E× R_B

5.17 ꢁs

C_A524 pF

22.9mꢀ ×1.00 kꢀ

T_C

=

= 9.87 kꢀ

T_B

560 ns

=

= 560 pF

= 34.2 pF

(42)

(43)

R_B1.00 kꢀ

T_D

338 ns

C_FB

=

R_A9.87 kꢀ

These are the starting values prior to tuning the design that account for layout and other parasitic effects (see the Tuning the ADP3197 section).

The final values selected after tuning are

C_A= 560 pF

R_A= 10.0 kΩ

C_B= 560 pF

C_FB= 27 pF

Rev. 0 | Page 24 of 32

ADP3197

An additional fixed resistor in parallel with the thermistor allows

tuning of the trip point temperatures to match the hottest tempera-

ture in the VR, when the thermistor itself is directly sensing a

proportionately lower temperature.

C_INSELECTION AND INPUT CURRENT

di/dt REDUCTION

In continuous inductor current mode, the source current of the

high-side MOSFET is approximately a square wave with a duty

ratio equal to n × V_OUT/V_INand an amplitude of one-nth the

maximum output current. To prevent large voltage transients,

a low ESR input capacitor, sized for the maximum rms current,

must be used. The maximum rms capacitor current is given by

Setting this resistor value is best accomplished with a variable

resistor during thermal validation and then fixing this value for

the final design.

Additionally, a 0.1 μF capacitor should be used for filtering noise.

1

SHUNT RESISTOR DESIGN

I_CRMS= D × I_O×

−1

N × D

The ADP3197 uses a shunt to generate 5 V from the 12 V

supply range. A trade-off can be made between the power

dissipated in the shunt resistor and the UVLO threshold.

Figure 14 shows the typical resistor value needed to realize

certain UVLO voltages. It also gives the maximum power

dissipated in the shunt resistor for these UVLO voltages.

(44)

1

I_CRMS= 0.108×110A ×

− 1 =17.2A

3×0.108

The capacitor manufacturer’s ripple-current ratings are often

based on only 2000 hours of life. As a result, it advisable to further

derate the capacitor or to choose a capacitor rated at a higher

temperature than required. Several capacitors can be placed

in parallel to meet size or height requirements in the design.

In this example, the input capacitor bank is formed by three

2700 μF, 16 V aluminum electrolytic capacitors and eight 4.7 μF

ceramic capacitors.

550

500

450

400

350

300

250

200

150

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

P

R

SHUNT

To reduce the input current di/dt to a level below the recom-

mended maximum of 0.1 A/μs, an additional small inductor

(L > 370 nH at 18 A) should be inserted between the converter

and the supply bus. This inductor also acts as a filter between

the converter and the primary power source.

7.0

7.5

8.0

8.5

9.0

(UVLO)

9.5

10.0

10.5

11.0

THERMAL MONITOR DESIGN

V

IN

A thermistor is used on the TTSENSE input of the ADP3197

for monitoring the temperature of the VR. A constant current

of 123 μA is sourced out of this pin and runs through a thermistor

network such as the one shown in Figure 13.

Figure 14. Typical Shunt Resistor Value and Power Dissipation

for Different UVLO Voltage

The maximum power dissipated is calculated using Equation 45.

2

(

V

_IN(MAX)−V_{CC(MIN )}

)

ADP3197

P_MAX

=

(45)

R_SHUNT

32

31

VRHOT

OPTIONAL

TEMPERATURE

ADJUST RESISTOR

where:

_IN(MAX)is the maximum voltage from the 12 V input supply

(if the 12 V input supply is 12 V 5%, V_IN(MAX)= 12.6 V; if the

TTSENSE

V

0.1µF

PLACE

THERMISTOR

NEAR CLOSEST

PHASE

12 V input supply is 12 V 10%, V_IN(MAX)= 13.2 V).

R

TTSENSE

V

_CC(MIN)is the minimum V_CCvoltage of the ADP3197. This is

specified as 4.75 V.

_SHUNTis the shunt resistor value.

Figure 13. VR Thermal Monitor Circuit

R

A voltage is generated from this current through the thermistor

and sensed inside the IC. When the voltage reaches 0.71 V, the

VRHOT is set. This corresponds to R_TTSENSEvalue of 6.58 kΩ.

The CECC standard specification for power rating in surface

mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W.

These values correspond to a thermistor temperature of ~100°C

and ~110°C when using the same type of 100 kΩ NTC thermistor

used in the current sense amplifier.

Rev. 0 | Page 25 of 32

ADP3197

TUNING THE ADP3197

13. Set the dynamic load for a transient step of about 40 A at

1 kHz with 50% duty cycle.

14. Measure the output waveform (use dc offset on scope to see

the waveform). Try to use a vertical scale of 100 mV/div or

finer. This waveform should look similar to Figure 15.

1. Build a circuit based on the compensation values

computed from the design spreadsheet.

2. Hook up the dc load to the circuit, turn it on, and verify its

operation. Also, check for jitter at no load and full load.

DC Load Line Setting

3. Measure the output voltage at no load (V_NL). Verify that it

is within tolerance.

4. Measure the output voltage at full load cold (V_FLCOLD). Let

the board sit for ~10 minutes at full load, and then measure

the output (V_FLHOT). If there is a change of more than a few

millivolts, adjust R_CS1and R_CS2using Equation 46 and

Equation 49.

V

ACDRP

V

DCDRP

V_NL−V_FLCOLD

V_NL−V_FLHOT

(46)

R_CS2

= R_CS2

×

OLD )

(

NEW

)

(

5. Repeat Step 4 until the cold and hot voltage measurements

remain the same.

6. Measure the output voltage from no load to full load using

5 A steps. Compute the load line slope for each change,

and then average to find the overall load line slope (R_OMEAS).

7. If R_OMEASis off from R_Oby more than 0.05 mΩ, use

Equation 47 to adjust the R_PHvalues.

Figure 15. AC Load Line Waveform

15. Use the horizontal cursors to measure V_ACDRPand V_DCDRP

as shown in Figure 15. Do not measure the undershoot

or overshoot that happens immediately after this step.

16. If V_ACDRPand V_DCDRPare different by more than a few

,

R_OMEAS

R_O

(47)

R_PH

= R_PH

×

OLD )

millivolts, use Equation 49 to adjust C_CS.Users may need to

parallel different values to get the right one because limited

standard capacitor values are available. It is a good idea to

have locations for two capacitors in the layout for this.

V_ACDRP

(

NEW

)

(

8. Repeat Step 6 and Step 7 to check the load line. Repeat

adjustments if necessary.

9. When the dc load line adjustment is complete, do not

change R_PH, R_CS1, R_CS2, or R_THfor the remainder of the

procedure.

(48)

C_CS

= C_CS

×

OLD)

(

NEW

)

(

V_DCDRP

10. Measure the output ripple at no load and full load with

17. Repeat Step 11 to Step 13 and repeat the adjustments,

if necessary. Once complete, do not change C_CSfor the

remainder of the procedure. Set the dynamic load step

a scope, and make sure it is within specifications.

AC Load Line Setting

to maximum step size. Do not use a step size larger than

needed. Verify that the output waveform is square, which

means that V_ACDRPand V_DCDRPare equal.

11. Remove the dc load from the circuit and hook up the

dynamic load.

12. Hook up the scope to the output voltage and set it to dc

coupling with the time scale at 100 μs/div.

1

R_CS1

=

NEW )

(49)

(

R_CS1₎+ R_TH

1

(

OLD

(

25°C

)

−

R_CS1₎× R_TH

+

(

R_CS1₎−R_CS2

)

×

(

R_CS1₎−R_TH

)

R_TH

(

OLD

(

25°C

)

(

OLD

(

NEW

)

(

OLD

(

25°C

)

(

25°C

)

Rev. 0 | Page 26 of 32

ADP3197

Initial Transient Setting

Because the ADP3197 turns off all of the phases (switches

inductors to ground), no ripple voltage is present during load

release. Therefore, the user does not have to add headroom for

ripple. This allows load release V_TRANRELto be larger than V_TRAN1

by the amount of ripple and still meet specifications.

18. With the dynamic load still set at the maximum step size,

expand the scope time scale to either 2 μs/div or 5 μs/div.

The waveform can have two overshoots and one minor

undershoot (see Figure 16). Here, V_DROOPis the final

desired value.

If V_TRAN1and V_TRANRELare less than the desired final droop,

capacitors can be removed. When removing capacitors, also

check the output ripple voltage to make sure it is still within

specifications.

V

DROOP

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

General Recommendations

For good results, a PCB with at least four layers is recommended.

This provides the needed versatility for control circuitry inter-

connections with optimal placement, power planes for ground,

input and output power, and wide interconnection traces in the

remainder of the power delivery current paths. Keep in mind

that each square unit of 1 oz copper trace has a resistance of

~0.53 mΩ at room temperature.

V

TRAN1

V

TRAN2

Figure 16. Transient Setting Waveform

19. If both overshoots are larger than desired, try making

the adjustments using the following suggestions:

Whenever high currents must be routed between PCB layers,

use vias liberally to create several parallel current paths, so the

resistance and inductance introduced by these current paths is

minimized and the via current rating is not exceeded.

•

Make the ramp resistor larger by 25% (R_RAMP).

For V_TRAN1, increase C_Bor increase the switching

frequency.

•

For V_TRAN2, increase R_Aand decrease C_Aby 25%.

If critical signal lines (including the output voltage sense lines of

the ADP3197) must cross through power circuitry, it is best to

interpose a signal ground plane between those signal lines and

the traces of the power circuitry. This serves as a shield to

minimize noise injection into the signals at the expense of

making signal ground a bit noisier.

If these adjustments do not change the response, the

design is limited by the output decoupling. Check the

output response every time a change is made, and check the

switching nodes to ensure that the response is still stable.

20. For load release (see Figure 17), if V_TRANRELis larger

than the allowed overshoot, there is not enough output

capacitance. Either more capacitance is needed, or the

inductor values need to be made smaller. When changing

inductors, start the design again using a spreadsheet and

this tuning procedure.

An analog ground plane should be used around and under the

ADP3197 as a reference for the components associated with the

controller. This plane should be tied to the nearest output

decoupling capacitor ground and should not be tied to any other

power circuitry to prevent power currents from flowing into it.

The components around the ADP3197 should be located close

to the controller with short traces. The most important traces

to keep short and away from other traces are the FB pin and the

CSSUM pin. The output capacitors should be connected as close

as possible to the load (or connector), for example, a micro-

processor core, that receives the power. If the load is distributed,

the capacitors should also be distributed and generally be in

proportion to where the load tends to be more dynamic.

V

TRANREL

V

DROOP

Avoid crossing any signal lines over the switching power path loop

(as described in the Power Circuitry Recommendations section).

Figure 17. Transient Setting Waveform

Rev. 0 | Page 27 of 32

ADP3197

Power Circuitry Recommendations

on the opposite side of the PCB to achieve the best thermal

dissipation in the air around the board. To further improve

thermal performance, use the largest possible pad area.

The switching power path should be routed on the PCB to

encompass the shortest possible length to minimize radiated

switching noise energy (EMI) and conduction losses in the

board. Failure to take proper precautions often results in EMI

problems for the entire PC system and noise-related operational

problems in the power converter control circuitry. The switching

power path is the loop formed by the current path through the

input capacitors and the power MOSFETs, including all inter-

connecting PCB traces and planes. Using short and wide

interconnection traces is especially critical in this path for two

reasons: it minimizes the inductance in the switching loop,

which can cause high energy ringing; and it accommodates the

high current demand with minimal voltage loss.

The output power path should also be routed to encompass a

short distance. The output power path is formed by the current

path through the inductor, the output capacitors, and the load.

For best EMI containment, a solid power ground plane should

be used as one of the inner layers extending fully under all the

power components.

Signal Circuitry Recommendations

The output voltage is sensed and regulated between the FB pin

and the FBRTN pin, which connect to the signal ground at the

load. To avoid differential mode noise pickup in the sensed

signal, the loop area should be small. Thus, the FB trace and

FBRTN trace should be routed adjacent to each other on top

of the power ground plane back to the controller.

When a power dissipating component, for example, a power

MOSFET, is soldered to a PCB, it is recommended that vias be

used liberally, both directly on the mounting pad and immediately

surrounding it. Two important reasons for this are improved

current rating through the vias and improved thermal perform-

ance from vias extended to the opposite side of the PCB, where

a plane can more readily transfer the heat to the air. Make a

mirror image of any pad being used to heat-sink the MOSFETs

The feedback traces from the switch nodes should be connected

as close as possible to the inductor. The CSREF signal should be

connected to the output voltage at the nearest inductor to the

controller.

Rev. 0 | Page 28 of 32

ADP3197

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

3.25

3.10 SQ

2.95

EXPOSED

PAD

(BOTTOM VIEW)

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

3.50 REF

0.80 MAX

0.65 TYP

12° MAX

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADP3197JCPZ-RL¹

Temperature Range Package Description

Package Option Ordering Quantity

0°C to 85°C

32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

2,500

¹Z = RoHS Compliant Part.

Rev. 0 | Page 29 of 32

ADP3197

NOTES

Rev. 0 | Page 30 of 32

ADP3197

NOTES

Rev. 0 | Page 31 of 32

ADP3197

NOTES

registered trademarks are the property of their respective owners.

D06668-0-5/07(0)

Rev. 0 | Page 32 of 32


型号：	ADP3197JCPZ-RL
厂家：	ADI
描述：	6-Bit Programmable 2-/3-Phase Synchronous Buck Controller 6位可编程2- / 3相同步降压控制器稳压器开关式稳压器或控制器电源电路开关式控制器
文件：	总32页 (文件大小：691K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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