ADP3331ARTZ-REEL7 [ADI]
High Accuracy, Ultra-Low Quiescent Current LDO; SOT-23;
| 型号： | ADP3331ARTZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | High Accuracy, Ultra-Low Quiescent Current LDO; SOT-23 光电二极管 输出元件 调节器 |
| 文件： | 总10页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Adjustable Output Ultralow IQ, 200 mA,
®
a
SOT-23, anyCAP Low Dropout Regulator
ADP3331
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High Accuracy over Line and Load: ؎0.7% @ 25؇C,
1.4% over Temperature
Ultralow Dropout Voltage: 140 mV (Typ) @ 200 mA
Can Be Used as a High Current (>1 A) LDO
Controller
Requires Only CO = 0.47 F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Q1
OUT
FB
IN
ADP3331
THERMAL
PROTECTION
CC
ERR
SD
g
m
Q2
DRIVER
BAND GAP
REF
Current and Thermal Limiting
Low Noise
Low Shutdown Current: 10 nA Typical
2.6 V to 12 V Supply Range
GND
1.5 V to 11.75 V Output Range
–40؇C to +85؇C Ambient Temperature Range
Ultrasmall Thermally Enhanced Chip-on-Lead™
SOT-23-6 Lead Package
ERR
E
V
OUT
R3
ADP3331
330k⍀
OUT
APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery-Powered Systems
PCMCIA Regulators
OUT
V
IN
IN
+
C 2
0.47F
R1
+
C 1
0.47F
FB
GND
4
SD
6
R2
ON
OFF
Bar Code Scanners
Camcorders, Cameras
Figure 1. Typical Application Circuit
GENERAL DESCRIPTION
for space restricted applications. The ADP3331 achieves excep-
tional accuracy of ±0.7% at room temperature and ±1.4% overall
accuracy over temperature, line, and load variations. The drop-
out voltage of the ADP3331 is only 140 mV (typical) at 200 mA.
This device also includes a safety current limit, thermal over-
load protection, and a shutdown feature. In shutdown mode, the
ground current is reduced to less than 2 mA. The ADP3331 has
ultralow quiescent current 34 mA (typical) in light load situations.
The SOT-23-6 package has been thermally enhanced using
Analog Device’s proprietary Chip-on-Lead feature to maxi-
mize power dissipation.
The ADP3331 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. The ADP3331 operates
with an input voltage range of 2.6 V to 12 V and delivers a load
current up to 200 mA. The ADP3331 stands out from the
conventional LDOs with a novel architecture and an enhanced
process that enables it to offer performance advantages and higher
output current than its competition. Its patented design requires
only a 0.47 mF output capacitor for stability. This device is insensi-
tive to capacitor equivalent series resistance (ESR), and is stable
with any good quality capacitor, including ceramic (MLCC) types
B
REV.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
781/461-3113
www.analog.com
Analog Devices, Inc. All rights reserved.
2014
Fax:
©
ADP3331* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DESIGN RESOURCES
• ADP3331 Material Declaration
• PCN-PDN Information
DOCUMENTATION
Application Notes
• Quality And Reliability
• Symbols and Footprints
• AN-1072: How to Successfully Apply Low Dropout
Regulators
DISCUSSIONS
View all ADP3331 EngineerZone Discussions.
• AN-262: Low-Noise Low Drop-Out Regulator for Portable
Equipment
Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
• ADP3331: Adjustable Output Ultralow IQ, 200 mA, SOT-23,
anyCAP® Low Dropout Regulator Data Sheet
Evaluation Kit Manuals
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• EVAL-ADP3330/ADP3331
TOOLS AND SIMULATIONS
• ADI Linear Regulator Design Tool and Parametric Search
DOCUMENT FEEDBACK
• ADIsimPower™ Voltage Regulator Design Tool
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
(TA = –40؇C to +85؇C, VIN = 7 V, CIN = 0.47 F, COUT = 0.47 F, unless otherwise
noted.)1, 2
ADP3331–SPECIFICATIONS
Parameter
Symbol
Conditions
Min Typ Max
Unit
OUTPUT VOLTAGE ACCURACY3
HIGH OUTPUT VOLTAGE RANGE
VIN = VOUTNOM + 0.25 V to 12 V,
V
OUTNOM ≥ 2.35 V,
IL = 0.1 mA to 200 mA,
TA = 25∞C
VIN = VOUTNOM + 0.25 V to 12 V,
–0.7
–1.4
–1.4
+0.7
+1.4
+1.4
%
%
%
V
OUTNOM ≥ 2.35 V,
IL = 0.1 mA to 150 mA,
TA = –40∞C to +85∞C
V
V
IN = VOUTNOM + 0.25 V to 12 V,
OUTNOM ≥ 2.35 V,
IL = 0.1 mA to 200 mA,
TA = –20∞C to +85∞C
OUTPUT VOLTAGE ACCURACY3
LOW OUTPUT VOLTAGE RANGE
VIN = 2.6 V to 12 V,
VOUTNOM = 1.5 V to 2.35 V,
IL = 0.1 mA to 200 mA,
TA = 25∞C
–0.7
–1.4
–1.4
+0.7
+1.4
+1.4
%
%
VIN = 2.6 V to 12 V,
V
OUTNOM = 1.5 V to 2.35 V,
IL = 0.1 mA to 150 mA,
TA = –40∞C to +85∞C
V
IN = 2.6 V to 12 V,
VOUTNOM = 1.5 V to 2.35 V,
IL = 0.1 mA to 200 mA,
TA = –20∞C to +85∞C
%
LINE REGULATION
LOAD REGULATION
GROUND CURRENT
DVO
VIN = VOUTNOM + 0.25 V to 12 V
TA = 25∞C
DVIN
0.06
0.04
mV/V
mV/mA
DVO
DIL
IL= 0.1 mA to 200 mA
TA = 25∞C
IGND
IL = 200 mA, TA = –20∞C to +85∞C
IL = 150 mA
IL = 50 mA
1.6
1.2
0.4
34
4.0
3.1
1.1
50
mA
mA
mA
mA
IL = 0.1 mA
GROUND CURRENT
IN DROPOUT
IGND
VIN = VOUTNOM – 100 mV
IL = 0.1 mA
37
55
mA
DROPOUT VOLTAGE2
VDROP
VOUT = 98% of VOUTNOM
IL = 200 mA, TA = –20∞C to +85∞C
IL = 150 mA
IL = 10 mA
IL = 1 mA
0.14 0.23
0.11 0.17
0.042 0.06
0.025 0.05
V
V
V
V
PEAK LOAD CURRENT
OUTPUT NOISE
ILDPK
VIN = VOUTNOM + 1 V
300
mA
VNOISE
f = 10 Hz–100 kHz, CL = 10 mF
IL = 200 mA, CNR = 10 nF, VOUT = 3 V
f = 10 Hz–100 kHz, CL = 10 mF
47
95
mV rms
mV rms
IL = 200 mA, CNR = 0 nF, VOUT = 3 V
SHUTDOWN THRESHOLD
VTHSD
ISD
ON
OFF
2.0
V
V
0.4
SHUTDOWN PIN INPUT CURRENT
0 < SD £ 12 V
0 < SD £ 5 V
1.9
1.4
9
6
mA
mA
GROUND CURRENT IN
SHUTDOWN MODE
IGNDSD
SD = 0 V, VIN = 12 V
0.01
2
mA
–2–
B
REV.
ADP3331
Parameter
Symbol Conditions
IOSD TA = 25∞C @ VIN = 12 V
Min
Typ
Max
Unit
OUTPUT CURRENT IN
SHUTDOWN MODE
1
2
mA
mA
TA = 85∞C @ VIN = 12 V
ERROR PIN OUTPUT LEAKAGE
IEL
VEO = 5 V
1
mA
ERROR PIN OUTPUT
LOW VOLTAGE
VEOL
ISINK = 400 mA
0.19
0.40
V
NOTES
1Ambient temperature of 85∞C corresponds to a junction temperature of 125∞C under typical full load test conditions.
2Application stable with no load.
3Assumes the use of ideal resistors. Overall accuracy also depends on the tolerance of the external resistors used to set the output voltage.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Input Supply Voltage . . . . . . . . . . . . . . . . . . . .–0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . .–0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . –40∞C to +85∞C
Operating Junction Temperature Range . . . –40∞C to +125∞C
1
2
3
6
5
4
OUT
IN
SD
ADP3331
FB
TOP VIEW
(Not to Scale)
GND
ERR
q
q
JA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . 165∞C/W
JA (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . 190∞C/W
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300∞C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
PIN FUNCTION DESCRIPTIONS
Name Function
Pin
1
OUT
Output of the Regulator. Bypass to ground
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
with a 0.47 mF or larger capacitor.
2
3
IN
Regulator Input.
ERR
Open Collector Output that goes low to
indicate that the output is about to go out
of regulation.
4
5
GND
FB
Ground.
Feedback Input. Connect to an external
resistor divider, which sets the output
voltage.
6
SD
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, this pin
should be connected to the input pin.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3331 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–3–
B
REV.
–Typical Performance Characteristics
ADP3331
3.010
3.005
45
40
35
30
V
= 3.0V
V
V
= 3.0V
OUT
V
= 3V
OUT
= 7V
OUT
3.004
3.008
3.006
IN
I
= 100A
= 0A
L
3.003
I
= 0mA
L
3.002
3.004
3.002
3.000
I
= 10mA
L
L
I
3.001
3.000
2.999
2.998
2.997
2.996
2.995
2.994
L
25
20
15
10
5
I
= 50mA
I
= 100mA
L
2.998
2.996
2.994
I
= 150mA
L
I
= 200mA
L
2.992
2.990
0
3.25
4
5
6
7
8
9
10 11 12
0
2
4
6
8
10
12
0
25
50 75 100 125 150 175 200
OUTPUT LOAD mA
INPUT VOLTAGE (V)
(
)
INPUT VOLTAGE (V)
TPC 2. Output Voltage vs. Load
Current
TPC 3. Ground Current vs. Supply
Voltage
TPC 1. Line Regulation Output
Voltage vs. Supply Voltage
0.4
3.0
1.6
I
= 0mA
V
= 7V
V
= 7V
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
L
IN
IN
I
= 200mA
L
1.4
1.2
1.0
0.3
0.2
0.1
I
= 50mA
L
I
= 150mA
L
I
= 100mA
L
0.8
0.6
I
= 150mA
= 200mA
L
I
L
0.4
0.2
0
0.0
I
= 50mA
L
I
= 0mA
L
–0.1
135
–45 –25 –5 15 35 55 75 95 115
0
–45 –25 –5 15 35 55 75 95 115 135
50
100
150
200
JUNCTION TEMPERATURE (؇C)
JUNCTION TEMPERATURE (؇C)
OUTPUT LOAD (mA)
TPC 6. Ground Current vs. Junction
Temperature
TPC 4. Ground Current vs. Load
Current
TPC 5. Output Voltage Variation % vs.
Junction Temperature
3.5
250
200
150
100
V
= 3V
OUT
SD = V
C
= 0.47F
L
3
2
3.0
2.5
2.0
1.5
1.0
0.5
0
IN
= 15⍀
R
L
V
V
= 7V
= 3V
IN
OUT
C
= 10F
L
SD = V
IN
1
R
= 15⍀
L
0
10
5
50
0
0
0
25
50
75 100
125 150 175 200
0
1.0
2.0
3.0
4.0
5.0
0
100
200
300
400
500
OUTPUT LOAD (mA)
TIME (sec)
TIME (s)
TPC 7. Dropout Voltage vs.
Output Current
TPC 8. Power-Up/Power-Down
TPC 9. Power-Up Response
–4–
B
REV.
ADP3331
3.100
3.050
3.000
2.950
2.900
200
3.040
3.000
2.960
2.920
3.040
3.000
2.960
2.920
V
R
C
= 3V
= 15⍀
= 10F
V
V
= 7V
V
R
C
= 3V
= 15⍀
= 0.47F
OUT
IN
OUT
= 3V
L
L
OUT
L
L
C
= 0.47F
L
100
7.5
7.0
7.5
7.0
20mA
800
0
0
100
200
300
400
500
0
200
400
600
1000
0
100
200
300
400
500
TIME (s)
TIME (s)
TIME (s)
TPC 11. Line Transient Response
TPC12. LoadTransientResponse
TPC 10. Line Transient Response
3.100
3.050
3.000
3
0
V
V
V
= 7V
OUT
IN
= 3V
= 10F
= 15⍀
3
2
OUT
C
R
L
500
400
300
200
100
0
L
V
V
V
C
= 7V
OUT
IN
1
0
3
0
= 3V
2.950
2.900
200
100
0
OUT
= 10F
L
I
OUT
V
ERR
2
0
V
IN
= 7V
V
20mA
800
SD
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TIME (Sec)
0
200
400
600
800
1000
0
200
400
600
1000
TIME (s)
TIME (s)
TPC 13. Load Transient Response
TPC 14. Short Circuit Current
TPC 15. Turn On–Turn Off Response
0
160
1
V
= 3.0V
C
C
= 0.47F
OUT
L
–10
–20
–30
–40
–50
–60
–70
= 0
140
NR
C
= 0.47F
= 0.1mA
L
C
C
= 10F
L
120
100
80
60
40
20
0
I
L
= 0
NR
I
= 200mA
L
C
C
= 0.47F
L
C
= 0.47F
= 200mA
L
= 10nF
NR
I
I = 0mA
L
L
0.1
C
= 10F
= 10nF
L
C
NR
I
= 200mA
WITH NOISE REDUCTION
L
C
= 10F
L
I
= 200mA
L
C
= 10F
V
= 3.0V
L
OUT
I
= 0mA WITH NOISE REDUCTION
–80
–90
L
I
= 0.1mA
I
= 200mA
L
L
0.01
0
10
20
30
(F)
40
50
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
C
FREQUENCY (Hz)
L
FREQUENCY (Hz)
TPC 17. RMS Noise vs. CL
(10 Hz to 100 kHz)
TPC 18. Output Noise Density
TPC 16. Power Supply Ripple
Rejection
–5–
B
REV.
ADP3331
THEORY OF OPERATION
innovative design allows the circuit to be stable with just a small
0.47 mF capacitor on the output. Additional advantages of the
pole-splitting scheme include superior line noise rejection and
very high regulator gain. The high gain leads to excellent regula-
tion, and ±1.4% accuracy is guaranteed over line, load, and
temperature.
The ADP3331 anyCAP LDO uses a single control loop for both
regulation and reference functions, as shown in Figure 2. The
output voltage is sensed by an external resistive voltage divider
consisting of R1 and R2. Feedback is taken from this network
by way of a series diode (D1) and a second resistor divider (R3
and R4) to the input of an amplifier.
Additional features of the circuit include current limit, thermal
shutdown, and an error flag. Compared to standard solutions that
give a warning after the output has lost regulation, the ADP3331
provides improved system performance by enabling the ERR pin
to give a warning just before the device loses regulation.
INPUT
Q1
OUTPUT
COMPENSATION
CAPACITOR
ATTENUATION
BANDGAP OUT
R1
(a)
(V
/V
)
R3 D1
C
PTAT
OS
LOAD
As the chip’s temperature rises above +165∞C, the circuit acti-
vates a soft thermal shutdown to reduce the current to a safe
level. The thermal shutdown condition is indicated by the ERR
signal going low.
NONINVERTING
WIDEBAND
DRIVER
V
g
m
PTAT
R
LOAD
CURRENT
R4
R2
ADP3331
APPLICATION INFORMATION
Capacitor Selection
GND
Output Capacitor: The stability and transient response of the
LDO is a function of the output capacitor. The ADP3331 is stable
with a wide range of capacitor values, types, and ESR (anyCAP).
A capacitor as low as 0.47 mF is all that is needed for stability;
larger capacitors can be used if high current surges on the output
are anticipated. The ADP3331 is stable with extremely low ESR
capacitors (ESR ª 0), such as multilayer ceramic capacitors
(MLCC) or OSCON. Note that the effective capacitance of some
capacitor types falls below the minimum over temperature or
with dc voltage.
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop.
The amplifier is constructed in such a way that at equilibrium it
produces a large, temperature-proportional input offset voltage
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a virtual band gap voltage, implicit in the
network, although it never appears explicitly in the circuit. Ulti-
mately, this patented design makes it possible to control the loop
with only one amplifier. This technique also improves the noise
characteristics of the amplifier by providing more flexibility on
the trade-off of noise sources, which leads to a low noise design.
Input Capacitor: An input bypass capacitor is not strictly required
but is recommended in any application involving long input
wires or high source impedance. Connecting a 0.47 mF capacitor
from the input to ground reduces the circuit’s sensitivity to
PC board layout and input transients. If a larger output capacitor
is necessary, a larger value input capacitor is also recommended.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values are chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider so that the error resulting from the base
current loading in conventional circuits is avoided.
Noise Reduction Capacitor: A noise reduction capacitor can be
used to reduce the output noise by 6 dB to 10 dB. This capaci-
tor limits the noise gain when connected between the feedback
pin (FB) and the output pin (OUT), as shown in Figure 3. Low
leakage capacitors in the 10 pF to 500 pF range provide the best
performance. Since FB is internally connected to a high imped-
ance node, any connection to this node should be carefully done
to avoid noise pickup from external sources. The pad connected
to this pin should be as small as possible; long PC board traces
are not recommended. When adding a noise reduction capacitor,
use the following guidelines:
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitor.
Most LDOs place strict requirements on the range of ESR values
for the output capacitor because they are difficult to stabilize due
to the uncertainty of the load capacitance and resistance. More-
over, the ESR value required to keep conventional LDOs stable
changes, depending on load and temperature. These ESR limita-
tions make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
∑ Maintain a minimum load current of 1 mA when not in
shutdown.
∑ For CNR values greater than 500 pF, add a 100 kW series
resistor (RNR).
It is important to note that as CNR increases, the turn-on time
will be delayed. With CNR values greater than 1 nF, this delay
may be on the order of several milliseconds.
The ADP3331 solves this problem. It can be used with any good
quality capacitor, with no constraint on the minimum ESR. The
–6–
B
REV.
ADP3331
Note that at output voltages above 5.2 V and below 1.6 V, non-
standard resistor values or the addition of a resistor to the divider
network is required to achieve the best performance. For output
voltages below 1.6 V, select a standard resistance value for R2 and
then calculate the value of R1:
ERR
E
V
OUT
R4
ADP3331
OUT
OUT
V
IN
R
NR
IN
+
C 2
0.47F
R1
R2
+
C
C 1
0.47F
NR
FB
GND
R3
SD
Ê
ˆ
VOUT
R1=
- 1 ¥ R2
Á
Ë
˜
(5)
V
FB
¯
ON
OFF
For output voltages above 5.2 V, select a standard resistance for
R1, and calculate the value of R2:
Figure 3. Noise Reduction Circuit
Output Voltage
The ADP3331 has an adjustable output voltage that can be set by
an external resistor divider. The output voltage will be divided by
R1 and R2, and then fed back to the FB pin. Refer to Figure 3.
Ê
ˆ
VFB
-VFB
R2 = R1¥
Á
Ë
˜
¯
(6)
V
OUT
After selecting values for R1 and R2, calculate the value of R3
needed to maintain the 230 kꢀ impedance:
For the output voltage to have the lowest possible sensitivity to
temperature variations, it is important that the parallel resistance
of R1 and R2 be as close as possible to 230 kW:
Ê R1¥ R2ˆ
R3 = 230 kW -
Á
˜
(7)
R1+ R2
Ë
¯
R1¥ R2
R1+ R2
= 230 kW
(1)
Using standard values, as shown in Table I, will sacrifice some
output voltage accuracy.
Also, for the best accuracy over temperature, the feedback voltage
should set for 1.204 V:
Output Current Limit
The ADP3331 is short-circuit protected by limiting the pass
transistor’s base drive current. The maximum output current is
limited to about 300 mA.
Ê
Á
ˆ
˜
R2
Ë R1 + R2¯
VOUT
=VFB
(2)
Thermal Overload Protection
Where VOUT is the desired output voltage and VFB is the virtual
band gap voltage. Note that VFB does not actually appear at the
FB pin due to loading by the internal PTAT current.
The ADP3331 is protected by its thermal overload protection
circuit against damage due to excessive power dissipation.
Thermal protection limits the die temperature to a maximum of
165∞C. Under extreme conditions (i.e., high ambient tempera-
ture and power dissipation) where the die temperature starts to
rise above 165∞C, the output current will be reduced until the
die temperature has dropped to a safe level.
Combining the above equations and solving for R1 and R2
results in the following formulas:
Ê
ˆ
VOUT
R1= 230
kW
kW
Á
Ë
˜
¯
(3)
(4)
V
FB
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device’s power dissipation should be externally
limited so that the junction temperature will not exceed 125∞C.
230
R2 =
Ê
ˆ
VFB
1-
Á
˜
VOUT
Ë
¯
Chip-on-Lead
The ADP3331 uses a patented Chip-on-Lead package design to
ensure the best thermal performance in a SOT-23 footprint. In a
standard SOT-23, most of the heat flows out of the ground pin.
The Chip-on-Lead package uses an electrically isolated die
attach, which allows all the pins to contribute to heat conduction.
This technique reduces the thermal resistance to 190∞C/W on a
2-layer board compared to >230∞C/W for a standard SOT-23
lead frame. Figure 4 shows the difference between the standard
SOT-23 and the Chip-on-Lead lead frames.
The output voltage can be adjusted to any voltage from 1.5 V to
11.75 V. For example, Table I shows some representative feed-
back resistor values for output voltages in the specified range.
Table I. Feedback Resistor Selection
VOUT (V)
R1 (1%)
R2 (1%)
R3 (1%)
1.5
1.8
2.2
2.7
3.3
5
243 kW
340 kW
422 kW
511 kW
634 kW
953 kW
1.00 MW
1.00 MW
698 kW
511 kW
412 kW
365 kW
301 kW
154 kW
34.8 kW
9
97.6 kW
–7–
B
REV.
ADP3331
degree of overshoot is determined by several factors: the output
voltage setting, the output load, the noise reduction capacitor,
and the output capacitor.
SILICON DIE
WITH
ELECTRICALLY
ISOLATED
DIE ATTACH
The output voltage setting is determined by the application and
cannot be tailored for minimum overshoot. In general, for output
voltages of 2.2 V or less, the overshoot becomes larger as the
output voltage decreases.
SILICON
DIE
NORMAL SOT-23-6 PACKAGE
THERMALLY ENHANCED
CHIP-ON-LEAD PACKAGE
The output load is also determined by the system requirements.
However, if the ADP3331 has no load on the output during
startup, a small amount of preload can be added to minimize
overshoot. A preload of 2 mA to 20 mA is recommended.
Figure 4. Chip-on-Lead Package
Calculating Junction Temperature
Device power dissipation is calculated as follows:
A noise reduction capacitor, if not already being used, is sug-
gested to reduce the overshoot. Values in the range of 10 pF to
100 pF work best, along with the preload suggested previously.
PD = V -VOUT
I
+ V
(
I
(8)
(
)
)
IN
LOAD
IN GND
Where ILOAD and IGND are load current and ground current and
The output capacitor can be adjusted to minimize the over-
shoot. Values in the 0.47 mF to 1.0 mF range should be used in
conjunction with the preload and noise reduction capacitor.
Further increases in the output capacitance may be acceptable if
the output already has a sizable load during startup.
V
IN and VOUT are the input and output voltages, respectively.
Assuming that the worst case operating conditions are ILOAD
200 mA, IGND = 4 mA, VIN = 4.2 V, and VOUT = 3.0 V, the
device power dissipation is
=
PD = 4.2V - 3.0V 200 mA + 4.2V 4 mA = 257 mW (9)
Higher Output Current
(
)
(
)
The ADP3331 can source up to 200 mA without any heat sink
or pass transistor. If higher current is needed, an appropriate pass
transistor can be used, as in Figure 5, to increase the output
current to 1 A.
The proprietary package used on the ADP3331 has a thermal
resistance of 165∞C/W when placed on a 4-layer board and
190∞C/W when placed on a 2-layer board. This allows the ambient
temperature to be significantly higher for a given power dissipa-
tion than with a standard package. Assuming a 4-layer board, the
junction temperature rise above ambient will be approximately
equal to
MJE253*
V
= 1.8V @ 1A
V
= 3.3V
OUT
IN
R1
50⍀
C1
47F
D TJA = 0.257W ¥ 165oC/W = 42.4oC
(10)
OUT
FB
IN
C2
10F
To limit the junction temperature to 125∞C, the maximum
allowable ambient temperature is
ADP3331
340k⍀
SD
TA(MAX ) = + 125oC - 42.4oC = 82.6oC
698k⍀
(11)
ERR
GND
*REQUIRES HEAT SINK
Shutdown Mode
Applying a TTL level high signal to the shutdown (SD) pin, or
tying it to the input pin, will turn the output ON. Pulling the
SD to 0.4 V or below, or tying it to ground, will turn the output
OFF. In shutdown mode, the quiescent current is reduced to
less than 1 mA.
Figure 5. High Output Current Linear Regulator
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
Error Flag Dropout Detector
1. PC board traces with larger cross sectional areas will remove
more heat from the ADP3331. For optimum heat transfer,
specify thick copper and use wide traces.
The ADP3331 will maintain its output voltage over a wide
range of load, input voltage, and temperature conditions. If the
output is about to lose regulation due to the input voltage
approaching the dropout level, the error flag will be activated.
The ERR output is an open collector, which will be driven low.
2. The thermal resistance can be decreased by approximately
10% by adding a few square centimeters of copper area to
the lands connected to the pins of the LDO.
Once set, the ERR flag’s hysteresis will keep the output low until
a small margin of operating range is restored either by raising
the supply voltage or reducing the load.
3. The feedback pin is a high impedance input, and care should
be taken when making a connection to this pin. The voltage
setting resistors and noise reduction network must be located
as close as possible. Long PC board traces are not recom-
mended. Avoid routing traces near possible noise sources.
Low Voltage Applications
In applications where the output voltage is 2.2 V or less, the
ADP3331 may begin to exhibit some turn-on overshoot. The
–8–
B
REV.
ADP3331
OUTLINE DIMENSIONS
3.00
2.90
2.80
6
1
5
2
4
3
3.00
2.80
2.60
1.70
1.60
1.50
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
4°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.30 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 6. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Output Voltage (V)
Package Option
Package Description
Branding Code
ADP3331ARTZ-REEL7
–40°C to +85°C
Adjustable
RJ-6
6-Lead SOT-23
L9B
1 Z = RoHS Compliant Part.
REVISION HISTORY
2/14—Rev. A to Rev. B
Updated Outline Dimensions..........................................................9
Changes to Ordering Guide.............................................................9
5/03— Rev. 0 to Rev. A
Renumbered figures and TPCs ........................................ Universal
Changes to Features ..........................................................................1
Changes to Figure 3 ..........................................................................7
Changes to Output Voltage Section................................................7
Changes to Table I.............................................................................7
Updated Outline Dimensions..........................................................9
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00146-0-2/14(B)
Rev. B | Page 9
相关型号：
ADP3333-5-REEL7
IC VREG 5 V FIXED POSITIVE LDO REGULATOR, 0.23 V DROPOUT, PDSO8, ULTRA SMALL, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
ADP3333ARM-1.5
IC VREG 1.5 V FIXED POSITIVE LDO REGULATOR, 0.23 V DROPOUT, PDSO8, ULTRA SMALL, MINI, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
ADP3333ARM-1.5-RL7
1.5 V FIXED POSITIVE LDO REGULATOR, 0.23 V DROPOUT, PDSO8, ULTRA SMALL, MO-187A, MSOP-8
ROCHESTER
ADP3333ARM-1.8
IC VREG 1.8 V FIXED POSITIVE LDO REGULATOR, 0.23 V DROPOUT, PDSO8, ULTRA SMALL, MINI, MSOP-8, Fixed Positive Single Output LDO Regulator
ADI
ADP3333ARM-1.8-RL
1.8 V FIXED POSITIVE LDO REGULATOR, 0.23 V DROPOUT, PDSO8, ULTRA SMALL, MO-187A, MSOP-8
ROCHESTER
ADP3333ARM-1.8-RL7
1.8 V FIXED POSITIVE LDO REGULATOR, 0.23 V DROPOUT, PDSO8, ULTRA SMALL, MO-187A, MSOP-8
ROCHESTER
©2020 ICPDF网 联系我们和版权申明