ADP3333ARM-3.15 [ADI]
IC VREG 3.15 V FIXED POSITIVE LDO REGULATOR, 0.23 V DROPOUT, PDSO8, ULTRA SMALL, MINI, MSOP-8, Fixed Positive Single Output LDO Regulator;
| 型号： | ADP3333ARM-3.15 |
| 厂家： | 
ADI |
| 描述： | IC VREG 3.15 V FIXED POSITIVE LDO REGULATOR, 0.23 V DROPOUT, PDSO8, ULTRA SMALL, MINI, MSOP-8, Fixed Positive Single Output LDO Regulator 光电二极管 输出元件 调节器 |
| 文件： | 总12页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Accuracy Ultralow IQ, 300 mA,
anyCAP Low Dropout Regulator
ADP3333
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High accuracy over line and load: 0.8% @ 25°C,
1.8% over temperature
Q1
IN
OUT
THERMAL
PROTECTION
ADP3333
Ultralow dropout voltage: 230 mV (maximum) @ 300 mA
Requires only COUT = 1.0 µF for stability
anyCAP is stable with any type of capacitor (including MLCC)
Current and thermal limiting
Low noise
Low shutdown current: < 1 µA
R1
CC
g
DRIVER
m
R2
SD
BAND GAP
REF
2.6 V to 12 V supply range
−40°C to +85°C ambient temperature range
Ultrasmall 8-lead MSOP package
GND
Figure 1.
APPLICATIONS
Cellular phones
PCMCIA cards
Personal digital assistants (PDAs)
DSP/ASIC supplies
GENERAL DESCRIPTION
The ADP3333 is a member of the ADP333x family of precision
low dropout (LDO) anyCAP® voltage regulators. Pin compatible
with the MAX8860, the ADP3333 operates with a wider input
voltage range of 2.6 V to 12 V and delivers a load current up to
300 mA. ADP3333 stands out from other conventional LDOs
with a novel architecture and an enhanced process that enables
it to offer performance advantages over its competition. Its
patented design requires only a 1.0 μF output capacitor for
stability. This device is insensitive to output capacitor equivalent
series resistance (ESR) and is stable with any good quality
capacitor, including ceramic (MLCC) types for space-restricted
applications. The ADP3333 achieves exceptional accuracy of
0.8% at room temperature and 1.8% over temperature, line,
and load variations. The dropout voltage of the ADP3333 is
only 140 mV (typical) at 300 mA. This device also includes a
safety current limit, thermal overload protection, and a shutdown
feature. In shutdown mode, the ground current is reduced to
less than 1 μA. The ADP3333 has ultralow quiescent current,
70 μA (typical) in light load situations.
ADP3333
4
1
NC
V
2
IN
IN
V
OUT
OUT
+
C
IN
1µF
+
C
OUT
1µF
SD
7
GND
3
ON
NC = NO CONNECT
OFF
Figure 2. Typical Application Circuit
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2001–2009 Analog Devices, Inc. All rights reserved.
ADP3333
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation .........................................................................9
Applications Information .............................................................. 10
Capacitor Selection .................................................................... 10
Output Current Limit ................................................................ 10
Thermal Overload Protection .................................................. 10
Calculating Junction Temperature........................................... 10
Shutdown Mode ......................................................................... 10
PCB Layout Considerations...................................................... 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
4/09—Rev. A to Rev. B
8/03—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Voltage Accuracy, Line Regulation, Load
Changes to Figure 1...........................................................................1
Updated Output Capacitor Section.............................................. 10
Updated Calculating Junction Temperature Section................. 10
Updated Outline Dimensions....................................................... 11
Updated Ordering Guide .............................................................. 11
Regulation, and Dropout Voltage Parameters, Table 1................ 3
Changes to Table 2............................................................................ 4
Added Thermal Resistance Section and Table 3; Renumbered
Sequentially ....................................................................................... 4
Changes to Table 4 ............................................................................ 5
Changes to Figure 5 and Figure 7................................................... 6
Changes to Figure 10, Figure 11, Figure 13, and Figure 15......... 7
Changes to Figure 16 and Figure 17............................................... 8
Changes to Output Capacitor Section and Calculating Junction
Temperature Section ...................................................................... 10
Updated Outline Dimensions....................................................... 11
Changes to Ordering Guide .......................................................... 11
Rev. B | Page 2 of 12
ADP3333
SPECIFICATIONS
VIN = 6.0 V, CIN = COUT = 1.0 µF, TJ = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter1
OUTPUT
Voltage Accuracy2
Symbol
Condition
Min Typ Max Unit
VOUT
VIN = VOUTNOM + 0.3 V to 12 V, IL = 0.1 mA to 300 mA, TJ = 25°C −0.8
VIN = VOUTNOM + 0.3 V to 12 V, IL = 0.1 mA to 300 mA −1.8
+0.8
+1.8
%
%
Line Regulation2
Load Regulation
Dropout Voltage
ΔVIN/ΔVOUT VIN = VOUTNOM + 0.3 V to 12 V, TJ = 25°C
ΔVOUT/ΔIOUT IL = 0.1 mA to 300 mA, TJ = 25°C
0.04
0.04
mV/V
mV/mA
VDROPOUT
VOUT = 98% of VOUTNOM
IL = 300 mA
140 230
105 185
30
mV
mV
mV
IL = 200 mA
IL = 0.1 mA
Peak Load Current
Output Noise
ILDPK
VNOISE
VIN = VOUTNOM + 1 V
f = 10 Hz to 100 kHz, CL = 10 μF, IL = 300 mA
600
45
mA
μV rms
GROUND CURRENT
In Regulation
IGND
IL = 300 mA
2.0
2.0
1.5
1.4
5.5
4.3
3.3
mA
mA
mA
mA
μA
IL = 300 mA, TJ = 25°C
IL = 300 mA, TJ = 85°C
IL = 200 mA
IL = 10 mA
200 275
IL = 0.1 mA
70
70
70
0.01
100
190
160
1
μA
μA
μA
μA
In Dropout
IGND
VIN = VOUTNOM − 100 mV, IL = 0.1 mA
VIN = VOUTNOM − 100 mV, IL = 0.1 mA, TJ = 0°C to 125°C
SD = 0 V, VIN = 12 V
In Shutdown
SHUTDOWN
IGNDSD
VTHSD
ISD
Threshold Voltage
Regulator on
2.0
V
Regulator off
0 ≤ SD ≤ 12 V
0.4
7
V
SD Input Current
0.85
0.8
μA
μA
μA
μA
0 ≤ SD ≤ 5 V
4.5
1
1
Output Current in Shutdown IOSD
TJ = 25°C, VIN = 12 V
TJ = 125°C, VIN = 12 V
0.01
0.01
1 Application stable with no load.
2 VIN = 2.6 V for models with VOUTNOM ≤ 2.3 V.
Rev. B | Page 3 of 12
ADP3333
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
THERMAL RESISTANCE
Rating
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Input Supply Voltage
Shutdown Input Voltage
Power Dissipation
Operating Ambient Temperature Range
Operating Junction Temperature Range
Soldering Conditions
−0.3 V to +16 V
−0.3 V to +16 V
Internally Limited
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
Table 3. Thermal Resistance
Package Type
θJA
Unit
°C/W
°C/W
8-Lead MSOP (4-Layer)
8-Lead MSOP (2-Layer)
158
220
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 4 of 12
ADP3333
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
OUT
IN
1
2
3
4
8
7
6
5
NC
SD
NC
NC
ADP3333
TOP VIEW
GND
(Not to Scale)
1
NC
NC = NO CONNECT
1
CAN BE CONNECTED
TO ANY OTHER PIN.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
OUT
IN
GND
Output of the Regulator. Bypass to ground with a 1.0 μF or larger capacitor.
Input Pin. Bypass to ground with a 1.0 μF or larger capacitor.
Ground Pin.
4 to 6, 8 NC
SD
No Connect. Best thermal performance is achieved when the NC pins are connected to the GND plane.
Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used,
connect this pin to the IN pin.
7
Rev. B | Page 5 of 12
ADP3333
TYPICAL PERFORMANCE CHARACTERISTICS
2.502
2.5
2.0
1.5
1.0
V
= 2.5V
V
= 6V
IN
OUT
0mA
2.500
2.498
2.496
2.494
2.492
100mA
200mA
300mA
0.5
0
2.490
2.488
3
4
5
6
7
8
9
10
11
12
0
50
100
150
200
250
300
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 4. Line Regulation Output Voltage vs. Input Voltage
Figure 7. Ground Current vs. Output Current
2.502
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
V
= 6V
= 2.5V
IN
OUT
0mA
2.500
2.498
2.496
2.494
2.492
200mA
300mA
–0.1
–0.2
–0.3
–0.4
2.490
2.488
0mA
–25
0
50
100
150
200
250
300
–50
0
25
50
75
100
125
OUTPUT CURRENT (mA)
JUNCTION TEMPERATURE (°C)
Figure 5. Output Voltage vs. Output Current
Figure 8. Output Voltage Variation % vs. Junction Temperature
140
120
100
80
3.5
V
= 2.5V
OUT
V
= 6V
I
= 100µA
IN
L
3.0
2.5
2.0
1.5
1.0
0.5
0
I
= 300mA
L
I
= 200mA
L
I
= 100mA
L
I
L
= 0µA
60
40
20
I
= 0mA
L
0
0
2
4
6
8
10
12
–50
–25
0
25
50
75
100
125
INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
Figure 6. Ground Current vs. Input Voltage
Figure 9. Ground Current vs. Junction Temperature
Rev. B | Page 6 of 12
ADP3333
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
V
R
C
= 2.5V
= 8.3Ω
= 1µF
OUT
L
L
2.52
2.51
2.50
2.49
3.50
3.00
0
50
100
150
200
250
300
40
80
140
TIME (µs)
180
OUTPUT CURRENT (mA)
Figure 10. Dropout Voltage vs. Output Current
Figure 13. Line Transient Response, CL = 1 µF
V
= 2.5V
V
= 2.5V
OUT
OUT
R
C
= 8.3Ω
= 10µF
L
L
SD = V
IN
3.0
2.5
2.0
1.5
1.0
0.5
0
2.52
2.51
2.50
2.49
R
= 8.3Ω
L
V
IN
V
OUT
3.50
3.00
1
2
3
4
40
80
140
TIME (µs)
180
TIME (Seconds)
Figure 11. VOUT During Power-Up/Power-Down
Figure 14. Line Transient Response, CL = 10 µF
V
V
C
= 4V
IN
C
= 1µF
OUT
= 2.5V
OUT
= 1µF
3
2
1
0
4
2
0
2.7
2.6
2.5
2.4
L
C
= 10µF
OUT
300
10
V
= 2.5V
OUT
SD = V
R
IN
= 8.3Ω
L
200
400
600
800
200
400
600
800
TIME (µs)
TIME (µs)
Figure 12. Power-Up Response
Figure 15. Load Transient Response, CL = 1 µF
Rev. B | Page 7 of 12
ADP3333
–20
–30
–40
–50
–60
–70
–80
–90
V
= 2.2V
OUT
V
V
C
= 4V
= 2.5V
IN
OUT
= 10µF
C
= 10µF
= 500mA
L
I
L
2.7
2.6
2.5
2.4
L
C
= 1µF
= 500mA
L
I
L
C
= 1µF
L
I
= 50µA
L
300
10
C
= 10µF
L
I
= 50µA
L
10
100
1k
10k
100k
1M
10M
200
400
600
800
FREQUENCY (Hz)
TIME (µs)
Figure 19. Power Supply Ripple Rejection
Figure 16. Load Transient Response, CL = 10 µF
120
100
2.5
0
80
60
40
3
300mA
V
= 6V
2
IN
0mA
1
20
0
0
V
= 3.6V
400
IN
0
10
20
30
40
50
200
600
800
C
(µF)
L
TIME (µs)
Figure 20. RMS Noise vs. CL (10 Hz to 100 kHz)
Figure 17. Short-Circuit Current
100
10
V
= 2.5V
OUT
= 1mA
I
L
1µF
3
2
1
0
10µF
C
= 10µF
L
C
= 1µF
L
1
10µF
0.1
0.01
1µF
V
V
R
= 6V
= 2.5V
IN
OUT
= 8.3Ω
L
2
0
0.001
10
100
1k
10k
100k
1M
200
400
600
800
FREQUENCY (Hz)
TIME (µs)
Figure 21. Output Noise Density
Figure 18. Turn-On/Turn-Off Response
Rev. B | Page 8 of 12
ADP3333
THEORY OF OPERATION
The ADP3333 anyCAP LDO uses a single control loop for
regulation and reference functions (see Figure 22). The output
voltage is sensed by a resistive voltage divider consisting of R1
and R2 that is varied to provide the available output voltage
option. Feedback is taken from this network by way of a series
diode (D1) and a second resistor divider (R3 and R4) to the
input of an amplifier.
temperature stable output. This unique arrangement specifically
corrects for the loading of the divider so that the error resulting
from base current loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
INPUT
OUTPUT
ATTENUATION
BAND GAP OUT
Q1
(V /V
)
R1
(a)
COMPENSATION
CAPACITOR
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resistance.
Moreover, the ESR value required to keep conventional LDOs
stable changes depending on load and temperature. These ESR
limitations make designing with LDOs more difficult because
of their unclear specifications and extreme variations over
temperature.
C
L
D1
R3
PTAT
OS
NONINVERTING
WIDEBAND
DRIVER
FB
V
g
m
PTAT
CURRENT
R
L
R4
R2
ADP3333
GND
Figure 22. Functional Block Diagram
A very high gain error amplifier is used to control this loop.
The amplifier is constructed in such a way that at equilibrium it
produces a large, temperature-proportional input offset voltage
that is repeatable and very well controlled. The temperature
proportional offset voltage is combined with the complementary
diode voltage to form a virtual band gap voltage, implicit in the
network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibility
on the trade-off of noise sources and leads to a low noise design.
With the ADP3333 anyCAP LDO, this is no longer true. This
device can be used with virtually any good quality capacitor,
with no constraint on the minimum ESR. Its innovative design
allows the circuit to be stable with just a small 1.0 μF capacitor
on the output. Additional advantages of the pole splitting
scheme include superior line noise rejection and very high
regulator gain, which leads to excellent line and load regulation.
An impressive 1.8% accuracy is guaranteed over line, load, and
temperature.
Additional features of the circuit include current limit and
thermal shutdown.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1/R2 resistor
divider is loaded by the diode, D1, and a second divider
consisting of R3 and R4, the values can be chosen to produce a
Rev. B | Page 9 of 12
ADP3333
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
CALCULATING JUNCTION TEMPERATURE
Device power dissipation is calculated as follows:
PD = (VIN − VOUT) IL + (VIN) IGND
The stability and transient response of the LDO is a function of
the output capacitor. The ADP3333 is stable with a wide range
of capacitor values, types, and ESR (anyCAP). A capacitor as
low as 1.0 μF is all that is needed for stability. Larger capacitors
can be used if high current surges on the output are anticipated.
The ADP3333 is stable with extremely low ESR capacitors (ESR
≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON.
Note that the effective capacitance of some capacitor types falls
below the minimum rated value over temperature or with dc
voltage. Ensure that the capacitor provides at least 1.0 μF of
capacitance over temperature and dc bias.
where IL and IGND are the load current and ground current, and
VIN and VOUT are the input and output voltages, respectively.
Assuming the worst-case operating conditions are IL = 300 mA,
IGND = 2.0 mA, VIN = 4.0 V, and VOUT = 3.0 V, the device power
dissipation is
PD = (4.0 V − 3.0 V) 300 mA + (4.0 V) 2.0 mA = 308 mW
The package used on the ADP3333 has a thermal resistance of
158°C/W for 4-layer boards. The junction temperature rise
above ambient is approximately equal to
Input Bypass Capacitor
TJA = 0.308 W × 158°C/W = 48.7°C
An input bypass capacitor is not strictly required but is recom-
mended in any application involving long input wires or high
source impedance. Connecting a 1.0 μF capacitor from the input to
ground reduces the circuit’s sensitivity to printed circuit board
(PCB) layout and input transients. If a larger output capacitor is
necessary, then a larger value input capacitor is also recommended.
Therefore, to limit the junction temperature to 125°C, the
maximum allowable ambient temperature is
TA(MAX) = 125°C − 48.7°C = 76.3°C
SHUTDOWN MODE
SD
Applying a high signal to the shutdown pin, , or connecting
OUTPUT CURRENT LIMIT
IN
it to the input pin, , turns the output on. Pulling the shutdown
The ADP3333 is short-circuit protected by limiting the pass
transistor’s base drive current. The maximum output current is
limited to about 1 A (see Figure 17).
pin to 0.3 V or below, or connecting it to ground, turns the
output off. In shutdown mode, the quiescent current is reduced
to less than 1 μA.
THERMAL OVERLOAD PROTECTION
PCB LAYOUT CONSIDERATIONS
The ADP3333 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit. Thermal
protection limits the die temperature to a maximum of 165°C.
Under extreme conditions (that is, high ambient temperature and
power dissipation) where the die temperature starts to rise above
165°C, the output current is reduced until the die temperature
drops to a safe level.
Use the following general guidelines when designing printed
circuit boards:
Keep the output capacitor as close as possible to the output
and ground pins.
Keep the input capacitor as close as possible to the input
and ground pins.
PCB traces with larger cross sectional areas remove more
heat from the ADP3333. For optimum heat transfer, use
thick copper with wide traces.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device’s power dissipation should be externally
limited so that the junction temperature does not exceed 125°C.
Connect the NC pins (Pin 4, Pin 5, Pin 6, and Pin 8) to
ground for better thermal performance.
The thermal resistance can be decreased by approximately
10% by adding a few square centimeters of copper area to
the lands connected to the pins of the LDO.
Use additional copper layers or planes to reduce the
thermal resistance. Again, connecting the other layers to
the GND and NC pins of the ADP3333 is best, but not
necessary. When connecting the ground pad to other
layers, use multiple vias.
Rev. B | Page 10 of 12
ADP3333
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 23. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Output Voltage (V)
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Package Option
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
LKA
LKA
LKB
LKB
LKC
LKC
LKD
LKD
LKE
ADP3333ARM-1.5-RL
ADP3333ARM-1.5-RL7
ADP3333ARM-1.8-RL
ADP3333ARM-1.8-RL7
ADP3333ARM-2.5-RL
ADP3333ARM-2.5-RL7
ADP3333ARM-2.77-RL
ADP3333ARM-2.77-R7
ADP3333ARM-3-REEL
ADP3333ARM-3-REEL7
ADP3333ARM-3.15-RL
ADP3333ARM-3.15-R7
ADP3333ARM-3.3-RL
ADP3333ARM-3.3-RL7
ADP3333ARM-5-REEL
ADP3333ARM-5-REEL7
ADP3333ARMZ-1.5-R71
ADP3333ARMZ-1.5-RL1
ADP3333ARMZ-1.8-RL1
ADP3333ARMZ-1.8RL71
ADP3333ARMZ-2.5-RL1
ADP3333ARMZ-2.5-R71
ADP3333ARMZ-2.77R71
ADP3333ARMZ-3-R71
ADP3333ARMZ-3.15R71
ADP3333ARMZ-3.3-R71
ADP3333ARMZ-3.3-RL1
ADP3333ARMZ-5-R71
ADP3333ARMZ-5-RL1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
1.5
1.5
1.8
1.8
2.5
2.5
2.77
2.77
3
3
LKE
LKF
LKF
3.15
3.15
3.3
3.3
5
LKG
LKG
LKH
LKH
L1X
L1X
L1U
L1U
L1V
L1V
L1Y
L1W
L1Z
L20
5
1.5
1.5
1.8
1.8
2.5
2.5
2.77
3.0
3.15
3.3
3.3
5.0
5.0
L20
L21
L21
1 Z = RoHS Compliant Part.
Rev. B | Page 11 of 12
ADP3333
NOTES
©2001–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02615-0-4/09(B)
Rev. B | Page 12 of 12
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