ADP3336ARMZ-REEL7 [ADI]
Small, Adjustable Output, 500 mA anyCAP® Low Dropout Regulator;
| 型号： | ADP3336ARMZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Small, Adjustable Output, 500 mA anyCAP® Low Dropout Regulator PC 光电二极管 输出元件 调节器 |
| 文件： | 总10页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Accuracy Ultralow IQ, 500 mA
®
a
anyCAP Adjustable Low Dropout Regulator
ADP3336
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High Accuracy Over Line and Load: ؎0.9% @ 25؇C,
؎1.8% Over Temperature
Ultralow Dropout Voltage: 200 mV (Typ) @ 500 mA
Requires Only CO = 1.0 F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Q1
IN
OUT
FB
ADP3336
THERMAL
PROTECTION
CC
g
DRIVER
m
Current and Thermal Limiting
Low Noise
Low Shutdown Current: < 1.0 A
2.6 V to 12 V Supply Range
SD
BANDGAP
REF
1.5 V to 10 V Output Range
–40؇C to +85؇C Ambient Temperature Range
Ultrasmall Thermally-Enhanced 8-Lead MSOP Package
GND
APPLICATIONS
PCMCIA Card
Cellular Phones
Camcorders, Cameras
Networking Systems, DSL/Cable Modems
Cable Set-Top Box
MP3/CD Players
ADP3336
OUT
OUT
OUT
IN
IN
SD
V
OUT
DSP Supply
R1
R2
C
V
OUT
1F
IN
FB
C
IN
GND
1F
ON
GENERAL DESCRIPTION
OFF
The ADP3336 is a member of the ADP333x family of precision
low dropout anyCAP voltage regulators. The ADP3336 operates
with an input voltage range of 2.6 V to 12 V and delivers a
continuous load current up to 500 mA. The ADP3336 stands
out from conventional LDOs with the lowest thermal resistance
of any MSOP-8 package and an enhanced process that enables
it to offer performance advantages beyond its competition.
Its patented design requires only a 1.0 µF output capacitor for
stability. This device is insensitive to output capacitor Equiva-
lent Series Resistance (ESR), and is stable with any good
quality capacitor, including ceramic (MLCC) types for space-
restricted applications. The ADP3336 achieves exceptional
accuracy of 0.9% at room temperature and 1.8% over tem-
perature, line, and load. The dropout voltage of the ADP3336 is
only 200 mV (typical) at 500 mA. This device also includes a
safety current limit, thermal overload protection and a shutdown
feature. In shutdown mode, the ground current is reduced to
less than 1 µA. The ADP3336 has ultralow quiescent current
80 µA (typical) in light load situations.
Figure 1. Typical Application Circuit
anyCAP is a registered trademark of Analog Devices Inc.
REV.
A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000-2011
781-461-3113
Fax:
ADP3336* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DESIGN RESOURCES
• ADP3336 Material Declaration
• PCN-PDN Information
DOCUMENTATION
Application Notes
• Quality And Reliability
• Symbols and Footprints
• AN-1072: How to Successfully Apply Low Dropout
Regulators
DISCUSSIONS
View all ADP3336 EngineerZone Discussions.
• AN-262: Low-Noise Low Drop-Out Regulator for Portable
Equipment
Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
• ADP3336:High Accuracy Ultralow IQ, 500 mA anyCAP®
Adjustable Low Dropout Regulator Data Sheet
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
TOOLS AND SIMULATIONS
• ADI Linear Regulator Design Tool and Parametric Search
• ADIsimPower™ Voltage Regulator Design Tool
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
REFERENCE DESIGNS
• CN0162
• CN0206
• CN0241
• CN0254
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ADP3336–SPECIFICATIONS1, 2(VIN = 6.0 V, CIN = COUT = 1.0 F, TJ = –40؇C to +125؇C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OUTPUT
Voltage Accuracy3, 4
VOUT
VIN = VOUT(NOM) + 0.4 V to 12 V
IL = 0.1 mA to 500 mA
TJ = 25°C
–0.9
+0.9
%
V
IN = VOUT(NOM) + 0.4 V to 12 V
–1.8
–2.3
+1.8
+2.3
%
IL = 0.1 mA to 500 mA
TJ = –40°C to +125°C
V
IN = VOUT(NOM) + 0.4 V to 12 V
%
IL = 0.1 mA to 500 mA
TJ = 150°C
Line Regulation3
VIN = VOUT(NOM) + 0.4 V to 12 V
IL = 0.1 mA
0.04
0.04
mV/V
mV/mA
TA = 25°C
Load Regulation
Dropout Voltage
IL = 0.1 mA to 500 mA
TA = 25°C
VDROP
VOUT = 98% of VOUT(NOM)
IL = 500 mA
200
140
60
400
235
130
mV
mV
mV
IL = 300 mA
IL = 50 mA
IL = 0.1 mA
10
mV
Peak Load Current
Output Noise
ILDPK
VNOISE
VIN = VOUT(NOM) + 1 V
f = 10 Hz–100 kHz, CL = 10 µF
IL = 500 mA, CNR = 10 nF, VOUT = 2.5
f = 10 Hz–100 kHz, CL = 10 µF
IL = 500 mA, CNR = 0 nF, VOUT = 2.5
800
27
mA
µV rms
45
µV rms
GROUND CURRENT5
In Regulation
IGND
IL = 500 mA
IL = 300 mA
IL = 50 mA
IL = 0.1 mA
VIN = VOUT(NOM) – 100 mV
IL = 0.1 mA
4.5
2.6
0.5
80
10
6
1.5
110
400
mA
mA
mA
µA
In Dropout
IGND
120
µA
In Shutdown
IGNDSD
SD = 0 V, VIN = 12 V
0.01
1
µA
SHUTDOWN
Threshold Voltage
VTHSD
ON
2.0
V
OFF
0.4
5
1
V
SD Input Current
Output Current In Shutdown
ISD
IOSD
0 ≤ SD ≤ 12 V
TA = 25°C, VIN = 12 V
TA = 85°C, VIN = 12 V
1.2
0.01
0.01
µA
µA
µA
1
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2Application stable with no load.
3VIN = 2.6 V to 12 V for models with VOUT(NOM) ≤ 2.2 V.
4Over the VOUT range of 1.5 V to 10 V.
5Ground current includes current through external resistors.
Specifications subject to change without notice.
–2–
REV.
A
ADP3336
PIN FUNCTION DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . –40°C to +85°C
Operating Junction Temperature Range . . . –40°C to +150°C
Pin
No.
Mnemonic Function
1, 2, 3 OUT
Output of the Regulator. Bypass to
ground with a 1.0 µF or larger capacitor.
All pins must be connected together for
proper operation.
θ
JA 2-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153°C/W
JA 4-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W
θ
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
4
5
GND
FB
Ground Pin.
Feedback Input. Connect to an external
resistor divider which sets the output
voltage. Can also be used for further
reduction of output noise (see text for
detail).
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
Capacitor required if COUT > 3.3 µF.
6
SD
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, this pin
should be connected to the input pin.
7, 8
IN
Regulator Input. All pins must be con-
nected together for proper operation.
PIN CONFIGURATION
1
2
3
4
8
7
6
5
IN
OUT
OUT
ADP3336
TOP VIEW
(Not to Scale)
IN
OUT
GND
SD
FB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3336 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
A
REV.
–3–
–Typical Performance Characteristics
ADP3336
2.201
140
120
100
80
2.202
V
V
= 2.2V
I
= 100A
V
= 2.2V
V
= 2.2V
OUT
= 6V
L
OUT
OUT
I
= 0
2.200
2.199
2.198
2.197
2.196
2.195
IN
2.201
2.200
2.199
2.198
2.197
2.196
L
150mA
300mA
I
= 0
L
60
40
20
0
2.194
2.193
2.195
2.194
500mA
0
0
100
200
300
400
500
2
4
6
8
10
12
2
4
6
8
10
12
INPUT VOLTAGE – Volts
OUTPUT LOAD – mA
INPUT VOLTAGE – Volts
TPC 2. Output Voltage vs. Load
Current
TPC 1. Line Regulation Output
Voltage vs. Supply Voltage
TPC 3. Ground Current vs. Supply
Voltage
0.5
5.0
8
0
I
= 500mA
V
V
= 6V
= 2.2V
L
IN
OUT
V
V
= 6V
= 2.2V
IN
OUT
7
0.4
300mA
4.0
3.0
6
5
4
3
0.3
0.2
300mA
0.1
2.0
1.0
0
500mA
0
100mA
50mA
2
1
500mA
–0.1
0
0
–0.2
0
0
–40 –15
5
25
65
85 105 125
100
200
300
400
500
45
–40 –15
5
25
45
65
85 105 125
OUTPUT LOAD – mA
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
TPC 4. Ground Current vs. Load
Current
TPC 5. Output Voltage Variation %
vs. Junction Temperature
TPC 6. Ground Current vs. Junction
Temperature
250
V
= 2.2V
OUT
V
= 2.2V
OUT
3.0
2.5
2.0
1.5
1.0
0.5
0
SD = V
R
3
IN
= 4.4⍀
200
150
C
= 1F
L
OUT
2
1
0
4
2
0
C
= 10F
OUT
100
50
0
V
= 2.2V
OUT
SD = V
IN
R
= 4.4⍀
L
1
2
3
4
200
400
600
800
TIME – Sec
TIME – s
0
100
200
300
400
500
OUTPUT LOAD – mA
TPC 8. Power-Up/Power-Down
TPC 7. Dropout Voltage vs.
Output Current
TPC 9. Power-Up Response
–4–
REV.
A
ADP3336
2.210
2.200
2.190
2.189
2.179
3.500
3.000
2.3
2.2
2.1
2.210
2.200
2.190
2.189
2.179
3.500
3.000
V
R
C
= 2.2V
= 4.4⍀
= 10F
V
R
C
= 2.2V
= 4.4⍀
= 1F
OUT
OUT
L
L
L
L
400
200
0
V
V
C
= 6V
= 2.2V
= 1F
IN
OUT
L
40
80
140
180
200
400
TIME – s
600
800
40
80
140
180
TIME – s
TIME – s
TPC 12. Load Transient Response
TPC 10. Line Transient Response
TPC 11. Line Transient Response
V
V
R
= 6V
IN
3
2
2.2
0
2.3
2.2
2.1
= 2.2V
= 4.4⍀
OUT
1F
L
1
0
10F
FULL SHORT
10F
800m⍀
SHORT
1F
3
2
400
2
0
V
V
C
= 2.2V
= 6V
= 10F
V
= 4V
1
0
200
0
OUT
IN
IN
L
200
400
TIME – s
600
800
200
400
TIME – s
600
800
200
400
TIME – s
600
800
TPC 15. Turn On–Turn Off Response
TPC 14. Short Circuit Current
TPC 13 Load Transient Response
100
160
140
–20
V
= 2.2V
= 1mA
V
= 2.2V
OUT
OUT
V
C
= 2.0V
= 10nF
OUT
C
= 10F
= 500mA
I
L
L
–30
–40
–50
–60
–70
–80
–90
NR
I
L
C
C
= 10F
C
= 1F
= 500mA
L
10
1
C
C
= 10F
L
L
= 0
I
NR
120
100
80
60
40
20
0
= 10nF
L
NR
IL = 500mA WITHOUT
NOISE REDUCTION
C
= 1F
= 0
L
C
NR
C
= 1F
= 50A
L
IL = 500mA WITH
NOISE REDUCTION
I
L
0.1
0.01
IL = 0mA WITHOUT
NOISE REDUCTION
C
C
= 1F
= 10nF
L
NR
C
= 10F
= 50A
L
I
L
IL = 0mA WITH NOISE REDUCTION
0.001
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
0
10
20
C
30
– F
40
50
FREQUENCY – Hz
L
TPC 18. Output Noise Density
TPC 16. Power Supply Ripple
Rejection
TPC 17. RMS Noise vs. CL
(10 Hz–100 kHz)
A
–5–
REV.
ADP3336
THEORY OF OPERATION
The new anyCAP LDO ADP3336 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
superior line noise rejection and very high regulator gain, which
leads to excellent line and load regulation. An impressive 1.8%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit and ther-
mal shutdown.
APPLICATION INFORMATION
Capacitor Selection
OUTPUT
R1
INPUT
Q1
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3336 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 1 µF is all that is
needed for stability; larger capacitors can be used if high output
current surges are anticipated. The ADP3336 is stable with
extremely low ESR capacitors (ESR ≈ 0), such as multilayer
ceramic capacitors (MLCC) or OSCON. Note that the effective
capacitance of some capacitor types may fall below the mini-
mum at cold temperature. Ensure that the capacitor provides
more than 1 µF at minimum temperature.
COMPENSATION
CAPACITOR
ATTENUATION
/V
(V
)
BANDGAP OUT
C
R
LOAD
D1
R3
PTAT
(a)
R2
FB
NONINVERTING
WIDEBAND
DRIVER
V
OS
g
m
LOAD
PTAT
CURRENT
R4
ADP3336
GND
Figure 2. Functional Block Diagram
Input Bypass Capacitor
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium pro-
duces a large, temperature-proportional input, “offset voltage”
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control
the loop with only one amplifier. This technique also improves
the noise characteristics of the amplifier by providing more flexibil-
ity on the trade-off of noise sources that leads to a low noise design.
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground
reduces the circuit's sensitivity to PC board layout. If a larger
value output capacitor is used, then a larger value input capaci-
tor is also recommended.
Noise Reduction
A noise reduction capacitor (CNR) can be placed between
the output and the feedback pin to further reduce the noise by
6 dB–10 dB (TPC 18). Low leakage capacitors in 100 pF–500 pF
range provide the best performance. Since the feedback pin (FB)
is internally connected to a high impedance node, any connection
to this node should be carefully done to avoid noise pickup from
external sources. The pad connected to this pin should be as
small as possible and long PC board traces are not recommended.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider thus avoiding the error resulting from
base current loading in conventional circuits.
When adding a noise reduction capacitor, maintain a mini-
mum load current of 1 mA when not in shutdown.
It is important to note that as CNR increases, the turn-on time
will be delayed. With CNR values greater than 1 nF, this delay
may be on the order of several milliseconds.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
ADP3336
IN
IN
OUT
OUT
OUT
V
IN
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. More-
over, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limita-
tions make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
C
IN
1F
V
OUT
SD
C
OUT
1F
C
R1
R2
ON
NR
FB
GND
OFF
With the ADP3336 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 µF capacitor on the out-
put. Additional advantages of the pole-splitting scheme include
Figure 3. Typical Application Circuit
A
–6–
REV.
ADP3336
Output Voltage
The ADP3336 has an adjustable output voltage that can be set
by an external resistor divider. The output voltage will be
divided by R1 and R2, and then fed back to the FB pin.
In order to have the lowest possible sensitivity of the output
voltage to temperature variations, it is important that the paral-
lel resistance of R1 and R2 is always 50 kΩ.
DIE
R1× R2
= 50 kΩ
R1+ R2
Also, for the best accuracy over temperature the feedback volt-
age should be set for 1.178 V:
Figure 4. Thermally Enhanced Paddle-Under-Lead Package
Thermal Overload Protection
R2
R1+ R2
The ADP3336 is protected against damage from excessive power
dissipation by its thermal overload protection circuit which limits
the die temperature to a maximum of 165°C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165°C, the output
current is reduced until the die temperature has dropped to a
safe level. The output current is restored when the die tempera-
ture is reduced.
VFB =VOUT
×
where VOUT is the desired output voltage and VFB is the “virtual
bandgap” voltage. Note that VFB does not actually appear at the
FB pin due to loading by the internal PTAT current.
Combining the above equations and solving for R1 and R2 gives
the following formulas:
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150°C.
VOUT
R1= 50 kΩ ×
VFB
50 kΩ
R2 =
VFB
Calculating Junction Temperature
Device power dissipation is calculated as follows:
1–
VOUT
PD = (VIN – VOUT) ILOAD + (VIN) IGND
Table I. Feedback Resistor Selection
Where ILOAD and IGND are load current and ground current, VIN
and VOUT are input and output voltages respectively.
VOUT
1.5 V
1.8 V
2.2 V
2.7 V
3.3 V
5 V
R1 (1% Resistor)
63.4 kΩ
R2 (1% Resistor)
Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V and
232 kΩ
147 kΩ
107 kΩ
88.7 kΩ
78.7 kΩ
64.9 kΩ
56.2 kΩ
VOUT = 3.3 V, device power dissipation is:
76.8 kΩ
PD = (5 – 3.3) 400 mA + 5.0(4 mA) = 700 mW
93.1 kΩ
The proprietary package used in the ADP3336 has a thermal
resistance of 110°C/W, significantly lower than a standard
MSOP-8 package. Assuming a 4-layer board, the junction tem-
perature rise above ambient temperature will be approximately
equal to:
115 kΩ
140 kΩ
210 kΩ
10 V
422 kΩ
∆TJA = 0.700W ×110°C = 77.0°C
Paddle-Under-Lead Package
To limit the maximum junction temperature to 150°C, maxi-
The ADP3336 uses a proprietary paddle-under-lead package
design to ensure the best thermal performance in an MSOP-8
footprint. This new package uses an electrically isolated die
attach that allows all pins to contribute to heat conduction.
This technique reduces the thermal resistance to 110°C/W on a
4-layer board as compared to >160°C/W for a standard MSOP-8
leadframe. Figure 4 shows the standard physical construction
of the MSOP-8 and the paddle-under-lead leadframe.
mum allowable ambient temperature will be:
T
AMAX = 150°C – 77.0°C = 73.0°C
Printed Circuit Board Layout Consideration
All surface mount packages rely on the traces of the PC board to
conduct heat away from the package.
REV. A
–7–
ADP3336
In standard packages the dominant component of the heat resis-
tance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement mean-
ingful, however, a significant copper area on the PCB must be
attached to these fused pins.
It is not recommended to use solder mask or silkscreen on the
PCB traces adjacent to the ADP3336’s pins since it will increase
the junction-to-ambient thermal resistance of the package.
Shutdown Mode
Applying a TTL high signal to the shutdown (SD) pin or tying
it to the input pin, will turn the output ON. Pulling SD down to
0.4 V or below, or tying it to ground will turn the output OFF.
In shutdown mode, quiescent current is reduced to much less
than 1 µA.
The proprietary paddle-under-lead frame design of the ADP3336
uniformly minimizes the value of the dominant portion of the
thermal resistance. It ensures that heat is conducted away by all
pins of the package. This yields a very low 110°C/W thermal
resistance for an MSOP-8 package, without any special board
layout requirements, relying only on the normal traces connected
to the leads. This yields a 33% improvement in heat dissipation
capability as compared to a standard MSOP-8 package. The
thermal resistance can be decreased by, approximately, an addi-
tional 10% by attaching a few square cm of copper area to the
IN pin of the ADP3336 package.
A
–8–
REV.
ADP3336
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 5. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
Output Voltage
Package Description
Package Option
Branding
ADP3336ARMZ-REEL7
Adjustable
8-Lead MSOP
RM-8
L22
1 Z = RoHS Compliant Part.
REVISION HISTORY
1/11—Rev. 0 to Rev. A
Changes to Ordering Guide.............................................................9
10/00—Revision 0: Initial Version
©2000-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09653-0-1/11(A)
Rev. A | Page 9
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