ADP3418JRZ [ADI]

IC 2 CHANNEL, HALF BRDG BASED MOSFET DRIVER, PDSO8, LEAD FREE, MS-012AA, SOIC-8, MOSFET Driver;


型号：	ADP3418JRZ
厂家：	ADI
描述：	IC 2 CHANNEL, HALF BRDG BASED MOSFET DRIVER, PDSO8, LEAD FREE, MS-012AA, SOIC-8, MOSFET Driver 驱动器
文件：	总12页 (文件大小：222K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Dual Bootstrapped 12 V MOSFET

Driver with Output Disable

ADP3418

FEATURES

FUNCTIONAL BLOCK DIAGRAM

All-In-One Synchronous Buck Driver

Bootstrapped High-Side Drive

1 PWM Signal Generates Both Drives

Anticross-Conduction Protection Circuitry

Output Disable Control Turns Off Both MOSFETs to

Float Output per Intel^®VRM 10 Specification

VCC

BST

DRVH

APPLICATIONS

Multiphase Desktop CPU Supplies

Single-Supply Synchronous Buck Converters

OVERLAP

PROTECTION

CIRCUIT

GENERAL DESCRIPTION

The ADP3418 is a dual high voltage MOSFET driver optimized

for driving two N-channel MOSFETs, which are the two switches

in a nonisolated synchronous buck power converter. Each of the

drivers is capable of driving a 3000 pF load with a 20 ns propa-

gation delay and a 30 ns transition time. One of the drivers can

be bootstrapped and is designed to handle the high voltage slew

rate associated with floating high-side gate drivers. The ADP3418

includes overlapping drive protection to prevent shoot-through

current in the external MOSFETs. The OD pin shuts off both

the high-side and the low-side MOSFETs to prevent rapid output

capacitor discharge during system shutdown.

DRVL

ADP3418

PGND

The ADP3418 is specified over the commercial temperature

range of 0°C to 85°C and is available in a thermally enhanced

8-lead SOIC package.

12V

VCC

BST

ADP3418

BST

DRVH

TO INDUCTOR

DELAY

+1V

DRVL

PGND

Figure 1. General Application Circuit

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

ADP3418–SPECIFICATIONS¹

(VCC = 12 V, BST = 4 V to 26 V, T_A= 0؇C to 85؇C, unless otherwise noted.)

Parameter

Symbol

Conditions

Min Typ Max

Unit

SUPPLY

Supply Voltage Range

Supply Current

V_CC

I_SYS

4.15

13.2

BST = 12 V, IN = 0 V

OD INPUT

Input Voltage High

Input Voltage Low

Input Current

2.8

–1

µA

0.8

Propagation Delay Time²

t_pdlOD

t_pdhOD

See Figure 2

PWM INPUT

Input Voltage High

Input Voltage Low

Input Current

3.5

–1

µA

0.8

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current

Output Resistance, Sinking Current

Transition Times²

V_BST– V_SW= 12 V

1.8

1.0

3.0

2.5

Ω

_BST– V_SW= 12 V

See Figure 3, V_BST– V_SW= 12 V,

_LOAD= 3 nF

t_rDRVH

t_fDRVH

See Figure 3, V_BST– V_SW= 12 V,

C_LOAD= 3 nF

See Figure 3, V_BST– V_SW= 12 V

V_BST– V_SW= 12 V

Propagation Delay^{2, 3}

t_pdhDRVH

t_pdlDRVH

LOW-SIDE DRIVER

Output Resistance, Sourcing Current

Output Resistance, Sinking Current

Transition Times²

1.8

1.0

3.0

2.5

Ω

t_rDRVL

t_fDRVL

t_pdhDRVL

t_pdlDRVL

See Figure 3, C_LOAD= 3 nF

See Figure 3

Propagation Delay^{2, 3}

See Figure 3

NOTES

¹All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).

²AC specifications are guaranteed by characterization but not production tested.

³For propagation delays, t_pdhrefers to the specified signal going high, and t_pdlrefers to it going low.

Specifications subject to change without notice.

–2–

REV. 0

ADP3418

ABSOLUTE MAXIMUM RATINGS*

Junction-to-Air Thermal Resistance (θ_JA)

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V

BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 15 V

BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V

DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +15 V

<200 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to +15 V

DRVH . . . . . . . . . . . . . . . . . . . . . . SW – 0.3 V to BST + 0.3 V

DRVL (<200 ns) . . . . . . . . . . . . . . . . . . . –2 V to VCC + 0.3 V

All Other Inputs and Outputs . . . . . . . –0.3 V to VCC + 0.3 V

Operating Ambient Temperature Range . . . . . . . . 0°C to 85°C

Operating Junction Temperature Range . . . . . . . 0°C to 150°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

2-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W

4-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability. Absolute maximum

ratings apply individually only, not in combination. Unless otherwise specified, all

voltages are referenced to PGND.

ORDERING GUIDE

Temperature Range

Model

Package Option

ADP3418JR

0°C to 85°C

RN-8 (SOIC-8)

PIN CONFIGURATION

RN-8

BST

DRVH

ADP3418

TOP VIEW

(Not to Scale)

PGND

DRVL

VCC

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds

this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be chosen between

100 nF and 1 µF.

Logic Level Input. This pin has primary control of the drive outputs.

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

Power Ground. Should be closely connected to the source of the lower MOSFET.

VCC

DRVL

PGND

This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating

return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of

the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high-low

transition delay is determined at this pin.

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADP3418 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

REV. 0

–3–

ADP3418

TIMING CHARACTERISTICS

t_pdlOD

t_pdhOD

DRVH

90%

DRVL

10%

Figure 2. Output Disable Timing Diagram

t_pdlDRVLt_fDRVL

t_pdlDRVH

t_rDRVL

DRVL

t_fDRVH

t_pdhDRVHt_rDRVH

DRVH-SW

t_pdhDRVL

Figure 3. Nonoverlap Timing Diagram (Timing is referenced to the 90% and 10% points, unless otherwise noted.)

–4–

REV. 0

Typical Performance Characteristics–ADP3418

= 12V

= 3nF

LOAD

DRVL

DRVH

DRVL

100

125

JUNCTION TEMPERATURE – ؇C

TPC 1. DRVH Rise and DRVL Fall Times

TPC 4. DRVH and DRVL Fall Times vs. Temperature

= 25؇C

= 12V

DRVH

DRVL

DRVH

DRVL

LOAD CAPACITANCE – nF

TPC 2. DRVH Fall and DRVL Rise Times

TPC 5. DRVH and DRVL Rise Times vs. Load Capacitance

= 12V

T = 25؇C

= 3nF

= 12V

LOAD

DRVH

DRVL

DRVH

DRVL

100

125

JUNCTION TEMPERATURE – ؇C

LOAD CAPACITANCE – nF

TPC 3. DRVH and DRVL Rise Times vs. Temperature

TPC 6. DRVH and DRVL Fall Times vs. Load Capacitance

REV. 0

–5–

ADP3418

= 25؇C

= 12V

= 3nF

LOAD

200

400

600

800

1000

1200

VOLTAGE – V

IN FREQUENCY – kHz

TPC 7. Supply Current vs. Frequency

TPC 9. DRVL Output Voltage vs. Supply Voltage

= 12V

= 3nF

LOAD

f_IN= 250kHz

100

125

JUNCTION TEMPERATURE – ؇C

TPC 8. Supply Current vs. Temperature

–6–

REV. 0

ADP3418

THEORY OF OPERATION

to fall from V_INto 1 V. Once the voltage on the SW pin has

fallen to 1 V, Q2 will begin turn-on. By waiting for the voltage on

the SW pin to reach 1 V, the overlap protection circuit ensures

that Q1 is off before Q2 turns on, regardless of variations in

temperature, supply voltage, gate charge, and drive current.

The ADP3418 is a dual MOSFET driver optimized for driving

two N-channel MOSFETs in a synchronous buck converter

topology. A single PWM input signal is all that is required to

properly drive the high-side and the low-side MOSFETs. Each

driver is capable of driving a 3 nF load at speeds up to 500 kHz.

To prevent the overlap of the gate drives during Q2’s turn-off

and Q1’s turn-on, the overlap circuit provides an internal delay

that is set to 50 ns. When the PWM input signal goes high, Q2

will begin to turn off (after a propagation delay), but before Q1

can turn on, the overlap protection circuit waits for the voltage

at DRVL to drop to around 10% of V_CC. Once the voltage at

DRVL has reached the 10% point, the overlap protection circuit

will wait for a 20 ns typical propagation delay. Once the delay

period has expired, Q1 will begin turn-on.

A more detailed description of the ADP3418 and its features

follows. Refer to the Functional Block Diagram.

Low-Side Driver

The low-side driver is designed to drive a ground-referenced

low R_DS(ON)N-channel MOSFET. The bias to the low-side

driver is internally connected to the VCC supply and PGND.

When the driver is enabled, the driver’s output is 180° out of

phase with the PWM input. When the ADP3418 is disabled, the

low-side gate is held low.

APPLICATION INFORMATION

Supply Capacitor Selection

High-Side Driver

For the supply input (V_CC) of the ADP3418, a local bypass

capacitor is recommended to reduce the noise and to supply some

of the peak currents drawn. Use a 4.7 µF, low ESR capacitor.

Multilayer ceramic chip (MLCC) capacitors provide the best

combination of low ESR and small size. Keep the ceramic

capacitor as close as possible to the ADP3418.

The high-side driver is designed to drive a floating low R_DS(ON)

N-channel MOSFET. The bias voltage for the high-side driver

is developed by an external bootstrap supply circuit, which is

connected between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap

capacitor, C_BST. When the ADP3418 is starting up, the SW pin

is at ground, so the bootstrap capacitor will charge up to VCC

through D1. When the PWM input goes high, the high-side

driver will begin to turn on the high-side MOSFET, Q1, by

pulling charge out of C_BST. As Q1 turns on, the SW pin will rise

up to V_IN, forcing the BST pin to V_IN+ V_C(BST), which is enough

gate-to-source voltage to hold Q1 on. To complete the cycle,

Q1 is switched off by pulling the gate down to the voltage at the

SW pin. When the low-side MOSFET, Q2, turns on, the SW

pin is pulled to ground. This allows the bootstrap capacitor to

charge up to VCC again.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (C_BST) and

a diode, as shown in Figure 1. Selection of these components

can be done after the high-side MOSFET has been chosen.

The bootstrap capacitor must have a voltage rating that is able

to handle twice the maximum supply voltage. A minimum 50 V

rating is recommended. The capacitance is determined using

the following equation

Q_GATE

∆V_BST

C_BST

(1)

The high-side driver’s output is in phase with the PWM input.

When the driver is disabled, the high-side gate is held low.

where Q_GATEis the total gate charge of the high-side MOSFET,

and ∆V_BSTis the voltage droop allowed on the high-side MOSFET

drive. For example, an IPD30N06 has a total gate charge of

about 20 nC. For an allowed droop of 200 mV, the required

bootstrap capacitance is 100 nF. A good quality ceramic capaci-

tor should be used.

Overlap Protection Circuit

The overlap protection circuit prevents both of the main power

switches, Q1 and Q2, from being on at the same time. This is

done to prevent shoot-through currents from flowing through

both power switches and the associated losses that can occur

during their on-off transitions. The overlap protection circuit

accomplishes this by adaptively controlling the delay from Q1’s

turn-off to Q2’s turn-on and by internally setting the delay from

Q2’s turn-off to Q1’s turn-on.

A small-signal diode can be used for the bootstrap diode due to

the ample gate drive voltage supplied by V_CC. The bootstrap diode

must have a minimum 15 V rating to withstand the maximum

supply voltage. The average forward current can be estimated by

I_F₍

= Q_GATE× f_MAX

(2)

AVG

)

To prevent the overlap of the gate drives during Q1’s turn-off

and Q2’s turn-on, the overlap circuit monitors the voltage at the

SW pin. When the PWM input signal goes low, Q1 will begin to

turn-off (after a propagation delay), but before Q2 can turn on,

the overlap protection circuit waits for the voltage at the SW pin

where f_MAXis the maximum switching frequency of the control-

ler. The peak surge current rating should be checked in-circuit,

since this is dependent on the source impedance of the 12 V

supply and the ESR of C_BST

REV. 0

–7–

ADP3418

1.6␮H

470␮F/16V

NICHICON PW SERIES

12V

4.7␮F

RTN

1N4148WS

ADP3418 ^100nF

IPD12N03L

BST

DRVH

1N4148WS

820␮F/2.5V

FUJITSU RE SERIES

14m⍀ ESR (EACH)

600nH/1.6m⍀

CC(CORE)

0.8375V – 1.6V

PGND

DRVL

C10

4.7nF

65A AVG, 74A PK

VCC

2.2⍀

CC(CORE) RTN

4.7␮F

C21

IPD06N03L

C28

IPD06N03L

C13

4.7␮F

10␮F

MLCC

C12

1N4148WS

ADP3418^100nF

IPD12N03L

SOCKET

BST

DRVH

600nH/1.6m⍀

PGND

DRVL

C14

4.7nF

VCC

C11

4.7␮F

2.2⍀

IPD06N03L

C17

4.7␮F

C16

1N4148WS

ADP3418 ^100nF

IPD12N03L

BST

DRVH

600nH/1.6m⍀

PGND

DRVL

C18

4.7nF

100k⍀, 5%

VCC

C15

4.7␮F

2.2⍀

IPD06N03L

C19

1␮F

C20

33␮F

10⍀

412k⍀

ADP3168

VID4

VCC 28

VID3

PWM1

PWM2

PWM3

PWM4

SW1

VID2

VID1

VID0

SW1

VID5

SW2

FBRTN

SW2

1.5nF

SW3

PH1

124k⍀

33pF

SW3

PH3

124k⍀

COMP

PWRGD

SW4

1.33k⍀

390pF

16.9k⍀

POWER

GOOD

GND

PH2

124k⍀

CS1

35.7k⍀

CS2

73.2k⍀

CS2

1.5nF

ENABLE

CSCOMP

CSSUM

CSREF

ILIMIT

DELAY

CS1

2.2nF

DLY

39nF

DLY

390k⍀

RAMPADJ

249k⍀

LIM

200k⍀

Figure 4. VRD 10 Compliant Intel CPU Supply Circuit

–8–

REV. 0

ADP3418

BST

PC BOARD LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed

circuit boards.

1. Trace out the high current paths and use short, wide (>20 mil)

traces to make these connections.

2. Connect the PGND pin of the ADP3418 as close as possible

to the source of the lower MOSFET.

3. The V_CCbypass capacitor should be located as close as

possible to the VCC and PGND pins.

4. Use vias to other layers when possible to maximize thermal

conduction away from the IC.

The circuit in Figure 4 shows how three drivers can be combined

with the ADP3168 to form a total power conversion solution for

generating V_CC(CORE)for an Intel CPU that is VRD 10 compliant.

Figure 5 gives an example of the typical land patterns based on the

guidelines given previously. For more detailed layout guidelines

for a complete CPU voltage regulator subsystem, refer to the

ADP3168 data sheet.

VCC

Figure 5. External Component Placement

Example for the ADP3418 Driver

REV. 0

–9–

ADP3418

OUTLINE DIMENSIONS

8-Lead Standard Small Outline Package [SOIC]

(RN-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

6.20 (0.2440)

5.80 (0.2284)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)

BSC

0.50 (0.0196)

0.25 (0.0099)

45؇

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.10 (0.0040)

8؇

0؇

0.51 (0.0201)

0.33 (0.0130)

1.27 (0.0500)

0.41 (0.0160)

COPLANARITY

0.10

0.25 (0.0098)

0.19 (0.0075)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

–10–

REV. 0

–11–

–12–

ADP3418JRZ [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E