ADP3510 [ADI]
CDMA Power Management System; CDMA电源管理系统
| 型号： | ADP3510 |
| 厂家： | 
ADI |
| 描述： | CDMA Power Management System |
| 文件： | 总16页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
CDMA Power Management System
ADP3510
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Handles All CDMA Baseband Power Management
Six LDOs Optimized for Specific CDMA Subsystems
Li-Ion and NiMH Battery Charge Function
Ambient Temperature: ꢀ20ꢁC to +85ꢁC
TSSOP 28-Lead Package
VBAT
VBAT2
VTRC
RTC
Optimized for LSI Logic Baseband Chipset
VIO
VIO
PWRONKEY
LDO
APPLICATIONS
CDMA Handsets
DIGITAL
VCORE
VAN
ROWX
CORE LDO
PWRONIN
ANALOG
LDO
POWER-UP
SEQUENCING
AND
ALARM
PDCAP
PROTECTION
LOGIC
TCXO
LDO
VTCXO
VMEM
MEMORY
LDO
TCXOEN
RESCAP
REF
REFOUT
RESET
BUFFER
GENERAL DESCRIPTION
The ADP3510 is a multifunction power system chip optimized for
CDMA handset power management. It contains six specialized
LDOs, one to power each of the critical CDMA subblocks.
Sophisticated controls are available for power-up during battery
charging, keypad interface, and RTC alarm. If a Li-Ion battery
is being charged, the charge circuit maintains low current
charging during the initial charge phase and provides an end of
charge (EOC) signal when the cell has been fully charged.
CHRDET
EOC
BATTERY
VOLTAGE
DIVIDER
MVBAT
CHGEN
GATEIN
BATSNS
ISENSE
GATEDR
CHRIN
BATTERY
DGND
AGND
CHARGE
CONTROLLER
ADP3510
The ADP3510 is specified over the temperature range of –20∞C to
+85∞C and is available in a narrow body TSSOP 28-Lead package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
ADP3510–SPECIFICATIONS
(–20ꢁC Յ TA Յ +85ꢁC, VBAT = VBAT2 = 3.2 V–7.5 V, CVIO = CVCORE = CVAN = CVMEM = 2.2 ꢃF,
VTCXO = 0.47 ꢃF, CVBAT = 10 ꢃF, min. loads applied on all outputs, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS1
P
arameter
Symbol
Conditions
Min
Typ
Max
Unit
SHUTDOWN SUPPLY CURRENT
VBAT £ 2.5 V
ICC
VBAT = VBAT2 = 2.3 V
5
15
mA
(Deep Discharged Lockout Active)
2.5 V < VBAT £ 3.2 V (UVLO Active)
VBAT >3.2 V
VBAT = VBAT2 = 3.15 V
VBAT = VBAT2 = 4.0 V
30
45
55
60
mA
mA
OPERATING GROUND CURRENT
All LDOs On Except TCXO
All LDOs On
IGND
Minimum Loads
Minimum Loads
Maximum Loads
300
340
2.0
390
430
3.5
mA
mA
% of
All LDOs On
Max Load
Current
UVLO ON THRESHOLD
UVLO HYSTERESIS
VBAT
VBAT
VBAT
3.1
2.0
3.2
3.3
V
200
2.4
mV
V
DEEP DISCHARGED LOCKOUT
ON THRESHOLD
2.75
DEEP DISCHARGED LOCKOUT
HYSTERESIS
VBAT
VIH
100
mV
V
INPUT HIGH VOLTAGE (PWRONIN,
TCXOEN, CHGEN, GATEIN)
2.0
INPUT LOW VOLTAGE (PWRONIN,
TCXOEN, CHGEN, GATEIN)
VIL
0.4
1.0
V
INPUT HIGH BIAS CURRENT
(PWRONIN, TCXOEN,
CHGEN, GATEIN)
IIH
mA
INPUT LOW BIAS CURRENT
(PWRONIN, TCXOEN,
CHGEN, GATEIN)
IIL
–1.0
mA
PWRONKEY INPUT HIGH VOLTAGE
PWRONKEY INPUT LOW VOLTAGE
VIH
VIL
0.7
70
ꢂ
VBAT
V
0.3
ꢂ
VBAT V
PWRONKEY INPUT PULLUP
RESISTANCE TO VBAT
THERMAL SHUTDOWN THRESHOLD2
105
150
25
145 kW
ºC
THERMAL SHUTDOWN HYSTERESIS
ºC
ROWX CHARACTERISTICS
ROWX Output Low Voltage
VOL
IL
PWRONKEY = Low
0.4
1
V
I
OL = 200 mA
ROWX Output High Leakage Current
PWRONKEY = High
V(ROWX) = 5 V
mA
I/O LDO (VIO)
Output Voltage
Line Regulation
Load Regulation
Output Capacitor Required for Stability
Dropout Voltage
VIO
DVIO
DVIO
CO
Line, Load, Temp
Minimum Load
50 mA £ ILOAD £ 25 mA
2.85
2.2
2.935
1
3
3.02
V
mV
mV
mF
VDO
VO = VINITIAL – 100 mV
ILOAD = 25 mA
50
150
1.92
mV
DIGITAL CORE LDO (VCORE)
Output Voltage
Line Regulation
Load Regulation
Output Capacitor Required for Stability
VCORE
Line, Load, Temp
1.78
2.2
1.85
1
8
V
DVCORE Minimum Load
DVCORE 50 mA £ ILOAD £ 120 mA
CO
mV
mV
mF
–2–
REV. 0
ADP3510
Parameter
Symbol
Conditions
Min
Typ Max
Unit
ANALOG LDO (VAN)
Output Voltage
Line Regulation
Load Regulation
Output Capacitor Required for Stability
VAN
DVAN
DVAN
CO
Line, Load, Temp
Minimum Load
50 mA £ ILOAD £ 75 mA
2.85
2.935 3.02
1
6
V
mV
mV
mF
2.2
Dropout Voltage
VDO
VO = VINITIAL 100 mV
I
LOAD = 75 mA
100 175
75
mV
dB
Ripple Rejection
DVBAT/
DVAN
VNOISE
f = 217 Hz (T = 4.6 ms)
VBAT = 3.6 V
f = 10 Hz to 100 kHz
Output Noise Voltage
80
mV rms
I
LOAD = 75 mA
VBAT = 3.6 V
TCXO LDO (VTCXO)
Output Voltage
Line Regulation
Load Regulation
Output Capacitor Required for Stability
Dropout Voltage
VTCXO
DVTCXO
DVTCXO
CO
Line, Load, Temp
Minimum Load
50 mA £ ILOAD £ 10 mA
2.71
0.47
2.765 2.82
1
3
V
mV
mV
mF
VDO
VO = VINITIAL – 100 mV
ILOAD = 10 mA
175
mV
Ripple Rejection
DVBAT/
DVTCXO
VNOISE
f = 217 Hz (T = 4.6 ms)
VBAT = 3.6 V
f = 10 Hz to 100 kHz
75
80
dB
Output Noise Voltage
mV rms
I
LOAD = 10 mA
VBAT = 3.6 V
REAL-TIME CLOCK LDO/
BATTERY CHARGER (VRTC)
Maximum Output Voltage
Off Reverse Input Current
Dropout Voltage
VRTC
IL
VDO
1 mA £ ILOAD £ 6 mA
2.77
2.85
2.85 2.93
V
mA
mV
2.0 V < VBAT < UVLO
VO = VINITIAL – 100 mV
1
175
I
LOAD = 10 mA
MEMORY LDO (VMEM)
Output Voltage
Line Regulation
Load Regulation
Output Capacitor Required for Stability
Dropout Voltage
VMEM
DVMEM
DVMEM
CO
Line, Load, Temp
Minimum Load
50 mA £ ILOAD £ 60 mA
2.935 3.02
1
5
2.2
V
mV
mV
mF
VDO
VO = VINITIAL – 100 mV
ILOAD = 60 mA
100 175
mV
REFOUT
Output Voltage
Line Regulation
Load Regulation
VREFOUT Line, Load, Temp
DVREFOUT Minimum Load
DVREFOUT 0 mA £ ILOAD £ 50 mA
VBAT = 3.6 V
1.19
1.210 1.23
0.3
0.6
V
mV
mV
Ripple Rejection
DVBAT/
f = 217 Hz (T = 4.6 ms)
DVREFOUT VBAT = 3.6 V
75
dB
Maximum Capacitive Load
Output Noise Voltage
CO
VNOISE
100
40
pF
mV rms
f = 10 Hz to 100 kHz
RESET GENERATOR (RESET)
Output High Voltage
Output Low Voltage
Output Current
Delay Time per Unit Capacitance
Applied to RESCAP Pin
VOH
VOL
IOH = +500 mA
IOL = –500 mA
2.4
0.8
V
V
mA
ms/nF
0.25
1
4.0
I
OL/IOH
TD
1.5
0.8
SEQUENCING
Delay Time per Unit Capacitance
Applied to PDCAP Pin
PDCAP Charging Current
VAN Discharge Resistance
VIO Discharge Resistance
TD
0.3
2.5
3.0
8
ms/nF
IOH
VPDCAP = 0
5
200
200
mA
W
W
–3–
REV. 0
ADP3510
Parameter
Symbol
Conditions
Min Typ Max
Unit
BATTERY VOLTAGE DIVIDER
Divider Ratio
Divider Impedance at MVBAT
Divider Leakage Current
Divider Resistance
BATSNS/MVBAT TCXOEN = High
2.94 3.00 3.06
ZO
50
80
110
1
kW
mA
kW
TCXOEN = Low
TCXOEN = High
230 350
430
BATTERY CHARGER
Charger Output Voltage
BATSNS
4.5 V < CHRIN < 10 V,
CHGEN = Low,
4.158 4.200 4.242
V
TA = 0∞C to 50∞C
Charger Output Voltage
Load Regulation
BATSNS
CHRIN = 10 V, VSENSE = 10 mV, 4.162 4.200 4.238
V
TA = 0∞C to 50∞C
CHRIN = 5 V,
⌬BATSNS
2
8
mV
0 < CHRIN – ISENSE
< Current Limit Threshold,
CHGEN = Low
CHRDET on Threshold
CHRDET Hysteresis
CHRDET Off Delay3
CHRIN Supply Current
CHRIN–VBAT
VBAT = 3.6 V
260
70
6
mV
mV
ms/nF
mA
CHRIN < VBAT
CHRIN = 5 V
0.6
1
Current Limit Threshold
High Current Limit
CHRIN–ISENSE
CHRIN = 5 V dc
VBAT = 3.6 V
CHGEN = Low
CHRIN = 5 V
VBAT = 2 V
CHGEN = Low
CHRIN = 5 V
150 172
195
mV
mV
(100%: UVLO Not Active)
Low Current Limit
(10%: UVLO Active)
2
2
15
30
ISENSE Bias Current
180
12
250
26
mA
End of Charge Signal Threshold
CHRIN–ISENSE CHRIN = 5 V dc
VBAT > 4.0 V
mV
CHGEN = Low
CHGEN = Low
End of Charge Reset Threshold
GATEDR Transition Time
VBAT
tR, tF
3.82 3.96 4.10
V
CHRIN = 5 V
VBAT > 3.6 V
1
10
ms
CHGEN = High, CL = 2 nF
GATEDR High Voltage
GATEDR Low Voltage
VOH
CHRIN = 5 V
VBAT = 3.6 V
CHGEN = High
GATEIN = High
4.5
V
V
I
OH = –1 mA
VOL
CHRIN = 5 V
VBAT = 3.6 V
CHGEN = High
GATEIN = Low
IOL = +1 mA
0.5
Output High Voltage
(EOC, CHRDET)
Output Low Voltage
(EOC, CHRDET)
Battery Overvoltage
Protection Threshold
(GATEDRÆHigh)
Battery Overvoltage
Protection Hysteresis
VOH
IOH = –250 mA
2.4
V
V
V
VOL
IOL = +250 mA
0.25
BATSNS
CHRIN = 7.5 V
CHGEN = High
GATEIN = Low
CHRIN = 7.5 V
CHGEN = High
GATEIN = Low
5.30 5.50 5.70
BATSNS
400
mV
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125ꢁC. Operation beyond 125ꢁC could cause
permanent damage to the device.
3Delay set by external capacitor on the RESCAP pin.
Specifications subject to change without notice.
–4–
REV. 0
ADP3510
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin with respect to
any GND Pin . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V
Voltage on any pin may not exceed VBAT, with the following
exceptions: CHRIN, GATEDR, ISENSE
ORDERING GUIDE
Model
Temperature Range
Package Option
ADP3510ARU
–20∞C to ꢄ85∞C
RU-28
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Operating Ambient Temperature Range . . . . –20∞C to +85∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C
qJA, Thermal Impedance (TSSOP-28)
2-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98∞C/W
4-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68∞C/W
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
Pin
Mnemonic
PWRONIN
Function
∑
1
Power-On/-Off Signal from
Microprocessor
PWRONIN
PWRONKEY
ROWX
TCXOEN
AGND
1
2
28
27
26
25
24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PWRONKEY Power-On/-Off Key
ROWX
3
REFOUT
VTCXO
VAN
Power Key Interface Output
ALARM
4
ALARM
PDCAP
VRTC
BATSNS
MVBAT
CHRDET
CHRIN
GATEIN
GATEDR
DGND
Alternative Power-On
Power-On Delay Timer Capacitor
VRTC LDO Output
Battery Voltage Sense Input
Divided Battery Voltage Output
Charge Detect Output
Charger Input Voltage
Microprocessor Gate Input Signal
Gate Drive Output
PDCAP
5
ADP3510
VRTC
6
23 VBAT
TOP VIEW
BATSNS
MVBAT
VCORE
VMEM
VBAT2
7
22
21
20
19
(Not to Scale)
8
CHRDET
9
CHRIN
VIO
10
GATEIN 11
18 RESET
GATEDR
DGND
RESCAP
CHGEN
EOC
12
13
14
17
16
15
Digital Ground
ISENSE
ISENSE
EOC
CHGEN
Charge Current Sense Input
End of Charge Signal
Charger Enable for GATEIN, NiMH
Pulse Charging
17
18
19
20
21
22
23
24
25
26
27
28
RESCAP
RESET
VIO
VBAT2
VMEM
VCORE
VBAT
Reset Delay Time
Main Reset
I/O LDO Output
Battery Input Voltage 2
Memory LDO Output
Digital Core LDO Output
Battery Input Voltage
Analog LDO Output
TCXO LDO Output
Output Reference
Analog Ground
TCXO LDO Enable and MVBAT
Enable
VAN
VTCXO
REFOUT
AGND
TCXOEN
CAUTION
ESD(electrostaticdischarge)sensitivedevice.Electrostaticchargesashighas4000 Vreadilyaccumulate
on the human body and test equipment and can discharge without detection. Although the
ADP3510 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
ADP3510
Table I. LDO Control Logic
ALARM
T
*
ONIN or
ONKEY
TC
VR
N
PWR
PWR
REFOUT
CHRDET
DDLO
MVBA
VIO
VA
TCXOEN
UVLO
VMEM
VCORE
VTCXO
Phone Status
State #1 battery
deep discharged
L
X
X
X
X
X
X
OFF OFF OFF OFF OFF OFF OFF OFF
State #2 phone off
H
H
H
H
H
L
X
X
H
X
L
X
OFF OFF OFF OFF OFF ON
OFF OFF
OFF OFF
OFF**ON
OFF**ON
OFF ON
State #3 phone off,
turn on allowed
H
H
H
H
L
L
X
L
L
L
OFF OFF OFF OFF OFF ON
State #4 charger
applied
H
X
L
X
X
H
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
State #5 phone
turned on by user key
State #6 phone
turned on by BB
H
OFF ON
State #7 phone and
TCXO LDO kept
on by BB
H
H
L
H
H
H
ON
ON
ON
ON
ON
ON
ON
ON
*UVLO is only active when phone is turned off. UVLO is ignored once the phone is turned on.
**Controlled by TCXOEN.
–6–
REV. 0
ADP3510
VBAT
23
VBAT2
20
IO LDO
ADP3510
VBAT
VREF
OUT
PG
19
VIO
DEEP
DISCHARGED
UVLO
EN
DGND
UVLO
S
110kꢅ
UVLO
Q
R
2
3
PWRONKEY
ROWX
DIGITAL CORE LDO
OVER TEMP
SHUTDOWN
VBAT
OUT
22
24
VCORE
VAN
VREF
PWRONIN
ALARM
1
4
EN
DGND
ANALOG LDO
VBAT
VREF
OUT
OUT
CHARGER
DETECT
EN
AGND
TCXOEN
RESCAP
CHRDET
28
17
9
TCXO LDO
RESET
GENERATOR
18
25
RESET
VTCXO
VBAT
VREF
15
EOC
EN
AGND
LI-ION
CHGEN 16
GATEIN 11
BATTERY
CHARGE
MEMORY LDO
VBAT
CONTROLLER
AND
VREF
OUT
PG
ꢃPROCESSOR
CHARGE
21
VMEM
BATSNS
ISENSE 14
GATEDR
7
EN
INTERFACE
DGND
RTC LDO
DGND
12
CHRIN 10
VBAT
VREF
OUT
6
VRTC
EN
DGND
POWER-
EN
ON
REF
DELAY
26
REFOUT
BUFFER
MVBAT
8
1.21V
AGND
DGND
27
13
AGND
5
PDCAP
Figure 1. Functional Block Diagram
EOC
CHGEN
GATEIN
ADP3510
BATTERY
CHARGE
CHRIN
(10V MAX)
CONTROLLER
ISENSE
GATEDR
BATSNS
CHRDET
Figure 2. Battery Charger Typical Application
REV. 0
–7–
(VBAT = 3.6 V, T = 25ꢁC, unless otherwise specified.)
ADP3510—Typical Performance Characteristics
A
160
400
400
350
300
250
200
+85ꢁC
140
120
100
80
ALL LDO, MVBAT, REFOUT ON,
MIN LOAD (TCXOEN = H)
ALL LDO, MVBAT, REFOUT,
ON MIN LOAD (TCXOEN = H)
350
+25ꢁC
300
–20ꢁC
VIO, VCORE, VMEM,
60
VRTC, VAN, REFOUT ON,
MIN LOAD (TCXOEN = L)
VIO, VCORE, VMEM, VRTC, VAN,
REFOUT, ON MIN LOAD (TCXOEN = L)
40
250
200
20
10
ꢀ40 ꢀ20
0
20 40
60 80 100 120
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VRTC – V
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE – ꢁC
VBAT – V
TPC 3. RTC I/V Characteristic
TPC 2. Ground Current
vs. Temperature
TPC 1. Ground Current
vs. Battery Voltage
180
160
140
120
100
80
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VTCXO
3.5V
3.3V
RTC REVERSE LEAKAGE
(VBAT = FLOAT)
VBAT
VTCXO
10mV/DIV
RTC REVERSE LEAKAGE
(VBAT = 2.3V)
VMEM
10mV/DIV
60
VSIM
VMEM
40
20
TIME ꢀ 100ꢃs/DIV
0
0
20
40
60
80
25 30 35 40 45 50 55 60 65 70 75 80 85
LOAD CURRENT – mA
TEMPERATURE – ꢁC
TPC 5. Dropout Voltage
vs. Load Current
TPC 6. Line Transient Response,
Minimum Loads
TPC 4. VTRC Reverse Leakage
Current vs. Temperature
3.5V
3.5V
3.5V
VBAT
VAN
VBAT
VAN
VBAT
3.3V
3.3V
3.3V
10mV/DIV
10mV/DIV
2mV/DIV
10mV/DIV
10mV/DIV
2mV/DIV
10mV/DIV
10mV/DIV
VCORE
VCORE
VIO
VTCXO
VMEM
VIO
TIME ꢀ 100ꢃs/DIV
TIME ꢀ 100ꢃs/DIV
TIME ꢀ 100ꢃs/DIV
TPC 9. Line Transient Response,
Maximum Loads
TPC 7. Line Transient Response,
Maximum Loads
TPC 8. Line Transient Response,
Minimum Loads
–8–
REV. 0
ADP3510
60mA
25mA
10mA
LOAD
1mA
LOAD
VIO
2mA
LOAD
VMEM
5mA
VTCXO
10mV/DIV
10mV/DIV
5mV/DIV
TIME ꢀ 200ꢃs/DIV
TIME ꢀ 200ꢃs/DIV
TIME ꢀ 200ꢃs/DIV
TPC 11. VIO Load Step
TPC 12. VMEM Load Step
TPC 10. VTCXO Load Step
120mA
75mA
PWRONIN (2V/DIV)
VAN (200mV/DIV)
LOAD
VCORE
LOAD
10mA
8mA
PDCAP = 1nF
VIO (200mV/DIV)
10mV/DIV
VAN
10mV/DIV
VCORE (200mV/DIV)
TIME ꢀ 200ꢃ
s/DIV
TIME – 200ꢃs/DIV
TIME ꢀ 200ꢃs/DIV
TPC 13. VCORE Load Step
TPC 14. VAN Load Step
TPC 15. Turn On Transient by
PWRONIN, Minimum Load
PWRONIN (2V/DIV)
REFOUT (200mV/DIV)
PWRONIN (2V/DIV)
REFOUT (200mV/DIV)
PWRONIN (2V/DIV)
PDCAP = 1nF
PDCAP = 1nF
VMEM (200mV/DIV)
VTCXO (200mV/DIV)
VAN (200mV/DIV)
VIO (200mV/DIV)
PDCAP = 1nF
VMEM (200mV/DIV)
VTCXO (200mV/DIV)
VCORE (200mV/DIV)
TIME ꢀ 200ꢃs/DIV
TIME ꢀ 200ꢃs/DIV
TIME ꢀ 200ꢃs/DIV
TPC 17. Turn On Transient by
PWRONIN, Maximum Load
TPC 18. Turn On Transient by
PWRONIN, Maximum Load
TPC 16. Turn On Transient by
PWRONIN, Minimum Load
–9–
REV. 0
ADP3510
4.25
4.22
4.21
4.20
4.19
4.18
4.210
4.205
4.200
4.195
4.190
V
LOAD
= 5.0V
V
= 5V
SENSE
R
= 250mꢅ
IN
IN
SENSE
4.24
4.23
4.22
4.21
4.20
4.19
4.18
4.17
4.16
4.15
I
= 10mA
R
= 250mꢅ
I
= 500mA
LOAD
I
= 10mA
LOAD
0
200
400
I
600
– mA
800
1000
5
6
7
8
9
10
–40 –20
0
20 40 60 80 100 120
TEMPERATURE – ꢁC
INPUT VOLTAGE – V
LOAD
TPC 21. Charger VOUT vs. VIN
TPC 19. Charger VOUT vs. Temperature,
IN = 5.0 V, ILOAD = 10mA
TPC 20. Charger VOUT vs. ILOAD
(VIN = 5.0 V)
V
THEORY OF OPERATION
These functions have traditionally been done either as a discrete
implementation or as a custom ASIC design. The ADP3510
combines the benefits of both worlds by providing an integrated
standard product where every block is optimized to operate in a
CDMA environment while maintaining a cost-competitive solution.
The ADP3510 is a total solution power management chip for use
with CDMA baseband chipsets and is optimized for the CBP3.0/
4.0 type chipsets. Figure 1 shows a block diagram of the ADP3510.
The ADP3510 contains several blocks:
Figure 3 shows the external circuitry associated with the ADP3510.
Only a minimal number of support components are required.
∑ Six Low Dropout Regulators (Input-Output, Core, Analog,
Crystal Oscillator, Memory, Realtime Clock)
Input Voltage
∑ Reset Generator
The input voltage range of the ADP3510 is 3.2 V to 7.5 V and is
optimized for a single Li-Ion cell or three NiMH cells. The thermal
impedance of the ADP3510 is 68∞C/W for four layer boards. The
end of charge voltage for high capacity NiMH cells can be as high
as 5.5 V. Power dissipation should be calculated at maximum ambi-
ent temperatures and battery voltage in order not to exceed the 125∞C
maximum allowable junction temperature. Figure 4 shows the maxi-
mum power dissipation as a function of ambient temperature.
∑ Buffered Precision Reference
∑ Lithium Ion Charge Controller and Processor Interface
∑ Power-On/-Off Logic
∑ Undervoltage Lockout
∑ Deep Discharge Lockout
ADP3510
PWRONIN
PWRONKEY
ROWX
PWRON
1
2
TCXOEN 28
TCXOEN
PWRONKEY
AGND
27
R2 10ꢅ
3
REFOUT 26
REF
KEYPADROW
ALARM
ALARM
PDCAP
VTCXO
VAN
4
25
24
VTCXO
VAN
5
C4
10ꢃF
C11
C9
C10
VRTC
VRTC
6
VBAT 23
0.1ꢃF
2.2ꢃF
C2
C1
0.22ꢃF
10nF
0.1ꢃF
BATSNS
MVBAT
VCORE
7
22
21
20
19
VCORE
VMEM
VMEM
VBAT2
VIO
ADC
GPIO
8
C7
CHRDET
9
2.2ꢃF
CHRIN
VIO
CHARGER IN
GPIO
10
11 GATEIN
RESET 18
RESET
C3
1.0nF
C8
C6
R1
GATEDR
DGND
RESCAP
CHGEN
EOC
12
13
14
17
16
15
2.2ꢃF
2.2ꢃF
0.25ꢅ
GPIO
GPIO
ISENSE
C5
0.1ꢃF
Q1
SI3441DY
D1
10BQ015
Liꢄ
BATTERY
Figure 3. Typical Application Circuit
–10–
REV. 0
ADP3510
1.2
1.0
0.8
0.6
0.4
0.2
0.0
(ML614, ML621, or ML1220) from Sanyo. The ML621 has a
small physical size (6.8 mm diameter) and will give many hours
of backup time.
The ADP3510 supplies current both for charging the coin cell
and for the RTC module. The nominal charging voltage is 2.85 V,
which ensures long cell life while obtaining in excess of 90% of
the nominal capacity. In addition, it features a very low quies-
cent current since this LDO is running all the time, even when
the handset is switched off. It also has reverse current protection
with low leakage, which is needed when the main battery is
removed and the coin cell supplies the RTC module.
IO LDO (VIO)
The IO LDO generates the voltage needed for the peripheral
subsystems of the baseband processor, including GPIO, display,
and serial interfaces. It is rated for 25 mA of supply current and
is controlled by the power-on delay block of the ADP3510.
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE – ꢁC
Figure 4. Power Dissipation vs. Temperature
However, high battery voltages normally occur only when the battery
is being charged and the handset is not in conversation mode. In
this mode, there is a relatively light load on the LDOs. A fully
charged Li-Ion battery is 4.245 V, where the ADP3510 can deliver
the maximum power (0.52 W) up to 85∞C ambient temperature.
Reference Output (REFOUT)
The reference output is a low noise, high precision reference with
a guaranteed accuracy of 1.65% over temperature. The reference
can be used with the baseband converter, if the converter’s own
reference is not accurate. This may significantly reduce the calibra-
tion time needed for the baseband converter during production.
Low Dropout Regulators (LDOs)
The ADP3510 high performance LDOs are optimized for their
given functions by balancing quiescent current, dropout voltage,
regulation, ripple rejection, and output noise. 2.2 mF tantalum or
MLCC ceramic capacitors are recommended for use with the core,
memory, IO, and analog LDOs. A 0.22 mF capacitor is recom-
mended for the TCXO LDO.
Power ON/OFF
The ADP3510 handles all issues regarding the powering ON and
OFF of the handset. It is possible to turn on the ADP3510 in
four different ways:
∑ Pulling the PWRONKEY Low
∑ Pulling PWRONIN High
Digital Core LDO (VCORE)
∑ Pulling ALARM High
The digital core LDO supplies the baseband circuitry in the
handset (baseband processor and baseband converter). The LDO
has been optimized for very low quiescent current at light loads
as this LDO is on at all times.
∑ CHRIN Exceeds CHRDET Threshold
Pulling the PWRONKEY low is the normal way of turning on the
handset. This will turn on all the LDOs, as long as the PWRONKEY
is held low. When the VIO LDO comes into regulation, the RESET
timer is started. After timing out, the RESET pin goes high, allowing
the baseband processor to start up. With the baseband processor
running, it can poll the ROWX pin of the ADP3510 to determine
if the PWRONKEY has been depressed and pull PWRONIN
high. Once the PWRONIN is taken high, the PWRONKEY can be
released. Note that by monitoring the ROWX pin, the baseband
processor can detect a second PWRONKEY press and turn the
LDOs off in an orderly manner. In this way, the PWRONKEY
can be used for ON/OFF control.
Memory LDO (VMEM)
The memory LDO supplies the memory of the baseband pro-
cessor. The memory LDO is capable of supplying 60 mA of
current and has also been optimized for low quiescent current
and will power up at the same time as the core LDO.
Analog LDO (VAN)
This LDO has the same features as the core LDO. It has further-
more been optimized for good low frequency ripple rejection for
use with the baseband converter sections in order to reject the
ripple coming from the RF power amplifier. VAN is rated to
75 mA load, which is sufficient to supply the complete analog
section of the baseband converter. The analog LDO is controlled
by the power-on delay block of the ADP3510.
Pulling the ALARM pin high is how the alarm in the realtime
clock module will turn the handset on. Asserting ALARM will
turn the core, IO, memory, and analog LDOs on, starting up
the baseband processor.
TCXO LDO (VTCXO)
The TCXO LDO is intended as a supply for a temperature compen-
sated crystal oscillator, which needs its own ultralow noise supply.
VTCXO is rated for 10 mA of output current and is turned on
when TCXOEN is asserted.
Applying an external charger can also turn the handset on. This
will turn on all the LDOs, again starting up the baseband processor.
Note that if the battery voltage is below the undervoltage lockout
threshold, applying the adapter will not start up the LDOs.
RTC LDO (VRTC)
The RTC LDO charges up a rechargeable lithium type coin
cell to run the realtime clock module. It has been designed to
charge manganese lithium batteries such as the ML series
REV. 0
–11–
ADP3510
Once the system is started and the core, memory, analog, and
IO LDOs are up and running, the UVLO function is entirely disabled.
The ADP3510 is then allowed to run until the battery voltage
reaches the DDLO threshold, typically 2.4 V. Normally, the
battery voltage is monitored by the baseband processor and
usually shuts the phone off at around 3.0 V.
Power On Delay
The power-on delay block in the ADP3510 controls the turn-on
sequence of VCORE, VIO, and VAN. Asserting a power-on in one
of the four above methods will start the LDOs in the following
sequence:
1. The VMEM LDO will start up.
If the handset is off and the battery voltage drops below 3.0 V,
the UVLO circuit disables startup and puts the ADP3510 into
UVLO shutdown mode. In this mode, the ADP3510 draws very
low quiescent current, typically 30 mA. The RTC LDO is still
running until the DDLO disables it. In this mode, the
ADP3510 draws 5 mA of quiescent current. NiMH batteries can
reverse polarity if the 3-cell battery voltage drops below 3.0 V,
which will degrade the battery’s performance. Lithium Ion bat-
teries will lose their capacity if over discharged repeatedly so
minimizing the quiescent currents helps prevent battery damage.
2. The VIO and VAN outputs will be discharged by the power-
on delay block. The discharge delay time is set by the value
of the PDCAP.
3. After the discharge time has expired, the VCORE LDO is
allowed to start up.
4. When the output of VCORE exceeds 1.2 V, the VIO and
VAN LDOs are allowed to start up.
The power-on delay is set by an external capacitor on PDCAP:
ms
nF
(1)
tPD = 0.8
¥ CPDCAP
RESET
The ADP3510 contains a reset circuit that is active both at power-up
and power-down. The RESET pin is held low at initial power-
up. An internal power good signal is generated by the IO LDO
when its output is in regulation which starts the reset delay timer.
The delay is set by an external capacitor on RESCAP:
See Figure 5 for the power-up timing sequence.
INTERNAL
POWER ON*
1.8V
ms
VCORE
tRESET = 1.5
¥ CRESCAP
(2)
1.2V
nF
Should the IO or MEM LDO drop out of regulation, the
RESET signal will go low and remain low until the IO and
MEM LDO outputs are back in regulation and the RESET
timer has timed out. At power-off, RESET will be kept low to
prevent any baseband processor starts.
3.0V
VMEM
Over-Temperature Protection
In case of a failure that causes excess power dissipation to the IC,
the thermal shutdown function will be activated. The maximum
die temperature for the ADP3510 is 125ꢁC. If the die temperature
exceeds 160ꢁC, the ADP3510 will disable all the LDOs except
the RTC LDO. The LDOs will not be re-enabled before the die
temperature is below 125ꢁC, regardless of the state of PWRONKEY,
PWRONIN, ALARM, and CHRDET. This ensures that the
handset will always power-off before the ADP3510 exceeds its
absolute maximum thermal ratings.
3.0V
V10, VAN
POWER-ON
DELAY
*PWRONIN or CHRDET
V10, VAN < VCORE
or ALARM or PWRONKEY
UNTIL VCORE > 1.2V
Figure 5. Power-Up Timing Diagram
Deep Discharge Lockout (DDLO)
The DDLO block in the ADP3510 will shut down the handset in
the event the software fails to turn off the phone when the battery
drops below 2.9 V to 3.0 V. The DDLO will shut down the
handset when the battery falls below 2.4 V to prevent further
discharge and damage to the cell.
Battery Charging
The ADP3510 battery charger can be used with lithium ion
(Li+) and nickel metal hydride (NiMH) batteries. The charger
initialization, trickle charging, and Li+ charging are imple-
mented in hardware. Battery type determination and NiMH
charging must be implemented in software.
The charger block works in three different modes:
Undervoltage Lockout (UVLO)
∑
∑
∑
Low Current (Trickle) Charging
Lithium Ion Charging
The UVLO function in the ADP3510 prevents startup when the
initial voltage of the battery is below the 3.2 V threshold. If the
battery voltage is this low with no load, there is insufficient
capacity left to run the handset. When the battery is greater than
3.2 V, such as inserting a fresh battery, the UVLO comparator trips
and the threshold is reduced to 3.0 V. This allows the handset to
start normally until the battery decays to below 3.0 V. Note that
the DDLO has enabled the RTC LDO under this condition.
Nickel Metal Hydride Charging
See Figure 6 for the battery charger flowchart.
–12–
REV. 0
ADP3510
NONCHARGING
MODE
poll the battery to determine which chemistry is present and set
the charger to the proper mode.
Lithium Ion Charging
For lithium ion charging, the CHGEN input must be low. This
allows the ADP3510 to continue charging the battery at the full
current. The full charge current can be calculated by using:
NO
CHARGER DETECTED
CHRIN > BATSNS
YES
172 mV
RSENSE
ICHR(FULL )
=
(4)
YES
VBAT > UVLO
NO
If the voltage at BATSNS is below the charger’s output voltage of
4.2 V, the battery will continue to charge in the constant current
mode. If the battery has reached the final charge voltage, a con-
stant voltage is applied to the battery until the charge current has
reduced to the charge termination threshold. The charge termination
threshold is determined by the voltage across the sense resistor.
If the battery voltage is above 4.0 V and the voltage across the
sense resistor has dropped to 12 mV, then an end of charge signal
is generated and the EOC output goes high (see Figure 7).
NiMH
BATTERYTYPE
LOW CURRENT
CHARGE MODE
V
= 15mV
SENSE
CHGEN = HIGH
NiMH
Liꢄ
CHGEN = LOW
CHARGING MODE
GATEIN = PULSED
HIGH CURRENT
CHARGE MODE
The baseband processor can either let the charger continue to
charge the battery for an additional amount of time or terminate
the charging. To terminate the charging, the processor must
pull the GATEIN and CHGEN pins high.
V
= 172mV
SENSE
NO
VBAT > 5.5V
YES
NO
VBAT > 4.2V
YES
4.2V
NiMH
CHARGER OFF
GATEIN = HIGH
VBAT
3.2V
CONSTANT
VOLTAGE MODE
NO
VBAT < 5.5V
YES
HIGH
CURRENT
NO
END OF CHARGE
V
< 12mV
I
SENSE
CHARGE
LOW
EOC
CURRENT
CURRENT
0
YES
EOC = HIGH
TERMINATE CHARGE
CHREN = HIGH
EOC
GATEIN = HIGH
INDICATOR
Figure 6. Battery Charger Flowchart
Trickle Charging
Figure 7. Lithium Ion Charging Diagram
NiMH Charging
When the battery voltage is below the UVLO threshold, the
charge current is set to the low current limit, or about 10% of
the full charge current. The low current limit is determined by the
voltage developed across the current sense resistor. Therefore,
the trickle charge current can be calculated by:
For NiMH charging, the processor must pull the CHGEN pin high.
This disables the internal Li+ mode control of the gate drive pin. The
gate drive must now be controlled by the baseband processor. By
pulling GATEIN high, the GATEDR pin is driven high, turning the
PMOS off. By pulling the GATEIN pin low, the GATEDR pin is
driven low, and the PMOS is turned on. So, by pulsing the GATEIN
input, the processor can charge a NiMH battery. Note that when
charging NiMH cells, a current limited adapter is required.
15 mV
ICHR(TRICKLE )
=
(3)
RSENSE
Trickle charging is performed for deeply discharged batteries to
prevent undue stress on either the battery or the charger.
During the PMOS off periods, the battery voltage needs to be moni-
tored through the MVBAT pin. The battery voltage is continually
polled until the final battery voltage is reached. Then the charge
can either be terminated or the frequency of the pulsing reduced. An
alternative method of determining the end of charge is to monitor
the temperature of the cells and terminate the charging when a
rapid rise in temperature is detected.
Trickle charging will continue until the battery voltage exceeds
the UVLO threshold.
Once the UVLO threshold has been exceeded, the charger will
switch to the high current limit, the LDOs will start up, and the
baseband processor will start to run. The processor must then
REV. 0
–13–
ADP3510
Power-On Delay Capacitor Selection
Battery Voltage Monitoring
The battery voltage can be monitored at MVBAT during charging
and discharging to determine the condition of the battery. An inter-
nal resistor divider is connected to BATSNS when both the
baseband processor and the crystal oscillator are powered up. To
enable MVBAT, both PWRONIN and TCXOEN must be high.
The PDCAP sets the interval that the VAN and VIO LDOs are
discharged. To ensure that the baseband processor is properly
reset, the VIO and VAN LDOs should be fully discharged before
power is reapplied. The discharge time can be estimated using:
(6)
tPD = 900 ¥ COUT SEC
The ratio BATSNS/MVBAT of the voltage divider is set to 3.0.
The divider will be disconnected from the battery when the
baseband processor is powered down.
where tPD is the discharge time, and COUT is the VIO or
VAN LDO output capacitor value.
Charge Detection
The power-on delay is set by an external capacitor on PDCAP.
For worst-case delay:
The ADP3510 charger block has a detection circuit that determines
if an adapter has been applied to the CHRIN pin. If the adapter
voltage exceeds the battery voltage by 260 mV, the CHRDET
output will go high. If the adapter is then removed or the voltage
at the CHRIN pin drops to around 190 mV above the BATSNS
pin, then CHRDET goes low.
ms
nF
tPD = 0.3
¥ CPDCAP or
nF
ms
CPDCAP = tPD ¥ 3.33
(7)
APPLICATION INFORMATION
Input Capacitor Selection
So, for a 2.2 mF output capacitor, the required delay is about 2 ms.
This results in a 6.8 nF PDCAP value.
For the input (VBAT and VBAT2) of the ADP3510, a local
bypass capacitor is recommended. Use a 10 mF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size but may not be cost
effective. A lower cost alternative may be to use a 10 mF tantalum
capacitor with a small (1 mF to 2 mF) ceramic in parallel.
Setting the Charge Current
The ADP3510 is capable of charging both lithium ion and
NiMH batteries. For NiMH batteries, the charge current is
limited by the adapter. For lithium ion batteries, the charge
current is programmed by selecting the sense resistor, R1.
The lithium ion charge current is calculated using:
A separate input for the IO LDO is supplied for additional
bypassing or filtering. The IO LDO has VBAT2 as its input.
VSENSE 172 mV
ICHR
=
=
(8)
(9)
LDO Capacitor Selection
R1
R1
The performance of any LDO is a function of the output capacitor.
The core, memory, IO, and analog LDOs require a 2.2 mF capaci-
tor, and the TCXO LDO requires a 0.22 mF capacitor. Larger
values may be used, but the overshoot at startup will increase
slightly. If a larger output capacitor is desired, be sure to check that
the overshoot and settling time are acceptable for the application.
Where VSENSE is the high current limit threshold voltage.
Or, if the charge current is known, R1 can be found:
VSENSE 172 mV
R1=
=
ICHR
ICHR
All the LDOs are stable with a wide range of capacitor types and
ESR (any CAP technology). The ADP3510 is stable with extremely
low ESR capacitors (ESR ~ 0), such as multilayer ceramic
capacitors, but care should be taken in their selection. Note that
the capacitance of some capacitor types show wide variations
over temperature or with dc voltage. A good quality dielectric
capacitor, X7R or better, is recommended.
Similarly the trickle charge current and the end of charge current
can be calculated:
VSENSE 15 mV
ITRICKLE
=
=
R1
R1
VSENSE
R1
12 mV
R1
The RTC LDO can have a rechargeable coin cell or an electric
double-layer capacitor as a load, but an additional 0.1 mF ceramic
capacitor is recommended for stability and best performance.
IEOC
=
=
(10)
Example: Assume a 850 mA-H capacity lithium ion battery and
a 1 C charge rate. R1 = 200 m⍀. Then ITRICKLE = 75 mA and
IEOC = 60 mA.
RESET Capacitor Selection
RESET is held low at power-up. An internal power-good signal
starts the reset delay when the IO LDO is up. The delay is set
by an external capacitor on RESCAP:
Appropriate sense resistors are available from the following
vendors:
(5)
tRESET = 1.5 ms / nF ¥ CRESCAP
Vishay Dale
IRC
Panasonic
A 100 nF capacitor will produce a 150 ms reset delay. The
current capability of RESET is minimal (a few hundred nA)
when VIO is off to minimize power consumption. When VIO is
on, RESET is capable of driving 500 mA.
Charger FET Selection
The type and size of the pass transistor is determined by the
threshold voltage, input-output voltage differential, and the
charge current. The selected PMOS must satisfy the physical,
electrical, and thermal design requirements.
–14–
REV. 0
ADP3510
VDS = VADAPTER(MIN ) - VDIODE - VSENSE - VBAT
(15)
To ensure proper operation, the minimum VGS the ADP3510
can provide must be enough to turn on the FET. The available
gate drive voltage can be estimated using the following:
= 5 V – 0.5 V – 0.170 V – 4.2 V
= 130 mV
(11)
VGS = VADAPTER(MIN ) - VSENSE - VGATEDR
where:
VDS
130 mV
RDS(ON )
=
=
(16)
ICHR(MAX ) 850 mV
V
V
V
V
ADAPTER(MIN) is the minimum adapter voltage.
DIODE is the maximum forward drop of the charger diode, D1.
GATEDR is the gate drive “low” voltage, 0.5 V.
= 153 mW
SENSE is the maximum high current limit threshold voltage.
PDISS = V
- VDIODE - VSENSE - UVLO ¥ I
(
)
ADAPTER(MAX )
CHR
The difference between the adapter voltage (VADAPTER) and the
final battery voltage (VBAT) must exceed the voltage drop due to
the blocking diode, the sense resistor, and the ON resistance of
the FET at maximum charge current.
PDISS = 6.5V - 0.5V - 0.170V - 3.2 ¥ 0 / 85A = 2.24W
(
)
Appropriate PMOS FETs are available from the following vendors:
Siliconix
IR
VDS = VADAPTER(MIN ) - VDIODE - VSENSE - VBAT
(12)
Fairchild
Then the RDS(ON) of the FET can be calculated.
Charger Diode Selection
VDS
ICHR(MAX )
RDS(ON )
=
The diode, D1, shown in Figure 3, is used to prevent the battery
from discharging through the PMOS’ body diode into the charger’s
internal bias circuits. A Schottky diode is recommended to
minimize the voltage difference from the charger to the battery
and the power dissipation. Choose a diode with a current rating
high enough to handle the battery charging current, a voltage
rating greater than VBAT, and a low leakage current. The blocking
diode is required for both lithium and nickel battery types.
(13)
The thermal characteristics of the FET must be considered
next. The worst-case dissipation can be determined using:
PDISS = V
- VDIODE - VSENSE - UVLO ¥ I
(
)
ADAPTER(MAX )
CHR
It should be noted that the adapter voltage can be either preregulated
or nonregulated. In the preregulated case, the difference between
the maximum and minimum adapter voltage is probably not sig-
nificant. In the unregulated case, the adapter voltage can have a
wide range specified. However, the maximum voltage specified is
usually with no load applied. So, the worst-case power dissipation
calculation will often lead to an over-specified pass device. In
either case, it is best to determine the load characteristics of the
adapter to optimize the charger design.
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
1. Connect the battery to the VBAT and VBAT2 pins of the
ADP3510. Locate the input capacitor as close to the pins as
possible.
2. VAN and VTCXO capacitors should be returned to AGND.
For example:
3. VCORE, VMEM, and VIO capacitors should be returned to
DGND.
V
V
V
V
V
V
ADAPTER(MIN) = 5.0 V
ADAPTER(MAX) = 6.5 V
DIODE = 0.5 V at 850 mA
GATEDR = 0.5 V
4. Split the ground connections. Use separate traces or planes for
the analog, digital, and power grounds and tie them together
at a single point, preferably close to the battery return.
(14)
5. Run a separate trace from the BATSNS pin to the battery to
prevent voltage drop error in the MVBAT measurement.
SENSE = 170 mV
GS = 5 V – 0.5 V – 0.170 V = 4.3 V.
6. Kelvin connect the charger’s sense resistor by running separate
traces to the CHRIN pin and ISENSE pin. Make sure that the
traces are terminated as close to the resistor’s body as possible.
So choose a low-threshold voltage FET.
7. Use the best industry practice for thermal considerations during
the layout of the ADP3510 and charger components. Careful
use of copper area, weight, and multilayer construction all
contribute to improved thermal performance.
REV. 0
–15–
ADP3510
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Thin Shrink Small Outline (TSSOP)
(RU-28)
0.386 (9.80)
0.378 (9.60)
28
15
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
14
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8ꢁ
0ꢁ
0.0256 (0.65) 0.0118 (0.30)
BSC
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
0.0075 (0.19)
REV. 0
–16–
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IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32, 5 X 5 MM, MO-220VHHD-2, LFCSP-32, Power Management Circuit
ADI
ADP3522ACP-3-REEL7
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32, 5 X 5 MM, MO-220VHHD-2, LFCSP-32, Power Management Circuit
ADI
ADP3522ACP-3-REEL7
1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32, 5 X 5 MM, MO-220VHHD-2, LFCSP-32
ROCHESTER
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