ADP3522ACP-1.8-RL7_技术文档

GSM Power Management System

ADP3522

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Handles all GSM Baseband Power Management

6 LDOs Optimized for Specific GSM Subsystems

Li-Ion Battery Charge Function

VBAT VBAT2 VRTCIN

Optimized for the AD20msp430 Baseband Chipset

Reduced Package Size: 5 mm ꢀ 5 mm LFCSP-32

SIM

LDO

POWER-UP

VSIM

APPLICATIONS

GSM/GPRS Handsets

SEQUENCING

AND

PROTECTION

LOGIC

SIMVSEL

PWRONKEY

ROWX

DIGITAL

CORE LDO

VCORE

GENERAL DESCRIPTION

PWRONIN

ANALOG

LDO

The ADP3522 is a multifunction power system chip optimized

for GSM/GPRS handsets, especially those based on the Analog

Devices AD20msp430 system solution with 1.8 V digital

baseband processors, such as the AD6525, AD6526, and

AD6528. It contains six LDOs, one to power each of the critical

GSM subblocks. Sophisticated controls are available for power-

up during battery charging, keypad interface, and RTC alarm.

The charge circuit maintains low current charging during the

initial charge phase and provides an end of charge (EOC) signal

when a Li-Ion battery is being charged. This product also meets

the market trend of reduced size with a new LFCSP package.

Its footprint is only 5 mm ꢀ 5 mm and yet offers excellent ther-

mal performance due to the exposed die attached paddle.

VAN

TCXOEN

SIMEN

TCXO

LDO

VTCXO

VMEM

MEMORY

LDO

RESCAP

RTC

LDO

VRTC

REF

BUFFER

REFOUT

RESET

CHRDET

The ADP3522 is specified over the temperature range of

–20°C to +85°C.

EOC

BATTERY

VOLTAGE

DIVIDER

BATTERY

CHARGE

CONTROLLER

MVBAT

DGND

CHGEN

BATSNS

ISENSE

GATEIN

CHRIN

AGND

ADP3522

GATEDR

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

ADP3522–SPECIFICATIONS

(–20ꢁC < T_A< +85ꢁC, VBAT = VBAT2 = 3 V–5.5 V, CVSIM = CVCORE = CVAN =

CVMEM = 2.2 ꢂF, VTCXO = 0.22 ꢂF, CVRTC = 0.1 ꢂF, CVBAT = 10 ꢂF, minimum

loads applied on all outputs, unless otherwise noted.)

ELECTRICAL CHARACTERISTICS¹

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SHUTDOWN SUPPLY CURRENT

VBAT ≤ 2.5 V

ICC

VBAT = VBAT2 = 2.3 V

VBAT = VBAT2 = 3.0 V

VBAT = VBAT2 = 4.0 V

15

30

45

40

55

80

µA

(Deep Discharged Lockout Active)

2.5 V < VBAT ≤ 3.2 V

(UVLO Active)

VBAT > 3.2 V

OPERATING GROUND CURRENT

VSIM, VCORE, VMEM, VRTC On

All LDOs On

IGND

VBAT = 3.6 V

Minimum Loads

Maximum Loads

225

345

1.0

300

450

3.0

µA

All LDOs On

% of Max

Load

UVLO ON THRESHOLD

UVLO HYSTERESIS

VUVLO

VDDLO

Rising Edge

Falling Edge

3.2

200

2.4

3.3

V

mV

V

DEEP DISCHARGED LOCKOUT ON

THRESHOLD

2.75

DEEP DISCHARGED LOCKOUT

HYSTERESIS

100

mV

INPUT HIGH VOLTAGE

PWRONIN

V_IH

1.0

1.5

V

TCXOEN, SIMEN,

CHGEN, GATEIN, SIMVSEL

INPUT LOW VOLTAGE

(PWRONIN, TCXOEN, SIMEN,

CHGEN, SIMVSEL)

V_IL

0.3

V

PWRONIN Pin Pull-Down Resistor

R_PD

I_IH

200

1000 5000

1.0

kꢁ

µA

INPUT HIGH BIAS CURRENT

(TCXOEN, SIMEN, CHGEN,

SIMVSEL )

INPUT LOW BIAS CURRENT

(PWRONIN, TCXOEN, SIMEN,

CHGEN, SIMVSEL)

I_IL

–1.0

µA

PWRONKEY INPUT HIGH VOLTAGE

PWRONKEY INPUT LOW VOLTAGE

V_IH

V_IL

0.7 ꢀ VBAT

V

0.3 ꢀ VBAT

V

PWRONKEY INPUT PULL-UP

70

100

160

45

130

kꢁ

RESISTANCE TO VBAT

THERMAL SHUTDOWN

THRESHOLD²

ºC

THERMAL SHUTDOWN

HYSTERESIS

–2–

REV. 0

ADP3522

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

ROWX CHARACTERISTICS

ROWX Output Low Voltage

V_OL

I_IH

PWRONKEY = Low

I_OL= 200 µA

PWRONKEY = High

V(ROWX) = 5 V

0.4

1

V

ROWX Output High Leakage Current

µA

SIM CARD LDO (VSIM)

Output Voltage

VSIM

Line, Load, Temperature

SIMVSEL = Low

Line, Load, Temperature

SIMVSEL = High

1.70

2.80

1.80

2.85

1.90

2.92

V

Output Voltage

Line Regulation

Load Regulation

ꢂVSIM

2

mV

50 µA ≤ I_LOAD≤ 20 mA

VBAT = 3.6 V

Output Capacitor Required for

Stability

Dropout Voltage

C_O

2.2

µF

V_DO

V_O= V_INITIAL– 100 mV,

I

_LOAD= 20 mA,

35

100

mV

VSIM = 2.85 V

DIGITAL CORE LDO (VCORE)

Output Voltage

VCORE

ꢂVCORE

ꢂVCORE 50 µA ≤ I_LOAD≤ 100 mA

VBAT = 3.6 V

C_O

Line, Load, Temperature

1.75

2.2

1.80

2

8

1.85

V

mV

Line Regulation

Load Regulation

Output Capacitor Required for

Stability

µF

RTC LDO

REAL-TIME CLOCK LDO/

COIN CELL CHARGER (VRTC)

Maximum Output Voltage

Maximum Output Current

Off Reverse Input Current

VRTC

I_L

1 µA ≤ I_LOAD≤10 µA

VRTC = 0.5 V

VRTC = 1.90 V,

1.86

1.95

4.0

2.0

0.5

V

mA

VBAT = 1.70 V, T_A= 25

°C

µA

µF

Output Capacitor Required for

Stability

C_O

0.1

ANALOG LDO (VAN)

Output Voltage

VAN

ꢂVAN

Line, Load, Temperature

2.50

2.55

2

11

2.60

V

mV

Line Regulation

Load Regulation

50 µA ≤ I_LOAD≤ 180 mA,

VBAT = 3.6 V

Output Capacitor Required for

Stability

Ripple Rejection

C_O

2.2

65

µF

ꢂVBAT/

ꢂVAN³

V_NOISE

f = 217 Hz (t = 4.6 ms)

VBAT = 3.6 V

f = 10 Hz to 100 kHz

I_LOAD= 180 mA

VBAT = 3.6 V

V_O= V_INITIAL– 100 mV,

I_LOAD= 180 mA

dB

Output Noise Voltage

Dropout Voltage

80

µV rms

160

400

mV

REV. 0

–3–

ADP3522

(–20ꢁC < T_A< +85ꢁC, VBAT = VBAT2 = 3 V–5.5 V, CVSIM = CVCORE = CVAN = CVMEM =

2.2 ꢂF, VTCXO = 0.22 ꢂF, CVRTC = 0.1 ꢂF, CVBAT = 10 ꢂF, minimum loads applied on

all outputs, unless otherwise noted.)

ELECTRICAL CHARACTERISTICS¹

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

TCXO LDO (VTCXO)

Output Voltage

VTCXO

ꢂVTCXO

Line, Load, Temperature

2.711 2.75

2.789

V

mV

Line Regulation

Load Regulation

2

50 µA ≤ I_LOAD≤ 20 mA,

VBAT = 3.6 V

Output Capacitor Required for

Stability

Dropout Voltage

C_O

0.22

160

65

µF

V_DO

V_O= V_INITIAL– 100 mV

I_LOAD= 20 mA

f = 217 Hz (t = 4.6 ms)

VBAT = 3.6 V

f = 10 Hz to 100 kHz

I_LOAD= 20 mA, VBAT = 3.6 V

300

mV

Ripple Rejection

ꢂVBAT/

ꢂVTCXO

V_NOISE

dB

Output Noise Voltage

80

µV rms

MEMORY LDO (VMEM)

Output Voltage-3

VMEM

ꢂVMEM

Line, Load, Temperature

2.740 2.80

2.850

1.90

V

mV

Output Voltage-1.8

Line Regulation

Load Regulation

1.80

1.85

2

50 µA < I_LOAD< 150 mA

VBAT = 3.6 V

12

Output Capacitor Required for

Stability

C_O

2.2

µF

Dropout Voltage-3

V_O= V_INITIAL– 100 mV

I_LOAD= 150 mA

160

360

mV

REFOUT

Output Voltage

Line Regulation

Load Regulation

VREFOUT

ꢂVREFOUT

Line, Load, Temperature

Min Load

0 µA < I_LOAD< 50 µA

VBAT = 3.6 V

1.19

1.21

0.2

0.5

1.23

V

mV

Ripple Rejection

ꢂVBAT/

ꢂVREFOUT

C_O

f = 217 Hz (t = 4.6 ms)

65

75

40

dB

Maximum Capacitive Load

Output Noise Voltage

100

pF

µV rms

V_NOISE

f = 10 Hz to 100 kHz

RESET GENERATOR (RESET)

Output High Voltage

Output Low Voltage

V_OH

V_OL

I_OL/I_OH

I_OH= +500 µA

I_OL= –500 µA

V_OL= 0.25 V,

V_MEM– 0.25

1

V

mA

0.25

2.4

Output Current

V

_OH= V_MEM– 0.25 V

Delay Time per Unit Capacitance

Applied to RESCAP Pin

t_D

0.6

1.2

ms/nF

BATTERY VOLTAGE DIVIDER

Divider Ratio

BATSNS/

MVBAT

Z_O

TCXOEN = High

2.32

59.5

215

2.35

85

2.37

Divider Impedance at MVBAT

Divider Leakage Current

Divider Resistance

110

1

385

kꢁ

µA

kꢁ

TCXOEN = Low

TCXOEN = High

300

–4–

REV. 0

ADP3522

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

BATTERY CHARGER

Charger Output Voltage

BATSNS

4.35 V ≤ CHRIN ≤ 10 V³

CHGEN = Low, No Load

CHRIN = 10 V

CHGEN = Low, No Load

0°C < T_A< 50°C

CHRIN = 5 V

4.150 4.200 4.250

V

4.155

4.250

15

Load Regulation

ꢂBATSNS

mV

0 ≤ CHRIN – ISENSE

< Current Limit Threshold

CHGEN = Low

CHRDET On Threshold

CHRIN –

VBAT

30

90

40

6

150

mV

ms/nF

mA

CHRDET Hysteresis

CHRDET Off Delay⁴

CHRIN Supply Current

Current Limit Threshold

CHRIN < VBAT

CHRIN = 5 V

0.6

CHRIN –

ISENSE

High Current Limit

(UVLO Not Active)

CHRIN = 5 V DC

VBAT = 3.6 V

CHGEN = Low

CHRIN = 5 V DC

VBAT = 3.6 V

142

149

160

190

180

mV

CHGEN = Low

0°C < T_A< 50°C

VBAT = 2 V

CHGEN = Low

CHRIN = 5 V – 10 V

Low Current Limit

(UVLO Active)

20

35

mV

ISENSE Bias Current

EOC Signal Threshold

200

14

µA

CHRIN –

ISENSE

CHRIN = 5 V DC

VBAT > 4.0 V

CHGEN = Low

CHRIN = 5 V

mV

EOC Reset Threshold

GATEDR Transition Time

VBAT

t_R, t_F

3.82

0.1

3.96

4.10

1

V

µs

VBAT > 3.6 V

CHGEN = High, C_L= 2 nF

CHRIN = 5 V

VBAT = 3.6 V

CHGEN = High

GATEIN = High

I_OH= –1 mA

GATEDR High Voltage

GATEDR Low Voltage

V_OH

4.5

V

V_OL

CHRIN = 5 V

0.5

VBAT = 3.6 V

CHGEN = High

GATEIN = Low

I_OL= 1 mA

Output High Voltage

(EOC, CHRDET)

Output Low Voltage

(EOC, CHRDET)

V_OH

V_OL

I_OH= –250 µA

V_MEM– 0.25

V

I_OL= 250 µA

0.25

NOTES

¹All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

²This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC

could cause permanent damage to the device.

³No isolation diode is present between the charger input and the battery.

⁴Delay set by external capacitor on the RESCAP pin.

Specifications subject to change without notice.

REV. 0

–5–

ADP3522

ABSOLUTE MAXIMUM RATINGS*

PIN FUNCTION DESCRIPTIONS

Voltage on Any Pin with Respect to

1

Mnemonic

SIMEN

Description

Any GND Pin . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V

Voltage on Any Pin May Not Exceed VBAT, with the Following

Exceptions: CHRIN, BASE, ISENSE

Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C

Operating Ambient Temperature Range . . . . . –20∞C to +85∞C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C

␪_JA, Thermal Impedance (LFCSP 5 mm ϫ 5 mm)

4-Layer JEDEC PCB . . . . . . . . . . . . . . . . . . . . . . . . . . 32∞C/W

2-Layer SEMI PCB . . . . . . . . . . . . . . . . . . . . . . . . . . 108∞C/W

Lead Temperature Range (Soldering, 60 sec.) . . . . . . . . 300∞C

SIM LDO Enable

RTC LDO Input Voltage

2

VRTCIN

VRTC

3

Real-Time Clock Supply/

Coin Cell Battery Charger

4

5

6

7

8

BATSNS

MVBAT

CHRDET

CHRIN

Battery Voltage Sense Input

Divided Battery Voltage Output

Charge Detect Output

Charger Input Voltage

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability. Absolute maximum

ratings apply individually only, not in combination. Unless otherwise specified all

other voltages are referenced to GND.

SIMVSEL

Programs VSIM Output;

Low: 1.8 V

9

GATEDR

GATEIN

Charger Drive Output

10

Microprocessor Charger Gate

Control Input

11

DGND

ISENSE

EOC

Digital Ground

ORDERING GUIDE

Memory

12

Charge Current Sense Input

End of Charge Output

Charge Enable Control Input

Reset Delay Time

13

LDO

Output

Temperature

Range

Package

Option

14

CHGEN

RESCAP

RESET

NC

Model

15

ADP3522ACP-3

ADP3522ACP-1.8

2.80 V

1.80 V

–20∞C to +85∞C CP-32

16

Main Reset, Open Drain

No Connection

17, 24, 32

18

VSIM

SIM LDO Output

PIN CONFIGURATION

19

VBAT2

VMEM

VCORE

VBAT

Battery Input Voltage 2

Memory LDO Output

Digital Core LDO Output

Battery Input Voltage

Analog LDO Output

TCXO LDO Output

Output Reference

20

21

22

23

VAN

SIMEN 1

NC

24

23

PIN 1

INDICATOR

VRTCIN 2

VRTC 3

VAN

22 VBAT

25

VTCXO

REFOUT

AGND

TCXOEN

BATSNS 4

21 VCORE

26

ADP3522

5

TOP VIEW

20

19

MVBAT

VMEM

VBAT2

(Not to Scale)

TOP VIEW

27

Analog Ground

CHRDET 6

CHRIN 7

SIMVSEL 8

18 VSIM

17 NC

28

TCXO LDO Enable and

MVBAT Enable

29

PWRONIN

Power On/Off Signal from

Microprocessor

30

31

PWRONKEY

ROWX

Power On/Off Key

Power Key Interface Output

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADP3522 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

–6–

REV. 0

Typical Performance Characteristics–ADP3522

450

400

350

300

10000

1000

100

1.8

ALL LDO, MVBAT, REFOUT,

ON_MIN_LOAD (SIMEN = H,

TCXOEN = H)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

RTC REVERSE LEAKAGE

(VBAT = FLOAT)

+85؇C

–20؇C

VSIM, VCORE, VMEM, VRTC,

ON_MIN_LOAD (SIMEN = H,

TCXOEN = L)

250

200

150

100

50

+25؇C

RTC REVERSE LEAKAGE

(VBAT = 2.3V)

VCORE, VMEM, VRTC,

ON_MIN_LOAD (SIMEN = L,

TCXOEN = L)

0

3.0

10

25 30 35 40 45 50 55 60 65 70 75 80 85

0

0.5

1.0

1.5

2.0

3.5

4.0

4.5

5.0

5.5

TEMPERATURE – ؇C

VBAT – V

VRTC – V

TPC 3. VRTC Reverse Leakage

Current vs. Temperature

TPC 1. Ground Current vs.

Battery Voltage

TPC 2. RTC I/V Characteristic

180

160

3.2

VTCXO

VAN

VMEM

140

120

100

80

VBAT

3.0

VBAT

3.0

VTCXO

VMEM

VTCXO

VMEM

10mV/DIV

60

VSIM

40

20

0

TIME – 100␮s/DIV

0

50

100

150

200

LOAD CURRENT – mA

TPC 4. Dropout Voltage vs.

Load Current

TPC 5. Line Transient

Response, Minimum Loads

TPC 6. Line Transient

Response, Maximum Loads

3.2

3.0

3.2

3.0

20mA

LOAD

VBAT

2mA

VAN

10mV/DIV

VAN

VTCXO

VCORE

VSIM

10mV/DIV

VCORE

VSIM

10mV/DIV

TIME – 100␮s/DIV

TIME – 200␮s/DIV

TPC 7. Line Transient

TPC 8. Line Transient

TPC 9. VTCXO Load Step

Response, Minimum Loads

Response, Maximum Loads

REV. 0

–7–

ADP3522

100mA

150mA

LOAD

VMEM

LOAD

20mA

15mA

10mA

LOAD

VSIM

2mA

VCORE

10mV/DIV

20mV/DIV

10mV/DIV

TIME – 200ꢂs/DIV

TPC 10. VSIM Load Step

TPC 11. VMEM Load Step

TPC 12. VCORE Load Setup

180mA

PWRONIN (2V/DIV)

LOAD

18mA

VAN (100mV/DIV)

VSIM = 2.8 (100mV/DIV)

VMEM = 1.8 (100mV/DIV)

20mV/DIV

VCORE (100mV/DIV)

TIME – 200ꢂs/DIV

TIME – 400ꢂs/DIV

TIME – 200ꢂs/DIV

TPC 13. VAN Load Step

TPC 15. Turn On Transient

by PWRONIN, Minimum

Load (Part 2)

TPC 14. Turn On Transient

by PWRONIN, Minimum

Load (Part 1)

PWRONIN (2V/DIV)

VAN (100mV/DIV)

REFOUT (100mV/DIV)

VSIM = 1.8 (100V/DIV)

VSIM = 2.8 (100mV/DIV)

VMEM = 2.8 (100mV/DIV)

VTCXO (100mV/DIV)

VCORE (100mV/DIV)

TIME – 100ꢂs/DIV

TIME – 1ms/DIV

TIME – 20ꢂs/DIV

TPC 16. Turn On Transient

by PWRONIN, Minimum

Load (Part 3)

TPC 17. Turn On Transient

by PWRONIN, Minimum

Load (Part 4)

TPC 18. Turn On Transient

by PWRONIN, Maximum

Load (Part 1)

–8–

REV. 0

ADP3522

PWRONIN (2V/DIV)

REFOUT (100mV/DIV)

VSIM = 1.8 (100mV/DIV)

VMEM = 2.8(100mV/DIV)

VTCXO (100mV/DIV)

VMEM = 1.8 (100mV/DIV)

TIME – 100ꢂs/DIV

TIME – 20ꢂs/DIV

TPC 20. Turn On Transient

by PWRONIN, Maximum

Load (Part 3)

TPC 21. Turn On Transient

by PWRONIN, Maximum

Load (Part 4)

TPC 19. Turn On Transient

by PWRONIN, Maximum

Load (Part 2)

80

600

500

400

300

200

100

0

80

70

REFOUT

FULL LOAD

VTCXO

70

60

50

40

30

20

10

0

MLCC CAPS

VAN

60

VCORE

TCXO

50

40

REFOUT

VSIM

MLCC OUTPUT CAPS

VBAT = 3.2V, FULL LOADS

VAN

30

20

REF

VTCXO

VMEM

VSIM = 2.8V

FREQ = 217Hz,

MAX LOADS

10

0

2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3

10

100

1k

10k

100k

4

10

100

1k

10k

100k

VBAT – V

FREQUENCY – Hz

TPC 23. Ripple Rejection vs.

Battery Voltage

TPC 24. Output Noise Density

TPC 22. Ripple Rejection vs.

Frequency

4.24

4.23

4.22

4.21

4.20

4.25

4.24

4.23

4.22

4.21

4.20

4.19

4.18

4.17

4.16

4.15

4.24

4.23

4.22

4.21

4.20

V

R

= 5.0V

IN

R

= 250mꢃ

SENSE

= 250mꢃ

SENSE

I

= 500mA

LOAD

I

= 10mA

LOAD

0

200

400

– mA

600

800

–40 –20

0

20

40 60 80 100 120

5

6

7

8

9

10

I

TEMPERATURE – ꢁC

LOAD

INPUT VOLTAGE – V

TPC 25. Charger V_OUTvs.

Temperature, V_IN= 5.0 V,

I_LOAD= 10 mA

TPC 26. Charger V_OUTvs.

I_LOAD(V_IN= 5.0 V)

TPC 27. Charger V_OUTvs. V_IN

REV. 0

–9–

ADP3522

Table I. LDO Control Logic

STATE NO.

PHONE STATUS

State No. 1

Battery Deep Discharged

L

X

L

X

OFF OFF OFF OFF OFF OFF OFF OFF

OFF OFF OFF ON OFF OFF OFF OFF

State No. 2

Phone Off

H

State No. 3

Phone Off,

Turn-On Allowed

H

L

H

X

L

X

L

OFF OFF OFF ON OFF OFF OFF OFF

State No. 4

Charger Applied

H

X

OFF ON ON ON ON ON ON ON*

State No. 5

Phone Turned On by

User Key

H

X

L

H

X

H

X

L

H

L

OFF ON ON ON ON ON ON ON*

ON ON ON ON OFF OFF OFF OFF

ON ON ON ON ON ON ON ON

OFF ON ON ON ON ON ON ON

State No. 6

Deep Sleep

State No. 7

Active

H

State No. 8

Reset SIM Card

*The state of MVBAT is determined by TCXOEN. When TCXOEN is high, MVBAT is ON.

–10–

REV. 0

ADP3522

VBAT

SIMVSEL

SIM LDO

VRTCIN

VBAT2

VSEL

OUT

VBAT

VREF

VSIM

DEEP

DISCHARGED

UVLO

110k⍀

EN DGND

UVLO

Q

S

R

PWRONKEY

ROWX

DIGITAL CORE LDO

VBAT

OVERTEMP

SHUTDOWN

VCORE

OUT

VREF

PG

PWRONIN

SIMEN

EN DGND

1M⍀

ANALOG LDO

VBAT

OUT

VAN

CHARGER

DETECT

VREF

EN

AGND

TCXOEN

RESCAP

CHRDET

TCXO LDO

RESET

GENERATOR

VBAT

VREF

VTCXO

OUT

EOC

EN

AGND

Li-ION

BATTERY

CHARGE

CONTROLLER

AND

CHGEN

MEMORY LDO

VBAT

GATEIN

␮PROCESSOR

CHARGE

INTERFACE

VMEM

VRTC

VREF

EN

OUT

BATSNS

ISENSE

DGND

RTC LDO

VBAT

GATEDR

CHRIN

VREF

OUT

EN

DGND

EN

REF

BUFFER

REFOUT

1.21V

MVBAT

AGND

DGND

AGND

Figure 1. Functional Block Diagram

REV. 0

–11–

ADP3522

PWRON

POWERKEY

ROWX

CLKON

R8

10ꢃ

REFOUT

VTCXO

C8

C9

0.1ꢂF

0.22ꢂF

SIMEN

VRTC

NC

VRTCIN

VRTC

VAN

C10

2.2ꢂF

VBAT

C1

0.1ꢂF

COIN CELL

VCORE

VMEM

VBAT2

VSIM

VCORE

VMEM

BATSNS

MVBAT

CHRDET

CHRIN

ADP3522

MVBAT

CHRDET

CHRIN

VSIM

SIMVSEL

SIMSEL

NC

C2

1nF

R1

0.25ꢃ

GATEDR

Q1

SI3441

RESET

D1

BAT1000

CHGEN

EOC

Li OR NiMH

BATTERY

C3

10ꢂF

C4

0.1ꢂF

C5

2.2ꢂF

C6

2.2ꢂF

C7

2.2ꢂF

GATEIN

Figure 2. Typical Application Circuit

THEORY OF OPERATION

ADP3522 needs to dissipate. The thermal impedance of the

The ADP3522 is a power management chip optimized for use

with GSM baseband chipsets in handset applications. Figure 1

shows a block diagram of the ADP3522. The ADP3522 con-

tains several blocks, such as:

CSP package is 32°C/W for a JEDEC standard 4-layer board.

The end of charge voltage for high capacity NiMH cells can be as

high as 5.5 V. This results in a worst-case power dissipation for

the ADP3522-1.8 to be as high as 1.6 W for NiMH cells. The

power dissipation for the ADP3522-3 is slightly lower at 1.45 W.

•

Six low dropout regulators (SIM, core, analog, crystal

oscillator, memory, real-time clock)

A fully charged Li-Ion battery is 4.25 V, where the ADP3522-3

can dissipate a maximum power of 0.85 W. However, the

ADP3522-1.8 can have a maximum dissipation of 1.0 W.

•

Reset generator

Buffered precision reference

Lithium ion charge controller and processor interface

Power on/off logic

High battery voltages normally occur when the battery is being

charged and the handset is not in conversation mode. In this

mode, there is a relatively light load on the LDOs. The worst-

case power dissipation should be calculated based on the actual

load currents and voltages used.

Undervoltage lockout

Deep discharge lockout

Figure 3 shows the maximum power dissipation as a function of

the input voltage. Figure 4 shows the maximum allowable

power dissipation as a function of the ambient temperature.

These functions have traditionally been done either as a discrete

implementation or as a custom ASIC design. The ADP3522

combines the benefits of both worlds by providing an integrated

standard product where every block is optimized to operate in a

GSM environment while maintaining a cost competitive solution.

Low Dropout Regulators (LDOs)

The ADP3522 high performance LDOs are optimized for their

given functions by balancing quiescent current, dropout voltage,

regulation, ripple rejection, and output noise. 2.2 µF tantalum

or MLCC ceramic capacitors are recommended for use with the

core, memory, SIM, and analog LDOs. A 0.22 µF capacitor is

recommended for the TCXO LDO.

Figure 2 shows the external circuitry associated with the

ADP3522. Only a minimal number of support components

are required.

Input Voltage

The input voltage range of the ADP3522 is 3 V to 5.5 V and is

optimized for a single Li-Ion cell or three NiMH cells. The type

of battery, the SIM LDO output voltage, and the memory LDO

output voltage will all affect the amount of power that the

–12–

REV. 0

ADP3522

Digital Core LDO (VCORE)

Applying a low to SIMEN shuts down the SIM LDO. A dis-

charge circuit is active when SIMEN is low. This pulls the SIM

LDO’s output down when the LDO is disabled.

The digital core LDO supplies the baseband circuitry in the

handset (baseband processor and baseband converter). The

LDO has been optimized for very low quiescent current at light

loads as this LDO is on whenever the handset is switched on.

SIMVSEL allows the SIM LDO to be programmed for either

1.8 V or 2.8 V. Asserting a high on SIMVSEL sets the output

for 2.8 V.

Memory LDO (VMEM)

The memory LDO supplies the system memory as well as the

subsystems of the baseband processor including memory IO,

display, and melody interfaces. It is capable of delivering up to

150 mA of current and is available for either 1.8 V or 3 V based

systems. The LDO has also been optimized for low quiescent

current and will power up at the same time as the core LDO.

SIMEN and SIMVSEL allow the baseband processor to prop-

erly sequence the SIM supply when determining which type of

SIM module is present.

Reference Output (REFOUT)

The reference output is a low noise, high precision reference with

a guaranteed accuracy of 1.5% overtemperature. The maximum

output current of the REFOUT supply is limited to 50 µA.

Analog LDO (VAN)

This LDO has the same features as the core LDO. It has fur-

thermore been optimized for good low frequency ripple

rejection for use with the baseband converter sections in order

to reject the ripple coming from the RF power amplifier. VAN is

rated to 180 mA, which is sufficient to supply the analog section

of the baseband converter, such as the AD6521, as well as the

microphone and speaker.

Power ON/OFF

The ADP3522 handles all issues regarding the powering ON

and OFF of the handset. It is possible to turn on the ADP3522

in three different ways:

•

Pulling the PWRONKEY low

Pulling the PWRONIN high

TCXO LDO (VTCXO)

CHRIN exceeds CHRDET threshold

The TCXO LDO is intended as a supply for a temperature

compensated crystal oscillator, which needs its own ultralow

noise supply. VTCXO is rated for 20 mA of output current and

is turned on along with the analog LDO when TCXOEN is

asserted. Note that the ADP3522 has been optimized for use

with the AD6534 (Othello One™).

Pulling the PWRONKEY low is the normal way of turning on the

handset. This will turn on all the LDOs, except the SIM LDO, as

long as the PWRONKEY is held low. When the VCORE LDO

comes into regulation, the RESET timer is started. After timing

out, the RESET pin goes high, allowing the baseband processor to

start up. With the baseband processor running, it can poll the

ROWX pin of the ADP3522 to determine if the PWRONKEY has

been depressed and pull PWRONIN high. Once the PWRONIN is

taken high, the PWRONKEY can be released. Note that by moni-

toring the ROWX pin, the baseband processor can detect a second

PWRONKEY and press and turn the LDOs off in an orderly manner.

In this way, the PWRONKEY can be used for ON/OFF control.

RTC LDO (VRTC)

The RTC LDO is capable of charging rechargeable Lithium or

capacitor-type backup coin cells to run the real-time clock mod-

ule. The RTC LDO supplies current both for charging the coin

cell and for the RTC module. In addition, it features a very low

quiescent current since this LDO is running all the time, even

when the handset is switched off. It also has reverse current

protection with low leakage, which is needed when the main

battery is removed and the coin cell supplies the RTC module.

Pulling the PWRONIN pin high is how the alarm in the real-

time clock module will turn the handset on. Asserting

PWRONIN will turn the core and memory LDOs on, starting

up the baseband processor.

SIM LDO (VSIM)

The SIM LDO generates the voltage needed for 1.8 V or 3 V

SIMs. It is rated for 20 mA of supply current and can be con-

trolled completely independently of the other LDOs.

1.8

1.6

1.8

1.6

LFCSP

32ꢁC/W

1.4

1.2

1.0

0.8

0.6

0.4

1.4

ADP3522-1.8

1.2

1.0

0.8

0.6

0.4

ADP3522-2.8

0.2

0

0.2

0

3.0

3.5

4.0

4.5

5.0

5.5

6.0

–20

0

20

40

60

80

INPUT VOLTAGE – V

AMBIENT TEMPERATURE – ꢁC

Figure 3. Power Dissipation vs. Input Voltage

Figure 4. Allowable Package Power Dissipation

vs. Temperature

REV. 0

–13–

ADP3522

NONCHARGING

MODE

NO

CHARGER DETECTED

CHRIN > BATSNS

YES

VBAT > UVLO

NNOO

NiMH

BATTERY TYPE

LOW CURRENT

CHARGE MODE

Li+

V

= 20mV

SENSE

CHGEN = LOW

CHGEN = HIGH

NiMH

CHARGING MODE

HIGH CURRENT

CHARGE MODE

GATEIN = PULSED

V

= 160mV

SENSE

NO

VBAT > 5.5V

YES

VBAT > 4.2V

YES

CONSTANT VOLTAGE

MODE

NiMH

CHARGER OFF

YES

GATEIN = HIGH

NO

END OF CHARGE

V

< 14mV

SENSE

NO

VBAT > 5.5V

YES

EOC = HIGH

TERMINATE CHARGE

CHGEN = HIGH

GATEIN = HIGH

Figure 5. Battery Charger Flow Chart

–14–

REV. 0

ADP3522

Applying an external charger can also turn the handset on. This

will turn on all the LDOs, except the SIM LDO, again starting

up the baseband processor. Note that if the battery voltage is

below the undervoltage lockout threshold, applying the adapter

will not start up the LDOs.

Overtemperature Protection

The maximum die temperature for the ADP3522 is 125°C. If

the die temperature exceeds 160°C, the ADP3522 will disable

all the LDOs except the RTC LDO. The LDOs will not be

re-enabled before the die temperature is below 125°C, regard-

less of the state of PWRONKEY, PWRONIN, and CHRDET.

This ensures that the handset will always power off before the

ADP3522 exceeds its absolute maximum thermal ratings.

Deep Discharge Lockout (DDLO)

The DDLO block in the ADP3522 shuts down the handset in

the event that the software fails to turn off the phone when the

battery voltage drops below 2.9 V to 3.0 V. The DDLO will

shut down the handset when the battery falls below 2.4 V to

prevent further discharge and damage to the battery.

Battery Charging

The ADP3522 battery charger can be used with lithium ion

(Li+) and nickel metal hydride (NiMH) batteries. The charger

initialization, trickle charging, and Li+ charging are imple-

mented in hardware. Battery type determination and NiMH

charging must be implemented in software.

The DDLO will also shut down the RTC LDO when the main

battery is removed. This will prevent reverse current from dis-

charging the backup coin cell.

The charger block works in three different modes:

1. Low current (trickle) charging

2. Lithium ion charging

Undervoltage Lockout (UVLO)

The UVLO function in the ADP3522 prevents startup when the

initial voltage of the battery is below the 3.2 V threshold. If the

battery voltage is this low with no load, there is insufficient

capacity left to run the handset. When the battery is greater

than 3.2 V, such as inserting a fresh battery, the UVLO com-

parator trips, and the threshold is reduced to 3.0 V. This allows

the handset to start normally until the battery decays to below 3.0 V.

3. Nickel metal hydride charging

See Figure 5 for the charger flow chart.

Charge Detection

The ADP3522 charger block has a detection circuit that deter-

mines if an adapter has been applied to the CHRIN pin. If the

adapter voltage exceeds the battery voltage by 100 mV, the

CHRDET output will go high. If the adapter is then removed

and the voltage at the CHRIN pin drops to only 50 mV above

the BATSNS pin, CHRDET goes low. The CHRDET signal is

not asserted if the battery voltage is below the UVLO threshold.

Once the system is started and the core and memory LDOs are

up and running, the UVLO function is entirely disabled. The

ADP3522 is then allowed to run until the battery voltage

reaches the DDLO threshold, typically 2.4 V. Normally, the

battery voltage is monitored by the baseband processor, which

usually shuts the phone off at a battery voltage of around 3.0 V.

If the handset is off and the battery voltage drops below 3.0 V,

the UVLO circuit disables startup and puts the ADP3522 into

UVLO shutdown mode. In this mode, the ADP3522 draws very

low quiescent current, typically 30 µA. In DDLO mode, the

ADP3522 draws 15 µA of quiescent current. NiMH batteries can

reverse polarity if the 3-cell battery voltage drops below 3.0 V,

which will degrade the batteries’ performance. Lithium ion bat-

teries will lose their capacity if overdischarged repeatedly, so

minimizing the quiescent currents helps prevent battery damage.

Trickle Charging

When the battery voltage is below the UVLO threshold, the

charge current is set to the low current limit, or about 10% of

the full charge current. The low current limit is determined by

the voltage developed across the current sense resistor. There-

fore, the trickle charge current can be calculated by

20mV

R_SENSE

I_{CHR(TRICKLE )}

=

(2)

RESET

Trickle charging is performed for deeply discharged batteries to

prevent undue stress on either the battery or the charger.

Trickle charging will continue until the battery voltage exceeds

the UVLO threshold.

The ADP3522 contains a reset circuit that is active both at

power-up and power-down. The RESET pin is held low at

initial power-up. An internal power good signal is generated by

the core LDO when its output is up, starting the reset delay

timer. The delay is set by an external capacitor on RESCAP:

Once the UVLO threshold has been exceeded, the charger will

switch to the default charge mode, the LDOs will start up, and

the baseband processor will start to run. The processor must

then poll the battery to determine which chemistry is present

and set the charger to the proper mode. Control of the charge

mode, Li+ or NiMH, is determined by the CHGEN input.

ms

nF

t_RESET= 1.2

×C_RESCAP

(1)

At power-off, RESET will be kept low to prevent any baseband

processor starts.

REV. 0

–15–

ADP3522

4.2V

processor can charge a NiMH battery. Note that when charging

NiMH cells, a current limited adapter is required.

During the PMOS off periods, the battery voltage needs to be

monitored through the MVBAT pin. The battery voltage is con-

tinually polled until the final battery voltage is reached. Then the

charge can either be terminated or the frequency of the pulsing

reduced. An alternative method of determining the end of charge

is to monitor the temperature of the cells and terminate the

charging when a rapid rise in temperature is detected.

V

BAT

3.2V

Battery Voltage Monitoring

HIGH CURRENT

The battery voltage can be monitored at MVBAT during charg-

ing and discharging to determine the condition of the battery. An

internal resistor divider can be connected to BATSNS when both

the digital and analog baseband sections are powered up. To

enable MVBAT, both PWRONIN and TCXOEN must be high.

I

CHARGE

EOC CURRENT

LOW CURRENT

0

The ratio of the voltage divider is selected so that the 2.4 V

maximum input of the AD6521’s auxiliary ADC will corre-

spond with the maximum battery voltage of 5.5 V. The divider

will be disconnected from the battery when the baseband sec-

tions are powered down.

EOC

INDICATOR

APPLICATION INFORMATION

Input Capacitor Selection

Figure 6. Lithium Ion Charging Diagram

For the input (VBAT, VBAT2, and VRTCIN) of the ADP3522, a

local bypass capacitor is recommended; use a 10 µF, low ESR

capacitor. Multilayer ceramic chip (MLCC) capacitors provide

the best combination of low ESR and small size but may not be

cost effective. A lower cost alternative may be to use a 10 µF

tantalum capacitor with a small (1 µF to 2 µF) ceramic in parallel.

Lithium Ion Charging

For lithium ion charging, the CHGEN input must be low. This

allows the ADP3522 to continue charging the battery at the full

current. The full charge current can be calculated by using

160mV

R_SENSE

I_CHR(FULL)

=

(3)

Separate inputs for the SIM LDO and the RTC LDO are sup-

plied for additional bypassing or filtering. The SIM LDO has

VBAT2 as its input and the RTC LDO has VRTCIN.

If the voltage at BATSNS is below the charger’s output voltage

of 4.2 V, the battery will continue to charge in the constant

current mode. If the battery has reached the final charge volt-

age, a constant voltage is applied to the battery until the charge

current has reduced to the charge termination threshold. The

charge termination threshold is determined by the voltage across

the sense resistor. If the battery voltage is above 4.0 V and the

voltage across the sense resistor has dropped to 14 mV, then an

end of charge signal is generated—the EOC output goes high

(see Figure 6).

LDO Capacitor Selection

The performance of any LDO is a function of the output capacitor.

The core, memory, SIM, and analog LDOs require a 2.2 µF

capacitor and the TCXO LDO requires a 0.22 µF capacitor.

Larger values may be used, but the overshoot at startup will

increase slightly. If a larger output capacitor is desired, be

sure to check that the overshoot and settling time are accept-

able for the application.

The baseband processor can either let the charger continue to

charge the battery for an additional amount of time or terminate

the charging. To terminate the charging, the processor must

pull the GATEIN pin high and the CHGEN pin high.

All the LDOs are stable with a wide range of capacitor types and

ESR (anyCAP^®technology). The ADP3522 is stable with

extremely low ESR capacitors (ESR ~ 0) such as multilayer

ceramic capacitors (MLCC), but care should be taken in their

selection. Note that the capacitance of some capacitor types

shows wide variations over temperature or with dc voltage. A

good quality dielectric, X7R or better, capacitor is recommended.

NiMH Charging

For NiMH charging, the processor must pull the CHGEN pin

high. This disables the internal Li+ mode control of the gate

drive pin. The gate drive must now be controlled by the

baseband processor. By pulling GATEIN high, the GATEDR

pin is driven high, turning the PMOS off. By pulling the

GATEIN pin low, the GATEDR pin is driven low, and the

PMOS is turned on. So, by pulsing the GATEIN input, the

The RTC LDO can have a rechargeable coin cell or an electric

double-layer capacitor as a load, but an additional 0.1 µF ceramic

capacitor is recommended for stability and best performance.

–16–

REV. 0

ADP3522

CHARGE CHARACTERISTIC

CHARGER CHARACTERISTIC

2.00

1.75

1.50

1.25

1.00

0.75

0.50

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.25

0

0.9

0

20

40

60

80

100

120

0

5

10

15

20

25

30

35

40

TIME – Minutes

TIME – Hours

Figure 7. Kanebo PAS621 Charge Characteristic

Figure 10. Seiko TS621 Charge Characteristic

RTC Backup Coin Cell Selection

CHARGER CHARACTERISTIC

2.00

The choice of the backup cell is based upon size, cost, and

capacity. It must be able to support the RTC module’s current

requirement and voltage range, as well as handle the charge

current supplied by the ADP3522 (see TPC 2). Check with the

coin cell vendor if the ADP3522’s charge current profile is

acceptable.

1.75

1.50

1.25

1.00

0.75

0.50

Some suitable coin cells are the electric double layer capacitors

available from Kanebo (PAS621), Seiko (XC621), or Panasonic

(EECEM0E204A). They have a small physical size (6.8 mm

diameter) and a nominal capacity of 0.2 F to 0.3 F, giving hours

of backup time. Rechargeable lithium coin cells, such as the

TC614 from Maxell or the TS621 from Seiko, are also small in

size but have higher capacity than the double layer capacitors,

resulting in longer backup times. Typical charge curves for each

cell type are shown in Figures 7 through 10. Note that the

rechargeable lithium type coin cells generally come precharged

from the vendor.

0.25

0

20

40

60

80

100

120

TIME – Minutes

Figure 8. Panasonic EECEM0E204A Charge Characteristic

RESET Capacitor Selection

CHARGE CHARACTERISTIC

2.0

RESET is held low at power up. An internal power-good signal

starts the reset delay when the core LDO is up. The delay is set

by an external capacitor on RESCAP:

1.9

1.8

1.7

1.6

ms

nF

t_RESET= 1.2

×C_RESCAP

(4)

A 100 nF capacitor will produce a 120 ms reset delay. The

current capability of RESET is minimal (a few hundred nA)

when VCORE is off to minimize power consumption. When

VCORE is on, RESET is capable of driving 500 µA.

1.5

1.4

1.3

1.2

1.1

1.0

Setting the Charge Current

The ADP3522 is capable of charging both lithium ion and

NiMH batteries. For NiMH batteries, the charge current is

limited by the adapter. For lithium ion batteries, the charge

0.9

0

5

10

15

20

25

30

TIME – Hours

Figure 9. Maxell TC614 Charge Characteristic

REV. 0

–17–

ADP3522

current is programmed by selecting the sense resistor, R1 (see

Figure 2).

The thermal characteristics of the FET must be considered

next. The worst-case dissipation can be determined using:

The lithium ion charge current is calculated using

P_DISS=V_{ADAPTER(MAX )}− V_DIODE− V_SENSE

− UVLO × I_CHR

(12)

V_SENSE160mV

I_CHR

=

(5)

R1

It should be noted that the adapter voltage can be either

where V_SENSEis the high current limit threshold voltage. Or if

the charge current is known, R1 can be found:

preregulated or nonregulated. In the preregulated case, the

difference between the maximum and minimum adapter voltage

is probably not significant. In the unregulated case, the adapter

voltage can have a wide range specified. However, the maxi-

mum voltage specified is usually with no load applied. So, the

worst-case power dissipation calculation will often lead to an

overspecified pass device. In either case, it is best to determine

the load characteristics of the adapter to optimize the charger

design.

V_SENSE160mV

R1 =

=

(6)

I_CHR

Similarly the trickle charge current and the end of charge cur-

rent can be calculated:

V_SENSE20mV

I_TRICKLE

=

(7)

(8)

R1

For example:

V

_ADAPTER(MIN)= 5.0 V

V_SENSE14mV

I_EOC

=

R1

_ADAPTER(MAX)= 6.5 V

Example: Assume an 800 mA-H capacity lithium ion battery

and a 1 C charge rate. R1 = 200 mꢁ. Then I_TRICKLE= 100 mA

and I_EOC= 70 mA.

_DIODE= 0.5 V at 800 mA

_GATEDR= 0.5 V

_SENSE= 160 mV

Appropriate sense resistors are available from the following

vendors:

_GS= 5 V – 0.5 V – 0.160 V = 4.3 V. So choose a low

threshold voltage FET.

•

Vishay Dale

IRC

V_DS=V_{ADAPTER(MIN )}-V_DIODE-V_SENSE-V_BAT

(13)

(14)

Panasonic

Charger FET Selection

V_DS= 5V -0.5V -0.160V - 4.2V =140 mV

The type and size of the pass transistor is determined by the

threshold voltage, input-output voltage differential, and charge

current. The selected PMOS must satisfy the physical, electri-

cal, and thermal design requirements.

V_DS

I_{CHR(MAX )}

140mV

800mA

R_{DS(ON )}

=

= 175mΩ

To ensure proper operation, the minimum VGS the ADP3522

can provide must be enough to turn on the FET. The available

gate drive voltage can be estimated using the following:

P_DISS= (V_{ADAPTER(MAX )}− V_DIODE− V_SENSE

− UVLO)× I_CHR

V_GS=V_{ADAPTER(MIN )}-V_GATEDR-V_SENSE

where

(9)

(15)

V

_ADAPTER(MIN)is the minimum adapter voltage.

_GATEDRis the gate drive “low” voltage, 0.5 V.

P_DISS= (6.5V − 0.5V − 0.160V − 3.2V )

×0.8 A = 2.1W

_SENSEis the maximum high current limit threshold voltage.

Appropriate PMOS FETs are available from the following vendors:

The difference between the adapter voltage (V_ADAPTER) and the

final battery voltage (V_BAT) must exceed the voltage drop due to

the blocking diode, the sense resistor, and the on resistance of

the FET at maximum charge current.

•

Siliconix

IR

Fairchild

(10)

V_DS=V_ADAPTER-V_DIODE-V_SENSE-V_BAT

Then the R_DS(ON)of the FET can be calculated:

V_DS

Charger Diode Selection

The diode, D1, shown in Figure 2 is used to prevent the battery

from discharging through the PMOS’ body diode into the

charger’s internal bias circuits. A Schottky diode is recom-

mended to minimize the voltage difference from the charger to

the battery and the power dissipation. Choose a diode with a

current rating high enough to handle the battery charging cur-

rent and a voltage rating greater than VBAT. The blocking

diode is required for both lithium and nickel battery types.

R_{DS(ON )}

=

(11)

I_{CHR(MAX )}

–18–

REV. 0

ADP3522

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed

circuit boards:

path to the inner or bottom layers. See Figure 12 for the

recommended via pattern. Note that the via diameter is

small. This is to prevent the solder from flowing through the

via and leaving voids in the thermal pad solder joint.

1. Connect the battery to the VBAT, VBAT2, and VRTCIN

pins of the ADP3522. Locate the input capacitor as close to

the pins as possible.

Note that the thermal pad is attached to the die substrate;

the thermal planes that the vias attach the package to must

be electrically isolated or connected to VBAT. Do NOT

connect the thermal pad to ground.

2. VAN and VTCXO output capacitors should be returned to

AGND.

3. The solder mask opening should be about 120 microns (4.7 mils)

larger than the pad size resulting in a minimum 60 microns

(2.4 mils) clearance between the pad and the solder mask.

3. VCORE, VMEM, and VSIM output capacitors should be

returned to DGND.

4. Split the ground connections. Use separate traces or planes

for the analog, digital, and power grounds and tie them to-

gether at a single point, preferably close to the battery return.

4. The paste mask opening is typically designed to match the

pad size used on the peripheral pads of the LFCSP package.

This should provide a reliable solder joint as long as the

stencil thickness is about 0.125 mm.

5. Run a separate trace from the BATSNS pin to the battery to

prevent voltage drop error in the MVBAT measurement.

The paste mask for the thermal pad needs to be designed for

the maximum coverage to effectively remove the heat from

the package. However, due to the presence of thermal vias

and the large size of the thermal pad, eliminating voids may

not be possible. Also, if the solder paste coverage is too large,

solder joint defects may occur. Therefore, it is recommended

to use multiple small openings over a single big opening in

designing the paste mask. The recommended paste mask

pattern is given in Figure 13. This pattern will result in about

80% coverage, which should not degrade the thermal perfor-

mance of the package significantly.

6. Kelvin connect the charger’s sense resistor by running

separate traces to the CHRIN pin and ISENSE pin. Make

sure the traces are terminated as close to the resistor’s

body as possible.

7. Use the best industry practice for thermal considerations

during the layout of the ADP3522 and charger components.

Careful use of copper area, weight, and multilayer construc-

tion all contribute to improved thermal performance.

LFCSP Layout Considerations

The CSP package has an exposed die paddle on the bottom that

efficiently conducts heat to the PCB. In order to achieve the

optimum performance from the CSP package, special consider-

ation must be given to the layout of the PCB. Use the following

layout guidelines for the CSP package:

5. The recommended paste mask stencil thickness is 0.125 mm.

A laser cut stainless steel stencil with trapezoidal walls should

be used.

A “No Clean,” Type 3 solder paste should be used for

mounting the LFCSP package. Also, a nitrogen purge during

the reflow process is recommended.

1. The pad pattern is given in Figure 11. The pad dimension

should be followed closely for reliable solder joints while

maintaining reasonable clearances to prevent solder bridging.

6. The package manufacturer recommends that the reflow

temperature should not exceed 220°C and the time above

liquids is less than 75 seconds. The preheat ramp should be

3°C/second or lower. The actual temperature profile depends

on the board’s density and must be determined by the assembly

house as to what works best.

2. The thermal pad of the CSP package provides a low thermal

impedance path (approximately 15°C/W) to the PCB.

Therefore, the PCB must be properly designed to effectively

conduct the heat away from the package. This is achieved by

adding thermal vias to the PCB, which provide a thermal

REV. 0

–19–

ADP3522

0.08

CREATE SOLDER PASTE

WEB FOR APPROX 80%

COVERAGE 125 MICRONS

WIDE TO SEPARATE

3.80

SOLDER PASTE AREA

5.36

3.56

3.96

THERMAL PAD AREA

0.70

0.30

0.20

Dimensions shown in millimeters

0.50

Figure 13. 5 mm ϫ 5 mm LFSCP Solder Paste Mask Pattern

Figure 11. 5 mm ϫ 5 mm LFCSP Pad Pattern

ARRAY OF 9 VIAS

0.25mm DIAMETER

0.35ꢂm PLATING

0.60

1.18

THERMAL PAD AREA

1.18

0.60

Dimensions shown in millimeters

Figure 12. 5 mm ϫ 5 mm LFSCP Via Pattern

OUTLINE DIMENSIONS

32-Lead Frame Chip Scale Package [LFCSP]

5 mm ꢀ 5 mm Body

Dimensions shown in millimeters

5.00

BSC SQ

0.60 MAX

PIN 1

0.60 MAX

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

4.75

BSC SQ

3.25

3.10

2.95

TOP

VIEW

BOTTOM

VIEW

SQ

0.50

0.40

0.30

17

16

8

9

3.50

REF

1.00 MAX

0.65 NOM

12ꢁ MAX

0.05 MAX

0.02 NOM

1.00

0.90

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

–20–

REV. 0


型号：	ADP3522ACP-1.8-RL7
厂家：	Rochester Electronics
描述：	1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32, 5 X 5 MM, MO-220VHHD-2, LFCSP-32
文件：	总21页 (文件大小：1132K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP3522ACP-1.8-RL7 [ROCHESTER]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E