ADP3631ARZ-R7 [ADI]
High Speed, Dual, 2 A MOSFET Driver; 高速，双通道，2 MOSFET驱动器
| 型号： | ADP3631ARZ-R7 |
| 厂家： | 
ADI |
| 描述： | High Speed, Dual, 2 A MOSFET Driver |
| 文件： | 总16页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Dual, 2 A MOSFET Driver
ADP3629/ADP3630/ADP3631
GENERAL DESCRIPTION
FEATURES
Industry-standard-compatible pinout
High current drive capability
Precise threshold shutdown comparator
UVLO with hysteresis
Overtemperature warning signal
Overtemperature shutdown
3.3 V-compatible inputs
Rise time and fall time: 10 ns typical at 2.2 nF load
Fast propagation delay
Matched propagation delays between channels
Supply voltage: 9.5 V to 18 V
Dual outputs can be operated in parallel
(ADP3629/ADP3630)
Rated from −40°C to +85°C ambient temperature
8-lead SOIC_N and 8-lead MSOP
The ADP3629/ADP3630/ADP3631 are dual, high current, high
speed drivers, capable of driving two independent N-channel
power MOSFETs. The ADP3629/ADP3630/ADP3631 use the
industry-standard footprint but add high speed switching per-
formance and improved system reliability.
The ADP3629/ADP3630/ADP3631 have an internal temperature
sensor and provide two levels of overtemperature protection: an
overtemperature warning and an overtemperature shutdown at
extreme junction temperatures.
The SD function, generated from a precise internal comparator,
provides fast system enable or shutdown. This feature allows
redundant overvoltage protection, complementing the protec-
tion inside the main controller device, or provides safe system
shutdown in the event of an overtemperature warning.
The wide input voltage range allows the driver to be compatible
with both analog and digital PWM controllers.
APPLICATIONS
AC-to-DC switch mode power supplies
DC-to-DC power supplies
Synchronous rectification
Motor drives
Digital power controllers are supplied from a low voltage supply,
and the driver is supplied from a higher voltage supply. The
ADP3629/ADP3630/ADP3631 add UVLO and hysteresis func-
tions, allowing safe startup and shutdown of the higher voltage
supply when used with low voltage digital controllers.
FUNCTIONAL BLOCK DIAGRAM
V
DD
ADP3629/ADP3630/ADP3631
8
OTW
1
SD
OVERTEMPERATURE
PROTECTION
V
V
DD
EN
NONINVERTING
2
3
4
INA,
INA
7
OUTA
INVERTING
PGND
6
5
UVLO
VDD
NONINVERTING
INB,
INB
OUTB
INVERTING
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADP3629/ADP3630/ADP3631
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuit ...................................................................................... 10
Theory of Operation ...................................................................... 11
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
INA
INB
, and SD).. 11
Input Drive Requirements (INA,
, INB,
Low-Side Drivers (OUTA, OUTB).......................................... 11
Shutdown (SD) Function .......................................................... 11
Overtemperature Protections ................................................... 12
Supply Capacitor Selection ....................................................... 12
PCB Layout Considerations...................................................... 12
Parallel Operation ...................................................................... 12
Thermal Considerations............................................................ 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
9/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADP3629/ADP3630/ADP3631
SPECIFICATIONS
VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted.1
Table 1.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
SUPPLY
Supply Voltage Range
Supply Current
VDD
IDD
9.5
18
3
V
mA
No switching, INA, INA, INB, and INB
disabled
SD = 5 V
1.2
1.2
Standby Current
UVLO
ISBY
3
mA
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Hysteresis
VUVLO_ON
VDD rising, TA = 25°C
8.0
7.0
8.7
7.7
1.0
9.5
8.5
V
V
V
VUVLO_OFF VDD falling, TA = 25°C
DIGITAL INPUTS (INA, INA, INB, INB, SD)
Input Voltage High
Input Voltage Low
Input Current
VIH
VIL
IIN
2.0
V
V
μA
V
V
V
mV
μA
0.8
0 V < VIN < VDD
−20
1.19
1.21
0.95
240
+20
1.38
1.35
1.05
320
SD Threshold High
VSD_H
1.28
1.28
1.0
280
6
TA = 25°C
TA = 25°C
TA = 25°C
SD Threshold Low
SD Hysteresis
VSD_L
VSD_HYST
Internal Pull-Up/Pull-Down Current
OUTPUTS (OUTA, OUTB)
Output Resistance, Unbiased
Peak Source Current
Peak Sink Current
VDD = PGND
See Figure 20
See Figure 20
80
2
−2
kΩ
A
A
SWITCHING TIME
OUTA, OUTB Rise Time
OUTA, OUTB Fall Time
OUTA, OUTB Rising Propagation Delay tD1
OUTA, OUTB Falling Propagation Delay
SD Propagation Delay Low
SD Propagation Delay High
Delay Matching Between Channels
OVERTEMPERATURE PROTECTION
Overtemperature Warning Threshold
tRISE
tFALL
CLOAD = 2.2 nF, see Figure 3 and Figure 4
CLOAD = 2.2 nF, see Figure 3 and Figure 4
CLOAD = 2.2 nF, see Figure 3 and Figure 4
CLOAD = 2.2 nF, see Figure 3 and Figure 4
See Figure 2
10
10
14
22
32
48
2
25
25
30
35
45
75
ns
ns
ns
ns
ns
ns
ns
tD2
tdL_SD
tdH_SD
See Figure 2
TW
See Figure 6
See Figure 6
See Figure 6
See Figure 6
120
150
135
165
30
150
180
°C
°C
°C
°C
V
Overtemperature Shutdown Threshold TSD
Temperature Hysteresis for Shutdown
Temperature Hysteresis for Warning
Overtemperature Warning Low
THYS_SD
THYS_W
VOTW_OL
10
Open drain, −500 μA
0.4
1 All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.
Rev. 0 | Page 3 of 16
ADP3629/ADP3630/ADP3631
TIMING DIAGRAMS
SD
tdL_SD
tdH_SD
90%
OUTA,
OUTB
10%
Figure 2. Shutdown Timing Diagram
INA,
INB
V
IH
V
IL
tD1
tRISE
tD2 tFALL
90%
90%
OUTA,
OUTB
10%
10%
Figure 3. Output Timing Diagram (Noninverting)
V
IL
V
IH
INA,
INB
tD1
tRISE
tD2 tFALL
90%
90%
OUTA,
OUTB
10%
10%
Figure 4. Output Timing Diagram (Inverting)
V
UVLO_ON
V
V
UVLO_OFF
DD
UVLO MODE
OUTPUTS DISABLED
NORMAL OPERATION
UVLO MODE
OUTPUTS DISABLED
Figure 5. UVLO Function
Rev. 0 | Page 4 of 16
ADP3629/ADP3630/ADP3631
T
SD
TSD – THYS_SD
T
W
TW – THYS_W
T
J
NORMAL OPERATION
OT WARNING
OT SHUTDOWN
OT WARNING
NORMAL OPERATION
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OTW
Figure 6. Overtemperature Warning and Shutdown
Rev. 0 | Page 5 of 16
ADP3629/ADP3630/ADP3631
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
θJA is specified for a device soldered in a 4-layer circuit board
and is measured per JEDEC standards JESD51-2, JESD51-5,
and JESD51-7.
Parameter
Rating
VDD
OUTA, OUTB
−0.3 V to +20 V
DC
<200 ns
INA, INA, INB, INB, SD
ESD
Human Body Model (HBM)
−0.3 V to VDD + 0.3 V
−2 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Table 3. Thermal Resistance
Package Type
8-Lead SOIC_N
8-Lead MSOP
θJA
Unit
°C/W
°C/W
110.6
162.2
3.5 kV
Field Induced Charged Device
Model (FICDM)
SOIC_N
1.5 kV
ESD CAUTION
MSOP
1.0 kV
Junction Temperature Range
Storage Temperature Range
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
−40°C to +150°C
−65°C to +150°C
300°C
215°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 16
ADP3629/ADP3630/ADP3631
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SD
INA
1
2
3
4
8
7
6
5
OTW
OUTA
VDD
ADP3629
PGND
INB
TOP VIEW
(Not to Scale)
OUTB
Figure 7. ADP3629 Pin Configuration
Table 4. ADP3629 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
8
SD
INA
Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
Inverting Input Pin for Channel A Gate Driver.
Ground. This pin should be closely connected to the source of the power MOSFET.
Inverting Input Pin for Channel B Gate Driver.
Output Pin for Channel B Gate Driver.
Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor.
Output Pin for Channel A Gate Driver.
PGND
INB
OUTB
VDD
OUTA
OTW
Overtemperature Warning Flag. Open drain, active low.
SD
INA
1
2
3
4
8
7
6
5
OTW
OUTA
VDD
ADP3630
PGND
INB
TOP VIEW
(Not to Scale)
OUTB
Figure 8. ADP3630 Pin Configuration
Table 5. ADP3630 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
8
SD
INA
Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
Input Pin for Channel A Gate Driver.
Ground. This pin should be closely connected to the source of the power MOSFET.
Input Pin for Channel B Gate Driver.
Output Pin for Channel B Gate Driver.
Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor.
Output Pin for Channel A Gate Driver.
PGND
INB
OUTB
VDD
OUTA
OTW
Overtemperature Warning Flag. Open drain, active low.
SD
INA
1
2
3
4
8
7
6
5
OTW
OUTA
VDD
ADP3631
PGND
INB
TOP VIEW
(Not to Scale)
OUTB
Figure 9. ADP3631 Pin Configuration
Table 6. ADP3631 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
8
SD
INA
Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
Inverting Input Pin for Channel A Gate Driver.
Ground. This pin should be closely connected to the source of the power MOSFET.
Input Pin for Channel B Gate Driver.
Output Pin for Channel B Gate Driver.
Power Supply Voltage. Bypass this pin to PGND with a 1 μF to 5 μF ceramic capacitor.
Output Pin for Channel A Gate Driver.
PGND
INB
OUTB
VDD
OUTA
OTW
Overtemperature Warning Flag. Open drain, active low.
Rev. 0 | Page 7 of 16
ADP3629/ADP3630/ADP3631
TYPICAL PERFORMANCE CHARACTERISTICS
25
20
15
10
5
9
V
UVLO_ON
8
V
UVLO_OFF
7
6
5
4
3
tFALL
tRISE
0
0
5
10
(V)
15
20
–50
–30
–10
10
30
50
70
90
110
130
130
130
V
TEMPERATURE (°C)
DD
Figure 10. UVLO vs. Temperature
Figure 13. Rise and Fall Times vs. VDD
14
70
60
50
40
30
20
10
0
12
10
8
tFALL
tdH_SD
tRISE
tdL_SD
6
tD2
tD1
4
2
0
–50
–30
–10
10
30
50
70
90
110
0
5
10
DD
15
20
TEMPERATURE (°C)
V
(V)
Figure 11. Rise and Fall Times vs. Temperature
Figure 14. Propagation Delay vs. VDD
60
50
40
30
20
10
0
1400
1200
1000
800
V
= 12V
DD
tdH_SD
V
V
SD_H
SD_L
tdL_SD
600
tD2
tD1
400
V
SD_HYST
200
0
–50
–50
–30
–10
10
30
50
70
90
110
–30
–10
10
30
50
70
90
110
130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Propagation Delay vs. Temperature
Figure 15. Shutdown Threshold vs. Temperature
Rev. 0 | Page 8 of 16
ADP3629/ADP3630/ADP3631
OUTA/OUTB
OUTA/OUTB
2
2
INA/INB
INA/INB
V
= 12V
V
= 12V
DD
DD
1
1
TIME = 20ns/DIV
TIME = 20ns/DIV
Figure 16. Typical Rising Propagation Delay (Noninverting)
Figure 18. Typical Rise Time (Noninverting)
OUTA/OUTB
OUTA/OUTB
2
2
INA/INB
INA/INB
V
= 12V
DD
TIME = 20ns/DIV
1
V
= 12V
1
DD
TIME = 20ns/DIV
Figure 17. Typical Falling Propagation Delay (Noninverting)
Figure 19. Typical Fall Time (Noninverting)
Rev. 0 | Page 9 of 16
ADP3629/ADP3630/ADP3631
TEST CIRCUIT
ADP3629/ADP3630/ADP3631
OTW
8
1
SD
SCOPE
PROBE
NONINVERTING
INA,
INA
A
OUTA
2
7
INVERTING
V
DD
PGND
VDD
3
4
6
5
4.7µF
CERAMIC
100nF
CERAMIC
NONINVERTING
C
LOAD
B
INB,
INB
OUTB
INVERTING
Figure 20. Test Circuit
Rev. 0 | Page 10 of 16
ADP3629/ADP3630/ADP3631
THEORY OF OPERATION
The ADP3629/ADP3630/ADP3631 family of dual drivers is
optimized for driving two independent enhancement N-channel
MOSFETs or insulated gate bipolar transistors (IGBTs) in high
switching frequency applications.
LOW-SIDE DRIVERS (OUTA, OUTB)
The ADP3629/ADP3630/ADP3631 family of dual drivers is
designed to drive ground referenced N-channel MOSFETs. The
bias is internally connected to the VDD supply and to PGND.
These applications require high speed, fast rise and fall times, and
short propagation delays. The capacitive nature of MOSFETs and
IGBTs requires high peak current capability, as well.
When the ADP3629/ADP3630/ADP3631 are disabled, both
low-side gates are held low. An internal impedance is present
between the OUTA/OUTB pins and GND, even when VDD is
not present; this feature ensures that the power MOSFET is
normally off when bias voltage is not present.
ADP3629/ADP3630/ADP3631
8
1
OTW
SD
V
DS
NONINVERTING
When interfacing the ADP3629/ADP3630/ADP3631 to exter-
nal MOSFETs, the designer should consider ways to create a
robust design that minimizes stresses on both the driver and
the MOSFETs. These stresses include exceeding the short time
duration voltage ratings on the OUTA and OUTB pins, as well
as on the external MOSFET.
INA,
INA
A
OUTA
2
7
INVERTING
V
DD
PGND
VDD
3
4
6
5
NONINVERTING
V
DS
B
INB,
INB
Power MOSFETs are usually selected to have low on resistance to
minimize conduction losses, which usually implies a large input
gate capacitance and gate charge.
OUTB
INVERTING
SHUTDOWN (SD) FUNCTION
The ADP3629/ADP3630/ADP3631 feature an advanced shut-
down function with accurate thresholds and hysteresis.
Figure 21. Typical Application Circuit
INPUT DRIVE REQUIREMENTS (INA, INA, INB, INB,
AND SD)
The SD signal is an active high signal. An internal pull-up is
present on this pin and, therefore, it is necessary to pull down
the pin externally for the drivers to operate normally.
The inputs of the ADP3629/ADP3630/ADP3631 are designed
to meet the requirements of modern digital power controllers;
the signals are compatible with 3.3 V logic levels. At the same
In some power systems, it is sometimes necessary to provide an
additional overvoltage protection (OVP) or overcurrent protection
(OCP) shutdown signal to turn off the power devices (MOSFETs
or IGBTs) in case of failure of the main controller.
time, the input structure allows for input voltages as high as VDD
.
INA INB
The signals applied to the inputs (INA,
, INB, and
)
should have steep and clean fronts. It is not recommended that
slow changing signals be applied to drive these inputs because
such signals can result in multiple switching output signals
when the thresholds are crossed, causing damage to the power
MOSFET or IGBT.
An accurate internal reference is used for the SD comparator so
that it can be used to detect OVP or OCP fault conditions.
+
DC
OUTPUT
An internal pull-down resistor is present at the input, which
guarantees that the power device is off in the event that the
input is left floating.
AC
INPUT
–
The SD input has a precision comparator with hysteresis and is
therefore suitable for slow changing signals (such as a scaled-
down output voltage); see the Shutdown (SD) Function section
for more information about this comparator.
OUTA
PGND
SD
V
EN
ADP3629/ADP3630/ADP3631
Figure 22. Shutdown Function Used for Redundant OVP
Rev. 0 | Page 11 of 16
ADP3629/ADP3630/ADP3631
OVERTEMPERATURE PROTECTIONS
PCB LAYOUT CONSIDERATIONS
The ADP3629/ADP3630/ADP3631 provide two levels of over-
temperature protection:
Use the following general guidelines when designing printed
circuit boards (PCBs) for the ADP3629/ADP3630/ADP3631:
OTW
•
•
Overtemperature warning (
)
•
•
•
•
•
Trace out the high current paths and use short, wide
(>40 mil) traces to make these connections.
Minimize trace inductance between the OUTA and OUTB
outputs and the MOSFET gates.
Connect the PGND pin as close as possible to the source of
the MOSFETs.
Place the VDD bypass capacitor as close as possible to the
VDD and PGND pins.
When possible, use vias to other layers to maximize thermal
conduction away from the IC.
Overtemperature shutdown
The overtemperature warning is an open-drain logic signal and
is active low. In normal operation, when no thermal warning is
present, the signal is high, whereas when the warning threshold
is crossed, the signal is pulled low.
3.3V
VDD
OTW
Figure 24 shows an example of the typical layout based on the
preceding guidelines.
FLAGIN
ADP3629/ADP3630/ADP3631
ADP1043
PGND
VDD
OTW
ADP3629/ADP3630/ADP3631
PGND
OTW
Figure 23.
Signaling Scheme Example
OTW
The
open-drain configuration allows the connection
Figure 24. External Component Placement Example
of multiple devices to the same warning bus in a wire-OR’ed
configuration, as shown in Figure 23.
PARALLEL OPERATION
The two driver channels in the ADP3629 and ADP3630 devices
can be combined to operate in parallel to increase drive capability
and minimize power dissipation in the driver.
The overtemperature shutdown turns off the device to protect it
in the event that the die temperature exceeds the absolute maxi-
mum limit of 150°C (see Table 2).
The connection scheme for the ADP3630 is shown in Figure 25.
In this configuration, INA and INB are connected together, and
OUTA and OUTB are connected together.
SUPPLY CAPACITOR SELECTION
A local bypass capacitor for the supply input (VDD) of the
ADP3629/ADP3630/ADP3631 is recommended to reduce the
noise and to supply some of the peak currents that are drawn.
Particular attention must be paid to the layout in this case to
optimize load sharing between the two drivers.
An improper decoupling can dramatically increase the rise times,
cause excessive resonance on the OUTA and OUTB pins, and, in
some extreme cases, even damage the device due to inductive
overvoltage on the VDD or OUTA/OUTB pins.
8
1
OTW
SD
ADP3630
INA
OUTA
2
A
7
The minimum capacitance required is determined by the size of
the gate capacitances being driven, but as a general rule, a 4.7 μF,
low ESR capacitor should be used. Multilayer ceramic chip
(MLCC) capacitors provide the best combination of low ESR
and small size. To further reduce noise, use a smaller ceramic
capacitor (100 nF) with a better high frequency characteristic
in parallel with the main capacitor.
V
DD
PGND
INB
VDD
3
4
6
5
V
DS
OUTB
B
Place the ceramic capacitor as close as possible to the ADP3629/
ADP3630/ADP3631 device and minimize the length of the
traces going from the capacitor to the power pins of the device.
Figure 25. Parallel Operation
Rev. 0 | Page 12 of 16
ADP3629/ADP3630/ADP3631
In all practical applications where the external resistor is in the
order of a few ohms, the contribution of the external resistor
can be ignored, and the extra loss is assumed to be in the driver,
providing a good guard band for the power loss calculations.
THERMAL CONSIDERATIONS
When designing a power MOSFET gate drive, the maximum
power dissipation in the driver must be considered to avoid
exceeding the maximum junction temperature.
In addition to the gate charge losses, there are also dc bias losses
(PDC) due to the bias current of the driver. This current is present
regardless of the switching frequency.
Data on package thermal resistance is provided in Table 3 to
help the designer in this task.
Several equally important aspects must also be considered.
P
DC = VDD × IDD
The total estimated loss is the sum of PDC and PGATE
LOSS = PDC + (n × PGATE
where n is the number of gates driven.
•
•
•
•
•
•
Gate charge of the power MOSFET being driven
Bias voltage value used to power the driver
Maximum switching frequency of operation
Value of external gate resistance
Maximum ambient (and PCB) temperature
Type of package
.
P
)
When the total power loss is calculated, the temperature
increase can be calculated as follows:
All of these factors influence and limit the maximum allowable
power dissipated in the driver.
ΔTJ = PLOSS × θJA
Design Example
The gate of a power MOSFET has a nonlinear capacitance
characteristic. For this reason, although the input capacitance
is usually reported in the MOSFET data sheet as CISS, it is not
useful to calculate power losses.
For example, consider driving two IRFS4310Z MOSFETs with a
VDD of 12 V at a switching frequency of 100 kHz, using an
ADP3630 in the MSOP package.
The maximum PCB temperature considered for this design is 85°C.
From the MOSFET data sheet, the total gate charge is QG = 120 nC.
The total gate charge necessary to turn on a power MOSFET
device is usually reported on the device data sheet under QG.
This parameter varies from a few nanocoulombs (nC) to several
hundreds of nC and is specified at a specific VGS value (10 V
or 4.5 V).
P
P
P
GATE = 12 V × 120 nC × 100 kHz = 144 mW
DC = 12 V × 1.2 mA = 14.4 mW
LOSS = 14.4 mW + (2 × 144 mW) = 302.4 mW
The power necessary to charge and then discharge the gate of a
power MOSFET can be calculated as follows:
The MSOP thermal resistance is 162.2°C/W (see Table 3).
ΔTJ = 302.4 mW × 162.2°C/W = 49.0°C
TJ = TA + ΔTJ = 134.0°C ≤ TJ_MAX
P
GATE = VGS × QG × fSW
where:
This estimated junction temperature does not factor in the
power dissipated in the external gate resistor and, therefore,
provides a certain guard band.
V
GS is the bias voltage powering the driver (VDD).
QG is the total gate charge.
f
SW is the maximum switching frequency.
If a lower junction temperature is required by the design,
the SOIC_N package, which provides a thermal resistance
of 110.6°C/W, can be used. Using the SOIC_N package, the
maximum junction temperature is
The power dissipated for each gate (PGATE) must be multiplied
by the number of drivers (in this case, 1 or 2) being used in each
package; this PGATE value represents the total power dissipated in
charging and discharging the gates of the power MOSFETs.
ΔTJ = 302.4 mW × 110.6°C/W = 33.4°C
TJ = TA + ΔTJ = 118.4°C ≤ TJ_MAX
Not all of this power is dissipated in the gate driver because
part of it is actually dissipated in the external gate resistor, RG.
The larger the external gate resistor, the smaller the amount of
power that is dissipated in the gate driver.
Other options to reduce power dissipation in the driver include
reducing the value of the VDD bias voltage, reducing the switching
frequency, and choosing a power MOSFET with a smaller gate
charge.
In modern switching power applications, the value of the gate
resistor is kept at a minimum to increase switching speed and
to minimize switching losses.
Rev. 0 | Page 13 of 16
ADP3629/ADP3630/ADP3631
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 27. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Ordering
Quantity
Model
Package Description
Branding
L8Q
ADP3629ARZ-R71
ADP3629ARMZ-R71
ADP3630ARZ-R71
ADP3630ARMZ-R71
ADP3631ARZ-R71
ADP3631ARMZ-R71
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
R-8
RM-8
R-8
RM-8
R-8
RM-8
2,500
3,000
2,500
3,000
2,500
3,000
L8R
L8S
1 Z = RoHS Compliant Part.
Rev. 0 | Page 14 of 16
ADP3629/ADP3630/ADP3631
NOTES
Rev. 0 | Page 15 of 16
ADP3629/ADP3630/ADP3631
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08401-0-9/09(0)
Rev. 0 | Page 16 of 16
相关型号：
ADP3633ACPZ-RL
High Speed, Dual, 4 A MOSFET Driver, inverting A/B input pins, 9.5V < Vin < 18V
ADI
ADP3634ARDZ-R7
High Speed, Dual, 4 A MOSFET Driver, non-inverting A/B input pins, 9.5V < Vin < 18V
ADI
©2020 ICPDF网 联系我们和版权申明