ADP3634ARHZ-RL [ADI]
High Speed, Dual, 4 A MOSFET Driver with Thermal Protection; 高速，双通道，4个MOSFET驱动器与过热保护
| 型号： | ADP3634ARHZ-RL |
| 厂家： | 
ADI |
| 描述： | High Speed, Dual, 4 A MOSFET Driver with Thermal Protection |
| 文件： | 总16页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Dual, 4 A MOSFET Driver
with Thermal Protection
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
FEATURES
GENERAL DESCRIPTION
Industry-standard-compatible pinout
High current drive capability
Precise threshold shutdown comparator
UVLO with hysteresis
Overtemperature warning signal
Overtemperature shutdown
The ADP362x/ADP363x is a family of high current and dual high
speed drivers, capable of driving two independent N-channel
power MOSFETs. The family uses the industry-standard foot-
print but adds high speed switching performance and improved
system reliability.
The family has an internal temperature sensor and provides
two levels of overtemperature protection, an overtemperature
warning, and an overtemperature shutdown at extreme junction
temperatures.
3.3 V-compatible inputs
10 ns typical rise time and fall time @ 2.2 nF load
Matched propagation delays between channels
Fast propagation delay
The SD function, generated from a precise internal comparator,
provides fast system enable or shutdown. This feature allows
redundant overvoltage protection, complementing the protec-
tion inside the main controller device, or provides safe system
shutdown in the event of an overtemperature warning.
9.5 V to 18 V supply voltage (ADP3633/ADP3634/ADP3635)
4.5 V to 18 V supply voltage (ADP3623/ADP3624/ADP3625)
Parallelable dual outputs
Rated from −40°C to +85°C ambient temperature
Thermally enhanced packages, 8-lead SOIC_N_EP and
8-lead MINI_SO_EP
The wide input voltage range allows the driver to be compatible
with both analog and digital PWM controllers.
APPLICATIONS
Digital power controllers are supplied from a low voltage
supply, and the driver is supplied from a higher voltage supply.
The ADP362x/ADP363x family adds UVLO and hysteresis
functions, allowing safe startup and shutdown of the higher
voltage supply when used with low voltage digital controllers.
AC-to-dc switch mode power supplies
DC-to-dc power supplies
Synchronous rectification
Motor drives
The device family is available in thermally enhanced SOIC_N_EP
and MINI_SO_EP packaging to maximize high frequency and
current switching in a small printed circuit board (PCB) area.
FUNCTIONAL BLOCK DIAGRAM
V
DD
ADP3623/ADP3624/ADP3625
ADP3633/ADP3634/ADP3635
8
OTW
1
SD
OVERTEMPERATURE
PROTECTION
V
V
DD
EN
NONINVERTING
2
3
4
INA,
INA
7
OUTA
INVERTING
PGND
6
5
UVLO
VDD
NONINVERTING
INB,
INB
OUTB
INVERTING
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Theory of Operation ...................................................................... 12
INA INB
Input Drive Requirements (INA,
, INB,
, and SD).. 12
Low-Side Drivers (OUTA, OUTB) .......................................... 12
Shutdown (SD) Function .......................................................... 12
Overtemperature Protections ................................................... 12
Supply Capacitor Selection ....................................................... 13
PCB Layout Considerations...................................................... 13
Parallel Operation ...................................................................... 13
Thermal Considerations............................................................ 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Timing %JBHSBNT .......................................................
.... ..... 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Test Circuit ...................................................................................... 11
REVISION HISTORY
7/09—Rev. 0 to Rev. A
Added ADP3623, ADP3625, ADP3633, and
Changes to Figure 16 to Figure 19 Captions............................... 10
Changes to Figure 20...................................................................... 11
Changes to Figure 21, Input Drive Requirements (INA,
ADP3635..............................................................................Universal
Changes to Features Section, General Description Section,
and Figure 1....................................................................................... 1
Changes to Table 1............................................................................ 3
Added Figure 4; Renumbered Sequentially .................................. 4
Added Figure 7.................................................................................. 7
Added Table 3; Renumbered Sequentially .................................... 7
Added Figure 9 and Table 5............................................................. 8
Changes to Figure 10........................................................................ 9
INA
INB
, INB,
, and SD) Section, and Figure 22........................ 12
Changes to Figure 23 and Parallel Operation Section............... 13
Changes to Design Example Section ........................................... 14
Changes to Ordering Guide.......................................................... 16
5/09—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
SPECIFICATIONS
VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted.1
Table 1.
Parameter
Symbol Test Conditions/Comments
Min Typ Max Unit
SUPPLY
Supply Voltage Range
VDD
VDD
IDD
ADP3633/ADP3634/ADP3635
ADP3623/ADP3624/ADP3625
No switching, INA, INA, INB, and INB disabled
SD = 5 V
9.5
4.5
18
18
3
V
V
mA
mA
Supply Current
Standby Current
UVLO
1.2
1.2
ISBY
3
Turn-On Threshold Voltage
VUVLO_ON
VUVLO_ON
VDD rising, TA = 25°C, ADP3633/ADP3634/ADP3635
VDD rising, TA = 25°C, ADP3623/ADP3624/ADP3625
8.0
3.8
7.0
3.5
8.7
4.2
7.7
3.9
1.0
0.3
9.5
4.5
8.5
4.3
V
V
V
V
V
V
Turn-Off Threshold Voltage
Hysteresis
VUVLO_OFF VDD falling, TA = 25°C, ADP3633/ADP3634/ADP3635
VUVLO_OFF VDD falling, TA = 25°C, ADP3623/ADP3624/ADP3625
ADP3633/ADP3634/ADP3635
ADP3623/ADP3624/ADP3625
DIGITAL INPUTS (INA, INA, INB, INB, SD)
Input Voltage High
Input Voltage Low
VIH
VIL
2.0
V
V
0.8
Input Current
SD Threshold High
IIN
0 V < VIN < VDD
−20
+20
µA
V
V
V
mV
µA
VSD_H
VSD_H
VSD_L
VSD_HYST
1.19 1.28 1.38
1.21 1.28 1.35
0.95 1.0
TA = 25°C
TA = 25°C
TA = 25°C
SD Threshold Low
SD Hysteresis
Internal Pull-Up/Pull-Down Current
OUTPUTS (OUTA, OUTB)
1.05
320
240
280
6
Output Resistance, Unbiased
Peak Source Current
Peak Sink Current
VDD = PGND
See Figure 20
See Figure 20
80
4
−4
kΩ
A
A
SWITCHING TIME
OUTA, OUTB Rise Time
OUTA, OUTB Fall Time
tRISE
tFALL
tD1
tD2
tdL_SD
tdH_SD
CLOAD = 2.2 nF, see Figure 3 and Figure 4
CLOAD = 2.2 nF, see Figure 3 and Figure 4
CLOAD = 2.2 nF, see Figure 3 and Figure 4
CLOAD = 2.2 nF, see Figure 3 and Figure 4
See Figure 2
10
10
14
22
32
48
2
25
25
30
35
45
75
ns
ns
ns
ns
ns
ns
ns
OUTA, OUTB Rising Propagation Delay
OUTA, OUTB Falling Propagation Delay
SD Propagation Delay Low
SD Propagation Delay High
Delay Matching Between Channels
OVERTEMPERATURE PROTECTION
Overtemperature Warning Threshold
Overtemperature Shutdown Threshold
Temperature Hysteresis for Shutdown
Temperature Hysteresis for Warning
Overtemperature Warning Low
See Figure 2
TW
TSD
THYS_SD
THYS_W
VOTW_OL
See Figure 6
See Figure 6
See Figure 6
See Figure 6
120
150
135
165
30
150
180
°C
°C
°C
°C
V
10
Open drain, −500 µA
0.4
1 All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.
Rev. A | Page 3 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
TIMING %*" ( 3" . 4
SD
tdL_SD
tdH_SD
90%
OUTA,
OUTB
10%
Figure 2. Shutdown Timing Diagram
INA,
INB
V
IH
V
IL
tD1
tRISE
tD2 tFALL
90%
90%
OUTA,
OUTB
10%
10%
Figure 3. Output Timing Diagram (Noninverting)
INA,
INB
V
V
IH
IL
tD1
tRISE
tD2 tFALL
90%
90%
OUTA,
OUTB
10%
10%
Figure 4. Output Timing Diagram (Inverting)
V
UVLO_ON
V
UVLO_OFF
DD
V
UVLO MODE
OUTPUTS DISABLED
NORMAL OPERATION
UVLO MODE
OUTPUTS DISABLED
Figure 5. UVLO Function
Rev. A | Page 4 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
T
SD
TSD THYS_SD
–
T
W
TW THYS_W
–
T
J
NORMAL OPERATION
OT WARNING
OT SHUTDOWN
OT WARNING
NORMAL OPERATION
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OTW
Figure 6. Overtemperature Warning and Shutdown
Rev. A | Page 5 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
Table 2.
Parameter
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
VDD
OUTA, OUTB
DC
<200 ns
INA, INA, INB, INB, and SD
ESD
−0.3 V to +20 V
−0.3 V to VDD + 0.3 V
−2 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
3.5 kV
ESD CAUTION
SOIC_N_EP
MINI_SO_EP
1.5 kV
1.0 kV
θJA, JEDEC 4-Layer Board
SOIC_N_EP1
MINI_SO_EP1
59°C/W
43°C/W
Junction Temperature Range
Storage Temperature Range
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
−40°C to +150°C
−65°C to +150°C
300°C
215°C
260°C
1 θJA is measured per JEDEC standards, JESD51-2, JESD51-5, and JESD51-7, as
appropriate with the exposed pad soldered to the PCB.
Rev. A | Page 6 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SD
1
8 OTW
ADP3623/
ADP3633
TOP VIEW
INA
PGND
INB
2
3
4
7
6
5
OUTA
VDD
(Not to Scale)
OUTB
NOTES
1. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY
CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS
ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE
SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE.
Figure 7. ADP3623/ADP3633 Pin Configuration
Table 3. ADP3623/ADP3633 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
8
SD
INA
Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
Inverting Input Pin for Channel A Gate Driver.
Ground. This pin should be closely connected to the source of the power MOSFET.
Inverting Input Pin for Channel B Gate Driver.
Output Pin for Channel B Gate Driver.
Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor.
Output Pin for Channel A Gate Driver.
PGND
INB
OUTB
VDD
OUTA
OTW
Overtemperature Warning Flag. Open drain, active low.
SD
INA
1
2
3
4
8
7
6
5
OTW
OUTA
VDD
ADP3624/
ADP3634
TOP VIEW
PGND
INB
(Not to Scale)
OUTB
NOTES
1. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY
CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS
ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE
SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE.
Figure 8. ADP3624/ADP3634 Pin Configuration
Table 4. ADP3624/ADP3634 Pin Function Descriptions
Pin No. Mnemonic
Description
1
2
3
4
5
6
7
8
SD
INA
Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
Input Pin for Channel A Gate Driver.
Ground. This pin should be closely connected to the source of the power MOSFET.
Input Pin for Channel B Gate Driver.
Output Pin for Channel B Gate Driver.
Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor.
Output Pin for Channel A Gate Driver.
PGND
INB
OUTB
VDD
OUTA
OTW
Overtemperature Warning Flag. Open drain, active low.
Rev. A | Page 7 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
SD
INA
1
2
3
4
8
7
6
5
OTW
OUTA
VDD
ADP3625/
ADP3635
TOP VIEW
PGND
INB
(Not to Scale)
OUTB
NOTES
1. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY
CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS
ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE
SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE.
Figure 9. ADP3625/ADP3635 Pin Configuration
Table 5. ADP3625/ADP3635 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
7
8
SD
INA
Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
Inverting Input Pin for Channel A Gate Driver.
Ground. This pin should be closely connected to the source of the power MOSFET.
Input Pin for Channel B Gate Driver.
Output Pin for Channel B Gate Driver.
Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor.
Output Pin for Channel A Gate Driver.
PGND
INB
OUTB
VDD
OUTA
OTW
Overtemperature Warning Flag. Open drain, active low.
Rev. A | Page 8 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
TYPICAL PERFORMANCE CHARACTERISTICS
25
20
15
10
5
9
8
7
6
5
4
V
UVLO_ON
V
UVLO_OFF
ADP3633/ADP3634/ADP3635
tFALL
tRISE
ADP3623/ADP3624/ADP3625
V
UVLO_ON
V
UVLO_OFF
0
3
0
5
10
(V)
15
20
–50
–30
–10
10
30
50
70
90
110
130
V
TEMPERATURE (°C)
DD
Figure 13. Rise and Fall Times vs. VDD
Figure 10. UVLO vs. Temperature
70
60
50
40
30
20
10
0
14
12
10
8
tFALL
tdH_SD
tRISE
tdL_SD
6
tD2
tD1
4
2
0
–50
0
5
10
DD
15
20
–30
–10
10
30
50
70
90
110
130
V
(V)
TEMPERATURE (°C)
Figure 11. Rise and Fall Times vs. Temperature
Figure 14. Propagation Delay vs. VDD
60
50
40
30
20
10
0
1400
1200
1000
800
V
= 12V
DD
tdH_SD
SD THRESHOLD HIGH
SD THRESHOLD LOW
tdL_SD
600
tD2
tD1
400
SD THRESHOLD HYSTERESIS
200
0
–50
–50
–30
–10
10
30
50
70
90
110
130
–30
–10
10
30
50
70
90
110
130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Propagation Delay vs. Temperature
Figure 15. Shutdown Threshold vs. Temperature
Rev. A | Page 9 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
OUTA/OUTB
OUTA/OUTB
2
2
INA/INB
= 12V
INA/INB
V
V
= 12V
TIME = 20ns/DIV
DD
DD
1
1
TIME = 20ns/DIV
Figure 16. Typical Rise Propagation Delay (Noninverting)
Figure 18. Typical Rise Time (Noninverting)
OUTA/OUTB
OUTA/OUTB
2
2
INA/INB
INA/INB
V
= 12V
DD
1
V
= 12V
1
DD
TIME = 20ns/DIV
TIME = 20ns/DIV
Figure 17. Typical Fall Propagation Delay (Noninverting)
Figure 19. Typical Fall Time (Noninverting)
Rev. A | Page 10 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
TEST CIRCUIT
ADP3623/ADP3624/ADP3625
ADP3633/ADP3634/ADP3635
OTW
8
1
SD
SCOPE
PROBE
NONINVERTING
INA,
INA
A
OUTA
2
7
INVERTING
V
DD
PGND
VDD
3
4
6
5
4.7µF
CERAMIC
100nF
CERAMIC
NONINVERTING
C
LOAD
B
INB,
INB
OUTB
INVERTING
Figure 20. Test Circuit
Rev. A | Page 11 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
THEORY OF OPERATION
The ADP362x/ADP363x family of dual drivers is optimized for
driving two independent enhancement N-channel MOSFETs or
insulated gate bipolar transistors (IGBTs) in high switching
frequency applications.
this feature ensures that the power MOSFET is normally off
when bias voltage is not present.
When interfacing the ADP362x/ADP363x family to external
MOSFETs, the designer should consider ways to make a robust
design that minimizes stresses on both the driver and the
MOSFETs. These stresses include exceeding the short time
duration voltage ratings on the OUTA and OUTB pins, as well
as the external MOSFET.
These applications require high speed, fast rise and fall times, as
well as short propagation delays. The capacitive nature of the
aforementioned gated devices requires high peak current
capability as well.
ADP3623/ADP3624/ADP3625
ADP3633/ADP3634/ADP3635
Power MOSFETs are usually selected to have a low on resistance
to minimize conduction losses, which usually implies a large
input gate capacitance and gate charge.
8
1
2
OTW
SD
V
DS
NONINVERTING
INA,
INA
A
SHUTDOWN (SD) FUNCTION
OUTA
7
The ADP362x/ADP363x family features an advanced shutdown
function, with accurate threshold and hysteresis.
INVERTING
V
DD
PGND
VDD
3
4
6
5
The SD signal is an active high signal. An internal pull-up is
present on this pin and, therefore, it is necessary to pull down
the pin externally for drivers to operate normally.
NONINVERTING
V
DS
B
INB,
INB
OUTB
In some power systems, it is sometimes necessary to provide an
additional overvoltage protection (OVP) or overcurrent protection
(OCP) shutdown signal to turn off the power devices (MOSFETs
or IGBTs) in case of failure of the main controller.
INVERTING
Figure 21. Typical Application Circuit
An accurate internal reference is used for the SD comparator so
INPUT DRIVE REQUIREMENTS (INA, INA, INB, INB,
AND SD)
that it can be used to detect OVP or OCP fault conditions.
+
The ADP362x/ADP363x family inputs are designed to meet the
requirements of modern digital power controllers; the signals
are compatible with 3.3 V logic levels. At the same time, the
DC
OUTPUT
AC
INPUT
–
input structure allows for input voltages as high as VDD
.
The signals applied to the inputs (INA, , INB, and
)
INA
INB
OUTA
PGND
should have steep and clean fronts. It is not recommended to
apply slow changing signals to drive these inputs because they
can result in multiple switching when the thresholds are
crossed, causing damage to the power MOSFET or IGBT.
SD
V
EN
An internal pull-down resistor is present at the input, which
guarantees that the power device is off in the event that the
input is left floating.
ADP3623/ADP3624/ADP3625
ADP3633/ADP3634/ADP3635
Figure 22. Shutdown Function Used for Redundant OVP
The SD input has a precision comparator with hysteresis and is
therefore suitable for slow changing signals (such as a scaled
down output voltage); see the Shutdown (SD) Function section
for more details on this comparator.
OVERTEMPERATURE PROTECTIONS
The ADP362x/ADP363x family provides two levels of
overtemperature protections:
LOW-SIDE DRIVERS (OUTA, OUTB)
•
•
Overtemperature warning (OTW)
Overtemperature shutdown
The ADP362x/ADP363x family of dual drivers is designed to
drive ground referenced N-channel MOSFETs. The bias is
internally connected to the VDD supply and PGND.
The overtemperature warning is an open-drain logic signal and
is active low. In normal operation, when no thermal warning is
present, the signal is high, whereas when the warning threshold
is crossed, the signal is pulled low.
When the ADP362x/ADP363x family is disabled, both low-side
gates are held low. An internal impedance is present between
the OUTA/OUTB pins and GND, even when VDD is not present;
Rev. A | Page 12 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
3.3V
•
Place the VDD bypass capacitor as close as possible to the
VDD and PGND pins.
VDD
•
Use vias to other layers, when possible, to maximize
thermal conduction away from the IC.
OTW
FLAGIN
Figure 24 shows an example of the typical layout based on the
preceding guidelines.
ADP3623/ADP3624/ADP3625/
ADP3633/ADP3634/ADP3635
ADP1043A
PGND
VDD
OTW
ADP3623/ADP3624/ADP3625/
ADP3633/ADP3634/ADP3635
PGND
OTW
Figure 23.
Signaling Scheme Example
OTW
The
open-drain configuration allows connection of
multiple devices to the same warning bus in a wire-OR’e d
configuration, as shown in Figure 23.
The overtemperature shutdown turns off the device to protect it
in the event that the die temperature exceeds the absolute maxi-
mum limit in Table 2.
Figure 24. External Component Placement Example
Note that the exposed pad of the package is not directly
connected to any pin of the package, but it is electrically and
thermally connected to the die substrate, which is the ground of
the device.
SUPPLY CAPACITOR SELECTION
For the supply input (VDD) of the ADP362x/ADP363x family, a
local bypass capacitor is recommended to reduce the noise and
to supply some of the peak currents that are drawn.
PARALLEL OPERATION
The two driver channels present in the ADP3623/ADP3633 or
ADP3624/ADP3634 devices can be combined to operate in
parallel to increase drive capability and minimize power
dissipation in the driver.
An improper decoupling can dramatically increase the rise
times, cause excessive resonance on the OUTA and OUTB pins,
and, in some extreme cases, even damage the device, due to
inductive overvoltage on the VDD or OUTA/OUTB pins.
The connection scheme for the ADP3624/ADP3634 devices is
shown in Figure 25. In this configuration, INA and INB are
connected together, and OUTA and OUTB are connected
together.
The minimum capacitance required is determined by the size
of the gate capacitances being driven, but as a general rule, a
4.7 µF, low ESR capacitor should be used. Multilayer ceramic
chip (MLCC) capacitors provide the best combination of low
ESR and small size. Use a smaller ceramic capacitor (100 nF)
with a better high frequency characteristic in parallel to the
main capacitor to further reduce noise.
Particular attention must be paid to the layout in this case to
optimize load sharing between the two drivers.
8
1
OTW
SD
ADP3624/ADP3634
Keep the ceramic capacitor as close as possible to the ADP362x/
ADP363x device, and minimize the length of the traces going
from the capacitor to the power pins of the device.
INA
OUTA
2
A
7
V
DD
PCB LAYOUT CONSIDERATIONS
PGND
INB
VDD
3
4
6
5
Use the following general guidelines when designing printed
circuit boards (PCBs):
V
DS
OUTB
B
•
•
•
Trace out the high current paths and use short, wide
(>40 mil) traces to make these connections.
Minimize trace inductance between the OUTA and OUTB
outputs and MOSFET gates.
Connect the PGND pin of the ADP362x/ADP363x device
as closely as possible to the source of the MOSFETs.
Figure 25. Parallel Operation
Rev. A | Page 13 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
In all practical applications where the external resistor is in the
THERMAL CONSIDERATIONS
order of a few ohms, the contribution of the external resistor
can be neglected, and the extra loss is assumed in the driver,
providing a good guard band to the power loss calculations.
When designing a power MOSFET gate drive, the maximum
power dissipation in the driver must be considered to avoid
exceeding maximum junction temperature.
In addition to the gate charge losses, there are also dc bias
losses, due to the bias current of the driver. This current is
present regardless of the switching.
Data on package thermal resistance is provided in Table 2 to
help the designer in this task.
There are several equally important aspects that must be
considered.
P
DC = VDD × IDD
The total estimated loss is the sum of PDC and PGATE
LOSS = PDC + (n × PGATE
where n is the number of gates driven.
.
•
•
•
•
•
•
Gate charge of the power MOSFET being driven
Bias voltage value used to power the driver
Maximum switching frequency of operation
Value of external gate resistance
Maximum ambient (and PCB) temperature
Type of package
P
)
When the total power loss is calculated, the temperature
increase can be calculated as
ΔTJ = PLOSS × θJA
All of these factors influence and limit the maximum allowable
power dissipated in the driver.
Design Example
For example, consider driving two IRFS4310Z MOSFETs with a
The gate of a power MOSFET has a nonlinear capacitance
characteristic. For this reason, although the input capacitance
is usually reported in the MOSFET data sheet as CISS, it is not
useful to calculate power losses.
V
DD of 12 V at a switching frequency of 300 kHz, using an
ADP3624 in the SOIC_N_EP package.
The maximum PCB temperature considered for this design is 85°C.
From the MOSFET data sheet, the total gate charge is QG = 120 nC.
The total gate charge necessary to turn on a power MOSFET
device is usually reported on the device data sheet under QG.
This parameter varies from a few nanocoulombs (nC) to several
hundreds of nC, and is specified at a specific VGS value (10 V
or 4.5 V).
P
P
P
GATE = 12 V × 120 nC × 300 kHz = 432 mW
DC = 12 V × 1.2 mA = 14.4 mW
LOSS = 14.4 mW + (2 × 432 mW) = 878.4 mW
From the MOSFET data sheet, the SOIC_N_EP thermal
resistance is 59°C/W.
The power necessary to charge and then discharge the gate of a
power MOSFET can be calculated as:
ΔTJ = 878.4 mW × 59°C/W = 51.8°C
TJ = TA + ΔTJ = 136.8°C ≤ TJMAX
P
GATE = VGS × QG × fSW
where:
This estimated junction temperature does not factor in the
power dissipated in the external gate resistor and, therefore,
provides a certain guard band.
V
GS is the bias voltage powering the driver (VDD).
QG is the total gate charge.
fSW is the maximum switching frequency.
If a lower junction temperature is required by the design,
the MINI_SO_EP package can be used, which provides a
thermal resistance of 43°C/W, so that the maximum junction
temperature is
The power dissipated for each gate (PGATE) still needs to be multip-
lied by the number of drivers (in this case, 1 or 2) being used
in each package, and it represents the total power dissipated in
charging and discharging the gates of the power MOSFETs.
ΔTJ = 878.4 mW × 43°C/W = 37.7°C
TJ = TA + ΔTJ = 122.7°C ≤ TJMAX
Not all of this power is dissipated in the gate driver because part
of it is actually dissipated in the external gate resistor, RG. The
larger the external gate resistor is, the smaller the amount of
power that is dissipated in the gate driver.
Other options to reduce power dissipation in the driver include
reducing the value of the VDD bias voltage, reducing switching fre-
quency, and choosing a power MOSFET with smaller gate charge.
In modern switching power applications, the value of the gate
resistor is kept at a minimum to increase switching speed and
minimize switching losses.
Rev. A | Page 14 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
OUTLINE DIMENSIONS
FOR PROPER CONNECTION OF
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
2.29 (0.090)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
SECTION OF THIS DATA SHEET.
2.29 (0.090)
8
5
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
TOP VIEW
1
4
BOTTOM VIEW
(PINS UP)
1.27 (0.05)
BSC
0.50 (0.020)
0.25 (0.010)
45°
1.65 (0.065)
1.25 (0.049)
1.75 (0.069)
1.35 (0.053)
1.27 (0.050)
0.40 (0.016)
0.10 (0.004)
MAX
SEATING
PLANE
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.51 (0.020)
0.31 (0.012)
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body (RD-8-1)
Dimensions shown in millimeters and (inches)
3.10
3.00
2.90
2.26
2.16
2.06
8
1
5
4
5.05
4.90
4.75
3.10
3.00
2.90
1.83
1.73
1.63
TOP
VIEW
EXPOSED
PAD
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
BOTTOM VIEW
0.525 BSC
1.10 MAX
0.65 BSC
SECTION OF THIS DATA SHEET.
0.94
0.86
0.78
0.23
0.18
0.13
0.70
0.55
0.40
0.15
0.10
0.05
SEATING
PLANE
8°
0°
0.40
0.33
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA-T
Figure 27. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP]
(RH-8-1)
Dimensions shown in millimeters
Rev. A | Page 15 of 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
ORDERING GUIDE
UVLO
Option Range
Temperature
Package Ordering
Model
Package Description
Option
Quantity
Branding
ADP3623ARDZ-RL1 4.5 V
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
8-Lead Standard Small Outline Package
(SOIC_N_EP), 13“ Tape and Reel
RD-8-1
2,500
ADP3623ARHZ-RL1 4.5 V
8-Lead Mini Small Outline Package (MINI_SO_EP), RH-8-1
13”Tape and Reel
3,000
2,500
P3
ADP3624ARDZ1
ADP3624ARDZ-RL1 4.5 V
ADP3624ARHZ1
4.5 V
4.5 V
8-Lead Standard Small Outline Package
(SOIC_N_EP)
8-Lead Standard Small Outline Package
(SOIC_N_EP), Tape Reel
RD-8-1
RD-8-1
−40°C to +85°C
−40°C to +85°C
8-Lead Mini Small Outline Package (MINI_SO_EP) RH-8-1
P4
P4
ADP3624ARHZ-RL1 4.5 V
ADP3625ARDZ-RL1 4.5 V
ADP3625ARHZ-RL1 4.5 V
ADP3633ARDZ-RL1 9.5 V
ADP3633ARHZ-RL1 9.5 V
8-Lead Mini Small Outline Package (MINI_SO_EP), RH-8-1
Tape Reel
3,000
2,500
3,000
2,500
3,000
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
8-Lead Standard Small Outline Package
(SOIC_N_EP), 13”Tape and Reel
RD-8-1
8-Lead Mini Small Outline Package (MINI_SO_EP), RH-8-1
13”Tape and Reel
P5
L3
8-Lead Standard Small Outline Package
(SOIC_N_EP), 13”Tape and Reel
RD-8-1
8-Lead Mini Small Outline Package (MINI_SO_EP), RH-8-1
13”Tape and Reel
ADP3634ARDZ1
ADP3634ARDZ-RL1 9.5 V
ADP3634ARHZ1
9.5 V
9.5 V
8-Lead Standard Small Outline Package
(SOIC_N_EP)
8-Lead Standard Small Outline Package
(SOIC_N_EP), 13”Tape and Reel
RD-8-1
RD-8-1
2,500
−40°C to +85°C
−40°C to +85°C
8-Lead Mini Small Outline Package (MINI_SO_EP) RH-8-1
L4
L4
ADP3634ARHZ-RL1 9.5 V
ADP3635ARDZ-RL1 9.5 V
ADP3635ARHZ-RL1 9.5 V
8-Lead Mini Small Outline Package (MINI_SO_EP), RH-8-1
13”Tape and Reel
3,000
2,500
3,000
−40°C to +85°C
−40°C to +85°C
8-Lead Standard Small Outline Package
(SOIC_N_EP), 13”Tape and Reel
RD-8-1
8-Lead Mini Small Outline Package (MINI_SO_EP), RH-8-1
13”Tape and Reel
L5
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08132-0-7/09(A)
Rev. A | Page 16 of 16
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