ADP3806JRUZ-12.5R7 [ADI]
High-Frequency Switch Mode Li-Ion Battery Charger; 高频开关模式锂离子电池充电器
| 型号： | ADP3806JRUZ-12.5R7 |
| 厂家： | 
ADI |
| 描述： | High-Frequency Switch Mode Li-Ion Battery Charger |
| 文件： | 总16页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Frequency Switch Mode
Li-Ion Battery Charger
ADP3806
FEATURES
GENERAL DESCRIPTION
Li-Ion Battery Charger
The ADP3806 is a complete Li-Ion battery-charging IC. The
device combines high output voltage accuracy with constant
current control to simplify the implementation of constant-
current, constant-voltage (CCCV) chargers. The ADP3806 is
available in three options: The ADP3806-12.6 guarantees the
final battery voltage selected is 12.6 V or 16.8 V ± 0.6%, the
ADP3806-12.5 guarantees 12.525 V/16.7 V ± 0.6%, and the
ADP3806 is adjustable using two external resistors to set the
battery voltage. The current sense amplifier has rail-to-rail inputs
to accurately operate under low dropout and short-circuit condi-
tions. The charge current is programmable with a dc voltage on
ISET. A second differential amplifier senses the system current
across an external sense resistor and outputs a linear voltage
on the ISYS pin. The bootstrapped synchronous driver allows
the use of two NMOS transistors for lower system cost.
Three Battery Voltage Options
Selectable 12.525 V/16.700 V
Selectable 12.600 V/16.800 V
Adjustable
High End-of-Charge Voltage Accuracy
؎0.4% @ 25؇C
؎0.6% @ 5؇C to 55؇C
؎0.7% @ 0؇C to 85؇C
Programmable Charge Current with Rail-to-Rail
Sensing
System Current Sense with Reverse Input Protection
Soft-Start Charge Current
Undervoltage Lockout
Bootstrapped Synchronous Drive for External NMOS
Programmable Oscillator Frequency
Oscillator SYNC Pin
Low Current Flag
Trickle Charge
APPLICATIONS
Portable Computers
Fast Chargers
FUNCTIONAL BLOCK DIAGRAM
VCC BST
CS+ CS–
SYS+ SYS–
ISYS
DRVH SW DRVL PGND
BOOTSTRAPPED
SYNCHRONOUS
DRIVER
+
–
+
–
AMP1
AMP2
DRVLSD
SD IN DRVLSD
–
+
–
LIMIT
VREF
VREF + VREG
UVLO
+
2.5V
V
BSTREG
TH
BIAS
–
+
–
g
1
+
m
ISET
BAT
LOGIC
CONTROL
SD
SELECT
12.6/16.8
–
2
+
g
m
LC
OSCILLATOR
VREF
ADP3806
AGND
REG
REF
SYNC
CT
COMP
BATSEL
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADP3806–SPECIFICATIONS1
(@ 0؇C £ TA £ 100؇C, VCC = 16 V, unless otherwise noted.)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
BATTERY SENSE INPUT
ADP3806-12.6 V and 16.8 V
ADP3806-12.525 V and 16.7 V
TA = 25∞C, 13 V £ VCC £ 20 V
5∞C £ TA £ 55∞C
VBAT
VBAT
VBAT
RBAT
–0.4
–0.6
–0.7
250
+0.4
+0.6
+0.7
%
%
%
kW
mA
0∞C £ TA £ 85∞C
Input Resistance
Input Current
Part in Operation
Part in Shutdown
350
0.2
IBAT(SD)
1.0
BATTERY SENSE INPUT
ADP3806
VBAT = 2.5 V
TA = 25∞C, 13 V £ VCC £ 20 V
0∞C £ TA £ 85∞C
BATSEL = Open, Part in Operation
BATSEL = 100 kW to GND, Part in Shutdown
VBAT
VBAT
–0.5
–0.7
+0.5
+0.7
1.0
%
%
mA
mA
Input Current Operating
Input Current Shutdown
0.2
0.2
1.0
OSCILLATOR
Maximum Frequency2
Frequency Variation3
CT Charge Current
0% Duty Cycle Threshold
Maximum Duty Cycle Threshold
SYNC Input High
fCT
fCT
ICT
1000
210
125
kHz
kHz
mA
V
V
V
CT = 180 pF
250
150
1.0
2.5
290
175
@ COMP Pin
@ COMP Pin
SYNCH
SYNCL
ISYNC
2.2
SYNC Input Low
SYNC Input Current
0.8
1.0
V
mA
0.2
GATE DRIVE
On Resistance
Rise, Fall Time
Overlap Protection Delay
IL = 10 mA
RON
tr, tf
tOP
6
35
50
10
W
ns
ns
CL = 1 nF, DRVL and DRVH
DRVL Falling to DRVH Rising,
DRVH Falling to DRVL Rising
Part in Shutdown, VSW = 12.6 V
VBST – VSW
SW Bias Current
BST Cap Refresh Threshold
0.2
3.7
1.0
mA
V
CURRENT SENSE AMPLIFIER
Input Common-Mode Range
Input Differential Mode Range
Input Offset Voltage5
Gain5
Input Bias Current
Input Offset Current
Input Bias Current
DRVL Shutdown Threshold
VCS+ and VCS–
VCS
0 V £ VCS(CM) £ VCC
VCS(CM)
VCS(DM)
VCS(VOS)
0.0
0.0
VCC + 0.3
160
V
4
mV
mV
V/V
mA
mA
mA
mV
1.0
25
50
1.0
0.2
48
0 V £ VCS(CM) £ VCC, Part in Operation
0 V £ VCS(CM) £ VCC
Part in Shutdown
VCS(IB)
VCS(IOS)
100
2.0
1.0
Measured between VCS+ and VCS–
VCS(SD
)
SYSTEM CURRENT SENSE6
Input Common-Mode Range
Input Differential Range
Input Offset Voltage
Input Bias Current, SYS+
Input Bias Current, SYS–
Voltage Gain
SYS+ and SYS–, IL = 0 mA, VISYS = 3 V
VSYS(CM)
VSYS(DM)
4.0
0
VCC + 0.3
100
V
(VSYS+) – (VSYS–
)
mV
mV
mA
mA
V/V
V
0.5
200
70
VSYS(DM) = 0 V, VSYS(CM) = 16 V
VSYS(DM) = 0 V, VSYS(CM) = 16 V
10 V £ VSYS(CM) £ VCC + 0.3 V, IL = 100 mA
IL = 1 mA7, VSYS(CM) > 6 V
IB(SYS+)
IB(SYS–)
300
125
51.5
5.0
48.5
0
50
Output Range
VISYS
Limit Output Threshold
Limit Output Voltage
VLIMIT £ 0.2 V, 50 kW Pull-up to 5 V
VISYS > 2.65 V, ISINK = 700 mA
VTH(LIMIT)
VO(LIMIT)
2.3
2.5
0.1
2.7
0.2
V
V
ISET INPUT
Charge Current Programming
Function
Programming Function Accuracy
0.0 V < VISET £ 4.0 V
VISET/VCS
25
±1.0
±10
V/V
%
%
VISET = 4.0 V, 1 V £ VCS(CM) £ 16 V
VISET = 0.50 V, 1 V £ VCS(CM) £ 10 V
5∞C £ TA £ 55∞C, VISET = 206 mV,
VCS(CM) = 5 V and 10 V
–5
–30
–46.7
+5
+30
+33
%
ISET Bias Current
0.0 V £ VISET £ 4.0 V
IB
0.2
1.0
mA
–2–
REV. B
ADP3806
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
BATSEL INPUT
VBAT = 12.6 V
2.0
V
VBAT = 16.8 V
BATSEL Input Current
0.8
5.0
V
mA
0.2
BOOST REGULATOR OUTPUT
Output Voltage
CL = 0.1 mF
VBSTREG
IBSTREG
6.8
3.0
7.0
5.0
7.2
V
mA
Output Current8
ANALOG REGULATOR OUTPUT
Output Voltage
C
L = 10 nF
VREG
IREG
5.8
3.0
6.0
5.0
6.2
V
mA
Output Current8
PRECISION REFERENCE OUTPUT
Output Voltage
VREF
IREF
2.47
0.5
2.5
1.1
2.53
V
mA
Output Current8
SHUTDOWN (SD)
ON
OFF
SDH
SDL
2.0
V
V
mA
0.8
1.0
SD Input Current
0.2
POWER SUPPLY
ON Supply Current
OFF Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
No External Loads, UVLO £ VCC £ 20 V
No External Loads, VCC £ 20 V
Turn On
ISYON
ISYOFF
VUVLO
6.0
1.0
6.0
0.3
8.0
5.0
6.25
0.5
mA
mA
V
5.65
0.1
Turn Off
V
LC OUTPUT
Output Voltage Low
Output Voltage High
High Current Mode9, ISINK = 100 mA
0.1
External
0.4
V
V
Low Current Mode10
OUTPUT REVERSE LEAKAGE
PROTECTION
Leakage Current
VCC = Floating, VBAT = 12.6 V
VCS > 180 mV to COMP < 1 V
VBAT > 120% to COMP < 1 V
IDISCH
1
5
mA
OVERCURRENT COMPARATOR
Overcurrent Threshold
Response Time
VCS(OC)
tOC
180
2
mV
ms
OVERVOLTAGE COMPARATOR
Overvoltage Threshold
Response Time
VBAT(OV)
tOV
120
2
%
ms
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2Guaranteed by design, not tested in production.
3If SYNC function is used, then fSYNC must be greater than fCT but less than 120% of fCT
4VCS = (VCS+) – (VCS–).
.
5Accuracy guaranteed by ISET input, programming function accuracy specification.
6System current sense is active during shutdown.
7Load current is supplied through SYS+ pin.
8Guaranteed output current from 0 to min specified value to maintain regulation.
9VBAT < 93% of final or VCS > 25 mV.
10
V
≥ 93% of final and VCS £ 25 mV.
BAT
Specifications subject to change without notice.
REV. B
–3–
ADP3806
ABSOLUTE MAXIMUM RATINGS*
Operating Ambient Temperature Range . . . . . . 0∞C to 100∞C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115∞C/W
JA
Operating Junction Temperature Range . . . . . . 0∞C to 125∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified all
other voltages are referenced to GND.
Input Voltage (VCC) . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
BAT, CS+, CS– . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
SYS+, SYS– . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V to +25 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
SW to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to +25 V
DRVL to PGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
ISET, BATSEL, SD, SYNC, CT,
LIMIT, ISYS, LC . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V
COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3 V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
ORDERING GUIDE
Battery
Voltage
Package
Description Option
Package Quantity
Model
per Reel
ADP3806JRU-REEL
ADP3806JRU-REEL7
ADP3806JRU-12.5-RL
ADP3806JRUZ-12.5RL*
ADP3806JRU-12.5-R7
ADP3806JRU-12.6-RL
ADP3806JRU-12.6-R7
Adjustable
Adjustable
TSSOP-24
TSSOP-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
2500
1000
2500
2500
1000
2500
1000
12.525 V/16.7 V TSSOP-24
12.525 V/16.7 V TSSOP-24
12.525 V/16.7 V TSSOP-24
12.600 V/16.8 V TSSOP-24
12.600 V/16.8 V TSSOP-24
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3806 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. B
ADP3806
PIN CONFIGURATION
PIN FUNCTION DESCRIPTION(continued)
Pin No. Mnemonic Function
1
2
24
23
22
21
20
19
18
17
VCC
SYS–
SYS+
ISYS
LIMIT
CT
SW
9
REF
2.5 V Precision Reference Output.
Shutdown Control Input.
External Compensation Node.
Low Current Output.
DRVH
BST
3
10
11
12
13
14
SD
4
BSTREG
DRVL
PGND
CS+
COMP
LC
5
ADP3806
TOP VIEW
(Not to Scale)
6
7
SYNC
REG
REF
AGND
BAT
Analog Ground.
8
CS–
Battery Sense Input.
9
16 ISET
2.5 V for ADP3806.
12.525 V/16.7 V for ADP3806-12.5.
12.6 V/16.8 V for ADP3806-12.6.
10
11
12
15
14
13
BATSEL
BAT
SD
COMP
LC
AGND
15
BATSEL
Battery Voltage Sense Input.
High = 3 Cells, Low = 4 Cells.
16
17
18
19
20
ISET
CS–
Charge Current Program Input.
Negative Current Sense Input.
Positive Current Sense Input.
Power Ground.
PIN FUNCTION DESCRIPTION
Pin No. Mnemonic Function
CS+
PGND
DRVL
1
2
3
4
5
6
7
8
VCC
SYS–
SYS+
ISYS
LIMIT
CT
Supply Voltage.
Low Drive Output Switches between
REG and PGND.
Negative System Current Sense Input.
Positive System Current Sense Input.
System Current Sense Output.
System Current Sense Limit Output.
Oscillator Timing Capacitor.
Oscillator Synchronization Pin.
6.0 V Analog Regulator Output.
21
22
23
BSTREG
BST
7.0 V Regulator Output for Boost.
Floating Bootstrap Supply for DRVH.
DRVH
High Drive Output Switches between
SW and BST.
SYNC
REG
24
SW
Buck Switching Node Reference for
DRVH.
REV. B
–5–
ADP3806–Typical Performance Characteristics
30
0.5
0.4
VCC = 16V
T
= 25؇C
VCC = 16V
A
25
20
15
10
5
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
0
20
40
60
C)
80
100
TEMPERATURE (
؇
V
ACCURACY (%)
BAT
TPC 1. VBAT Accuracy Distribution
TPC 4. VREF Accuracy vs. Temperature
0.4
0.3
0.10
0.08
0.06
0.04
0.02
0
VCC = 16V
T = 25؇C
A
0.2
0.1
0
–0.1
–0.02
–0.04
–0.06
–0.08
–0.10
–0.2
–0.3
–0.4
0
20
40
60
80
100
5
10
15
20
TEMPERATURE (؇C)
VCC (V)
TPC 2. VBAT Accuracy vs. Temperature
TPC 5. VREF Accuracy vs. VCC
0.10
0.05
0
6.0
5.6
5.2
4.8
4.4
4.0
NO LOADS
T
= 25؇C
A
T
= 100؇C
A
T
= 0؇C
A
T
= 25؇C
A
–0.05
–0.10
12
10
14
16
18
20
10
12
14
16
18
20
VCC (V)
VCC (V)
TPC 3. VBAT Accuracy vs. VCC
TPC 6. ON Supply Current vs. VCC
–6–
REV. B
ADP3806
6
5
18
16
14
12
10
8
VCC = 16V
= 25
T
؇C
A
VCC = 16V
50k⍀TO 5V
fOSC = 250kHz
T
= 25؇C
A
4
3
2
50k⍀TO 2.5V
6
4
1
0
2
0
0
500
1000
1500
2000
2500
3000
3500
2.0
2.2
2.4
2.6
2.8
3.0
3.2
DRIVER LOAD CAPACITANCE (pF)
V
(V)
ISYS
TPC 7. Supply Current vs. Driver Load Capacitance
TPC 10. VLIMIT vs. VISYS
10
8
1.0
0.8
VCC = 16V
DRIVER SOURCING
DRIVER SINKING
T
= 100؇C
A
6
4
0.6
0.4
0.2
0
T
= 25؇C
A
T
= 0؇C
A
2
0
0
20
40
60
80
100
10.0
12.5
15.0
VCC (V)
17.5
20.0
TEMPERATURE (
؇C)
TPC 8. OFF Supply Current vs. VCC
TPC 11. Driver On Resistance vs. Temperature
600
VCC = 16V
= 25
V
T
= 16V
= 25؇C
CC
DRVH
5V/DIV
T
؇C
A
A
500
400
300
200
100
0
FIGURE 1
DRVL 5V/DIV
200ns/DIV
0
200
400
600
800
CT (pF)
TPC 9. Oscillator Frequency vs. CT
TPC 12. Driver Waveforms
REV. B
–7–
ADP3806
100
95
90
85
80
75
70
100
98
96
94
92
90
88
19V 0؇C
IN
19V 85؇C
IN
VCC = 19V
= 12.4V
V
86
84
BAT
T
= 25؇C
A
FIGURE 1
82
80
2
4
6
8
10
12
14
0.1
1
10
V
(V)
CHARGE CURRENT (A)
BAT
TPC 13. Conversion Efficiency vs. Charge Current
TPC 15. Conversion Efficiency vs. Battery Voltage
at Given Temperatures
96
I
= 2A
94
92
90
88
86
84
82
CHARGE
I
= 3A
CHARGE
VCC = 19V
= 25
T
؇C
A
FIGURE 1
3
4
5
6
7
8
9
10
11 12
13
V
(V)
BAT
TPC 14. Conversion Efficiency vs. Battery Voltage
–8–
REV. B
ADP3806
THEORY OF OPERATION
The synchronous driver provides high efficiency when charging at
high currents. Efficiency is important mainly to reduce the amount
of heat generated in the charger but also to stay within the power
limits of the ac adapter. With the addition of a bootstrapped high
side driver, the ADP3806 drives two external power NMOS
transistors for a simple, lower cost power stage.
The ADP3806 combines a bootstrapped synchronous switching
driver with programmable current control and accurate final
battery voltage control in a constant-current, constant-voltage
(CCCV) Li-Ion battery charger. High accuracy voltage control
is needed to safely charge Li-Ion batteries, which are typically
specified at 4.2 V ± 1% per cell. For a typical notebook computer
battery pack, three or four cells are in series giving a total volt-
age of 12.6 V or 16.8 V. The ADP3806 is available in three
versions, a selectable 12.525 V/16.7 V output, a selectable
12.6 V/16.8 V output, and an adjustable output. The adjustable
output can be programmed for a wide range of battery voltages
using two external precision resistors.
The ADP3806 also provides an uncommitted current sense
amplifier. This amplifier provides an analog output pin for
monitoring the current through an external sense resistor. The
amplifier can be used anywhere in the system that high side
current sensing is needed.
Charge Current Control
AMP1 in Figure 1 has a differential input to amplify the voltage
drop across an external sense resistor RCS. The input common-
mode range is from ground to VCC, allowing current control in
short circuit and low dropout conditions. The gain of AMP1 is
internally set to 25 V/V for low voltage drop across the sense
resistor. During CC mode, gm1 forces the voltage at the output
of AMP1 to be equal to the external voltage at the ISET pin.
By choosing RCS and VISET appropriately, a wide range of
charge currents can be programmed.
Another requirement for safely charging Li-Ion batteries is
accurate control of the charge current. The actual charge cur-
rent depends on the number of cells in parallel within the
battery pack. Typically, this is in the range of 2 A to 3 A. The
ADP3806 provides flexibility in programming the charge cur-
rent over a wide range. An external resistor is used to sense the
charge current and this voltage is compared to a dc input volt-
age. This programmability allows the current to be changed
during charging. For example, the charge current can be reduced
for trickle charging.
VREF
ICHARGE
=
(1)
25 ¥ RCS
R
SS
10m⍀
SYSTEM
DC/DC
1/2 Q1
FD56990A
R
L1
CS
40m⍀
VIN
22H
+
–
+
R13
10⍀
C15
22F
1/2 Q1
FD56990A
R3
249⍀
R4
249⍀
R1
2.2⍀
R2
2.2⍀
C16
BATTERY
12.6V/16.8V
–
22F
C13
22nF
C14
2.2F
C1
470nF
C2
470nF
C9
100nF
ISYS
DRVH SW DRVL PGND
SYS–
VCC
CS+
CS–
SYS+
BST
BOOTSTRAPPED
SYNCHRONOUS
DRIVER
–
+
–
+
AMP2
AMP1
SD
IN DRVLSD
DRVLSD
*R11
412k⍀
–
+
–
LIMIT
0.1%
VREF
VREF +VREG
UVLO
+
VTH
BSTREG
7.0V
2.5V
BIAS
C10
–
ISET
BAT
g
1
+
–
0.1F
m
+
SD
LOGIC
CONTROL
SELECT
12.6/16.8
–
LC
g
2
m
+
OSCILLATOR
VREF
**R7
100k⍀
ADP3806
COMP
C8
0.22F
REF
2.5V
SYNC
CT
REG
6.0V
BATSEL
AGND
*R12
102k⍀
0.1%
C7
200pF
C6
180pF
R8
56⍀
*R14
0⍀
R5
6.81k⍀
C17
100nF
R6
7.5k⍀
*ADP3806-12.6, ADP3806-12.5: R11 = SHORT, R12 = OPEN;
ADP3806, R11 = 412k⍀, R12 = 102k⍀, R14 = OPEN.
**R7, OPEN IF LC FUNCTION IS NOT USED.
Figure 1. Typical Application
–9–
REV. B
ADP3806
Typical values of RCS range from 25 mW to 50 mW, and the
input range of ISET is from 0 V to 4 V. If, for example, a 3 A
charger is required, RCS could be set to 40 mW and VISET = 3 V.
The power dissipation in RCS should be kept below 500 mW.
In this example, the power is a maximum of 360 mW. Once
RCS has been chosen, the charge current can be adjusted during
operation with VISET. Lowering VISET to 125 mV gives a charge
current of 125 mA for trickle charging. Components R3, R4,
and C13 provide high frequency filtering for the current
sense signal.
The reference and internal resistor divider are referenced to the
AGND pin, which should be connected close to the negative
terminal of the battery to minimize sensing errors.
In contrast, the ADP3806 requires external, precision resistors.
The divider ratio should be set to divide the desired final voltage
down to 2.5 V at the BAT pin
R11 VBATTERY
=
– 1
(2)
R12
2.5V
These resistors should have a parallel impedance of approximately
80 kW to minimize bias current errors. When the ADP3806 is in
shutdown, an internal switch disconnects the BAT pin as shown
in Figure 2. This disconnects the resistor, R11, from the battery
and minimizes leakage. The resistance of the internal switch is
less than 200 W.
Final Battery Voltage Control
As the battery approaches its final voltage, the ADP3806 switches
from CC mode to CV mode. The change is achieved by the
common output node of gm1 and gm2. Only one of the two
outputs controls the voltage at the COMP pin. Both amplifiers
can only pull down on COMP, such that when either amplifier
has a positive differential input voltage, its output is not active.
For example, when the battery voltage, VBAT, is low, gm2 does
not control VCOMP. When the battery voltage reaches the desired
final voltage, gm2 takes control of the loop, and the charge cur-
rent is reduced.
ADP3806
R11
412k⍀
0.1%
SD
BAT
BATTERY
g
2
m
V
REF
Amplifier gm2 compares the battery voltage to the internal refer-
ence voltage of 2.5 V. In the case of the ADP3806-12.5 and
ADP3806-12.6, an internal resistor divider sets the selectable
final battery voltage.
BATSEL
R12
102k⍀
0.1%
Figure 2. Battery Sense Disconnect Circuit
Oscillator and PWM
The oscillator generates a triangle waveform between 1 V and
2.5 V, which is compared to the voltage at the COMP pin,
setting the duty cycle of the driver stage. When VCOMP is below
1 V, the duty cycle is zero. Above 2.5 V, the duty cycle reaches
its maximum.
When BATSEL is high, the final battery voltage is set to three
cells (12.6 V or 12.525 V). BATSEL can be tied to REG for
this state. When BATSEL is tied to ground, VBAT equals four
cells (16.8 V or 16.7 V). BATSEL has a 2 mA pull-up current as
a fail-safe to select three cells when it is left open.
BSTREG
ADP3806
BOOTSTRAPPED
SYNCHRONOUS DRIVER
BST
CMP3
CBST
MIN
OFF
IN
DRVH
Q1
TIME
+
–
SD
SW
–
CMP2
+
DELAY
DELAY
1V
DRVL
Q2
–
CMP1
+
PGND
1V
DRVLSD
Figure 3. Bootstrapped Synchronous Driver
–10–
REV. B
ADP3806
The oscillator frequency is set by the external capacitor at the
CT pin and the internal current source of 150 mA according to
the following formula:
The driver stage monitors the voltage across the BST capacitor
with CMP3. When this voltage is less than 4 V, CMP3 forces a
minimum offtime of 200 ns. This ensures that the BST capacitor is
charged even during DRVLSD. However, because a minimum
off time is only forced when needed, the maximum duty cycle is
greater than 99%.
150 mA
fOSC
=
(3)
2.2 ¥Cr ¥1.5V
A 180 pF capacitor sets the frequency to 250 kHz. The frequency
can also be synchronized to an external oscillator by applying a
square wave input on SYNC. The SYNC function is designed
to allow increases only in the oscillator frequency. The fSYNC
should be no more than 20% higher than fOSC. The duty cycle
of the SYNC input is not important and can be anywhere
between 5% and 95%.
2.5 V Precision Reference
The voltage at the BAT pin is compared to an internal preci-
sion, low temperature drift reference of 2.5 V. The reference is
available externally at the REF pin. This pin should be bypassed
with a 100 pF capacitor to the analog ground pin, AGND. The
reference can be used as a precision voltage externally. How-
ever, the current draw should not be greater than 100 mA, and
noisy, switching type loads should not be connected.
7 V Bootstrap Regulator
The driver stage is powered by the internal 7 V bootstrap regu-
lator, which is available at the BSTREG pin. Because the
switching currents are supplied by this regulator, decoupling
must be added. A 0.1 mF capacitor should be placed close to the
ADP3806, with the ground side connected close to the power
ground pin, PGND. This supply is not recommended for use
externally due to high switching noise.
6 V Regulator
The 6 V regulator supplies power to most of the analog circuitry
on the ADP3806. This regulator should be bypassed to AGND
with a 0.1 mF capacitor. This reference has a 3 mA source capa-
bility to power external loads if needed.
LC
The ADP3806 provides a low current (LC) logic output to signal
when the current sense voltage (VCS) is below a fixed threshold
and the battery voltage is greater than 95%. LC is an open-drain
output that is pulled low when VCS is above the threshold. When
the low current threshold condition is reached, LC is pulled
high by an external resistor to REF or another appropriate pull-up
voltage. To determine when LC goes low, an internal compara-
tor senses when the current falls below 12.5% of full scale (20 mV
across the CS pins). The comparator has hysteresis to prevent
oscillation around the trip point.
Bootstrapped Synchronous Driver
The PWM comparator controls the state of the synchronous
driver shown in Figure 3. A high output from the PWM com-
parator forces DRVH on and DRVL off. The drivers have an on
resistance of approximately 6 W for fast rise and fall times when
driving external MOSFETs. Furthermore, the bootstrapped
drive allows an external NMOS transistor for the main switch
instead of a PMOS. An external boost diode should be con-
nected between BSTREG and BST, and a boost capacitor of
0.1 mF must be added externally between BST and SW. The
voltage between BST and SW is typically 6.5 V.
To prevent false triggering (such as during soft-start), the com-
parator is only enabled when the battery voltage is within 5% of
its final voltage. As the battery is charging up, the comparator
will not go low even if the current falls below 12.5% as long as
the battery voltage is below 95% of full scale. Once the battery
has risen above 95%, the comparator is enabled. This pin can
be used to indicate the end of the charge process.
The DRVL pin switches between BSTREG and PGND. The 7 V
output of BSTREG drives the external NMOS with high VGS
to lower the on resistance. PGND should be connected close to
the source pin of the external synchronous NMOS. When DRVL
is high, this turns on the lower NMOS and pulls the SW node
to ground. At this point, the boost capacitor is charged up through
the boost diode. When the PWM switches high, DRVL is turned
off and DRVH turns on. DRVH switches between BST and
SW. When DRVH is on, the SW pin is pulled up to the input
supply (typically 16 V), and BST rises above this voltage by
approximately 6.5 V.
System Current Sense
An uncommitted differential amplifier is provided for additional
high side current sensing. This amplifier, AMP2, has a fixed
gain of 50 V/V from the SYS+ and SYS– pins to the analog
output at ISYS. ISYS has a 1 mA source capability to drive an
external load. The common-mode range of the input pins is
from 4 V to VCC. This amplifier is the only part of the ADP3806
that remains active during shutdown. The power to this block is
derived from the bias current on the SYS+ and SYS– pins.
Overlap protection is included in the driver to ensure that both
external MOSFETs are not on at the same time. When DRVH
turns off the upper MOSFET, the SW node goes low due to the
inductor current. The ADP3806 monitors the SW voltage, and
DRVL goes high to turn on the lower MOSFET when SW goes
below 1 V. When DRVL turns off, an internal timer adds a
delay of 50 ns before turning DRVH on.
A separate comparator at the LIMIT pin signals when the voltage
on the ISYS pin exceeds 2.5 V typically. The internal compara-
tor has an open-drain output, which produces the function
shown in the TPC 10 graph of VLIMIT versus VISYS. The LIMIT
pin should be externally pulled up to 5 V, 2.5 V, or some other
voltage as needed through a resistor. This graph was taken with
a 50 kW pull-up resistor to 5 V and to 2.5 V. When ISYS is
below 2.4 V, the LIMIT pin has high output impedance. The
open-drain output is capable of sinking 700 mA when the thresh-
old is exceeded. This comparator is turned off during shutdown
to conserve power.
When the charge current is low, the DRVLSD comparator
signals the driver to turn off the low side MOSFET and DRVL
is held low. As shown in Figure 1, the DRVLSD comparator
looks at the output of AMP1. The DRVLSD threshold is set to
1.2 V, corresponding to 48 mV differential voltage between the
CS pins.
REV. B
–11–
ADP3806
Shutdown
APPLICATION INFORMATION
A high impedance CMOS logic input is provided to turn off the
ADP3806. When the voltage on SD is less than 0.8 V, the
ADP3806 is placed in low power shutdown. With the exception
of the system current sense amplifier, AMP2, all other circuitry
is turned off. The reference and regulators are pulled to ground
during shutdown and all switching is stopped. During this state,
the supply current is less than 5 mA. Also, the BAT, CS+, CS–,
and SW pins go to high impedance to minimize current drain
from the battery.
Design Procedure
Refer to Figure 1, the typical application circuit, for the follow-
ing description. The design follows that of a buck converter.
With Li-Ion cells it is important to have a regulator with accu-
rate output voltage control.
Battery Voltage Settings
The ADP3806 has three options for voltage selection:
1. 12.525 V/16.7 V as selectable fixed voltages
2. 12.6 V/16.8 V as selectable fixed voltages
3. Adjustable
UVLO
Undervoltage lock-out, UVLO, is included in the ADP3806 to
ensure proper startup. As VCC rises above 1 V, the reference
and regulators will track VCC until they reach their final volt-
ages. However, the rest of the circuitry is held off by the UVLO
comparator. The UVLO comparator monitors both regulators
to ensure that they are above 5 V before turning on the main
charger circuitry. This occurs when VCC reaches 6 V. Monitor-
ing the regulator outputs makes sure that the charger circuitry
and driver stage have sufficient voltage to operate normally. The
UVLO comparator includes 300 mV of hysteresis to prevent
oscillations near the threshold.
When using the fixed versions, R11 should be a short or 0 W
wire jumper and R12 should be an open circuit. When using the
adjustable version, the following equation gives the ratio of the
two resistors:
R11 ÊVBAT
ˆ
=
Á
– 1
(5)
˜
¯
Ë
R12
2.5
Often 0.1% resistors are required to maintain the overall accu-
racy budget in the design.
Inductor Selection
Startup Sequence
Usually the inductor is chosen based on the assumption that the
inductor ripple current is ±15% of the maximum output dc
current at maximum input voltage. As long as the inductor used
has a value close to this, the system should work fine. The final
choice affects the trade-offs between cost, size, and efficiency.
For example, the lower the inductance, the size is smaller but
ripple current is higher. This situation, if taken too far, will lead
to higher ac losses in the core and the windings. Conversely, a
higher inductance results in lower ripple current and smaller
output filter capacitors, but the transient response will be slower.
With these considerations, the required inductance can be
found from
During a startup from either SD going high or VCC exceeding
the UVLO threshold, the ADP3806 initiates a soft-start sequence.
The soft-start timing is set by the compensation capacitor at the
COMP pin and an internal 40 mA source. Initially, both DRVH
and DRVL are held low until VCOMP reaches 1 V. This delay
time is set by
CCOMP ¥1V
tDELAY
=
(4)
40 mA
For a 0.22 mF COMP capacitor, tDELAY is 5 ms. After this initial
delay, the duty cycle is very low and then ramps up to its final
value with the same ramp rate given for tDELAY. For example, if
VIN is 16 V and the battery is 10 V when charging is started, the
duty cycle will be approximately 65%, corresponding to a VCOMP
of ~2 V. The time for the duty cycle to ramp from 0% at VCOMP
= 1 V to 65% at VCOMP = 2 V is approximately 5 ms. Because
the charge current is equal to zero at first, DRVLSD is active
and DRVL will not turn on. However, if the BST capacitor is
discharged, DRVL will be forced on for a minimum on time
of 200 ns each clock period until the BST capacitor is charged
to greater than 4 V. Typically the BST capacitor is charged in five
to ten clock cycles.
VIN, MAX –VBAT
L1=
¥ DMIN ¥TS
(6)
DI
where the maximum input voltage VIN, MAX is used with the
minimum duty ratio DMIN. The duty ratio is defined as the ratio
of the output voltage to the input voltage, VBAT/VIN. The ripple
current is found from
(7)
DI = 0.3¥ IBAT, MAX
the maximum peak-to-peak ripple is 30%, that is 0.3, and maxi-
mum battery current, IBAT, MAX, is used.
Loop Feed Forward
For example, with VIN, MAX = 19 V, VBAT = 12.6 V, IBAT,MAX
=
As the startup sequence discussion shows, the response time at
COMP is slowed by the large compensation capacitor. To speed
up the response, two comparators can quickly feed forward around
the normal control loop and pull the COMP node down to limit
any overshoot in either short-circuit or overvoltage conditions.
The overvoltage comparator has a trip point set to 20% higher
than the final battery voltage. The overcurrent comparator thresh-
old is set to 180 mV across the CS pins, which is 15% above the
maximum programmable threshold. When these comparators
are tripped, a normal soft-start sequence is initiated. The over-
voltage comparator is valuable when the battery is removed
during charging. In this case, the current in the inductor causes
the output voltage to spike up, and the comparator limits the
maximum voltage. Neither of these comparators affects the loop
under normal charging conditions.
3A, and TS = 4 ms, the value of L1 is calculated as 18.9 mH.
Choosing the closest standard value gives L1 = 22 mH.
Output Capacitor Selection
An output capacitor is needed in the charger circuit to absorb
the switching frequency ripple current and smooth the output
voltage. The rms value of the output ripple current is given by
VIN, MAX
Irms
=
D 1– D
(
(8)
)
fL1 12
The maximum value occurs when the duty cycle is 0.5. Thus
VIN, MAX
Irms_MAX = 0.072
fL1
(9)
–12–
REV. B
ADP3806
For an input voltage of 19 V and a 22 mH inductance, the maxi-
mum rms current is 0.26 A. A typical 10 mF or 22 mF ceramic
capacitor is a good choice to absorb this current.
MOSFET Selection
One of the features of the ADP3806 is that it allows use of a
high side NMOS switch instead of a more costly PMOS device.
The converter also uses synchronous rectification for optimal
efficiency. In order to use a high side NMOS, an internal boot-
strap regulator automatically generates a 7 V supply across C9.
Input Capacitor Ripple
As is the case with a normal buck converter, the pulse current at
the input has a high rms component. Therefore, since the input
capacitor has to absorb this current ripple, it must have an
appropriate rms current rating. The maximum input rms cur-
rent is given by
Maximum output current determines the RDS(ON) requirement
for the two power MOSFETs. When the ADP3806 is operating
in continuous mode, the simplifying assumption can be made
that one of the two MOSFETs is always conducting the load
current. The power dissipation for each MOSFET is given by:
D 1– D
(
)
PBAT
h ¥ D ¥VIN
Irms
=
¥
(10)
D
Upper MOS
2
where h is the estimated converter efficiency (approximately
90%, 0.9) and PBAT is the maximum battery power consumed.
This is a worst-case calculation and, depending on total charge
time, the calculated number could be relaxed. Consult the
capacitor manufacturer for further technical information.
PDISS = RDS (ON ) ¥ IBAT ¥ D +VIN ¥ IBAT
¥
(
)
(11)
D ¥TSW ¥ f
Lower MOS
2
Decoupling the VCC Pin
PDISS = RDS (ON ) ¥ IBAT ¥ 1– D +VIN ¥ IBAT
¥
(
)
It is a good idea to use an RC filter (R13 and C14) from the
input voltage to the IC both to filter out switching noise and to
supply bypass to the chip. During layout, this capacitor should
be placed as close to the IC as possible. Values between 0.1 mF
and 2.2 mF are recommended.
(12)
1– D ¥TSW ¥ f
where f is the switching frequency and TSW is the switch transi-
tion time, usually 10 ns. The first term accounts for conduction
losses while the second term estimates switching losses. Using
these equations and the manufacturer’s data sheets, the proper
device can be selected.
Current-Sense Filtering
During normal circuit operation, the current-sense signals can
have high frequency transients that need filtering to ensure
proper operation. In the case of the CS+ and CS– inputs, the
resistors (R3 and R4) are set to 249 W while the filter capacitor
(C13) value is 22 nF. For the system current sense circuits,
common-mode filtering from SYS+ and SYS– to ground is
needed. 470 nF ceramic capacitors (C1, C2) with 2.2 W resistors
(R1, R2) will often do. These time constants can be adjusted in
the laboratory if required but represent a good starting point.
A Schottky diode, D1, in parallel with Q2 conducts only during
dead time between the two power MOSFETs. D1’s purpose is
to prevent the body diode of the lower N-channel MOSFET
from turning on, which could cost as much as 1% in efficiency.
One option is to use a combined MOSFET with the Schottky
diode in a single package; these integrated packages often work
better in practice. Examples are the IRF7807D2 and the Si4832.
REV. B
–13–
ADP3806
OUTLINE DIMENSIONS
24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8؇
0؇
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153AD
–14–
REV. B
ADP3806
Revision History
Location
Page
2/04—Data Sheet changed from REV. A to REV. B.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6/03—Data Sheet changed from REV. 0 to REV. A.
Updated SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Updated ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REV. B
–15–
–16–
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