ADP3808JCPZ-RL [ADI]
High Efficiency Switch Mode Li-Ion Battery Charger; 高效率开关模式锂离子电池充电器
| 型号： | ADP3808JCPZ-RL |
| 厂家： | 
ADI |
| 描述： | High Efficiency Switch Mode Li-Ion Battery Charger |
| 文件： | 总16页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Efficiency Switch Mode
Li-Ion Battery Charger
ADP3808
FEATURES
GENERAL DESCRIPTION
Selectable 3-cell or 4-cell operation
Adjustable 4.0 V to 4.5 V per cell
High end-of-charge voltage accuracy
0.4ꢀ ꢁ 25°C
0.6ꢀ ꢁ 5°C to 55°C
0.8ꢀ ꢁ 0°C to 100°C
Programmable charge current, including trickle charge
Bootstrapped synchronous drive for external N-channel
MOSFETs
The ADP3808 is a complete Li-Ion battery charging controller
for 3- or 4-cell battery packs. The device combines accurate
final battery charge voltage control with constant current
control to simplify the implementation of constant-current,
constant-voltage (CCCV) chargers.
The final battery charge voltage is programmable between 4.0 V
to 4.5 V per cell, allowing the charging of various cell types. The
charge current is programmable over a wide range from trickle
charging to full charging. The system current sense amplifier
includes an ac adapter detection output to signal that the
adapter is connected. The bootstrapped synchronous driver
controls two N-channel MOSFET transistors for high efficiency
charging at a low system cost.
Programmable oscillator frequency
APPLICATIONS
Portable computers
Portable equipment
The ADP3808 is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 24-lead
LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
VCC
22
LOW-SIDE
DRIVE
REGULATOR
UVLO
AND BIAS
8
EN
DRVREG
BST
19
20
21
EN
IN
DRVH
SW
REFERENCE
OSCILLATOR
DRVREG
10
AGND
CONTROL
LOGIC
18 DRVREG
17
DRVLSD
DRVL
5
RT
CELLSEL
BAT
16
PGND
12
11
3-/4-
CELL
VTH
CSP
CSM
15
14
6
REFIN
BATTERY
VOLTAGE
ADJUST
g
m
7
9
BATADJ
COMP
g
m
CHARGE
CURRENT
SETPOINT
23
24
SYSM
SYSP
13
4
CSADJ
CMP
1V
EXTPWR
CMP
SYS+
CMP
18.25V
1
2
3
ISYS LIMSET
LIMIT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
ADP3808
TABLE OF CONTENTS
Features .............................................................................................. 1
LIMIT........................................................................................... 13
AC Adaptor Detection............................................................... 13
EN................................................................................................. 13
UVLO........................................................................................... 13
Loop Feed Forward.................................................................... 13
Application Information................................................................ 14
Design Procedure....................................................................... 14
Battery Voltage Settings............................................................. 14
Inductor Selection.................................................................. 14
Output Capacitor Selection .................................................. 14
Input Capacitor Ripple .......................................................... 14
Decoupling the VCC Pin ...................................................... 14
Current Sense Filtering.......................................................... 14
MOSFET Selection................................................................. 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Setting the Charge Current ....................................................... 10
Final Battery Voltage Control ................................................... 11
Oscillator and PWM .................................................................. 11
5.25 V Bootstrap Regulator....................................................... 12
Bootstrapped Synchronous Driver........................................... 12
System Current Sense ................................................................ 12
REVISION HISTORY
6/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADP3808
SPECIFICATIONS
VCC = 20 V, EN = 5 V, REFIN = 3 V, TA = 0°C to 100°C, unless otherwise noted.1
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
BATTERY VOLTAGE SENSING
Accuracy
TA = 25°C, 13 V ≤ VCC ≤ 21 V,
BATADJ = 0 V or BATADJ = REFIN
5°C ≤ TA ≤ 55°C, 13 V ≤ VCC ≤ 21 V,
BATADJ = 0 V or BATADJ = REFIN
13 V ≤ VCC ≤ 21 V,
−0.4
−0.6
−0.8
+0.4
+0.6
+0.8
%
%
%
ΔVBAT
BATADJ = 0 V or BATADJ = REFIN
Input Resistance
RBAT
170
0.2
135
1
kΩ
μA
%
Shutdown Leakage Current
Overvoltage Threshold
Overvoltage Response Time
BATTERY VOLTAGE ADJUST
BATADJ Input Range
REFIN Input Range
3-Cell Voltage Low
3-Cell Voltage High
4-Cell Voltage Low
4-Cell Voltage High
IBAT(SD)
VBAT(OV)
tBAT(OV)
EN = 0 V
1.0
120
VBAT(OV) to COMP < 1 V
μs
VBATADJ
VREFIN
VBAT
VBAT
VBAT
0
2.0
REFIN
3.5
V
V
V
V
V
BATADJ = 0 V, CELLSEL = 3.3 V
BATADJ = REFIN, CELLSEL = 3.3 V
BATADJ = 0 V, CELLSEL = 0 V
BATADJ = REFIN, CELLSEL = 0 V
12.0
13.5
16.0
18.0
VBAT
BATTERY CURRENT SENSE AMPLIFIER
Accuracy2
CSADJ = REFIN, 3.9 V ≤ VCS(CM) ≤ 21 V
CSADJ = 0.2 × REFIN, 3.9 V ≤ VCS(CM) ≤ 21 V
−8
−20
0
+8
+30
VCC
%
%
V
μA
μA
μA
V/V
μA
mV
μs
Input Common Mode Range
Input Bias Current—Operating
Input Bias Current—Shutdown
Input Bias Current—CSM
Gain
VCM(CS)
IB(CSP)
IB(CSP,SD)
IB(CSM)
40
EN = 0 V
0.1
0.1
31.25
1
100
1
1
2
AV(CS)
CSADJ Bias Current
IB(CSADJ)
VCS(OC)
tDC
2
110
Overcurrent Threshold2
Overcurrent Response Time
DRVL Shutdown Threshold
SYSTEM CURRENT SENSE AMPLIFIER
Input Common Mode Range
Input Bias Current, SYSP
Input Bias Current, SYSM
Voltage Gain
90
10
VOC > 130 mV to COMP < 1 V
VCS(DRVLSD)
32
mV
VCM(SYS)
IB(SYSP)
IB( SYSM)
SYSP and SYSM to AGND
VSYS(CM) = 19 V
VSYS(CM) = 19 V
22
400
1
V
300
0.1
μA
μA
V/V
ꢀA
mV
V
mV
μs
mV
VISYS/(VSYSP − VSYSM
VISYS = 2.5 V
)
49.5 50
5
48
0
51.5
ISYS Output Current
LIMIT Threshold
LIMSET Input Range
LIMIT Output Voltage Low
LIMIT Propagation Delay Time
VTH(LIMIT)
VLIMSET
VOL(LIMIT)
tpdl(LIMIT)
SYSP to SYSM, LIMSET = 2.5 V
53
58
3.5
75
ILIMIT = −100 μA
(SYSP) – (SYSM) rising > 55 mV to LIMIT going low
SYSP to SYSM
30
1
EXTPWR
EXTPWR
EXTPWR
EXTPWR
17.5 22.5
27.5
Current Threshold
VTH(EXTPWR)
VTH(EXTPWR)
VTH(EXTPWR)
tdpl(EXTPWR)
SYSP to AGND
18.0 18.25 18.5
V
Voltage Threshold
5
1
50
mV
μs
IEXTPWR = −100 μA
Output Voltage Low
Propagation Delay Time
SYSP Rising > 18.5 V to EXTPWR going low
Rev. 0 | Page 3 of 16
ADP3808
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OSCILLATOR
Maximum Frequency
Frequency Variation
fOSC
1
290
2
MHz
kHz
V
RT = 150 kΩ
250
1.9
340
2.1
ΔfOSC
VRT
RT Output Voltage
Zero Duty Cycle Threshold
Maximum Duty Cycle Threshold
LOGIC INPUTS (EN, CELLSEL)
Input Voltage High
Input Voltage Low
Input Current
Measured at COMP
Measured at COMP
1
2
V
V
VIH
VIL
IIN
2.0
–1
V
V
μA
0.8
+1
Inputs = 0 V or 5 V
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Time
Propagation Delay Time
LOW-SIDE DRIVER
BST to SW = 5 V
BST to SW = 5 V
BST to SW = 0 V
3
3
10
20
60
8
8
Ω
Ω
kΩ
ns
ns
trDRVH, tfDRVH BST to SW = 5 V, CLOAD = 1 nF
40
85
tpdhDRVH
BST to SW = 5 V, CLOAD = 1 nF
25
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Time
Propagation Delay Time3
Timeout Delay4
3.8
1.5
10
20
15
8
8
Ω
Ω
VCC = PGND
CLOAD = 1 nF
CLOAD = 1 nF
SW = 5 V
kΩ
ns
ns
ns
ns
trDRVL, tfDRVL
tpdhDRVL
40
35
150
150
300
300
SW = PGND
SUPPLY VCC
Supply Voltage Range
Supply Current
VCC
10
22
V
Normal Mode
Shutdown Mode
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
DRV Regulator Output Voltage
DRV Regulator Output Current
IVCC
IVCC(SD)
VUVLO
EN = 5 V
EN = 0 V
VCC rising
9.8
5
9.5
600
5.25
12
10
10
mA
μA
V
mV
V
9
VDRVREG
IDRVREG
CL = 100 nF
5.0
10
5.5
mA
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2 Measured between CSP and CSM. (VCSP − VCSM) = 96 mV × CSADJ/REFIN.
3 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
4 The turn-on of DRVL is initiated after DRVH turns off by either SW crossing a ~1 V threshold or by expiration of the timeout delay.
Rev. 0 | Page 4 of 16
ADP3808
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VCC
PGND
BST
BST to SW
SW
DRVH
DRVL
−0.3 V to +25 V
−0.3 V to +0.3 V
−0.3 V to +30 V
−0.3 V to +6 V
−4 V to +25 V
SW − 0.3 V to BST + 0.3 V
PGND − 0.3 V to
DRVREG + 0.3 V
ESD CAUTION
SYSP, SYSM to AGND
BAT, CSP, CSM to AGND
SYSP to SYSM
−25 V to +25 V
−0.3 V to VCC + 0.3 V
−5 V to +5 V
CSP to CSM
−5 V to +5 V
All Other Inputs and Outputs
θJA
−0.3 V to +6 V
2-Layer Board
4-Layer Board
125°C/W
83°C/W
Operating Ambient Temperature
Range
0°C to 100°C
Junction Temperature Range
Storage Temperature Range
Lead Temperature
0°C to 150°C
−65°C to +150°C
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
300°C
215°C
220°C
Rev. 0 | Page 5 of 16
ADP3808
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ISYS
LIMSET
LIMIT
1
2
3
4
5
6
18 DRVREG
17 DRVL
16 PGND
15 CSP
ADP3808
TOP VIEW
EXTPWR
RT
(Not to Scale)
14 CSM
REFIN
13 CSADJ
Figure 2. LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
ISYS
LIMSET
LIMIT
Output for System Current Sense Amplifier.
System Current Limit Set Point Input.
System Current Limit Output. This is an open-drain pin and requires a pull-up resistor to a maximum of 6 V.
External Adapter Sense Open-Drain Output. This pin pulls low when the ac adapter voltage is present. A pull-up
resistor is required to a maximum of 6 V.
EXTPWR
5
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and AGND sets the oscillator
frequency of the device.
6
7
REFIN
BATADJ
Reference Input for BATADJ and CSADJ.
Battery Voltage Adjust Input. This pin uses an analog voltage referenced to REFIN to program voltage from 4.0 V to
4.5 V per cell.
8
EN
Charger Enable Input. Pulling this pin to AGND disables the DRVH and DRVL outputs and puts the circuitry
powered by VCC into a low power state. The system amplifier and EXTPWR are still active.
9
COMP
AGND
BAT
CELLSEL
CSADJ
Output of Error Amplifiers and Compensation Point.
Analog Ground. Reference point for the battery sense and all analog functions.
Battery Sense Input.
Battery Cell Selection Input. Pulling this pin high selects 3-cell operation; pulling it low selects 4-cell operation.
Charge Current Programming Input. This pin uses an analog voltage referenced to REFIN to program the battery
charge current. (VCSP − VCSM) = 96 mV x CSADJ/REFIN.
10
11
12
13
14
15
16
17
18
CSM
CSP
PGND
DRVL
DRVREG
Negative Current Sense Input. This pin connects to the battery side of the battery current sense resistor.
Positive Current Sense Input. This pin connects to the inductor side of the battery current sense resistor.
Power Ground. This pin should closely connect to the source of the lower MOSFET.
Synchronous Rectifier Drive. Output drive for the lower MOSFET.
Driver Supply Output. A bypass capacitor should be connected from this pin to PGND to provide filtering for the
low-side supply.
19
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.
20
21
DRVH
SW
Main Switch Drive. Output drive for the upper MOSFET.
Switch Node Input. This pin is connected to the buck-switching node, close to the source of the upper MOSFET,
and is the floating return for the upper MOSFET drive signal.
22
23
24
VCC
SYSM
SYSP
Input Supply. This pin does not power the SYS amplifier section.
Negative System Current Sense Input. This pin connects to the battery side of the system current sense resistor.
Positive System Current Sense Input. This pin connects to the adapter side of the system current sense resistor.
This pin also provides power to the system amplifier section.
25
Paddle
This pin should be connected to AGND.
Rev. 0 | Page 6 of 16
ADP3808
TYPICAL PERFORMANCE CHARACTERISTICS
30
12
11
10
9
V
= 16V
CC
A
NO LOADS
T
= 25°C
T
= 0°C
A
25
20
15
10
5
T
= 25°C
A
T
= 100°C
A
8
7
6
0
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
12
13
14
15
16
V (V)
CC
17
18
19
20
V
ACCURACY (%)
BAT
Figure 3. VBAT Accuracy Distribution
Figure 6. On Supply Current vs. VCC
0.15
0.1
126
V
= 16V
CC
T
= 100°C
A
106
86
0.05
0
–0.05
–0.1
–0.15
–0.2
T
= 25°C
A
66
46
T
= 0°C
A
26
6
–0.25
–0.3
0
100
13
14
15
16
(V)
17
18
19
12
20
10
20
30
40
50
60
70
80
90
V
TEMPERATURE (°C)
CC
Figure 4. VBAT Accuracy vs. Temperature
Figure 7. Off Supply Current vs. VCC
0.07
20
T
= 25°C
V
T
= 16V
fOASC = 300kHz
A
CC
0.06
0.05
0.04
0.03
0.02
0.01
0
= 25°C
18
16
14
12
–0.01
–0.02
–0.03
–0.04
10
0
13
14
15
16
V
17
(V)
18
19
20
0
500
1000
1500
2000
2500
3000
3500
DRIVER LOAD CAPACITANCE (pF)
CC
Figure 8. Supply Current vs. Driver Load Capacitance
Figure 5. VBAT Accuracy vs. VCC
Rev. 0 | Page 7 of 16
ADP3808
4.5
4
V
= 16V
CC
400
350
SOURCE
3.5
3
300
250
2.5
2
SINK
1.5
1
200
90
110
130
150
170
190
210
0
20
40
60
80
100
RT (kΩ)
TEMPERATURE (°C)
Figure 9. Oscillator Frequency vs. RT
Figure 12. DRVL On Resistance vs. Temperature
6
5
V
= 16V
CC
= 25°C
ISYS RISING
ISYS FALLING
DRVH
5V/DIV
T
A
4
3
2
1
DRVL 5V/DIV
200ns/DIV
0
0
0.5
1
1.5
2
2.5
3.0
V
(V)
ISYS
Figure 13. Driver Waveforms
Figure 10. VLIMIT vs. VISYS
100
95
3.3
V
V
CC
V
= 16V
CC
T
A
3.2
3.1
90
85
80
75
70
65
60
SINK
3.0
2.9
2.8
2.7
SOURCE
0
0.5
1.0
1.5
2.0
2.5
3.0
0
20
40
60
80
100
CHARGE CURRENT (A)
TEMPERATURE (°C)
Figure 14. Conversion Efficiency vs. Charge Current
Figure 11. DRVH On Resistance vs. Temperature
Rev. 0 | Page 8 of 16
ADP3808
97
96
95
94
93
92
91
90
89
88
I
= 2A
CHARGE
I
= 3A
CHARGE
V
T
= 19V
CC
= 25°C
A
3
4
5
6
7
8
9
10
11
12
13
V
(V)
BAT
Figure 15. Conversion Efficiency vs. Battery Voltage
Rev. 0 | Page 9 of 16
ADP3808
THEORY OF OPERATION
The ADP3808 combines a bootstrapped synchronous switching
driver with programmable current control and accurate final
battery voltage control in a constant-current, constant-voltage
(CCCV) Li-Ion battery charger. High accuracy voltage control
is needed to safely charge Li-Ion batteries, which are typically
specified at 4.2 V 1ꢀ per cell. For a typical notebook computer
battery pack, three or four cells are in series, giving a total
voltage of 12.6 V or 16.8 V. The ADP3808 allows the final
battery voltage to be programmed. The programmable range is
4.0 V to 4.5 V per cell. The total number of cells to be charged
can be set to either 3 or 4 via a control pin.
strapped high-side driver, the ADP3808 drives two external
power NMOS transistors for a simple, lower cost power stage.
The ADP3808 also provides an uncommitted current sense
amplifier. This amplifier provides an analog output pin for
monitoring the current through an external sense resistor. The
amplifier can be used anywhere in the system that high-side
current sensing is needed. The sense amplifier output is compared
to a programmable voltage limit. If the limit is exceeded, the
LIMIT pin is asserted. The system sense amplifier is also used
to detect the presence of an ac adaptor. If the adaptor is detected,
the ADP3808 asserts a logic pin to signal the detection.
Another requirement for safely charging Li-Ion batteries is
accurate control of the charge current. The actual charge current
depends on the number of cells in parallel within the battery
pack. Typically, this is in the range of 2 A to 3 A. The ADP3808
provides flexibility in programming the charge current over a
wide range. An external resistor is used to sense the charge
current. The charge current can be set by programming the
sense resistor voltage drop. The voltage drop can be set to a
maximum of 96 mV. This programmability allows the current
to be changed during charging. For example, the charge current
can be reduced for trickle charging.
SETTING THE CHARGE CURRENT
The charge current is measured across an external sense
resistor, RCS, between the CSP and CSM pins. The input
common-mode range is from ground to VCC, allowing current
control in short-circuit and low dropout conditions. The voltage
between CSP and CSM is programmed by a ratio of the voltages
at CSADJ and REFIN according to Equation 1.
CSADJ
VCSP − VCSM = 96 mV
(1)
REFIN
For example, using a 20 mΩ sense resistor gives a range from
150 mA with CSADJ = REFIN/32 to 4.8 A maximum when
CSADJ = REFIN.
The synchronous driver provides high efficiency when charging
at high currents. Efficiency is important mainly to reduce the
amount of heat generated in the charger, but also to stay within
the power limits of the ac adapter. With the addition of a boot-
The power dissipation in RCS should be kept below 500 mW.
Components R4 and C13 provide high frequency filtering for
the current sense signal.
Rev. 0 | Page 10 of 16
ADP3808
R
SS
10mꢀ
SYSTEM
DC/DC
R
20mꢀ
1/2 Q1
FD56990A
CS
L1
V
IN
+
–
22µH
+
C15
22µF
R13
10ꢀ
1/2 Q1
FD56990A
R4
510ꢀ
R2
510ꢀ
C16
–
BATTERY
12.6V/16.8V
22µF
C13
22µF
C1
2.2µF
3.3V
C14
2.2µF
C9
100nF
BST DRV
ISYS
LIMIT
SW DRVL PGND
V
CSP
CSM
SYSP
SYSM
CC
BOOTSTRAPPED
SYNCHRONOUS
DRIVER
3.3V
R9
–
+
+
–
AMP2
AMP1
–
+
EN
IN DRVLSD DRVLSD
LIMSET
–
+
V
+ V
REG
REF
–
R10
V
TH
UVLO
DRVREG
7.0V
C10
BIAS
1V
+
EXTPWR
–
g
m
1
+
–
0.1µF
+
–
+
SYSP
BAT
EN
CSADJ
BAT
LOGIC
CONTROL
CHARGE
CURRENT
SETPOINT
3.3V
R11
3-/4-CELL
OSCILLATOR
–
2
+
SELECTION
g
m
REFIN
BATTERY
VOLTAGE
ADJUST
ADP3808
BATADJ
R12
COMP
RT
CELLSEL
AGND
C8
0.22µF
150kꢀ
R8
56ꢀ
C11
Figure 16. Typical Application Circuit
and is ratioed to the REFIN pin. The battery voltage VBAT is set
according to Equation 2 and Equation 3.
FINAL BATTERY VOLTAGE CONTROL
As the battery approaches its final voltage, the ADP3808
switches from CC mode to CV mode. The change is achieved
by the common output node of gm1 and gm2. Only one of the
two outputs controls the voltage at the COMP pin. Both
amplifiers can only pull down on COMP, such that when either
amplifier has a positive differential input voltage, its output is
not active. For example, when the battery voltage, VBAT, is low,
gm2 does not control VCOMP. When the battery voltage reaches
the desired final voltage, gm2 takes control of the loop, and the
charge current is reduced.
For CELLSEL > 2 V:
BATADJ
VBAT = 12 V+ 1.5 V
(2)
(3)
REFIN
For CELLSEL < 0.8 V:
BATADJ
REFIN
VBAT = 16 V+ 2 V
OSCILLATOR AND PWM
The oscillator generates a triangle waveform between 1 V and
2 V, which is compared to the voltage at the COMP pin, setting
the duty cycle of the driver stage. When VCOMP is below 1.0 V,
the duty cycle is zero. Above 2.0 V, the duty cycle reaches its
maximum. The oscillator frequency is set by the external
resistor at the RT pin, ROSC, and is given by Equation 4.
Amplifier gm2 compares the battery voltage to a programmable
level set by pins BATADJ and REFIN. The target battery voltage
is dependent on the state of the CELLSEL pin as CELLSEL sets
the number of cells to be charged. Pulling CELLSEL high sets
the ADP3808 to charge three cells. When CELLSEL is tied to
ground, four cells are selected. CELLSEL has a 2 μA pull-up
current as a fail-safe to select three cells when it is left open.
41 × 109
fOSC
=
(4)
The final battery voltage is programmable from 4.0 V to 4.5 V
per cell. The programming voltage is applied to the BATADJ pin
ROSC
Rev. 0 | Page 11 of 16
ADP3808
DRVREG
ADP3808
BOOTSTRAPPED
SYNCHRONOUS DRIVER
BST
CMP3
CBST
DRVH
MIN
OFF
TIME
IN
Q1
EN
SW
–
DELAY
CMP2
+
1V
DRVL
PGND
–
Q2
CMP1
+
1V
DELAY
DRVLSD
Figure 17. Bootstrapped Synchronous Driver
Overlap protection is included in the driver to ensure that both
external MOSFETs are not on at the same time. When DRVH
turns off the upper MOSFET, the SW node goes low due to the
inductor current. The ADP3808 monitors the SW voltage, and
DRVL goes high to turn on the lower MOSFET when SW goes
below 1 V. When DRVL turns off, an internal timer adds a delay
of 50 ns before turning DRVH on.
5.25 V BOOTSTRAP REGULATOR
The driver stage is powered by the internal 5.25 V bootstrap
regulator, which is available at the DRVREG pin. Because the
switching currents are supplied by this regulator, decoupling
must be added. A 0.1 μF capacitor should be placed close to the
ADP3808, with the ground side connected close to the power
ground pin, PGND. This supply is not recommended for use
externally due to high switching noise.
When the charge current is low, the DRVLSD comparator
signals the driver to turn off the low-side MOSFET and DRVL
is held low. The DRVLSD threshold is set to 0.8 V correspond-
ing to a 32 mV differential between the CS pins.
BOOTSTRAPPED SYNCHRONOUS DRIVER
The PWM comparator controls the state of the synchronous
driver shown in Figure 17. A high output from the PWM
comparator forces DRVH on and DRVL off. The drivers have
an on resistance of less than 4 Ω for fast rise and fall times when
driving external MOSFETs. Furthermore, the bootstrapped drive
allows an external NMOS transistor for the main switch instead
of a PMOS. A boost capacitor of 0.1 μF must be added
externally between BST and SW.
The driver stage monitors the voltage across the BST capacitor
with CMP3. When this voltage is less than 4 V, CMP3 forces a
minimum off time of 200 ns. This ensures that the BST capacitor
is charged even during DRVLSD. However, because a minimum
off time is only forced when needed, the maximum duty cycle is
greater than 99ꢀ.
SYSTEM CURRENT SENSE
The DRVL pin switches between DRVREG and PGND. The
5.25 V output of DRVREG drives the external NMOS with high
An uncommitted differential amplifier is provided for
additional high-side current sensing. This amplifier, AMP2,
has a fixed gain of 50 V/V from the SYSP and SYSM pins to the
analog output at ISYS. ISYS has a 100 μA source capability to
drive an external load. The common-mode range of the input
pins is from 10 V to 22 V. This amplifier is the only part of the
ADP3808 that remains active during shutdown. The power to
this block is derived from the bias current on the SYSP and
SYSM pins.
VGS to lower the on resistance. PGND should be connected
close to the source pin of the external synchronous NMOS.
When DRVL is high, this turns on the lower NMOS and pulls
the SW node to ground. At this point, the boost capacitor is
charged up through the internal boost diode. When the PWM
switches high, DRVL is turned off and DRVH turns on. DRVH
switches between BST and SW. When DRVH is on, the SW pin
is pulled up to the input supply (typically 16 V), and BST rises
above this voltage by approximately 4.75 V.
Rev. 0 | Page 12 of 16
ADP3808
LIMIT
UVLO
The LIMIT pin is an open-drain output that signals when the
voltage at ISYS exceeds the voltage at LIMSET. The internal
comparator produces the function shown in Figure 10. This is
a graph of VLIMIT vs. VISYS where LIMSET is set to 1.5 V. The
LIMIT pin should be pulled up to a maximum of 6 V through a
resistor. When ISYS is below LIMSET, the LIMIT pin has high
output impedance. The open-drain output is capable of sinking
700 μA when the threshold is exceeded. This comparator is
turned off during shutdown to conserve power.
Undervoltage lock-out, UVLO, is included in the ADP3808 to
ensure proper startup. As VCC rises above 1 V, the regulator
tracks VCC until it reaches its final voltage. However, the rest of
the circuitry is held off by the UVLO comparator. The UVLO
comparator monitors the regulator to ensure that it is above 5 V
before turning on the main charger circuitry. This occurs when
V
CC reaches 9.5 V. Monitoring the regulator outputs makes sure
that the charger circuitry and driver stage have sufficient
voltage to operate normally. The UVLO comparator includes
600 mV of hysteresis to prevent oscillations near the threshold.
AC ADAPTOR DETECTION
LOOP FEED FORWARD
EXTPWR
The
pin on the ADP3808 is an open-drain active low
As the startup sequence discussion shows, the response time at
COMP is slowed by the large compensation capacitor. To speed
up the response, two comparators can quickly feed forward
around the normal control loop and pull the COMP node down
to limit any overshoot in either short-circuit or overvoltage
conditions. The overvoltage comparator has a trip point set to
35ꢀ higher than the final battery voltage. The overcurrent
comparator threshold is set to 100 mV across the CS pins.
When these comparators are tripped, a normal soft start
sequence is initiated. The overvoltage comparator is valuable
when the battery is removed during charging. In this case, the
current in the inductor causes the output voltage to spike up,
and the comparator limits the maximum voltage. Neither of
these comparators affects the loop under normal charging
conditions.
output used to signal that an ac adaptor is connected. If the
ISYS voltage level is greater than 1 V or the SYSP sense pin
EXTPWR
voltage is greater then 18.25 V, the
pin is driven low.
A pull-up resistor must be connected when this function is
required. The maximum pull-up voltage is 6 V.
EN
A high impedance CMOS logic input is provided to turn off the
ADP3808. When the voltage on EN is less than 0.8 V, the
ADP3808 is placed in low power shutdown. With the exception
of the system current sense amplifier, AMP2, all other circuitry
is turned off. The reference and regulators are pulled to ground
during shutdown and all switching is stopped. During this state,
the supply current is less than 5 A. In addition, the BAT, CSP,
CSM, and SW pins go to high impedance to minimize current
drain from the battery.
Rev. 0 | Page 13 of 16
ADP3808
APPLICATION INFORMATION
input capacitor has to absorb this current ripple, it must have an
appropriate rms current rating. The maximum input rms
current is given by
DESIGN PROCEDURE
Refer to Figure 16, the typical application circuit, for the
following description. The design follows that of a buck
converter. With Li-Ion cells it is important to have a regulator
with accurate output voltage control.
PBAT
D(1 − D)
Irms
=
×
(10)
η × D VIN
D
BATTERY VOLTAGE SETTINGS
Inductor Selection
where η is the estimated converter efficiency (approximately
90ꢀ, 0.9) and PBAT is the maximum battery power consumed.
Usually the inductor is chosen based on the assumption that the
inductor ripple current is 15ꢀ of the maximum output dc
current at maximum input voltage. As long as the inductor used
has a value close to this, the system should work fine. The final
choice affects the trade-offs between cost, size, and efficiency.
For example, the lower the inductance, the size is smaller but
ripple current is higher. This situation, if taken too far, leads to
higher ac losses in the core and the windings. Conversely, a
higher inductance results in lower ripple current and smaller
output filter capacitors, but the transient response will be
slower. With these considerations, the required inductance can
be calculated using Equation 6.
This is a worst-case calculation and, depending on total charge
time, the calculated number could be relaxed. Consult the
capacitor manufacturer for further technical information.
Decoupling the VCC Pin
It is a good idea to use an RC filter (R13 and C14) from the
input voltage to the IC both to filter out switching noise and to
supply bypass to the chip. During layout, this capacitor should
be placed as close to the IC as possible. Values between 0.1 μF
and 2.2 μF are recommended.
Current Sense Filtering
During normal circuit operation, the current sense signals can
have high frequency transients that need filtering to ensure
proper operation. In the case of the CSP and CSM inputs,
Resistor R4 is set to 510 Ω and the filter capacitor C13 is 22 nF.
For the system current sense filter on SYSP, SYSM, R2 is set to
510 Ω, C1 is 2.2 ꢁF, and C2 is 470 nF.
VIN, MAX − VBAT
L1 =
× DMIN × TS
(6)
ΔI
where the maximum input voltage VIN, MAX is used with the
minimum duty ratio DMIN. The duty ratio is defined as the ratio
of the output voltage to the input voltage, VBAT/VIN. The ripple
current is calculated using Equation 7.
MOSFET Selection
One of the features of the ADP3808 is that it allows use of a
high-side NMOS switch instead of a more costly PMOS device.
The converter also uses synchronous rectification for optimal
efficiency. To use a high-side NMOS, an internal bootstrap
regulator automatically generates a 5.25 V supply
across C9.
ΔI = 0.3 × IBAT, MAX
(7)
The maximum peak-to-peak ripple is 30ꢀ, that is 0.3, and
maximum battery current, IBAT, MAX, is used.
For example, with VIN, MAX = 19 V, VBAT = 12.6 V, IBAT, MAX = 3A,
and TS = 4 μs, the value of L1 is calculated as 18.9 μH. Choosing
the closest standard value gives L1 = 22 μH.
Maximum output current determines the RDS(ON) requirement
for the two power MOSFETs. When the ADP3808 is operating
in continuous mode, the simplifying assumption can be made
that one of the two MOSFETs is always conducting the load
current. The power dissipation for each MOSFET is given by
Output Capacitor Selection
An output capacitor is needed in the charger circuit to absorb
the switching frequency ripple current and smooth the output
voltage. The rms value of the output ripple current is given by
VIN ,MAX
Upper MOSFET:
Irms
=
D
(
1 − D
)
(8)
PDISS = RDS(ON) × (IBAT × √D)2 + VIN × IBAT × √D × TSW × f (11)
fL1 12
Lower MOSFET:
The maximum value occurs when the duty cycle is 0.5. Thus,
VIN, MAX
Irms _ MAX = 0.072
fL1
PDISS = RDS(ON) × (IBAT × √D)2 + VIN × (IBAT × √1 − D)2 ×
tSW × f
(9)
(12)
where f is the switching frequency and tSW is the switch
transition time, usually 10 ns.
For an input voltage of 19 V and a 22 μH inductance, the
maximum rms current is 0.26 A. A typical 10 μF or 22 μF
ceramic capacitor is a good choice to absorb this current.
The first term accounts for conduction losses while the second
term estimates switching losses. Using these equations and the
manufacturer’s data sheets, the proper device can be selected.
Input Capacitor Ripple
As is the case with a normal buck converter, the pulse current at
the input has a high rms component. Therefore, because the
Rev. 0 | Page 14 of 16
ADP3808
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
PIN 1
INDICATOR
0.50
BSC
2.25
2.10 SQ
1.95
TOP
VIEW
3.75
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
6
13
12
7
0.25 MIN
0.80 MAX
0.65TYP
2.50 REF
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 20. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Ordering
Model
Temperature Range
Package Description
Package Option Quantity
ADP3808JCPZ1
ADP3808JCPZ-RL1
0°C to 100°C
0°C to 100°C
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
CP-24-1
CP-24-1
5000
1 Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
ADP3808
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06632-0-6/07(0)
Rev. 0 | Page 16 of 16
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