ADP5024ACPZ-1-R7_技术文档

Dual 3 MHz, 1200 mA Buck

Regulators with One 300 mA LDO

Data Sheet

ADP5024

FEATURES

GENERAL DESCRIPTION

Main input voltage range: 2.3 V to 5.5 V

Two 1200 mA buck regulators and one 300 mA LDO

24-lead, 4 mm × 4 mm LFCSP package

The ADP5024 combines two high performance buck regula-

tors and one low dropout (LDO) regulator in a small, 24-lead,

4 mm × 4 mm LFCSP to meet demanding performance and

board space requirements.

Regulator accuracy: 3ꢀ

Factory programmable or external adjustable VOUTx

3 MHz buck operation with forced PWM and automatic

PWM/PSM modes

BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V

LDO: output voltage range from 0.8 V to 5.2 V

LDO: input supply voltage from 1.7 V to 5.5 V

LDO: high PSRR and low output noise

The high switching frequency of the buck regulators enables tiny

multilayer external components and minimizes the board space.

When the MODE pin is set high, the buck regulators operate in

forced PWM mode. When the MODE pin is set low, the buck

regulators operate in PWM mode when the load current is above

a predefined threshold. When the load current falls below a pre-

defined threshold, the regulator operates in power save mode

(PSM), improving the light load efficiency.

APPLICATIONS

Power for processors, ASICS, FPGAs, and RF chipsets

Portable instrumentation and medical devices

Space constrained devices

The two bucks operate out of phase to reduce the input capacitor

requirement. The low quiescent current, low dropout voltage, and

wide input voltage range of the LDO extends the battery life of

portable devices. The ADP5024 LDO maintains power supply

rejection greater than 60 dB for frequencies as high as 10 kHz

while operating with a low headroom voltage.

Regulators in the ADP5024 are activated though dedicated

enable pins. The default output voltages can be either externally

set in the adjustable version or factory programmable to a wide

range of preset values in the fixed voltage version.

TYPICAL APPLICATION CIRCUIT

AVIN

HOUSEKEEPING

C

0.1µF

AVIN

VOUT1

L1 1µH

VIN1

SW1

FB1

2.3V TO

5.5V

V

AT

OUT1

C1

1200mA

R1

R2

4.7µF

BUCK1

MODE

C5

10µF

PGND1

ON

EN1

OFF

PWM

MODE

PSM/PWM

VOUT2

VIN2

EN2

MODE

L2 1µH

SW2

FB2

C2

V

AT

OUT2

4.7µF

1200mA

R3

R4

BUCK2

C6

10µF

EN2

EN3

PGND2

ON

OFF

EN3

VOUT3

FB3

V

AT

OUT3

LDO

(ANALOG)

300mA

R5

R6

VIN3

1.7V TO

5.5V

C7

1µF

C3

1µF

ADP5024

AGND

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

ADP5024

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 16

Power Management Unit........................................................... 17

BUCK1 and BUCK2 .................................................................. 19

LDO.............................................................................................. 20

Applications Information .............................................................. 21

Buck External Component Selection....................................... 21

LDO External Component Selection....................................... 23

Power Dissipation and Thermal Considerations ....................... 24

Buck Regulator Power Dissipation .......................................... 24

Junction Temperature ................................................................ 25

PCB Layout Guidelines.................................................................. 26

Typical Application Schematics.................................................... 27

Bill of Materials........................................................................... 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Applications....................................................................................... 1

General Description ......................................................................... 1

Typical Application Circuit ............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

General Specifications ................................................................. 3

BUCK1 and BUCK2 Specifications ........................................... 4

LDO Specifications ...................................................................... 5

Input and Output Capacitor, Recommended Specifications.. 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

REVISION HISTORY

1/1 —Rev. 0 to Rev. A

Changes to Features Section and Figure 1..................................... 1

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 5

Changes to Table 4............................................................................ 6

Changes to Table 7............................................................................ 8

Changes to Figure 34...................................................................... 14

Changes to LDO Section and Figure 48 ...................................... 20

Changes to Table 9 and Figure 50................................................. 22

Changes to Buck Regulator Power Dissipation Section ............ 24

Changes to Figure 52 and Figure 53............................................. 27

Changes to Ordering Guide .......................................................... 28

8/11—Revision 0: Initial Version

Rev. A | Page 2 of 28

Data Sheet

ADP5024

SPECIFICATIONS

GENERAL SPECIFICATIONS

V_AVIN= V_IN1= V_IN2= 2.3 V to 5.5 V; V_IN3= 1.7 V to 5.5 V; T_J= −40°C to +125°C for minimum/maximum specifications, and T_A= 25°C for

typical specifications, unless otherwise noted.

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

INPUT VOLTAGE RANGE

THERMAL SHUTDOWN

Threshold

V_AVIN, V_IN1, V_IN2

2.3

5.5

V

TS_SD

TS_SD-HYS

T_Jrising

150

20

°C

Hysteresis

START-UP TIME¹

BUCK1, LDO

BUCK2

t_START1

t_START2

250

300

µs

EN1, EN2, EN3, MODE INPUTS

Input Logic High

V_IH

1.1

V

Input Logic Low

Input Leakage Current

INPUT CURRENT

V_IL

V_I-LEAKAGE

0.4

1

V

µA

0.05

All Channels Enabled

All Channels Disabled

VIN1 UNDERVOLTAGE LOCKOUT

High UVLO Input Voltage Rising

High UVLO Input Voltage Falling

Low UVLO Input Voltage Rising

Low UVLO Input Voltage Falling

I_STBY-NOSW

I_SHUTDOWN

No load, no buck switching

T_J= −40°C to +85°C

108

0.3

175

1

µA

UVLO_VIN1RISE

UVLO_VIN1FALL

UVLO_VIN1RISE

UVLO_VIN1FALL

3.9

V

3.1

2.275

1.95

¹Start-up time is defined as the time from EN1 = EN2 = EN3 from 0 V to V_AVINto VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal levels. Start-up times are

shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.

Rev. A | Page 3 of 28

ADP5024

Data Sheet

BUCK1 AND BUCK2 SPECIFICATIONS

V_AVIN= V_IN1= V_IN2= 2.3 V to 5.5 V; T_J= −40°C to +125°C for minimum/maximum specifications, and T_A= 25°C for typical

specifications, unless otherwise noted.¹

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

OUTPUT CHARACTERISTICS

Output Voltage Accuracy

ΔV_OUT1/V_OUT1

ΔV_OUT2/V_OUT2

(ΔV_OUT1/V_OUT1)/ΔV_IN1

(ΔV_OUT2/V_OUT2)/ΔV_IN2

(ΔV_OUT1/V_OUT1)/ΔI_OUT1

(ΔV_OUT2/V_OUT2)/ΔI_OUT2

,

I_LOAD1= I_LOAD2= 0 mA to 1200 mA, PWM mode

PWM mode

−3

+3

%

Line Regulation

Load Regulation

,

−0.05

−0.1

%/V

%/A

V

,

I_LOAD= 0 mA to 1200 mA, PWM mode

VOLTAGE FEEDBACK

OPERATING SUPPLY CURRENT

BUCK1 Only

V_FB1, V_FB2

Models with adjustable outputs

MODE = ground

I_LOAD1= 0 mA, device not switching, all other

channels disabled

I_LOAD2= 0 mA, device not switching, all other

channels disabled

I_LOAD1= I_LOAD2= 0 mA, device not switching, LDO

channels disabled

0.485 0.5

0.515

I_IN

44

μA

mA

BUCK2 Only

I_IN

55

BUCK1 and BUCK2

I_IN

67

PSM CURRENT THRESHOLD

SW CHARACTERISTICS

SW On Resistance

I_PSM

PSM to PWM operation

100

R_NFET

R_PFET

R_NFET

R_PFET

V_IN1= V_IN2= 3.6 V

V_IN1= V_IN2= 5.5 V

155

205

137

162

240

310

204

243

mΩ

Current Limit

I_LIMIT1, I_LIMIT2

R_PDWN-B

f_SW

PFET switch peak current limit

Channel disabled

1600 1950

75

2300 mA

Ω

ACTIVE PULL-DOWN

OSCILLATOR FREQUENCY

2.5

3.0

3.5

MHz

¹All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

Rev. A | Page 4 of 28

Data Sheet

ADP5024

LDO SPECIFICATIONS

V_IN3= (V_OUT3+ 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; C_IN= C_OUT= 1 µF; T_J= −40°C to +125°C for minimum/maximum

specifications, and T_A= 25°C for typical specifications, unless otherwise noted.¹

Table 3.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

Bias Current per LDO²

V_IN3

1.7

5.5

V

I_VIN3BIAS

I_OUT3= 0 µA

I_OUT3= 10 mA

I_OUT3= 300 mA

10

60

165

30

100

245

µA

I_IN

Total System Input Current

LDO Only

Includes all current into AVIN, VIN1,

VIN2, and VIN3

I_OUT3= 0 µA, all other channels

disabled

53

µA

OUTPUT CHARACTERISTICS

Output Voltage Accuracy

Line Regulation

ΔV_OUT3/V_OUT3

(ΔV_OUT3/V_OUT3)/ΔV_IN3

(ΔV_OUT3/V_OUT3)/ΔI_OUT3

V_FB3

100 µA < I_OUT3< 300 mA

I_OUT3= 1 mA

I_OUT3= 1 mA to 300 mA

−3

−0.03

+3

%

+0.03

0.003

0.515

%/V

%/mA

V

Load Regulation³

0.001

0.5

VOLTAGE FEEDBACK

DROPOUT VOLTAGE⁴

0.485

V_DROPOUT

V_OUT3= 5.2 V, I_OUT3= 300 mA

V_OUT3= 3.3 V, I_OUT3= 300 mA

V_OUT3= 2.5 V, I_OUT3= 300 mA

V_OUT3= 1.8 V, I_OUT3= 300 mA

50

75

100

180

600

mV

140

mV

mA

Ω

CURRENT-LIMIT THRESHOLD⁵I_LIMIT3

335

ACTIVE PULL-DOWN

OUTPUT NOISE

R_PDWN-L

Channel disabled

Regulator LDO

NOISE_LDO

PSRR

10 Hz to 100 kHz, V_IN3= 5V, V_OUT3= 2.8 V

100

µV rms

POWER SUPPLY REJECTION

RATIO

Regulator LDO

10 kHz, V_IN3= 3.3 V, V_OUT3= 2.8 V,

60

62

63

dB

I

_OUT3= 1 mA

100 kHz, V_IN3= 3.3 V, V_OUT3= 2.8 V,

_OUT3= 1 mA

I

1 MHz, V_IN3= 3.3 V, V_OUT3= 2.8 V,

I_OUT3= 1 mA

¹All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

²This is the input current into VIN3, which is not delivered to the output load.

³Based on an endpoint calculation using 1 mA and 300 mA loads.

⁴Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages

above 1.7 V.

⁵Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.

Rev. A | Page 5 of 28

ADP5024

Data Sheet

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

T_A= −40°C to +125°C, unless otherwise specified.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS

BUCK1, BUCK2 Input Capacitor Ratings

BUCK1, BUCK2 Output Capacitor Ratings

LDO¹Input and Output Capacitor Ratings

CAPACITOR ESR

C_MIN1, C_MIN2

C_MIN3, C_MIN4

R_ESR

4.7

10

1.0

40

µF

Ω

0.001

1

¹The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are

recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics.

Rev. A | Page 6 of 28

Data Sheet

ADP5024

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 5.

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Parameter

Rating

AVIN to AGND

VIN1, VIN2 to AVIN

PGND1, PGND2 to AGND

VIN3, VOUT1, VOUT2, FB1, FB2, FB3,

EN1, EN2, EN3, MODE to AGND

−0.3 V to +6 V

−0.3 V to +0.3 V

−0.3 V to (AVIN + 0.3 V)

Table 6. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

24-Lead, 0.5 mm pitch LFCSP

35

3

°C/W

VOUT3 to AGND

SW1 to PGND1

SW2 to PGND2

Storage Temperature Range

−0.3 V to (VIN3 + 0.3 V)

−0.3 V to (VIN1 + 0.3 V)

−0.3 V to (VIN2 + 0.3 V)

−65°C to +150°C

ESD CAUTION

Operating Junction Temperature

Range

−40°C to +125°C

Soldering Conditions

JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

For detailed information on power dissipation, see the Power

Dissipation and Thermal Considerations section.

Rev. A | Page 7 of 28

ADP5024

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

18

17

16

15

14

13

AGND

VIN2

AGND

AVIN

VIN1

ADP5024

TOP VIEW

SW1

SW2 4

5

6

PGND2

NC

PGND1

MODE

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. IT IS RECOMMENDED THAT THE EXPOSED PAD

BE SOLDERED TO THE GROUND PLANE.

Figure 2. Pin Configuration—View from Top of the Die

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

5

6

7

8

AGND

VIN2

SW2

PGND2

NC

Analog Ground.

BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1 and AVIN.

BUCK2 Switching Node.

Dedicated Power Ground for BUCK2.

No Connect. Leave this pin unconnected.

BUCK2 Enable Pin. High level turns on this regulator, and low level turns it off.

EN2

FB2

BUCK2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the

BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.

9

10

11

VOUT2

VOUT1

FB1

BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2.

BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1.

BUCK1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the

BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.

12

13

EN1

MODE

BUCK1 Enable Pin. High level turns on this regulator, and low level turns it off.

BUCK1/BUCK2 Operating Mode. MODE = high for forced PWM operation. MODE = low for automatic PWM/PSM

operation.

14

15

16

17

18

19

PGND1

SW1

VIN1

AVIN

AGND

FB3

Dedicated Power Ground for BUCK1.

BUCK1 Switching Node.

BUCK1 Input Supply (2.3 V to 5.5 V). Connect VIN1 to VIN2 and AVIN.

Analog Input Supply (2.3 V to 5.5 V). Connect AVIN to VIN1 and VIN2.

Analog Ground.

LDO Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the

LDO resistor divider. For device models with a fixed output voltage, connect this pin to the top of the capacitor

on VOUT3.

20

21

22

23

24

VOUT3

VIN3

EN3

AGND

EPAD (EP)

LDO Output Voltage.

LDO Input Supply (1.7 V to 5.5 V).

LDO Enable Pin. High level turns on this regulator, and low level turns it off.

Analog Ground.

Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane.

Rev. A | Page 8 of 28

Data Sheet

ADP5024

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN1= V_IN2= V_IN3= 3.6 V, T_A= 25°C, unless otherwise noted.

3.35

3.33

3.31

3.29

3.27

3.25

140

120

100

80

V

= 3.6V, +25°C

IN

V

= 3.6V, +85°C

= 3.6V, –40°C

IN

60

V

40

IN

20

0

2.3

2.8

3.3

3.8

4.3

4.8

5.3

0

0.2

0.4

0.6

(A)

0.8

1.0

1.2

INPUT VOLTAGE (V)

I

OUT

Figure 3. System Quiescent Current vs. Input Voltage, V_OUT1= 3.3 V,

_OUT2= 1.8 V, V_OUT3= 1.2 V, All Channels Unloaded

Figure 6. BUCK1 Load Regulation Across Temperature, V_OUT1= 3.3 V,

Automatic Mode

V

1.864

T

SW

1.844

4

2

V

= 3.6V, +25°C

IN

IOUT

1.824

1.804

1.784

1.764

V

= 3.6V, +85°C

IN

VOUT

EN

1

3

V

= 3.6V, –40°C

IN

B

CH1 2.00V

CH3 5.00V

CH2 50.0mA Ω

CH4 5.00V

M 40.0µs

A CH3

2.2V

W

0

0.2

0.4

0.6

(A)

0.8

1.0

1.2

B

T

11.20%

I

OUT

Figure 4. BUCK1 Startup, V_OUT1= 1.8 V, I_OUT1= 5 mA

Figure 7. BUCK2 Load Regulation Across Temperature, V_OUT2= 1.8 V,

Automatic Mode

0.799

0.798

T

V

= 3.6V, +85°C

= 3.6V, +25°C

IN

SW

0.797

0.796

0.795

0.794

0.793

0.792

0.791

0.790

0.789

4

V

IN

IOUT

2

VOUT

EN

1

3

V

= 3.6V, –40°C

0.4

IN

B

CH1 2.00V

CH3 5.00V

CH2 50.0mA Ω

CH4 5.00V

M 40.0µs

A CH3

2.2V

W

0

0.2

0.6

(A)

0.8

1.0

1.2

W

T

11.20%

I

OUT

Figure 8. BUCK1 Load Regulation Across Input Voltage, V_OUT1= 0.8 V,

PWM Mode

Figure 5. BUCK2 Startup, V_OUT2= 3.3 V, I_OUT2= 10 mA

Rev. A | Page 9 of 28

ADP5024

Data Sheet

100

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

0

V

= 3.9V

IN

V

= 3.6V

IN

V

= 4.2V

V

= 2.3V

IN

V

= 5.5V

V

= 5.5V

IN

V

= 4.2V

IN

0

0.0001

0.001

0.01

(A)

0.1

1

0.001

0.01

0.1

1

I

(A)

OUT

Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

_OUT1= 3.3 V, Automatic Mode

Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage,

_OUT2= 1.8 V, PWM Mode

V

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 5.5V

IN

V

= 3.9V

IN

V

= 2.3V

IN

V

= 5.5V

IN

V

= 4.2V

IN

V

= 3.6V

IN

V

= 4.2V

IN

0.001

0.01

0.1

1

0.001

0.01

0.1

1

I

(A)

I

(A)

OUT

Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

_OUT1= 3.3 V, PWM Mode

Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

_OUT1= 0.8 V, Automatic Mode

V

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 3.6V

IN

V

= 2.3V

IN

V

= 2.3V

IN

V

= 5.5V

IN

V

= 4.2V

IN

V

= 3.6V

V

= 5.5V

IN

V

= 4.2V

IN

0.001

0.01

0.1

1

0.001

0.01

0.1

1

I

(A)

I

OUT

(A)

OUT

Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage,

_OUT2= 1.8 V, Automatic Mode

Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage,

_OUT1= 0.8 V, PWM Mode

V

Rev. A | Page 10 of 28

Data Sheet

ADP5024

3.3

3.2

3.1

3.0

2.9

2.8

2.7

2.6

2.5

100

90

80

70

60

50

40

30

20

10

+25°C

–40°C

+25°C

+85°C

0

0.2

0.4

0.6

(A)

0.8

1.0

1.2

0.001

0.01

0.1

1

I

OUT

I

(A)

OUT

Figure 18. BUCK2 Switching Frequency vs. Output Current, Across

Temperature, V_OUT2= 1.8 V, PWM Mode

Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature,

V_IN= 3.9 V, V_OUT1= 3.3 V, Automatic Mode

100

T

VOUT

+85°C

90

80

70

60

50

40

30

20

10

0

+25°C

1

I

–40°C

SW

2

SW

4

CH1 50mV

CH2 500mA Ω

CH4 2.00V

M 4.00µs A CH2

28.40%

240mA

0.001

0.01

0.1

1

T

I

(A)

OUT

Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature,

_OUT2= 1.8 V, Automatic Mode

Figure 19. Typical Waveforms, V_OUT1= 3.3 V, I_OUT1= 30 mA, Automatic Mode

V

100

90

80

70

60

50

40

30

20

10

0

T

+25°C

VOUT

1

+85°C

–40°C

I

SW

2

SW

4

B

CH1 50mV

CH2 500mA Ω

CH4 2.00V

M 4.00µs A CH2

220mA

W

0.001

0.01

0.1

1

B

W

T

28.40%

I

(A)

OUT

Figure 20. Typical Waveforms, V_OUT2= 1.8 V, I_OUT2= 30 mA, Automatic Mode

Figure 17. BUCK1 Efficiency vs. Load Current, Across Temperature,

_OUT1= 0.8 V, Automatic Mode

V

Rev. A | Page 11 of 28

ADP5024

Data Sheet

T

VOUT

1

2

VIN

I

SW

VOUT

SW

1

SW

4

3

4

B

CH1 50mV

CH2 500mA Ω

CH4 2.00V

M 400ns A CH2

220mA

CH1 50.0mV

CH3 1.00V

M 1.00ms

A

CH3

4.80V

W

B

W

CH4 2.00V

W

T

30.40%

T

28.40%

Figure 21. Typical Waveforms, V_OUT1= 3.3 V, I_OUT1= 30 mA, PWM Mode

Figure 24. Buck2 Response to Line Transient, V_IN= 4.5 V to 5.0 V,

_OUT2= 1.8 V, PWM Mode

V

T

SW

VOUT

1

4

1

I

SW

VOUT

2

SW

I

OUT

2

4

B

CH1 50mV

CH2 500mA Ω

CH4 2.00V

M 400ns A CH2

220mA

CH1 50.0mV

_WCH2 50.0mA Ω

CH4 5.00V

M 20.0µs A CH2

T 60.000µs

356mA

W

B

W

T

28.40%

Figure 22. Typical Waveforms, V_OUT2= 1.8 V, I_OUT2= 30 mA, PWM Mode

Figure 25. BUCK1 Response to Load Transient, I_OUT1from 1 mA to 50 mA,

_OUT1= 3.3 V, Automatic Mode

V

T

SW

4

1

VIN

VOUT

1

SW

I

OUT

3

2

B

CH1 50.0mV

CH3 1.00V

M 1.00ms

A

CH3

4.80V

CH1 50.0mV

_WCH2 50.0mA Ω

CH4 5.00V

M 20.0µs A CH2

379mA

W

B

CH4 2.00V

W

T

30.40%

T

22.20%

Figure 23. BUCK1 Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, V_OUT1= 3.3 V, PWM Mode

Figure 26. BUCK2 Response to Load Transient, I_OUT2from 1 mA to 50 mA,

_OUT2= 1.8 V, Automatic Mode

V

Rev. A | Page 12 of 28

Data Sheet

ADP5024

T

SW

4

1

I

IN

2

1

3

VOUT

EN

I

OUT

2

B

CH1 2.00V

CH3 5.00V

CH2 50.0mA Ω

M 40.0µs

A CH3

2.2V

CH1 50.0mV

_WCH2 200mA Ω

CH4 5.00V

M 20.0µs A CH2

408mA

W

B

T

20.40%

T 11.20%

Figure 30. LDO Startup, V_OUT3= 3.0 V, I_OUT3= 5 mA

Figure 27. BUCK1 Response to Load Transient, I_OUT1from 20 mA to 180 mA,

_OUT1= 3.3 V, Automatic Mode

V

2.820

2.815

2.810

2.805

2.800

2.795

2.790

2.785

2.780

T

SW

4

1

VOUT

V

= 4.5V

V

= 3.3V

IN

I

OUT

V

= 5.5V

IN

2

V

= 5.0V

IN

B

CH1 100mV

CH2 200mA Ω

CH4 5.00V

M 20.0µs A CH2

88.0mA

W

0

0.05

0.10

0.15

0.20

0.25

0.30

T

19.20%

I

(A)

OUT

Figure 28. BUCK2 Response to Load Transient, I_OUT2from 20 mA to 180 mA,

_OUT2= 1.8 V, Automatic Mode

Figure 31. LDO Load Regulation Across Input Voltage, V_OUT3= 2.8 V

V

400

350

T

VOUT2

SW1

2

3

300

+125°C

250

200

150

100

50

+25°C

–40°C

VOUT1

SW2

1

4

0

2.3

B

CH1 5.00V

CH3 5.00V

CH2 5.00V

CH4 5.00V

M 400ns

50.00%

A

CH4

1.90V

W

2.8

3.3

3.8

4.3

4.8

5.3

B

W

T

INPUT VOLTAGE (V)

Figure 32. NMOS RDS_ONvs. Input Voltage Across Temperature

Figure 29. VOUTx and SW Waveforms for BUCK1 and BUCK2 in PWM Mode

Showing Out-of-Phase Operation

Rev. A | Page 13 of 28

ADP5024

Data Sheet

250

200

150

100

50

45

40

35

30

25

20

15

10

5

+125°C

+25°C

–40°C

0

2.3

0

2.8

3.3

3.8

4.3

4.8

5.3

0

0.05

0.10

0.15

0.20

0.25

INPUT VOLTAGE (V)

LOAD CURRENT (A)

Figure 33. PMOS RDS_ONvs. Input Voltage Across Temperature

Figure 36. LDO Ground Current vs. Output Load, V_IN3= 3.3 V, V_OUT3= 2.8 V

3.45

T

3.40

3.35

3.30

3.25

3.20

3.15

I

OUT

2

1

V

= 4.2V, +85°C

IN

V

= 4.2V, +25°C

IN

VOUT

= 4.2V, –40°C

IN

B

W

CH1 100mV

CH2 100mA Ω

M 40.0µs A CH2

52.0mA

W

0

0.05

0.10

0.15

(A)

0.20

0.25

0.30

I

T

19.20%

OUT

Figure 34. LDO Load Regulation Across Temperature, V_IN3= 4.2 V, V_OUT3= 3.3 V

Figure 37. LDO Response to Load Transient, I_OUT3from 1 mA to 80 mA,

_OUT3= 2.8 V

V

3.0

T

I

= 10mA

I

= 100µA

OUT

I

= 1mA

= 100mA

= 150mA

2.5

2.0

1.5

1.0

0.5

0

OUT

I

OUT

VIN

I

OUT

= 300mA

I

OUT

VOUT

21

3

CH1 20.0mV

CH3 1.00V

M 100µs

28.40%

A

CH3

4.80V

2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4

T

V

(V)

IN

Figure 38. LDO Response to Line Transient, Input Voltage from 4.5 V to 5.5 V,

_OUT3= 2.8 V

Figure 35. LDO Line Regulation Across Output Load, V_OUT3= 2.8 V

V

Rev. A | Page 14 of 28

Data Sheet

ADP5024

0

60

55

50

45

V

= 5V

IN

–20

–40

–60

–80

V

= 3.3V

IN

40

35

30

100µA

1mA

10mA

50mA

100mA

150mA

–100

–120

25

0.001

0.01

0.1

1

10

100

10

100

1k

10k

100k

1M

10M

I

(mA)

FREQUENCY (Hz)

LOAD

Figure 39. LDO Output Noise vs. Load Current, Across Input Voltage,

_OUT3= 2.8 V

Figure 42. LDO PSRR Across Output Load, V_IN3= 3.3 V, V_OUT3= 3.0 V

V

0

65

60

100µA

1mA

10mA

50mA

100mA

150mA

V

= 5V

IN

–20

V

IN

= 3.3V

55

50

45

40

35

30

–40

–60

–80

–100

–120

25

0.001

0.01

0.1

1

10

100

10

100

1k

10k

100k

1M

10M

I

(mA)

FREQUENCY (Hz)

LOAD

Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage,

_OUT3= 3.0 V

Figure 43. LDO PSRR Across Output Load, V_IN3= 5.0 V, V_OUT3= 2.8 V

V

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

100µA

1mA

10mA

50mA

100mA

150mA

100µA

1mA

10mA

50mA

100mA

150mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 44. LDO PSRR Across Output Load, V_IN3= 5.0 V, V_OUT3= 3.0 V

Figure 41. LDO PSRR Across Output Load, V_IN3= 3.3 V, V_OUT3= 2.8 V

Rev. A | Page 15 of 28

ADP5024

Data Sheet

THEORY OF OPERATION

VOUT1 FB1 FB2 VOUT2

ENBK1

ENBK2

GM ERROR

AMP

75Ω

GM ERROR

AMP

AVIN

PWM

COMP

PWM

COMP

SOFT START

VIN2

VIN1

I

LIMIT

PSM

COMP

PWM/

PSM

CONTROL

BUCK1

PWM/

PSM

CONTROL

BUCK2

LOW

CURRENT

LOW

CURRENT

SW2

SW1

OSCILLATOR

DRIVER

AND

ANTISHOOT

THROUGH

DRIVER

AND

ANTISHOOT

THROUGH

SYSTEM

UNDERVOLTAGE

LOCKOUT

OP

MODE

SEL

PGND2

MODE

MODE2

THERMAL

SHUTDOWN

B

A

PGND1

Y

EN1

EN2

EN3

ENBK1

ENBK2

ENLDO

ENABLE

AND

MODE

LDO

UNDERVOLTAGE

LOCKOUT

CONTROL

R1

R2

LDO

CONTROL

AVIN

ENLDO

600Ω

ADP5024

VIN3

AGND FB3 VOUT3

Figure 45. Functional Block Diagram

Rev. A | Page 16 of 28

Data Sheet

ADP5024

Thermal Protection

POWER MANAGEMENT UNIT

In the event that the junction temperature rises above 150°C,

the thermal shutdown circuit turns off all of the regulators.

Extreme junction temperatures can be the result of high current

operation, poor circuit board design, or high ambient tempera-

ture. A 20°C hysteresis is included so that when thermal shutdown

The ADP5024 is a micropower management unit (microPMU)

combing two step-down (buck) dc-to-dc convertors and one

low dropout linear regulator (LDO). The high switching frequency

and tiny 24-lead LFCSP package allow for a small power manage-

ment solution.

occurs, the regulators do not return to operation until the on-chip

temperature drops below 130°C. When emerging from thermal

shutdown, all regulators restart with soft start control.

To combine these high performance regulators into the

microPMU, there is a system controller allowing them to

operate together.

Undervoltage Lockout

The buck regulators can operate in forced PWM mode if the

MODE pin is at a logic level high. In forced PWM mode, the

buck switching frequency is always constant and does not

change with the load current. If the MODE pin is at logic level

low, the switching regulators operate in automatic PWM/PSM

mode. In this mode, the regulators operate at a fixed PWM

frequency when the load current is above the PSM current

threshold. When the load current falls below the PSM current

threshold, the regulator in question enters PSM, where the

switching occurs in bursts. The burst repetition rate is a

function of the current load and the output capacitor value.

This operating mode reduces the switching and quiescent

current losses. The automatic PWM/PSM mode transition is

controlled independently for each buck regulator. The two

bucks operate synchronized to each other.

To protect against battery discharge, undervoltage lockout

(UVLO) circuitry is integrated in the system. If the input

voltage on VIN1 drops below a typical 2.15 V UVLO threshold,

all channels shut down. In the buck channels, both the power

switch and the synchronous rectifier turn off. When the voltage

on VIN1 rises above the UVLO threshold, the part is enabled

once more.

Alternatively, the user can select device models with a UVLO

set at a higher level, suitable for USB applications. For these

models, the device reaches the turn off threshold when the

input supply drops to 3.65 V typical.

In case of a thermal or UVLO event, the active pull-downs (if

factory enabled) are enabled to discharge the output capacitors

quickly. The pull-down resistors remain engaged until the thermal

fault event is no longer present or the input supply voltage falls

below the V_PORvoltage level. The typical value of V_PORis approx-

imately 1 V.

The ADP5024 has individual enable pins (EN1 to EN3) that

control the activation of each regulator. The regulators are

activated by a logic level high applied to the respective EN pin,

wherein EN1 controls BUCK1, EN2 controls BUCK2, and EN3

controls the LDO.

Enable/Shutdown

The ADP5024 has an individual control pin for each regulator.

A logic level high applied to the ENx pin activates a regulator

whereas a logic level low turns off a regulator.

Regulator output voltages are set through external resistor

dividers or can be optionally factory programmed to default

values (see the Ordering Guide section).

Figure 46 shows the regulator activation timings for the

ADP5024 when all enable pins are connected to AVIN. Also

shown is the active pull-down activation.

When a regulator is turned on, the output voltage ramp rate is

controlled though a soft start circuit to avoid a large inrush

current due to the charging of the output capacitors.

Rev. A | Page 17 of 28

ADP5024

Data Sheet

V

UVLO

AVIN

V

POR

VOUT1

VOUT3

30µs

(MIN)

30µs

(MIN)

50µs (MIN)

VOUT2

50µs (MIN)

BUCK1, LDO

PULL-DOWNS

BUCK2

PULL-DOWN

Figure 46. Regulator Sequencing (EN1 = EN2 = EN3 = V_AVIN

)

Rev. A | Page 18 of 28

Data Sheet

ADP5024

mode. The output capacitor discharges until the output voltage

falls to the PWM regulation voltage, at which point the device

drives the inductor to make the output voltage rise again to the

upper threshold. This process is repeated while the load current

is below the PSM current threshold.

BUCK1 AND BUCK2

The buck uses a fixed frequency and high speed current

mode architecture. The buck operates with an input voltage

of 2.3 V to 5.5 V.

The buck output voltage is set through external resistor

dividers, shown in Figure 47 for BUCK1. The output voltage

can optionally be factory programmed to default values, as

indicated in the Ordering Guide section. In this event, R1 and

R2 are not needed, and FB1 can remain unconnected. In all cases,

VOUT1 must be connected to the output capacitor. FB1 is 0.5 V.

The ADP5024 has a dedicated MODE pin controlling the PSM

and PWM operation. A logic level high applied to the MODE

pin forces both bucks to operate in PWM mode. A logic level

low sets the bucks to operate in automatic PSM/PWM.

PSM Current Threshold

The PSM current threshold is set to100 mA. The bucks employ

a scheme that enables this current to remain accurately controlled,

independent of input and output voltage levels. This scheme

also ensures that there is very little hysteresis between the PSM

current threshold for entry to and exit from the PSM. The PSM

current threshold is optimized for excellent efficiency over all

load currents.

VOUT1

VIN1

L1

1µH

SW1

VOUT1

BUCK

R1

R2

C5

10µF

FB1

AGND

Oscillator/Phasing of Inductor Switching

R1

R2

V

= V

+ 1

OUT1

FB1

The ADP5024 ensures that both bucks operate at the same

switching frequency when both bucks are in PWM mode.

Figure 47. BUCK1 External Output Voltage Setting

Additionally, the ADP5024 ensures that when both bucks are in

PWM mode, they operate out of phase, whereby the Buck2

PFET starts conducting exactly half a clock period after the

BUCK1 PFET starts conducting.

Control Scheme

The bucks operate with a fixed frequency, current mode PWM

control architecture at medium to high loads for high efficiency,

but shift to a power save mode (PSM) control scheme at light

loads to lower the regulation power losses. When operating in

fixed frequency PWM mode, the duty cycle of the integrated

switches is adjusted and regulates the output voltage. When

operating in PSM at light loads, the output voltage is controlled

in a hysteretic manner, with higher output voltage ripple. During

part of this time, the converter is able to stop switching and

enters an idle mode, which improves conversion efficiency.

Short-Circuit Protection

The bucks include frequency foldback to prevent output current

runaway on a hard short. When the voltage at the feedback pin

falls below half the target output voltage, indicating the possi-

bility of a hard short at the output, the switching frequency is

reduced to half the internal oscillator frequency. The reduction

in the switching frequency allows more time for the inductor to

discharge, preventing a runaway of output current.

PWM Mode

Soft Start

In PWM mode, the bucks operate at a fixed frequency of 3 MHz,

set by an internal oscillator. At the start of each oscillator cycle,

the PFET switch is turned on, sending a positive voltage across

the inductor. Current in the inductor increases until the current

sense signal crosses the peak inductor current threshold, which

turns off the PFET switch and turns on the nFET synchronous

rectifier. This sends a negative voltage across the inductor,

causing the inductor current to decrease. The synchronous

rectifier stays on for the remainder of the cycle. The buck

regulates the output voltage by adjusting the peak inductor

current threshold.

The bucks have an internal soft start function that ramps the

output voltage in a controlled manner upon startup, thereby

limiting the inrush current. This prevents possible input voltage

drops when a battery or a high impedance power source is

connected to the input of the converter.

Current Limit

Each buck has protection circuitry to limit the amount of

positive current flowing through the PFET switch and the

amount of negative current flowing through the synchronous

rectifier. The positive current limit on the power switch limits

the amount of current that can flow from the input to the

output. The negative current limit prevents the inductor

current from reversing direction and flowing out of the load.

Power Save Mode (PSM)

The bucks smoothly transition to PSM operation when the load

current decreases below the PSM current threshold. When

either of the bucks enters PSM, an offset is induced in the PWM

regulation level, which makes the output voltage rise. When the

output voltage reaches a level approximately 1.5% above the

PWM regulation level, PWM operation is turned off. At this

point, both power switches are off, and the buck enters an idle

100% Duty Operation

With a drop in input voltage, or with an increase in load

current, the buck may reach a limit where, even with the PFET

switch on 100% of the time, the output voltage drops below the

Rev. A | Page 19 of 28

ADP5024

Data Sheet

desired output voltage. At this limit, the buck transitions to a

mode where the PFET switch stays on 100% of the time. When

the input conditions change again and the required duty cycle

falls, the buck immediately restarts PWM regulation without

allowing overshoot on the output voltage.

configurations where the LDO supply voltage is provided from

one of the buck regulators.

The LDO output voltage is set through external resistor dividers,

as shown in Figure 48. The output voltage can optionally be

factory programmed to default values, as indicated in the Ordering

Guide section. In this event, Ra and Rb are not needed, and FB3

must be connected to the top of the capacitor on VOUT3. FB3 is

0.5 V.

Active Pull-Down Resistors

All regulators have optional, factory programmable, active pull-

down resistors discharging the respective output capacitors

when the regulators are disabled. The pull-down resistors are

connected between VOUTx and AGND. Active pull-downs are

disabled when the regulators are turned on. The typical value of

the pull-down resistor is 600 Ω for the LDO and 75 Ω for each

buck. Figure 46 shows the activation timings for the active pull-

downs during regulator activation and deactivation.

VIN3

VOUT3

C7

1µF

LDO

Ra

Rb

FB3

LDO

The ADP5024 contains one LDO with low quiescent current

and low dropout voltage and provides up to 300 mA of output

current. Drawing a low 10 μA quiescent current (typical) at no

load makes the LDO ideal for battery-operated portable

equipment.

Ra

Rb

V

= V

+ 1

OUT3

FB3

Figure 48. LDO External Output Voltage Setting

The LDO also provides high power supply rejection ratio

(PSRR), low output noise, and excellent line and load transient

response with only a small 1 µF ceramic input and output

capacitor.

The LDO operates with an input voltage of 1.7 V to 5.5 V. The

wide operating range makes the LDO suitable for cascading

Rev. A | Page 20 of 28

Data Sheet

ADP5024

APPLICATIONS INFORMATION

Ceramic capacitors are manufactured with a variety of dielec-

trics, each with a different behavior over temperature and applied

voltage. Capacitors must have a dielectric that is adequate to

ensure the minimum capacitance over the necessary temperature

range and dc bias conditions. X5R or X7R dielectrics with a

voltage rating of 6.3 V or 10 V are recommended for best per-

formance. Y5V and Z5U dielectrics are not recommended for

use with any dc-to-dc converter because of their poor temperature

and dc bias characteristics.

BUCK EXTERNAL COMPONENT SELECTION

Trade-offs between performance parameters such as efficiency

and transient response can be made by varying the choice of

external components in the applications circuit, as shown in

Figure 1.

Feedback Resistors

For the adjustable model, shown in Figure 47, the total

combined resistance for R1 and R2 is not to exceed 400 kΩ.

Inductor

The worst-case capacitance accounting for capacitor variation

over temperature, component tolerance, and voltage is calcu-

lated using the following equation:

The high switching frequency of the ADP5024 bucks allows for

the selection of small chip inductors. For best performance, use

inductor values between 0.7 μH and 3 μH. Suggested inductors

are shown in Table 8.

C

_EFF= C_OUT× (1 − TEMPCO) × (1 − TOL)

where:

_EFFis the effective capacitance at the operating voltage.

The peak-to-peak inductor current ripple is calculated using

the following equation:

C

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

V_OUT×(V_IN−V_OUT

)

I_RIPPLE

=

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and C_OUTis 9.2 μF at 1.8 V, as shown in Figure 49.

V

_IN× f_SW×L

where:

_SWis the switching frequency.

L is the inductor value.

f

Substituting these values in the equation yields

The minimum dc current rating of the inductor must be greater

than the inductor peak current. The inductor peak current is

calculated using the following equation:

C_EFF= 9.2 μF × (1 − 0.15) × (1 − 0.1) ≈ 7.0 μF

To guarantee the performance of the bucks, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

12

I_RIPPLE

2

I_PEAK= I_LOAD(MAX)

+

Inductor conduction losses are caused by the flow of current

through the inductor, which has an associated internal dc

resistance (DCR). Larger sized inductors have smaller DCR,

which may decrease inductor conduction losses. Inductor core

losses are related to the magnetic permeability of the core material.

Because the bucks are high switching frequency dc-to-dc

converters, shielded ferrite core material is recommended for

its low core losses and low EMI.

10

8

6

4

Output Capacitor

2

Higher output capacitor values reduce the output voltage ripple

and improve load transient response. When choosing this value,

it is also important to account for the loss of capacitance due to

output voltage dc bias.

0

1

2

3

4

5

6

DC BIAS VOLTAGE (V)

Figure 49. Capacitance vs. Voltage Characteristic

Table 8. Suggested 1.0 μH Inductors

Vendor

Model

Dimensions (mm)

2.0 × 1.6 × 0.9

3.2 × 2.5 × 1.6

3.2 × 2.5 × 2.5

4.0 × 4.0 × 2.1

1.9 × 2.0 × 1.0

2.5 × 2.0 × 1.2

I_SAT(mA)

1400

2300

2000

5400

DCR (mΩ)

Murata

Taiyo Yuden

Coilcraft

Toko

LQM2MPN1R0NG0B

LQH32PN1R0NN0

CBC3225T1R0MR

XFL4020-102ME

XPL2010-102ML

MDT2520-CN

85

45

71

11

89

85

1800

1350

Rev. A | Page 21 of 28

ADP5024

Data Sheet

The peak-to-peak output voltage ripple for the selected output

capacitor and inductor values is calculated using the following

equation:

To minimize supply noise, place the input capacitor as close as

possible to the VINx pin of the buck. As with the output capa-

citor, a low ESR capacitor is recommended.

I_RIPPLE

8× f_SW×C_OUT

V_IN

²×L×C_OUT

A 4.7 µF capacitor is recommended for a typical application;

depending on the application, a smaller or larger output capacitor

may be chosen. A list of suggested 4.7 µF capacitors is shown in

Table 10. The effective capacitance needed for stability, which

includes temperature and dc bias effects, is a minimum of 3 µF

and a maximum of 10 µF.

V_RIPPLE

=

≈

(

2π× f_SW

)

Capacitors with lower equivalent series resistance (ESR) are

preferred to guarantee low output voltage ripple, as shown in

the following equation:

V_RIPPLE

I_RIPPLE

ESR_COUT

≤

Table 9. Suggested 10 μF Capacitors

Voltage

The effective capacitance needed for stability, which includes

temperature and dc bias effects, is a minimum of 7 µF and a

maximum of 40 µF.

Case Rating

Vendor

Murata

TDK

Type Model

Size

(V)

X5R

GRM188R60J106

C1608JB0J106K

ECJ1VB0J106M

0603 6.3

The buck regulators require 10 µF output capacitors to guarantee

stability and response to rapid load variations and to transition

into and out of the PWM/PSM modes. A list of suggested capaci-

tors is shown in Table 9. In certain applications where one or

both buck regulator powers a processor, the operating state is

known because it is controlled by software. In this condition,

the processor can drive the MODE pin according to the operating

state; consequently, it is possible to reduce the output capacitor

from 10 µF to 4.7 µF because the regulator does not expect a

large load variation when working in PSM mode (see Figure 50).

Panasonic

Table 10. Suggested 4.7 μF Capacitors

Voltage

Case Rating

Size (V)

GRM188R60J475ME19D 0402 6.3

Vendor

Type Model

X5R

Murata

Taiyo Yuden X5R

Panasonic X5R

JMK107BJ475

ECJ-0EB0J475M

0402 6.3

Table 11. Suggested 1.0 μF Capacitors

Input Capacitor

Voltage

Case Rating

Size (V)

Higher value input capacitors help to reduce the input voltage

ripple and improve transient response. Maximum input

capacitor current is calculated using the following equation:

Vendor

Murata

TDK

Panasonic

Taiyo

Type Model

X5R

GRM155B30J105K

C1005JB0J105KT

ECJ0EB0J105K

0402 6.3

0402 10.0

V_OUT(V_IN−V_OUT

)

I_CIN≥ I_LOAD(MAX)

LMK105BJ105MV-F

V_IN

Yuden

AVIN

VIN1

HOUSEKEEPING

BUCK1

C_AVIN

0.1µF

VOUT1

L1 1µH

2.3V TO

5.5V

SW1

FB1

V

_OUT1AT

C1

4.7µF

1200mA

R1

R2

C5

10µF

ON

PGND1

EN1

VIN2

EN2

EN1

OFF

MODE

PWM

MODE

VOUT2

PSM/PWM

V

MODE

L2 1µH

R3

SW2

FB2

_OUT2AT

1200mA

C2

4.7µF

BUCK2

EN2

C6

10µF

R4

PGND2

ON

OFF

VOUT3

FB3

EN3

V

_OUT3AT

EN3

LDO

300mA

R5

R6

VIN3

1.7V TO

5.5V

(ANALOG)

C7

1µF

C3

1µF

ADP5024

AGND

Figure 50. Processor System Power Management with PSM/PWM Control

Rev. A | Page 22 of 28

Data Sheet

ADP5024

1.2

1.0

0.8

0.6

LDO EXTERNAL COMPONENT SELECTION

Feedback Resistors

For the adjustable model, the maximum value of Rb must not

exceed 200 kΩ (see Figure 48).

Output Capacitor

The ADP5024 LDO is designed for operation with small, space-

saving ceramic capacitors, but functions with most commonly

used capacitors as long as care is taken with the ESR value. The

ESR of the output capacitor affects stability of the LDO control

loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or

less is recommended to ensure stability of the ADP5024. Transient

response to changes in load current is also affected by output

capacitance. Using a larger value of output capacitance improves

the transient response of the ADP5024 to large changes in load

current.

0.4

0.2

0

1

2

3

4

5

6

DC BIAS VOLTAGE (V)

Figure 51. Capacitance vs. Voltage Characteristic

Use the following equation to determine the worst-case capa-

citance accounting for capacitor variation over temperature,

component tolerance, and voltage.

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN3 to ground reduces the

circuit sensitivity to printed circuit board (PCB) layout, especially

when encountering long input traces or high source impedance.

If greater than 1 µF of output capacitance is required, increase

the input capacitor to match it.

C

_EFF= C_BIAS× (1 − TEMPCO) × (1 − TOL)

where:

C

_BIASis the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

Input and Output Capacitor Properties

In this example, the worst-case temperature coefficient

Use any good quality ceramic capacitors with the ADP5024

as long as they meet the minimum capacitance and maximum

ESR requirements. Ceramic capacitors are manufactured with a

variety of dielectrics, each with a different behavior over temper-

ature and applied voltage. Capacitors must have a dielectric that

is adequate to ensure the minimum capacitance over the necessary

temperature range and dc bias conditions. X5R or X7R dielectrics

with a voltage rating of 6.3 V or 10 V are recommended for best

performance. Y5V and Z5U dielectrics are not recommended

for use with any LDO because of their poor temperature and dc

bias characteristics.

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and C_BIASis 0.85 μF at 1.8 V, as shown in Figure 51.

Substituting these values into the following equation yields:

C_EFF= 0.85 μF × (1 − 0.15) × (1 − 0.1) = 0.65 μF

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over

temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP5024, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

Figure 51 depicts the capacitance vs. voltage bias characteristic

of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the

X5R dielectric is about 15% over the −40°C to +85°C tempera-

ture range and is not a function of package or voltage rating.

Rev. A | Page 23 of 28

ADP5024

Data Sheet

POWER DISSIPATION AND THERMAL CONSIDERATIONS

The ADP5024 is a highly efficient micropower management

unit (microPMU), and, in most cases, the power dissipated in

the device is not a concern. However, if the device operates at

high ambient temperatures and maximum loading condition,

the junction temperature can reach the maximum allowable

operating limit (125°C).

BUCK REGULATOR POWER DISSIPATION

The power loss of the buck regulator is approximated by

_LOSS= P_DBUCK+ P_L

where:

_DBUCKis the power dissipation on one of the ADP5024 buck

P

(3)

P

regulators.

P_Lis the inductor power loss.

When the temperature exceeds 150°C, the ADP5024 turns off

all of the regulators allowing the device to cool down. When the

die temperature falls below 130°C, the ADP5024 resumes normal

operation.

The inductor losses are external to the device and they do not

have any effect on the die temperature.

This section provides guidelines to calculate the power dissi-

pated in the device and ensure that the ADP5024 operates

below the maximum allowable junction temperature.

The inductor losses are estimated (without core losses) by

P_L≈ I_OUT1(RMS)²× DCR_L

(4)

where:

The efficiency for each regulator on the ADP5024 is given by

DCR_Lis the inductor series resistance.

P_OUT

P_IN

I

_OUT1(RMS)is the rms load current of the buck regulator.

η =

×100%

(1)

r

I_OUT1(RMS)= I_OUT1× 1+

(5)

(6)

where:

12

η is the efficiency.

P_INis the input power.

_OUTis the output power.

where r is the normalized inductor ripple current.

r = V_OUT1× (1 − D)/(I_OUT1× L × f_SW)

P

where:

L is the inductance.

Power loss is given by

P

_LOSS= P_IN− P_OUT

(2a)

(2b)

f

_SWis the switching frequency.

or

D is the duty cycle.

_LOSS= P_OUT(1− η)/η

D = V_OUT1/V_IN1

(7)

Power dissipation can be calculated in several ways. The most

intuitive and practical is to measure the power dissipated at the

input and at all of the outputs. Perform the measurements at the

worst-case conditions (voltages, currents, and temperature). The

difference between input and output power is dissipated in the

device and the inductor. Use Equation 4 to derive the power lost

in the inductor, and from this result use Equation 3 to calculate

the power dissipation in the ADP5024 buck converter.

The buck regulator power dissipation, P_DBUCK, of the ADP5024

includes the power switch conductive losses, the switch losses, and

the transition losses of each channel. There are other sources of

loss, but these are generally less significant at high output load

currents, where the thermal limit of the application is located.

Equation 8 captures the calculation that must be made to

estimate the power dissipation in the buck regulator.

P

_DBUCK= P_COND+ P_SW+ P_TRAN

The power switch conductive losses are due to the output current,

_OUT1, flowing through the P-MOSFET and the N-MOSFET

(8)

A second method to estimate the power dissipation uses the effi-

ciency curves provided for the buck regulator, and the power

lost on the LDO can be calculated using Equation 12. When

the buck efficiency is known, use Equation 2b to derive the

total power lost in the buck regulator and inductor, use Equa-

tion 4 to derive the power lost in the inductor, and then calculate

the power dissipation in the buck converter using Equation 3.

Add the power dissipated in the buck and in the LDO to find the

total dissipated power.

I

power switches that have internal resistance, RDS_ON-Pand

RDS_ON-N. The amount of conductive power loss is found by

2

P

_COND= [RDS_ON-P× D + RDS_ON-N× (1 − D)] × I_OUT1

(9)

where RDS_ON-Pis approximately 0.2 Ω, and RDS_ON-Nis approxi-

mately 0.16 Ω at a junction temperature of 125°C and V_IN1= V_IN2

3.6 V. At V_IN1= V_IN2= 2.3 V, these values change to 0.31 Ω and

0.21 Ω, respectively, and at V_IN1= V_IN2= 5.5 V, the values are

0.16 Ω and 0.14 Ω, respectively.

=

Note that the buck efficiency curves are typical values and may

not be provided for all possible combinations of V_IN, V_OUT, and

I

_OUT. To account for these variations, it is necessary to include a

safety margin when calculating the power dissipated in the buck.

A third way to estimate the power dissipation is analytical and

involves modeling the losses in the buck circuit provided by

Equation 8 to Equation 11 and calculating the losses in the LDO

provided by Equation 12.

Rev. A | Page 24 of 28

Data Sheet

ADP5024

Switching losses are associated with the current drawn by the

driver to turn on and turn off the power devices at the switching

frequency. The amount of switching power loss is given by

JUNCTION TEMPERATURE

In cases where the board temperature, T_A, is known, the

thermal resistance parameter, θ_JA, can be used to estimate the

junction temperature rise. T_Jis calculated from T_Aand P_Dusing

the formula

P

_SW= (C_GATE-P+ C_GATE-N) × V_IN1²× f_SW

(10)

where:

C

_GATE-Pis the P-MOSFET gate capacitance.

_GATE-Nis the N-MOSFET gate capacitance.

T_J= T_A+ (P_D× θ_JA)

(14)

The typical θ_JAvalue for the 24-lead, 4 mm × 4 mm LFCSP is

35°C/W (see Table 6). A very important factor to consider is

that θ_JAis based on a 4-layer, 4 in × 3 in, 2.5 oz copper, as per

JEDEC standard, and real applications may use different sizes

and layers. To remove heat from the device, it is important to

maximize the use of copper. Copper exposed to air dissipates

heat better than copper used in the inner layers. Connect the

exposed pad to the ground plane with several vias.

For the ADP5024, the total of (C_GATE-P+ C_GATE-N) is approx-

imately 150 pF.

The transition losses occur because the P-channel power

MOSFET cannot be turned on or off instantaneously, and the

SW node takes some time to slew from near ground to near

V_OUT1(and from V_OUT1to ground). The amount of transition

loss is calculated by

If the case temperature can be measured, the junction temperature

is calculated by

P

_TRAN= V_IN1× I_OUT1× (t_RISE+ t_FALL) × f_SW

(11)

where t_RISEand t_FALLare the rise time and the fall time of the

switching node, SW. For the ADP5024, the rise and fall times of

SW are in the order of 5 ns.

T_J= T_C+ (P_D× θ_JC)

(15)

where T_Cis the case temperature and θ_JCis the junction-to-case

thermal resistance provided in Table 6.

If the preceding equations and parameters are used for estimating

the converter efficiency, it must be noted that the equations do

not describe all of the converter losses, and the parameter values

given are typical numbers. The converter performance also

depends on the choice of passive components and board layout;

therefore, include a sufficient safety margin in the estimate.

When designing an application for a particular ambient

temperature range, calculate the expected ADP5024 power

dissipation (P_D) due to the losses of all channels by using

Equation 8 to Equation 13. From this power calculation, the

junction temperature, T_J, can be estimated using Equation 14.

LDO Regulator Power Dissipation

The reliable operation of the converter and the LDO regulator

can be achieved only if the estimated die junction temperature of

the ADP5024 (see Equation 14) is less than 125°C. Reliability

and mean time between failures (MTBF) is highly affected by

increasing the junction temperature. Additional information

about product reliability can be found from the ADI Reliability

Handbook, which is available at the following URL:

The power loss of the LDO regulator is given by

P

_DLDO= [(V_IN− V_OUT) × I_LOAD] + (V_IN× I_GND

where:

_LOADis the load current of the LDO regulator.

)

(12)

I

V_INand V_OUTare input and output voltages of the LDO,

respectively.

www.analog.com/reliability_handbook.

I_GNDis the ground current of the LDO regulator.

Power dissipation due to the ground current is small, and it

can be ignored.

The total power dissipation in the ADP5024 simplifies to

P_D= P_DBUCK1+ P_DBUCK2+ P_DLDO

(13)

Rev. A | Page 25 of 28

ADP5024

Data Sheet

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5024 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines. Also, refer to User

Guide UG-271.

•

Maximize the size of ground metal on the component side

to help with thermal dissipation.

Use a ground plane with several vias connected to the

component side ground to further reduce noise

interference on sensitive circuit nodes.

•

Connect VIN1, VIN2, and AVIN together close to the IC

using short tracks.

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

•

Rev. A | Page 26 of 28

Data Sheet

ADP5024

TYPICAL APPLICATION SCHEMATICS

AVIN

HOUSEKEEPING

BUCK1

C_AVIN

0.1µF

VOUT1

L1 1µH

VIN1

EN1

2.3V TO

5.5V

SW1

FB1

V

_OUT1AT

C1

1200mA

4.7µF

C5

10µF

ON

PGND1

EN1

OFF

MODE

PWM

MODE

VOUT2

PSM/PWM

VIN2

EN2

MODE

L2 1µH

SW2

FB2

V_OUT2AT

1200mA

C2

4.7µF

BUCK2

EN2

C6

10µF

PGND2

ON

OFF

VOUT3

FB3

EN3

V

_OUT3AT

EN3

LDO

300mA

VIN3

C7

1µF

1.7V TO

5.5V

(ANALOG)

C3

1µF

ADP5024

AGND

Figure 52. Fixed Output Voltages with Enable Pins

AVIN

HOUSEKEEPING

C_AVIN

0.1µF

VOUT1

L1 1µH

VIN1

EN1

2.3V TO

5.5V

SW1

FB1

V

_OUT1AT

C1

4.7µF

1200mA

R1

R2

BUCK1

MODE

C5

10µF

ON

PGND1

EN1

OFF

PWM

MODE

VOUT2

PSM/PWM

V

VIN2

EN2

MODE

L2 1µH

R3

SW2

FB2

_OUT2AT

1200mA

C2

4.7µF

BUCK2

C6

10µF

R4

EN2

EN3

PGND2

ON

OFF

VOUT3

FB3

EN3

V_OUT3AT

LDO

300mA

R5

R6

VIN3

1.7V TO

5.5V

(ANALOG)

C7

1µF

C3

1µF

ADP5024

AGND

Figure 53. Adjustable Output Voltages with Enable Pins

BILL OF MATERIALS

Table 12.

Reference

Value

Part Number

Vendor

Package or Dimension (mm)

C_AVIN

0.1 µF, X5R, 6.3 V

1 µF, X5R, 6.3 V

4.7 µF, X5R, 6.3 V

10 µF, X5R, 6.3 V

1 µH, 0.18 Ω, 850 mA

1 µH, 0.085 Ω, 1400 mA

1 µH, 0.059 Ω, 900 mA

1 µH, 0.086 Ω, 1350 mA

JMK105BJ104MV-F

LMK105BJ105MV-F

ECJ-0EB0J475M

JMK107BJ106MA-T

BRC1608T1R0M

LQM2MPN1R0NG0B

EPL2014-102ML

MDT2520-CN

Taiyo-Yuden

Panasonic-ECG

Taiyo-Yuden

Murata

Coilcraft

Toko

Analog Devices

0402

0603

C3, C7

C1, C2

C5, C6

L1, L2

0603

2.0 × 1.6 × 0.9

2.0 × 2.0 × 1.4

2.5 × 2.0 × 1.2

24-lead LFCSP

IC1

Three-regulator microPMU ADP5024

Rev. A | Page 27 of 28

ADP5024

Data Sheet

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

0.30

0.25

0.20

PIN 1

INDICATOR

PIN 1

INDICATOR

24

19

0.50

BSC

18

1

6

EXPOSED

PAD

2.20

2.10 SQ

2.00

13

12

7

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.

Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-24-10)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Range

Output

Active

Model¹

Voltage²

UVLO³Pull-Down⁴

Package Description

Package Option

ADP5024ACPZ-R7

−40°C to +125°C Adjustable

Low

Enabled on buck

channels

24-Lead Lead Frame Chip

Scale Package [LFCSP_WQ]

CP-24-10

ADP5024ACPZ-1-R7 −40°C to +125°C VOUT1 = 1.2 V Low

Enabled on buck

channels

24-Lead Lead Frame Chip

Scale Package [LFCSP_WQ]

CP-24-10

VOUT2 = 3.3 V

VOUT3 = 2.8 V

ADP5024CP-EVALZ

Evaluation Board for

ADP5024ACPZ-R7

¹Z = RoHS Compliant Part.

²For additional options, contact a local sales or distribution representative. Additional options available are:

BUCK1 and BUCK2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V or adjustable.

LDO: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, 0.8 V or adjustable.

³UVLO: Low or High.

⁴BUCK1, BUCK2, LDO: active pull-down resistor is programmable to be either enabled or disabled.

registered trademarks are the property of their respective owners.

D09888-0-1/12(A)

Rev. A | Page 28 of 28


型号：	ADP5024ACPZ-1-R7
厂家：	ADI
描述：	Dual 3 MHz, 1200 mA Buck 双3兆赫， 1200毫安巴克
文件：	总28页 (文件大小：993K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP5024ACPZ-1-R7 [ADI]

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