ADP5062ACPZ-1-R7 [ADI]
Linear Li-Ion Battery Charger with Power Path and USB Compatibility in LFCSP;
| 型号： | ADP5062ACPZ-1-R7 |
| 厂家： | 
ADI |
| 描述： | Linear Li-Ion Battery Charger with Power Path and USB Compatibility in LFCSP 电池 |
| 文件： | 总44页 (文件大小：879K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Linear Li-Ion Battery Charger with Power
Path and USB Compatibility in LFCSP
Data Sheet
ADP5062
FEATURES
GENERAL DESCRIPTION
4 mm × 4 mm LFCSP package
Fully programmable via I2C
Flexible digital control inputs
The ADP5062 charger is fully compliant with USB 3.0 and the
USB Battery Charging Specification 1.2 and enables charging
via the mini USB VBUS pin from a wall charger, car charger, or
Up to 2.1 A current from an ac charger in LDO mode
Operating input voltage from 4.0 V to 6.7 V
Tolerant input voltage from −0.5 V to +20 V (USB VBUS)
Fully compatible with USB 3.0 and USB Battery Charging
Specification 1.2
Built-in current sensing and limiting
As low as 54 mΩ battery isolation FET between battery and
charger output
Thermal regulation prevents overheating
Compliant with JEITA 1 and JEITA 2 Li-Ion battery charging
temperature specifications
SYS_EN flag permits the system to be disabled until battery is at
the minimum required level for guaranteed system start-up
USB host port.
The ADP5062 operates from a 4 V to 6.7 V input voltage range
but is tolerant of voltages up to 20 V thereby alleviating concerns
about USB bus spikes during disconnect or connect scenarios.
The ADP5062 features an internal FET between the linear
charger output and the battery. This permits battery isolation
and, hence, system powering under a dead battery or no battery
scenario, which allows for immediate system function on connec-
tion to a USB power supply.
Based on the type of USB source, which is detected by an external
USB detection chip, the ADP5062 can be set to apply the correct
current limit for optimal charging and USB compliance.
The ADP5062 has three factory-programmable digital input/out-
put pins that provide maximum flexibility for different systems.
These digital input/output pins permit combinations of features
such as, input current limits, charging enable and disable, charging
current limits, and a dedicated interrupt output pin.
APPLICATIONS
Digital still cameras
Digital video cameras
Single cell Li-Ion portable equipment
PDAs, audio, and GPS devices
Portable medical devices
Mobile phones
TYPICAL APPLICATION CIRCUIT
ADP5062
SYSTEM
ISO_Sx
VBUS
VIN
AC OR
USB
CBP
C3
22µF
C4
10µF
C1
10nF
SCL
SDA
ISO_Bx
CHARGER
CONTROL
BLOCK
C2
22µF
BAT_SNS
DIG_IO1
DIG_IO2
DIG_IO3
Li-ion
+
THR
SYS_EN
ILED
VLED
AGND
Figure 1.
Rev. B
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Technical Support
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ADP5062
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Battery Isolation FET................................................................. 21
Battery Detection ....................................................................... 21
Battery Pack Temperature Sensing .......................................... 22
I2C Interface ................................................................................ 26
I2C Register Map......................................................................... 27
Register Bit Descriptions........................................................... 28
Applications Information .............................................................. 36
External Components................................................................ 36
PCB Layout Guidelines.............................................................. 38
Power Dissipation and Thermal Considerations ....................... 39
Charger Power Dissipation ....................................................... 39
Junction Temperature ................................................................ 39
Factory-Programmable Options .................................................. 40
Charger Options......................................................................... 40
I2C Register Defaults.................................................................. 41
Digital Input and Output Options ........................................... 41
Packaging and Ordering Information ......................................... 43
Outline Dimensions................................................................... 43
Ordering Guide .......................................................................... 43
Applications....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Recommended Input and Output Capacitances...................... 6
I2C-Compatible Interface Timing Specifications..................... 6
Absolute Maximum Ratings ....................................................... 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Temperature Characteristics..................................................... 12
Typical Waveforms ..................................................................... 14
Theory of Operation ...................................................................... 15
Summary of Operation Modes................................................. 15
Introduction ................................................................................ 16
Charger Modes............................................................................ 18
Thermal Management ............................................................... 21
REVISION HISTORY
10/13—Rev. A to Rev. B
Changes to Table 19........................................................................ 28
Changes to Table 26........................................................................ 32
Changes to Charger Options Section and Table 41 ................... 40
Changes to Ordering Guide .......................................................... 43
4/13—Rev. 0 to Rev. A
Changes to Figure 3.......................................................................... 9
9/12—Revision 0: Initial Version
Rev. B | Page 2 of 44
Data Sheet
ADP5062
SPECIFICATIONS
−40°C < TJ < +125°C, VVINx = 5.0 V, RHOT_RISE < RTHR < RCOLD_FALL, VBAT_SNS = 3.6 V, V ISO_Bx = VBAT_SNS, CVIN = 10 µF, CISO_S = 22 µF, CISO_B = 22 µF,
C
CBP = 10 nF, all registers at default values, unless otherwise noted.
Table 1.
Parameter
Symbol
VUVLO
ILIM
Min
Typ
Max
Unit
Test Conditions/Comments
GENERAL PARAMETERS
Undervoltage Lockout
Hysteresis
1
2.25
50
2.35
100
92
2.5
V
Falling threshold, higher of VVINx and VBAT_SNS
Hysteresis, higher of VVINx and VBAT_SNS rising1
Nominal USB initialized current level2
USB super speed
USB enumerated current level (specification for
China)
150
100
150
300
mV
mA
mA
mA
Total Input Current
74
114
425
470
500
900
1500
mA
mA
mA
mA
µA
USB enumerated current level
Dedicated charger input
Dedicated wall charger
Charging or LDO mode
DIS_IC1 = high, VISO_Bx < VINx < 5.5 V
LDO mode, VISO_Sx > VBAT_SNS
VINx Current Consumption
Battery Current Consumption
IQVIN
IQVIN_DIS
IQBATT
2
280
20
450
µA
5
µA
Standby, includes ISO_Sx pin leakage, VVINx = 0 V,
TJ = −40°C to +85°C
0.5
0.9
mA
mA
Standby, battery monitor active
CHARGER
Fast Charge Current CC Mode
ICHG
700
750
790
VISO_Bx = 3.9 V; fast charge current accuracy is
guaranteed at temperatures from TJ = −40°C to the
isothermal regulation limit (typically TJ = +115°C)2, 3
Fast Charge Current Accuracy
−8
+7
%
ICHG = 400 mA to 1300 mA
ICHG = 250 mA to 350 mA
ICHG = 50 mA to 200 mA
−33
−45
16
+29
+40
25
mA
mA
mA
mA
Trickle Charge Current2
Weak Charge Current2, 3
Trickle to Weak Charge Threshold
Dead Battery
ITRK_DEAD
ICHG_WEAK
20
ITRK_DEAD + ICHG
2, 4
VTRK_DEAD
2.4
2.5
2.6
V
VTRK_DEAD < VBAT_SNS < VWEAK
On BAT_SNS2
Hysteresis
ΔVTRK_DEAD
100
mV
Weak Battery Threshold
Weak to Fast Charge Threshold
On BAT_SNS2, 4
VWEAK
ΔVWEAK
VTRM
2.89
3.0
3.11
V
100
4.200
mV
V
%
Battery Termination Voltage
Termination Voltage Accuracy
On BAT_SNS, TJ = 25°C, IEND = 52.5 mA2
TJ = 0°C to 115°C2
−0.25
−1.04
−1.16
+0.25
+0.89
+1.20
%
%
TJ = −40°C to +125°C
Battery Overvoltage Threshold
Charge Complete Current
Charging Complete Current Threshold
Accuracy
VBATOV
IEND
VIN − 0.075
52.5
V
mA
mA
Relative to VINx voltage, BAT_SNS rising
VBAT_SNS = VTRM
IEND = 52.5 mA, TJ = 0°C to 115°C2
15
17
98
83
59
160
2.2
123
390
2.5
mA
mV
V
IEND = 92.5 mA, TJ = 0°C to 115°C
Relative to VTRM, BAT_SNS falling2
Recharge Voltage Differential
Battery Node Short Threshold Voltage2
Battery Short Detection Current
Charging Start Voltage Limit
Charging Soft Start Current
VRCH
260
2.4
20
VBAT_SHR
ITRK_SHORT
VCHG_VLIM
ICHG_START
tCHG_START
2
mA
V
mA
ms
ITRK_SHORT = ITRK_DEAD
3.6
185
3.7
260
3
3.8
365
Voltage limit is not active by default
VBAT_SNS > VTRK_DEAD
Charging Soft Start Timer
Rev. B | Page 3 of 44
ADP5062
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
BATTERY ISOLATION FET
Pin to Pin Resistance Between ISO_Sx
and ISO_Bx
RDSON_ISO
VISO_SFC
VTHISO
54
89
mΩ
On battery supplement mode, VINx = 0 V, VISO_Bx
=
4.2 V, IISO_Bx = 500 mA
Regulated System Voltage: VBAT Low
3.6
3.2
0
3.8
3.4
5
4.0
3.5
12
V
V
mV
VTRM[5:0] programming ≥ 4.00 V
VTRM[5:0] programming < 4.00 V
Battery Supplementary Threshold
LDO AND HIGH VOLTAGE BLOCKING
Regulated System Voltage
VISO_Sx < VISO_Bx, VSYS rising
VISO_STRK
4.214
4.3
4.386
485
4.0
V
VSYSTEM[2:0] = 000 (binary) = 4.3 V, IISO_Sx
100 mA, LDO mode2
=
Load Regulation
High Voltage Blocking FET (LDO FET)
On Resistance
Maximum Output Current
VINx Input Voltage, Good Threshold
Rising
VINx Falling
VINx Input Overvoltage Threshold
Hysteresis
−0.56
330
%/A
mΩ
IISO_Sx = 0 m A to 1500 mA
IVINx = 500 mA
RDS(ON)HV
2.1
3.9
A
V
VISO_Sx = 4.3 V, LDO mode
VVIN_OK_RISE
3.75
6.7
VVIN_OK_FALL
VVIN_OV
ΔVVIN_OV
TVIN_RISE
3.6
6.9
0.1
3.7
7.2
V
V
V
µs
µs
VINx Transition Timing
10
10
Minimum rise time for VINx from 5 V to 20 V
Minimum fall time for VINx from 4 V to 0 V
TVIN_FALL
THERMAL CONTROL
Isothermal Charging Temperature
Thermal Early Warning Temperature
Thermal Shutdown Temperature
TLIM
TSDL
TSD
115
130
140
110
°C
°C
°C
°C
TJ rising
TJ falling
THERMISTOR CONTROL
Thermistor Current
10,000 NTC
100,000 NTC
INTC_10k
INTC_100k
CNTC
400
40
μA
μA
pF
°C
Thermistor Capacitance
Cold Temperature Threshold
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
Hot Temperature Threshold
Resistance Thresholds
Hot to Typical Resistance
Typical to Hot Resistance
100
0
TNTC_COLD
No battery charging occurs
No battery charging occurs
RCOLD_FALL
RCOLD_RISE
TNTC_HOT
20,500
25,600
24,400
60
30,720
Ω
Ω
°C
RHOT_FALL
RHOT_RISE
3700
3350
Ω
Ω
2750
3950
JEITA1 Li-ION BATTERY CHARGING
SPECIFICATION DEFAULTS5
JEITA Cold Temperature
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
JEITA Cool Temperature
TJEITA_COLD
0
°C
No battery charging occurs
RCOLD_FALL
RCOLD_RISE
TJEITA_COOL
20,500
13,200
25,600
24,400
10
30,720
19,800
Ω
Ω
°C
Battery charging occurs at 50% of programmed
level
Resistance Thresholds
Typical to Cool Resistance
Cool to Typical Resistance
JEITA Warm Temperature
RTYP_FALL
RTYP_RISE
TJEITA_WARM
16,500
15,900
45
Ω
Ω
°C
Battery termination voltage (VTRM) is reduced by
100 mV
Resistance Thresholds
Warm to Typical Resistance
Typical to Warm Resistance
RWARM_FALL
RWARM_RISE
5800
5200
Ω
Ω
4260
6140
Rev. B | Page 4 of 44
Data Sheet
ADP5062
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
JEITA Hot Temperature
Resistance Thresholds
Hot to Warm Resistance
Warm to Hot Resistance
TJEITA_HOT
60
°C
No battery charging occurs
RHOT_FALL
RHOT_RISE
3700
3350
Ω
Ω
2750
3950
JEITA2 Li-ION BATTERY CHARGING
SPECIFICATION DEFAULTS5
JEITA Cold Temperature
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
JEITA Cool Temperature
TJEITA_COLD
0
°C
No battery charging occurs
RCOLD_FALL
RCOLD_RISE
TJEITA_COOL
20,500
13,200
25,600
24,400
10
30,720
19,800
Ω
Ω
°C
Battery termination voltage (VTRM) is reduced by
100 mV
Resistance Thresholds
Typical to Cool Resistance
Cool to Typical Resistance
JEITA Warm Temperature
RTYP_FALL
RTYP_RISE
TJEITA_WARM
16,500
15,900
45
Ω
Ω
°C
Battery termination voltage (VTRM) is reduced by
100 mV
Resistance Thresholds
Warm to Typical Resistance
Typical to Warm Resistance
JEITA Hot Temperature
Resistance Thresholds
Hot to Warm Resistance
Warm to Hot Resistance
BATTERY DETECTION
Sink Current
RWARM_FALL
RWARM_RISE
TJEITA_HOT
5800
5200
60
Ω
Ω
°C
4260
2750
6140
3950
No battery charging occurs
RHOT_FALL
RHOT_RISE
3700
3350
Ω
Ω
ISINK
ISOURCE
13
7
20
10
34
13
mA
mA
Source Current
Battery Threshold
Low
High
Battery Detection Timer
TIMERS
VBATL
VBATH
tBATOK
1.8
1.9
3.4
333
2.0
V
V
ms
Clock Oscillator Frequency
Start Charging Delay
Trickle Charge
Fast Charge
Charge Complete
Deglitch
fCLK
tSTART
tTRK
tCHG
tEND
tDG
2.7
3
1
60
600
7.5
31
3.3
MHz
sec
min
min
min
ms
VBAT_SNS = VTRM, ICHG < IEND
Applies to VTRK_DEAD, VRCH, IEND, VWEAK, VVIN_OK_RISE, and
VVIN_OK_FALL
Watchdog2
Safety
Battery Short2
ILED OUTPUT PINS
Voltage Drop over ILED
tWD
32
40
30
sec
min
sec
tSAFE
tBAT_SHR
36
44
VILED
VMAXILED
200
mV
V
IILED = 20 mA
Maximum Operating Voltage over
ILED
5.5
SYS_EN OUTPUT PIN
SYS_EN FET On Resistance
RON_SYS_EN
10
Ω
ISYS_EN = 20 mA
Rev. B | Page 5 of 44
ADP5062
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUT PINS
Maximum Voltage on Digital Inputs
Maximum Logic Low Input Voltage
Minimum Logic High Input Voltage
Pull-Down Resistance
VDIN_MAX
VIL
VIH
5.5
0.5
V
V
V
kΩ
Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Applies to DIG_IO1, DIG_IO2, DIG_IO3
1.2
215
350
610
1 Undervoltage lockout generated normally from ISO_Sx or ISO_Bx; in certain transition cases, it can be generated from VINx.
2 These values are programmable via I2C. Values are given with default register values.
3 The output current during charging may be limited by the input current limit or by the isothermal charging mode.
4 During weak charging mode, the charger provides at least 20 mA of charging current via the trickle charge branch to the battery unless trickle charging is disabled.
Any residual current that is not required by the system is also used to charge the battery.
5 Either JEITA1 (default) or JEITA2 can be selected in I2C, or both JEITA functions can be enabled or disabled in I2C.
RECOMMENDED INPUT AND OUTPUT CAPACITANCES
Table 2.
Parameter
CAPACITANCES
VINx
CBP
ISO_Sx
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
CVINx
CCBP
CISO_Sx
CISO_Bx
4
6
10
10
10
14
100
μF
nF
μF
μF
Effective capacitance
Effective capacitance
Effective capacitance
Effective capacitance
10
22
22
ISO_Bx
I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Table 3.
Parameter1
Symbol
Min
Typ
Max
Unit
I2C-COMPATIBLE INTERFACE2
Capacitive Load for Each Bus Line
SCL Clock Frequency
SCL High Time
SCL Low Time
CS
fSCL
400
400
pF
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
ns
ns
tHIGH
tLOW
tSU, DAT
tHD, DAT
tSU, STA
tHD, STA
tBUF
tSU, STO
tR
tF
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20
20
0
Data Setup Time
Data Hold Time
0.9
Setup Time for Repeated Start
Hold Time for Start/Repeated Start
Bus Free Time Between a Stop and a Start Condition
Setup Time for Stop Condition
Rise Time of SCL/SDA
300
300
50
Fall Time of SCL/SDA
Pulse Width of Suppressed Spike
tSP
1 Guaranteed by design.
2 A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2).
Rev. B | Page 6 of 44
Data Sheet
ADP5062
Timing Diagram
SDA
tF
tSP
tR
tBUF
tLOW
tR
tSU, DAT
tF
tHD, STA
SCL
tSU, STO
tSU, STA
tHIGH
tHD, DAT
S
Sr
P
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Figure 2. I2C Timing Diagram
Rev. B | Page 7 of 44
ADP5062
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Maximum Power Dissipation
Table 4. Absolute Maximum Ratings
Parameter
The maximum safe power dissipation in the ADP5062 package
is limited by the associated rise in junction temperature (TJ) on
the die. At a die temperature of approximately 150°C (the glass
transition temperature), the properties of the plastic change.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, thereby perma-
nently shifting the parametric performance of the ADP5062.
Exceeding a junction temperature of 175°C for an extended
period can result in changes in the silicon devices, potentially
causing failure.
Rating
VIN1, VIN2, VIN3 to AGND
All Other Pins to AGND
Continuous Drain Current, Battery Supple-
mentary Mode, from ISO_Bx to ISO_Sx
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
–0.5 V to +20 V
–0.3 V to +6 V
2.1 A
–65°C to +150°C
–40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is
specified for a device soldered in a circuit board for surface-
mount packages.
Table 5. Thermal Resistance
Package Type
θJA
θJC
Unit
20-Lead LFCSP
35.6
3.65
°C/W
Rev. B | Page 8 of 44
Data Sheet
ADP5062
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
SCL
DIG_IO3
DIG_IO2
BAT_SNS
DIG_IO1
1
2
3
4
5
15 ILED
14 ISO_B3
13 ISO_B2
12 ISO_B1
11 ISO_S3
ADP5062
TOP VIEW
(Not to Scale)
NOTES
1. CONNECTION OF THE EXPOSED PAD IS NOT REQUIRED. THE
EXPOSED PAD CAN BE CONNECTED TO ANALOG GROUND TO
IMPROVE HEAT DISSIPATION FROM THE PACKAGE TO BOARD.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Name
Type1 Description
9, 10, 11
ISO_S1, ISO_S2,
ISO_S3
I/O
Linear Charger Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. High
current input/output.
6, 7, 8
20
VIN1, VIN2, VIN3 I/O
AGND
Power Connections to USB VBUS. These pins are high current inputs when in charging mode.
Analog Ground.
G
12, 13, 14
ISO_B1, ISO_B2, I/O
ISO_B3
Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET.
1
17
5
SCL
SDA
DIG_IO1
I
I2C-Compatible Interface Serial Clock.
I2C-Compatible Interface Serial Data.
Set Input Current Limit. This pin sets the input current limit directly. When DIG_IO1 = low or
high-Z, the input limit is 100 mA. When DIG_IO1 = high, the input limit is 500 mA.2, 3
I/O
GPIO
3
DIG_IO2
GPIO
Disable IC1. The DIG_IO2 pin sets the charger to the low current mode. When DIG_IO2 = low or
high-Z, the charger operates in normal mode. When DIG_IO2 = high, the LDO and the charger are
disabled and VINx current consumption is 280 µA (typical). In addition, when DIG_IO2 is high,
20 V VINx input protection is disabled and the VINx voltage level must fulfill the condition,
V
ISO_Bx < VVINx < 5.5 V.2, 3
2
DIG_IO3
THR
GPIO
I
Enable Charging. When DIG_IO3 = low or high-Z, charging is disabled. When DIG_IO3 = high,
charging is enabled.2, 3
Battery Pack Thermistor Connection. If this pin is not used, connect a dummy 10 kΩ resistor from
THR to GND.
18
4
15
16
BAT_SNS
ILED
SYS_EN
I
O
O
Battery Voltage Sense Pin.
Open-Drain Output to Indicator LED.
System Enable. This pin is the battery OK flag/open-drain pull-down FET to enable the system
when the battery reaches the VWEAK level.
19
N/A4
CBP
EP
I/O
N/A4
Bypass Capacitor Input.
Exposed Pad. Connection of the exposed pad is not required. The exposed pad can be connected
to analog ground to improve heat dissipation from the package to the board.
1 I is input, O is output, I/O is input/output, G is ground, and GPIO is the factory programmable general-purpose input/output.
2 See the Digital Input and Output Options section for details.
3 The DIG_IOx setting defines the initial state of the ADP5062. If the parameter or the mode that is related to each DIG_IOx pin setting is changed (by programming an
equivalent I2C register bit or bits), the I2C register setting takes precedence over the DIG_IOx pin setting. VINx connection or disconnection resets control to the
DIG_IOx pin.
4 N/A means not applicable.
Rev. B | Page 9 of 44
ADP5062
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VVINx = 5.0 V, C VINx = 10 µF, CISO_Sx = 44 µF, CISO_Bx = 22 µF, CCBP = 10 nF, all registers at default values, unless otherwise noted.
4.40
4.38
4.36
4.34
4.32
4.30
4.28
4.26
4.24
4.22
4.20
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
0.01
0.1
1
0.01
0.1
1
SYSTEM OUTPUT CURRENT (A)
SYSTEM OUTPUT CURRENT (A)
Figure 7. System Voltage vs. System Output Current, LDO Mode, VVINx = 6.0 V,
VSYSTEM[2:0] = 111 (Binary) = 5.0 V
Figure 4. System Voltage vs. System Output Current, LDO Mode,
VSYSTEM[2:0] = 000 (Binary) = 4.3 V
4.5
5.4
LOAD = 100mA
LOAD = 100mA
LOAD = 500mA
LOAD = 500mA
4.4
5.2
LOAD = 1000mA
LOAD = 1000mA
5.0
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
4.0
4.4
4.8
5.2
5.6
6.0
6.4
6.8
4.0
4.4
4.8
5.2
5.6
6.0
6.4
6.8
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 5. System Voltage vs. Input Voltage (in Dropout), LDO Mode,
VSYSTEM[2:0] = 000 (Binary) = 4.3 V
Figure 8. System Voltage vs. Input Voltage (in Dropout), LDO Mode,
VSYSTEM[2:0] = 111 (Binary) = 5.0 V
1000
900
700
WEAK
600
CHARGE
800
500
700
600
500
400
300
200
100
0
LIMIT = 900mA
LIMIT = 500mA
LIMIT = 100mA
FAST CHARGE
400
300
200
TRICKLE CHARGE
100
0
2.3
2.7
3.2
3.7
4.2
2.8
3.3
3.8
4.3
BATTERY VOLTAGE (V)
BATTERY VOLTAGE (V)
Figure 6. Input Current-Limited Charge Current vs. Battery Voltage
Figure 9. Battery Charge Current vs. Battery Voltage, ICHG[4:0] = 01001
(Binary) = 500 mA, ILIM[3:0] = 1111 (Binary) = 2100 mA
Rev. B | Page 10 of 44
Data Sheet
ADP5062
70
65
60
55
50
45
70
65
60
55
50
45
40
40
2.7
0
0.5
1.0
1.5
2.0
3.2
3.7
4.2
LOAD CURRENT (A)
BATTERY VOLTAGE (V)
Figure 10. Ideal Diode RON vs. Battery Voltage, IISO_Sx = 500 mA, VINx Open
Figure 12. Ideal Diode RON vs. Load Current, VISO_Bx = 3.6 V
4.0
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
0.7
DEFAULT STARTUP
DIS_LDO = HIGH
DIS_IC1 = HIGH
V
I
BAT_SNS
ISO_Bx
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
4
6
8
0
50
100
150
VINx VOLTAGE (V)
CHARGE TIME (min)
Figure 11. VINx Current vs. VINx Voltage, No Battery
Figure 13. Charge Profile, ILIM[3:0] = 0110 (Binary) = 500 mA, Battery
Capacity = 925 mAh
Rev. B | Page 11 of 44
ADP5062
Data Sheet
TEMPERATURE CHARACTERISTICS
1.5
0.5
0.4
V
V
V
= 3.6V
= 4.2V
= 5.5V
ISO_Bx
ISO_Bx
ISO_Bx
V
V
= 4.3V
= 5.0V
ISO_Sx
ISO_Sx
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–40
–15
10
35
60
85
–40 –25 –10
5
20
35
50
65
80
95 110 125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 14. Battery Leakage Current vs. Ambient Temperature
Figure 17. System Voltage vs. Temperature, Trickle Charge Mode,
ISO_Sx = 4.3 V and VINx = 5.0 V, or VISO_Sx = 5.0 V and VINx = 6.0 V
V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
V
V
= 4.0V
= 5.0V
= 5.5V
V
V
V
= 4.0V
= 5.0V
= 6.7V
IN
IN
IN
IN
IN
IN
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40 –25 –10
5
20
35
50
65
80
95 110 125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 18. VINx Quiescent Current vs. Ambient Temperature, LDO Mode
Figure 15. VINx Quiescent Current vs. Ambient Temperature, DIS_IC1 = High
0.5
0.5
V
V
V
= 3.8V
= 4.2V
= 4.5V
V
V
= 4.3V
= 5.0V
TRM
TRM
TRM
ISO_Sx
ISO_Sx
0.4
0.3
0.4
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40 –25 –10
5
20
35
50
65
80
95 110 125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 19. Termination Voltage vs. Ambient Temperature
Figure 16. LDO Mode Voltage vs. Ambient Temperature,
Load = 100 mA, VVINx = 5.5 V
Rev. B | Page 12 of 44
Data Sheet
ADP5062
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
I
= 1300mA
CHG
I
= 1500mA
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
LIM
I
I
I
= 900mA
= 500mA
= 100mA
LIM
LIM
LIM
I
I
= 750mA
CHG
= 500mA
–15
CHG
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40
10
35
60
85
110
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 20. Fast Charge CC Mode Current vs. Ambient Temperature
Figure 22. Input Current Limit vs. Ambient Temperature
7.00
6.95
6.90
6.85
6.80
–40 –25 –10
5
20
35
50
65
80
95 110 125
AMBIENT TEMPERATURE (°C)
Figure 21. VINx Overvoltage Threshold vs. Ambient Temperature
Rev. B | Page 13 of 44
ADP5062
Data Sheet
TYPICAL WAVEFORMS
T
T
V
ISO_Sx
VINx
V
V
ISO_Sx
V
VINx
4
1
4
1
I
ISO_Bx
I
ISO_Bx
I
VINx
2
2
I
VINx
3
3
CH1 2.00V
CH3 200mA CH4 2.00V
CH2 200mA
M200.0µs
A
CH2
216mA
CH1 2.00V
CH3 200mA CH4 2.00V
CH2 200mA
M1.00ms
1.00ms
A
CH2
120mA
T
0.00s
T
Figure 26. USB VBUS Disconnect
Figure 23. Charging Startup, VVINx = 5.0 V, ILIM[3:0] = 0110 (Binary) = 500 mA,
ICHG[4:0] = 01110 (Binary) = 750 mA
V
ISO_Sx
T
T
V
ISO_Sx
1
I
I
ISO_Bx
1
2
I
ISO_Sx
ISO_Sx
2
CH1 1.00V
CH3 500mA
CH2 500mA
M1.0ms
3.00ms
A
CH2
–610mA
CH1 100mV CH2 500mA
M1.00ms
3.00ms
A
CH2
820mA
T
T
Figure 27. Load Transient, IISO_Sx Load = 300 mA to 1500 mA to 300 mA,
EN_CHG = High, ILIM[3:0] = 0110 (Binary) = 500 mA
Figure 24. Load Transient, IISO_Sx Load = 300 mA to 1500 mA to 300 mA
T
T
V
ISO_Sx
2
1
V
VINx
V
ISO_Bx
2
3
I
ISO_Bx
I
ISO_Bx
3
4
I
VINx
CH2 2.00V
M200ms
0.00s
A
CH3
17.2mA
CH1 200mV CH2 200mV
CH3 500mA CH4 500mA
M40.0µs
0.00s
A
CH3
610mA
CH3 10.0mA
T
T
Figure 28. Battery Detection Waveform, VSYSTEM[2:0] = 000 (Binary) = 4.3 V,
No Battery
Figure 25. Input Current-Limit Transition from 100 mA to 900 mA,
ISO_Sx Load = 66 Ω, Charging = 750 mA
Rev. B | Page 14 of 44
Data Sheet
ADP5062
THEORY OF OPERATION
SUMMARY OF OPERATION MODES
Table 7. Summary of the ADP5062 Operation Modes
VINx
Trickle
Charge
LDO FET Battery
System Voltage
ISO_Sx
Mode Name
Condition
Battery Condition
State
Isolation FET
Additional Conditions1
IC Off, Standby
0 V
Any battery condition
Off
Off
On/Off
Battery voltage
or 0 V
Disable IC1
IC Off, Suspend
LDO Mode Off, Isolation
FET On
5 V
5 V
Any battery condition
Any battery condition
Off
Off
Off
Off
On
On
Battery voltage
Battery voltage
Disable IC1
Disable LDO and enable
isolation FET
LDO Mode Off, Isolation
FET Off (System Off)
5 V
Any battery condition
Off
Off
Off
0 V
Enable battery charging
LDO Mode, Charger Off
Trickle Charge Mode
Weak Charge Mode
Fast Charge Mode
Charge Mode, No Battery
Charge Mode, Battery
(ISO_Bx) Shorted
5 V
5 V
5 V
5 V
5 V
5 V
Any battery condition
Battery < VTRK_DEAD
VTRK_DEAD ≤ battery < VWEAK
Battery ≥ VWEAK
Open
Off
On
On
Off
Off
On
LDO
LDO
CHG
CHG
LDO
LDO
Off
Off
CHG
CHG
Off
5.0 V
5.0 V
3.8 V
3.8 V (minimum)
5.0 V
Enable battery charging
Enable battery charging
Enable battery charging
Enable battery charging
Enable battery charging
Enable battery charging
Shorted
Off
5.0 V
1 See Table 8 for details.
Table 8. Operation Mode Controls
Equivalent I2C
Address, Data Bit(s) Description
Pin Configuration
DIG_IOx
Enable Battery Charging
DIG_IO3
0x07, D0
Low = all charging modes disabled (fast, weak, trickle).
High = all charging modes enabled (fast, weak, trickle).
VINx1 Supply
Disable IC1
DIG_IO2
0x07, D6
Disable IC1
Connected
LDO_FET ISO_FET
Low
No
Off
On
Yes
No2
Yes
CHG
Off
Off
CHG
On
On
High
Disable LDO and Enable Isolation FET
0x07, D3, D0
Low = LDO enabled.
High = LDO disabled. In addition, when EN_CHG = low, the
battery isolation FET is on; when EN_CHG = high, the battery
isolation FET is off.
1 When disable IC1 mode is active, the VINx supply must always be connected and the supply voltage level must fulfill the following condition: VISO_Bx < VINx < 5.5 V.
2 When disable IC1 mode is active, the back gate of the LDO FET is not controlled. If the VINx pins are not connected to any voltage supply, the body diode of the LDO
FET can become forward biased and the voltage at VINx is VISO_Bx – VF (VF is the forward voltage of the LDO FET body diode).
Rev. B | Page 15 of 44
ADP5062
Data Sheet
by an external USB detection device, the ADP5062 can be set to
apply the correct current limit for optimal charging and USB
compliance. The USB charger permits correct operation under
all USB compliant sources such as wall chargers, host chargers,
hub chargers, and standard host and hubs.
A processor can control the USB charger using the I2C to
program the charging current and numerous other parameters,
including
INTRODUCTION
The ADP5062 is a fully-programmable I2C charger for single
cell lithium-ion or lithium-polymer batteries suitable for a wide
range of portable applications.
The linear charger architecture enables up to 2.1 A output
current at 4.3 V to 5.0 V (I2C programmable) on the system
power supply, and up to 1.3 A charge current into the battery
from a dedicated charger.
•
•
•
•
•
•
•
•
•
•
•
•
Trickle charge current level
The ADP5062 operates from an input voltage of 4 V up to 6.7 V
but is tolerant of voltages of up to 20 V. The 20 V voltage tolerance
alleviates the concerns of the USB bus spiking during discon-
nection or connection scenarios.
Trickle charge voltage threshold
Weak charge (constant current) current level
Fast charge (constant current) current level
Fast charge (constant voltage) voltage level at 1% accuracy
Fast charge safety timer period
Watchdog safety timer parameters
Weak battery threshold detection
Charge complete threshold
Recharge threshold
Charge enable/disable
Battery pack temperature detection and automatic charger
shutdown
The ADP5062 features an internal FET between the linear charger
output and the battery. This feature permits battery isolation
and, hence, system powering under a dead battery or no battery
scenario, which allows for immediate system function upon
connection to a USB power supply.
The ADP5062 is fully compliant with USB 3.0 and the USB
Battery Charging Specification 1.2. The ADP5062 is chargeable
via the mini USB VBUS pin from a wall charger, car charger, or
USB host port. Based on the type of USB source, which is detected
Rev. B | Page 16 of 44
Data Sheet
ADP5062
ISO_S1
ISO_S2
ISO_S3
VIN1
HIGH VOLTAGE
BLOCKING
LDO FET
6
9
TO USB VBUS
OR WALL
TO SYSTEM
LOAD
ADAPTER
VIN2
VIN3
10
7
8
+
11
+
–
LDO FET
CONTROL
VIN LIMIT
–
6.85V
VIN
OVERVOLTAGE
CBP
BATTERY
ISOLATION FET
19
TRICKLE
CURRENT
SOURCE
+
–
3.9V
3MHz OSC
ISO_B1
ISO_B2
ISO_B3
12
13
14
+
–
VIN GOOD
EOC
SCL
SDA
1
CHARGE CONTROL
+
–
17
CV MODE
RECHARGE
2
I C INTERFACE
DIG_IO1
DIG_IO2
DIG_IO3
AND
5
3
2
CONTROL LOGIC
+
–
WEAK
BATTERY
DETECTION
SINK
+
–
TRICKLE
BATTERY:
OPEN
BAT_SNS
4
+
–
SHORT
3.4V
1.9V
SYS_EN
16
BATTERY DETECTION
+
SYS_EN OUTPUT
LOGIC
–
VIN – 150mV
BATTERY OVERVOLTAGE
COLD
ILED
15
COOL
ILED OUTPUT
LOGIC
NTC CURRENT
CONTROL
WARM
HOT
THR
+
–
18
0.5V
THERMAL CONTROL
AGND
20
SINGLE
CELL
Li-Ion
Figure 29. Block Diagram
Rev. B | Page 17 of 44
ADP5062
Data Sheet
The ADP5062 includes a number of significant features to
optimize charging and functionality including
Table 9. DIG_IO1 Operation
DIG_IO1
Function
0
100 mA input current limit or I2C programmed
value
•
•
•
•
Thermal regulation for maximum performance.
USB host current limit.
Termination voltage accuracy: 1%.
Battery thermistor input with automatic charger shutdown
in the event that the battery temperature exceeds limits
(compliant with the JEITA Li-Ion battery charging
temperature specification).
1
500 mA input current limit or I2C programmed
value (or reprogrammed I2C value from 100 mA
default)
USB Compatibility
The ADP5062 features an I2C-programmable input current
limit to ensure compatibility with the requirements listed in
Table 10. The current limit defaults to 100 mA to allow com-
patibility with a USB host or hub that is not configured.
The I2C register default is 100 mA. An I2C write command to
the ILIM register overrides the DIG_IOx pins and the I2C
register default value can be reprogrammed for alternative
requirements.
•
Three external pins (DIG_IO1, DIG_IO2, and DIG_IO3)
that directly control a number of parameters. These pins
are factory programmable for maximum flexibility. They
can be factory programmed for functions such as
•
•
•
•
•
Enable/disable charging.
Control of 100 mA or 500 mA input current limit.
Control of 1500 mA input current limit.
Control of the battery charge current.
Interrupt output pin.
When the input current-limit feature is used, the available input
current may be too low for the charger to meet the programmed
charging current, ICHG, thereby reducing the rate of charge and
setting the VIN_ILIM flag.
See the Digital Input and Output Options section for details.
CHARGER MODES
Input Current Limit
The VINx input current limit is controlled via the internal I2C
ILIM bits. The input current limit can also be controlled via the
DIG_IO1 pin (if factory programmed to do so) as outlined in
Table 9. Any change in the I2C default from 100 mA takes
precedence over the pin setting.
When connecting voltage to VINx without the proper voltage
level on the battery side, the high voltage blocking mechanism
is in a state wherein it draws only the current of <1 mA until
VIN reaches the VIN_OK level.
The ADP5062 charger provides support for the following con-
nections through the single connector VINx pin, as shown in
Table 10.
Table 10. Input Current Compatibility with Standard USB Limits
Mode
Standard USB Limit
ADP5062 Function
USB (China Only)
100 mA limit for standard USB host or hub
300 mA limit for Chinese USB specification
100 mA limit for standard USB host or hub
500 mA limit for standard USB host or hub
150 mA limit for superspeed USB 3.0 host or hub
100 mA input current limit or I2C programmed value
300 mA input current limit or I2C programmed value
100 mA input current limit or I2C programmed value
500 mA input current limit or I2C programmed value
150 mA input current limit or I2C programmed value
USB 2.0
USB 3.0
900 mA limit for superspeed, high speed USB host or hub
charger
900 mA input current limit or I2C programmed value
Dedicated Charger 1500 mA limit for dedicated charger or low/full speed USB host
or hub charger
1500 mA input current limit or I2C programmed value
Rev. B | Page 18 of 44
Data Sheet
ADP5062
Trickle Charge Mode
Fast Charge Mode (Constant Current)
A deeply discharged Li-Ion cell can exhibit a very low cell voltage
making it unsafe to charge the cell at high current rates. The
ADP5062 charger uses a trickle charge mode to reset the battery
pack protection circuit and lift the cell voltage to a safe level for
fast charging. A cell with a voltage below VTRK_DEAD is charged
with the trickle mode current, ITRK_DEAD. During trickle charging
mode, the CHARGER_STATUS bits are set.
When the battery voltage exceeds VTRK_DEAD and VWEAK, the
charger switches to fast charge mode, charging the battery with
the constant current, ICHG. During fast charge mode (constant
current), the CHARGER_STATUS bits are set to 010.
During constant current mode, other features may prevent the
current, ICHG, from reaching its full programmed value. Isothermal
charging mode or input current limiting for USB compatibility
can affect the value of ICHG under certain operating conditions.
The voltage on ISO_Sx is regulated to stay at VISO_SFC by the
During trickle charging, the ISO_Sx node is regulated to VISO_STRK
by the LDO and the battery isolation FET is off, which means
that the battery is isolated from the system power supply.
battery isolation FET when VISO_Bx < VISO_SFC
.
Trickle Charge Mode Timer
Fast Charge Mode (Constant Voltage)
The duration of trickle charge mode is monitored to ensure that
the battery is revived from its deeply discharged state. If trickle
charge mode runs for longer than 60 minutes without the cell
voltage reaching VTRK_DEAD, a fault condition is assumed and
charging stops. The fault condition is asserted on the CHARGER_
STATUS bits, allowing the user to initiate the fault recovery
procedure specified in the Fault Recovery section.
As the battery charges, its voltage rises and approaches the termi-
nation voltage, VTRM. The ADP5062 charger monitors the voltage
on the BAT_SNS pin to determine when charging should end.
However, the internal ESR of the battery pack combined with
the printed circuit board (PCB) and other parasitic series
resistances creates a voltage drop between the sense point at the
BAT_SNS pin and the cell terminal. To compensate for this and to
ensure a fully charged cell, the ADP5062 enters a constant voltage
charging mode when the termination voltage is detected on the
BAT_SNS pin. The ADP5062 reduces charge current gradually as
the cell continues to charge, maintaining a voltage of VTRM on the
BAT_SNS pin. During fast charge mode (constant voltage), the
CHARGER_ STATUS[2:0] bits are set to 011.
Weak Charge Mode (Constant Current)
When the battery voltage exceeds VTRK_DEAD but is less than
V
WEAK, the charger switches to intermediate charge mode.
During the weak charge mode, the battery voltage is too low to
allow the full system to power-up. Because of the low battery
level, the USB transceiver cannot be powered and, therefore,
cannot enumerate for more current from a USB host. Conse-
quently, the USB limit remains at 100 mA.
Fast Charge Mode Timer
The duration of fast charge mode is monitored to ensure that
the battery is charging correctly. If the fast charge mode runs
for longer than tCHG without the voltage at the BAT_SNS pin
reaching VTRM, a fault condition is assumed and charging stops.
The fault condition is asserted on the CHARGER_STATUS[2:0]
bits, allowing the user to initiate the fault recovery procedure as
specified in the Fault Recovery section.
The system microcontroller may or may not be powered by the
charger output voltage (VISO_SFC), depending upon the amount
of current that the microcontroller and/or the system architecture
requires. When the ISO_Sx pins power the microcontroller, the
battery charge current (ICHG_WEAK) cannot be increased above
20 mA to ensure microcontroller operation (if doing so), nor
can ICHG_WEAK be increased above the 100 mA USB limit. There-
fore, set the battery charging current as follows:
If the fast charge mode runs for longer than tCHG, and VTRM has
been reached on the BAT_SNS pin but the charge current has
not yet fallen below IEND, charging stops. No fault condition is
asserted in this circumstance and charging resumes as normal if
the recharge threshold is breached.
•
Set the default 20 mA via the linear trickle charger branch (to
ensure that the microprocessor remains alive if powered by
the main charger output, ISO_Sx). Any residual current on
the main charger output, ISO_Sx, is used to charge the
battery.
Watchdog Timer
The ADP5062 charger features a programmable watchdog timer
function to ensure charging is under the control of the processor.
The watchdog timer starts running when the ADP5062 charger
determines that the processor should be operational, that is,
when the processor sets the RESET_WD bit for the first time or
when the battery voltage is greater than the weak battery threshold,
•
During weak current mode, other features may prevent the
weak charging current from reaching its full programmed
value. Isothermal charging mode or input current limiting for
USB compatibility can affect the programmed weak charging
current value under certain operating conditions. During
weak charging, the ISO_Sx node is regulated to VISO_SFC by
the battery isolation FET.
V
WEAK. When the watchdog timer has been triggered, it must be
reset regularly within the watchdog timer period, tWD
.
While in charger mode, if the watchdog timer expires without
being reset, the ADP5062 charger assumes that there is a software
problem and triggers the safety timer, tSAFE. For more infor-
mation see the Safety Timer section.
Rev. B | Page 19 of 44
ADP5062
Data Sheet
Safety Timer
Battery Voltage Limit to Prevent Charging
While in charger mode, if the watchdog timer expires, the
ADP5062 charger initiates the safety timer, tSAFE (see the
Watchdog Timer section). If the processor has programmed
charging parameters by the time the charger initiates the safety
timer, the ILIM is set to the default value. Charging continues for
a period of tSAFE, and then the charger switches off and sets the
CHARGER_STATUS [2:0] bits.
The battery monitor of the ADP5062 charger can be configured
to monitor battery voltage and prevent charging when the battery
voltage is higher than VCHG_VLIM (typically 3.7 V) during charging
start-up (enabled by EN_CHG or DIG_IO3). This function can
prevent unnecessary charging of a half discharged battery and,
as such, can extend the lifetime of the Li-Ion battery cell. Charging
starts automatically when the battery voltage drops below VCHG_VLIM
and continues through full charge cycle until the battery voltage
reaches VTRM (typically 4.2 V).
Charge Complete
The ADP5062 charger monitors the charging current while
in constant voltage fast charge mode. If the current falls
below IEND and remains below IEND for tEND, charging stops
and the CHDONE flag is set. If the charging current falls below
By default, the charging voltage limit is disabled and it can be
enabled from I2C Register Address 0x08, Bit 5 (EN_CHG_VLIM).
SYS_EN Output
I
END for less than tEND and then rises above IEND again, the tEND
The ADP5062 features a SYS_EN open-drain FET to enable the
system until the battery is at the minimum required level for
guaranteed system start-up. When there are minimum battery
voltage and/or minimum battery charge level requirements, the
operation of SYS_EN can be set by I2C programming. The SYS_EN
operation can be factory programmed to four different operating
conditions as described in Table 11.
timer resets.
Recharge
After the detection of charge complete, and the cessation of
charging, the ADP5062 charger monitors the BAT_SNS pin as
the battery discharges through normal use. If the BAT_SNS pin
voltage falls to VRCH, the charger reactivates charging. Under most
circumstances, triggering the recharge threshold results in the
charger starting directly into fast charge constant voltage mode.
The recharge function can be disabled in the I2C, but a status bit
(Register Address 0x0C, Bit 3) informs the system that a recharge
cycle is required.
Table 11. SYS_EN Mode Descriptions
SYS_EN Mode
Description
Selection
SYS_EN is activated when LDO is active and
system voltage is available.
00
SYS_EN is activated by the ISO_Bx voltage, the
battery charging mode.
01
10
IC Enable/Disable
The ADP5062 IC can be disabled by the DIG_IO2 digital input
pin (if factory programmed to do so) or by the I2C registers. All
internal control circuits are disabled when the IC is disabled. Dis-
abling the IC1 option can also control the states of the LDO FET
and the battery isolation FET.
SYS_EN is activated and the isolation FET is
disabled when the battery drops below VWEAK
.
This option is active when VINx = 0 V and the
battery monitor is activated from Register 0x07,
Bit 5 (EN_BMON).
SYS_EN is active in LDO mode when the charger is
disabled.
11
It is critical to note that during the disable IC1 mode, a high
voltage at VINx passes to the internal supply voltage because all
of the internal control circuits are disabled. The VINx supply
voltage must fulfill the following condition:
SYS_EN is active in charging mode when VISO_Bx
VWEAK
≥
.
VISO_Bx < VINx < 5.5 V
Indicator LED Output (ILED)
Battery Charging Enable/Disable
The ILED is an open-drain output for an indicator LED connec-
tion. Optionally, the ILED output can be used as a status output
for a microcontroller. Indicator LED modes are listed in Table 12.
The ADP5062 charging function can be disabled by setting the
I2C EN_CHG bit to low. The LDO to the system still operates
under this circumstance and can be set in I2C to the default or
I2C programmed system voltage from 4.3 V to 5.0 V (see Table 26
for details).
Table 12. Indicator LED Operation Modes
ADP5062 Mode
ILED Mode
On/Off Time
IC Off
Off
The ADP5062 charging function can also be controlled via one
of the external DIG_IOx pins (if factory programmed to do so).
Any change in the I2C EN_CHG bit takes precedence over the pin
setting.
LDO Mode Off
LDO Mode On
Charge Mode
Timer Error (tTRK, tCHG, tSAFE
Overtemperature (TSD)
Off
Off
Continuously on
Blinking
Blinking
)
167 ms/833 ms
1 sec/1 sec
Rev. B | Page 20 of 44
Data Sheet
ADP5062
THERMAL MANAGEMENT
BATTERY ISOLATION FET
Isothermal Charging
The ADP5062 charger features an integrated battery isolation
FET for power path control. The battery isolation FET isolates a
deeply discharged Li-Ion cell from the system power supply in
both trickle and fast charge modes, thereby allowing the system
to be powered at all times.
The ADP5062 includes a thermal feedback loop that limits the
charge current when the die temperature exceeds TLIM (typically
115°C). As the on-chip power dissipation and die temperature
increase, the charge current is automatically reduced to maintain
the die temperature within the recommended range. As the die
temperature decreases due to lower on-chip power dissipation
or ambient temperature, the charge current returns to the pro-
grammed level. During isothermal charging, the THERM_LIM
I2C flag is set to high.
When VINx is below VVIN_OK_RISE, the battery isolation FET is in
full conducting mode.
The battery isolation FET is off during trickle charge mode.
When the battery voltage exceeds VTRK_DEAD, the battery iso-
lation FET switches to the system voltage regulation mode.
During system voltage regulation mode, the battery isolation
FET maintains the VISO_SFC voltage on the ISO_Sx pins. When
the battery voltage exceeds VISO_SFC, the battery isolation FET is
in full conducting mode.
This thermal feedback control loop allows the user to set the
programmed charge current based on typical rather than worst
case conditions.
The ADP5062 does not include a thermal feedback loop to limit
ISO_Sx load current in LDO mode. If the power dissipated on
chip during LDO mode causes the die temperature to exceed
130°C, an interrupt is generated. If the die temperature continues
to rise beyond 140°C, the device enters thermal shutdown.
The battery isolation FET supplements the battery to support
high current functions on the system power supply. When the
voltage on ISO_Sx drops below VISO_Bx, the battery isolation FET
enters into full conducting mode. When voltage on ISO_Sx
rises above VISO_Bx, the isolation FET enters regulating mode or
full conduction mode, depending on the Li-Ion cell voltage and
the linear charger mode.
Thermal Shutdown and Thermal Early Warning
The ADP5062 charger features a thermal shutdown threshold
detector. If the die temperature exceeds TSD, the ADP5062 charger
is disabled, and the TSD 140°C bit is set. The ADP5062 charger
can be reenabled when the die temperature drops below the TSD
falling limit and the TSD 140°C bit is reset. To reset the TSD
140°C bit, write to the I2C fault register, Register Address 0x0D
(Bit 0) or cycle the power.
BATTERY DETECTION
Battery Voltage Level Detection
The ADP5062 charger features a battery detection mechanism to
detect an absent battery. The charger actively sinks and sources
current into the ISO_Bx node, and voltage vs. time is detected.
The sink phase is used to detect a charged battery, whereas the
source phase is used to detect a discharged battery.
Before the die temperature reaches TSD, the early warning bit is
set if TSDL is exceeded. This allows the system to accommodate
power consumption before thermal shutdown occurs.
The sink phase (see Figure 30) sinks ISINK current from the ISO_Bx
pins for a time period, tBATOK. If ISO_Bx is below VBATL when the
Fault Recovery
t
BATOK timer expires, the charger assumes no battery is present and
Before performing the following operation, it is important to
ensure that the cause of the fault has been rectified.
starts the source phase. If the ISO_Bx pin exceeds the VBATL voltage
when the tBATOK timer expires, the charger assumes the battery is
present and begins a new charge cycle.
To recover from a charger fault (when CHARGER_STATUS[2:0] =
110), cycle power on VINx or write high to reset the I2C fault bits
in the fault register (Register Address 0x0D).
The source phase sources ISOURCE current to the ISO_Bx pins for
a time period, tBATOK. If If ISO_Bx exceeds VBATH before the tBATOK
timer expires, the charger assumes that no battery is present. If
the ISO_Bx pin does not exceed the VBATH voltage when the tBATOK
timer expires, the charger assumes that a battery is present and
begins a new charge cycle.
Rev. B | Page 21 of 44
ADP5062
Data Sheet
SOURCE PHASE
SINK PHASE
VBATL
V
BATH
LOGIC
STATUS
LOGIC
STATUS
tBAT_OK
tBAT_OK
OPEN
OR
SHORT
OPEN
ISO_Bx
ISO_Bx
Figure 30. Sink Phase
SINK PHASE
TRICKLE CHARGE
SOURCE PHASE
V
V
V
BATL
BATH
BAT_SHR
LOGIC
STATUS
LOGIC
STATUS
LOGIC
STATUS
tBAT_OK
tBAT_OK
tBAT_SHR
SHORT
OR
OPEN
OR
SHORT
SHORT
LOW
ISO_Bx
BATTERY
ISO_Bx
ISO_Bx
Figure 31. Trickle Charge
Battery (ISO_Bx) Short Detection
The battery pack temperature sensing can be controlled by
I2C, using the conditions shown in Table 13. Note that the
I2C register default setting for EN_THR (Register Address 0x07)
is 0 = temperature sensing off.
A battery short occurs under a damaged battery condition or
when the battery protection circuitry is enabled.
On commencing trickle charging, the ADP5062 charger moni-
tors the battery voltage. If this battery voltage does not exceed
Table 13. THR Input Function
VBAT_SHR within the specified timeout period, tBAT_SHR, a fault is
Conditions
declared and the charger is stopped by turning the battery
isolation FET off, but the system voltage is maintained at
VINx
VISO_Bx
THR Function
Off
Off, controlled by I2C
Open or VIN = 0 V to 4.0 V <2.5 V
Open or VIN = 0 V to 4.0 V >2.5 V
VISO_STRK by the linear regulator.
4.0 V to 6.7 V
Don't care Always on
After source phase, if the ISO_Bx or BAT_SNS level remains
below VBATH, either the battery voltage is low or the battery node
is shorted. Because the battery voltage is low, trickle charging mode
is initiated (see Figure 31). If the BAT_SNS level remains below
If the battery pack thermistor is not connected directly to the
THR pin, a 10 kΩ (tolerance 20%) dummy resistor must be
connected between the THR input and GND. Leaving the THR
pin open results in a false detection of the battery temperature
being <0°C and charging is disabled.
V
BAT_SHR after tBAT_SHR has elapsed, the ADP5062 assumes that the
battery node is shorted.
The trickle charge branch is active during the battery short
scenario, and trickle charge current to the battery is main-
tained until the 60-minute trickle charge mode timer expires.
The ADP5062 charger monitors the voltage in the THR pin and
suspends charging when the current is outside the range of less
than 0°C or greater than 60°C.
BATTERY PACK TEMPERATURE SENSING
Battery Thermistor Input
The ADP5062 charger is designed for use with an NTC thermistor
in the battery pack with a nominal room temperature value of
either 10 kΩ at 25°C or 100 kΩ at 25°C, which is selected by
factory programming.
The ADP5062 charger features battery pack temperature sensing
that precludes charging when the battery pack temperature is
outside the specified range. The THR pin provides an on and
off switching current source that should be connected directly
to the battery pack thermistor terminal. The activation interval
of the THR current source is 167 ms.
The ADP5062 charger is designed for use with an NTC thermistor
in the battery pack with a temperature coefficient curve (beta).
Factory programming supports eight beta values covering a
range from 3150 to 4400 (see Table 43).
Rev. B | Page 22 of 44
Data Sheet
ADP5062
JEITA Li-Ion Battery Temperature Charging Specification
Alternatively, the JEITA1 or JEITA2 can be set as enabled to
default by factory programming.
The ADP5062 is compliant with the JEITA1 and JEITA2 Li-Ion
battery charging temperature specifications as outlined in Table 14
and Table 16, respectively.
When the ADP5062 identifies a hot or cold battery condition,
the ADP5062 takes the following actions:
JEITA function can be enabled via the I2C interface and, optionally,
•
•
Stops charging the battery.
Connects or enables the battery isolation FET such that the
ADP5062 continues in LDO mode.
the JEITA1 or JEITA2 function can be selected in I2C.
Table 14. JEITA1 Specifications
Parameter
Symbol
IJEITA_COLD
IJEITA_COOL
Conditions
Min Max Unit
JEITA1 Cold Temperature Limits
JEITA1 Cool Temperature Limits
No battery charging occurs.
Battery charging occurs at approximately 50% of the programmed
level. See Table 15 for specific charging current reduction levels.
0
10
°C
°C
0
JEITA1Typical Temperature Limits
JEITA1 Warm Temperature Limits
IJEITA_TYP
Normal battery charging occurs at the default/programmed levels.
10
45
45
60
°C
°C
IJEITA_WARM Battery termination voltage (VTRM) is reduced by 100 mV from the
programmed value.
JEITA1 Hot Temperature Limits
IJEITA_HOT
No battery charging occurs.
60
°C
Table 15. JEITA1 Reduced Charge Current Levels, Battery Cool Temperature
ICHG[4:0] (Default)
00000 = 50 mA
00001 = 100 mA
00010 = 150 mA
00011 = 200 mA
00100 = 250 mA
00101 = 300 mA
00110 = 350 mA
00111 = 400 mA
01000 = 450 mA
01001 = 500 mA
01010 = 550 mA
01011 = 600 mA
ICHG JEITA1
ICHG[4:0] (Default)
01100 = 650 mA
01101 = 700 mA
01110 = 750 mA
01111 = 800 mA
10000 = 850 mA
10001 = 900 mA
10010 = 950 mA
10011 = 1000 mA
10100 = 1050 mA
10101 = 1100 mA
10110 = 1200 mA
10111 = 1300 mA
ICHG JEITA1
50 mA
50 mA
50 mA
300 mA
350 mA
350 mA
400 mA
400 mA
450 mA
450 mA
500 mA
500 mA
550 mA
600 mA
650 mA
100 mA
100 mA
150 mA
150 mA
200 mA
200 mA
250 mA
250 mA
300 mA
Table 16. JEITA2 Specifications
Parameter
Symbol
IJEITA_COLD
IJEITA_COOL
Conditions
No battery charging occurs.
Battery termination voltage (VTRM) is reduced by 100 mV from the
programmed value.
Min Max Unit
JEITA2 Cold Temperature Limits
JEITA2 Cool Temperature Limits
0
10
°C
°C
0
JEITA2 Typical Temperature Limits IJEITA_TYP
Normal battery charging occurs at the default/programmed levels.
10
45
45
60
°C
°C
JEITA2 Warm Temperature Limits
IJEITA_WARM Battery termination voltage (VTRM) is reduced by 100 mV from the
programmed value.
JEITA2 Hot Temperature Limits
IJEITA_HOT
No battery charging occurs.
60
°C
Rev. B | Page 23 of 44
ADP5062
Data Sheet
POWER-ON RESET
RESET ALL
REGISTERS
NO
NO
IC OFF
VIN_OK =
HIGH
SYSTEM
OFF
YES
YES
NO
ENABLE
CHARGER
ENABLE
LDO
YES
LDO MODE
ENABLE
NO
CHARGER
YES
LOW
BATTERY
CHG
V
< V
YES
BAT_SNS
NO
CHG_VLIM
NO
YES
TO
CHARGING MODE
Figure 32. Simplified Battery and VINx Connect Flowchart
Rev. B | Page 24 of 44
Data Sheet
ADP5062
TO CHARGING
MODE
TO IC OFF
YES
RUN
BATTERY
DETECTION
tSTART
EXPIRED
NO
YES
NO
V
BAT_SNS
< V
TRK
POWER-DOWN
TRICKLE
CHARGE
FAST CHARGE
NO
NO
NO
NO
VIN_OK =
HIGH
VIN_OK =
HIGH
YES
YES
V
VIN_ILIM = HIGH
= I
BAT_SNS
I
< I
LIM
VINx
< V
I
TRK
VINx
LIM
YES
YES
WATCHDOG
EXPIRED
YES
YES
tWD EXPIRED
NO
NO
START tSAFE
THERM_LIM = HIGH
TEMP < T
LIM
I
= 100mA
TEMP = T
BUS
LIM
YES
TIMER FAULT
OR
BAD BATTERY
tSAFE OR tTRK
EXPIRED
WATCHDOG
EXPIRED
YES
tWD EXPIRED
NO
START tSAFE
I
= 100 mA
BUS
NO
TIMER FAULT OR
BAD BATTERY
SEE TIMER SPECS
1
YES
tSAFE OR tCHG
EXPIRED
1
NO
RUN
BATTERY
DETECTION
NO
V
=
BAT_SNS
CC MODE
CHARGING
V
YES
TRM
YES
V
=
BAT_SNS
V
RCH
NO
YES
NO
CHARGE
COMPLETE
CV MODE
CHARGING
I
< I
END
OUT
Figure 33. Simplified Charging Mode Flowchart
Rev. B | Page 25 of 44
ADP5062
Data Sheet
I2C INTERFACE
the master after the 8-bit data byte has been written (see Figure 34
for an example of the I2C write sequence to a single register).
The ADP5062 increments the subaddress automatically and
starts receiving a data byte at the next register until the master
sends an I2C stop as shown in Figure 35.
Figure 36 shows the I2C read sequence of a single register.
ADP5062 sends the data from the register denoted by the
subaddress and increments the subaddress automatically,
sending data from the next register until the master sends an
I2C stop condition, as shown in Figure 37.
The ADP5062 includes an I2C-compatible serial interface for
control of the charging and LDO functions, as well as for a
readback of the system status registers. The I2C chip address
is 0x28 in write mode and 0x29 in read mode.
Register values are reset to the default values when the VINx
supply falls below the falling voltage threshold, VVIN_OK_FALL
.
The I2C registers also reset when the battery is disconnected and
VIN is 0 V.
The subaddress content selects which of the ADP5062 registers
is written to first. The ADP5062 sends an acknowledgement to
MASTER STOP
0 = WRITE
ST
0
0
1
0
1
0
0
0
0
0
0
SP
CHIP ADDRESS
SUBADDRESS
ADP5062 RECEIVES
DATA
Figure 34. I2C Single Register Write Sequence
0 = WRITE
MASTER STOP
ST
0
0
1
0
1
0
0
0
0
0
0
0
SP
0
CHIP ADDRESS
SUBADDRESS
REGISTER N
ADP5062 RECEIVES
DATA TO REGISTER N
ADP5062 RECEIVES
DATA TO REGISTER N + 1
ADP5062 RECEIVES
DATA TO LAST REGISTER
Figure 35. I2C Multiple Register Write Sequence
MASTER
STOP
0 = WRITE
1 = READ
0
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
SP
ST
ST
CHIP ADDRESS
CHIP ADDRESS
ADP5062 SEND
SDATA
SUBADDRESS
Figure 36. I2C Single Register Read Sequence
MASTER
STOP
0 = WRITE
1 = READ
0
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
SP
ST
ST
SUBADDRESS
REGISTER N
ADP5062 SENDS
DATA OF REGISTER N
ADP5062 SENDS
DATA OF REGISTER
N + 1
CHIP ADDRESS
CHIP ADDRESS
ADP5062 SENDS
DATA OF LAST
REGISTER
Figure 37. I2C Multiple Register Read Sequence
Rev. B | Page 26 of 44
Data Sheet
ADP5062
I2C REGISTER MAP
See the Factory-Programmable Options section for programming option details. Note that a blank cell indicates a bit that is not used or is
reserved for future use.
Table 17. I2C Register Map
Register
Addr. Name
D7
D6
D5
D4
D3
D2
D1
Model[3:0]
D0
0x00 Manufac-
turer and
MANUF[3:0]
model ID
0x01 Silicon
revision
REV[3:0]
0x02 VINx pin
settings
ILIM[3:0]1
1 2
,
VTRM[5:0]1
CHG_VLIM[1:0]
, 2
0x03 Termination
settings
1 2
,
ITRK_DEAD[1:0]1
0x04 Charging
current
ICHG[4:0]
settings
1
, 3
1 3
,
0x05 Voltage
thresholds
DIS_RCH
VRCH[1:0]1
VTRK_DEAD[1:0]
EN_CHG_TIMER1 CHG_TMR_PERIOD1
VWEAK[2:0]1
EN_TEND1
EN_WD
WD_PERIOD1
1 3
,
0x06 Timer
settings
RESET_WD
EN_CHG1
DIS_IC11
EN_BMON1
EN_THR1
DIS_LDO1
EN_EOC1
0x07 Functional
Settings 1
EN_JEITA1, 3
IDEAL_DIODE[1:0]1, 3
VSYSTEM[2:0]1, 3
1 3
,
1 3
,
0x08 Functional
Settings 2
JEITA_SELECT
EN_CHG_VLIM
0x09 Interrupt
enable
EN_THERM_LIM_INT EN_WD_INT
EN_TSD_INT
TSD_INT
EN_THR_INT
THR_INT
EN_BAT_INT EN_CHG_INT EN_VIN_INT
BAT_INT CHG_INT VIN_INT
0x0A Interrupt
active
THERM_LIM_INT
VIN_OK
WD_INT
VIN_ILIM
0x0B Charger
Status 1
VIN_OV
THERM_LIM
CHDONE
CHARGER_STATUS[2:0]
BATTERY_STATUS[2:0]
0x0C Charger
Status 2
THR_STATUS[2:0]
RCH_LIM_INFO
BAT_SHR1
TSD 130°C1
TSD 140°C1
0x0D Fault
TBAT_SHR[2:0]1
VBAT_SHR[2:0]1
0x10 Battery
short
1 3
,
1 3
,
C/20 EOC1
C/10 EOC1
C/5 EOC1
SYS_EN_SET[1:0]
0x11 IEND
IEND[2:0]
1 These bits reset to default I2C values when VINx is connected or disconnected.
2 The default I2C values of these bits are partially factory programmable.
3 The default I2C values of these bits are fully factory programmable.
Rev. B | Page 27 of 44
ADP5062
Data Sheet
REGISTER BIT DESCRIPTIONS
In Table 18 through Table 33, the following abbreviations are used: R is read only, W is write only, R/W is read/write, and N/A means not
applicable.
Table 18. Manufacturer and Model ID, Register Address 0x00
Bit No.
Bit Name
Access
Default
Description
[7:4]
MANUF[3:0]
MODEL[3:0]
R
R
0001
The 4-bit manufacturer identification bus
The 4-bit model identification bus
[3:0]
1001
Table 19. Silicon Revision, Register Address 0x01
Bit No.
Bit Name
Not used
REV[3:0]
Access
Default
Description
[7:4]
R
R
[3:0]
0100/ADP5062ACPZ-1-R7
0111/ADP5062ACPZ-2-R7
The 4-bit silicon revision identification bus
Table 20. VINx Pin Settings, Register Address 0x02
Bit No.
[7:5]
4
Bit Name
Not used
RFU
Access
Default
Description
R
R/W
R/W
0
Reserved for future use.
[3:0]
ILIM[3:0]
0000 = 100 mA
VINx input current-limit programming bus. The current into VINx can
be limited to the following programmed values:
0000 = 100 mA.
0001 = 150 mA.
0010 = 200 mA.
0011 = 250 mA.
0100 = 300 mA.
0101 = 400 mA.
0110 = 500 mA.
0111 = 600 mA.
1000 = 700 mA.
1001 = 800 mA.
1010 = 900 mA.
1011 = 1000 mA.
1100 = 1200 mA.
1101 = 1500 mA.
1110 = 1800 mA.
1111 = 2100 mA.
Rev. B | Page 28 of 44
Data Sheet
ADP5062
Table 21. Termination Settings, Register Address 0x03
Bit No. Bit Name
Access
Default
Description
[7:2] VTRM[5:0]
R/W
100011 = 4.20 V Termination voltage programming bus. The values of the floating voltage can
be programmed to the following values:
000101 = 3.60 V.
000110 = 3.62 V.
000111 = 3.64 V.
001000 = 3.66 V.
001001 = 3.68 V.
001010 = 3.70 V.
001011 = 3.72 V.
001100 = 3.74 V.
001101 = 3.76 V.
001110 = 3.78 V.
001111 = 3.80 V.
010000 = 3.82 V.
010001 = 3.84 V.
010010 = 3.86 V.
010011 = 3.88 V.
010100 = 3.90 V.
010101 = 3.92 V.
010110 = 3.94 V.
010111 = 3.96 V.
011000 = 3.98 V.
011001 = 4.00 V.
011010 = 4.02 V.
011011 = 4.04 V.
011100 = 4.06 V.
011101 = 4.08 V.
011110 = 4.10 V.
011111 = 4.12 V.
100000 = 4.14 V.
100001 = 4.16 V.
100010 = 4.18 V.
100011 = 4.20 V.
100100 = 4.22 V.
100101 = 4.24 V.
100110 = 4.26 V.
100111 = 4.28 V.
101000 = 4.30 V.
101001 = 4.32 V.
101010 = 4.34 V.
101011 = 4.36 V.
101100 = 4.38 V.
101101 = 4.40 V.
101110 = 4.42 V.
101111 = 4.44 V.
110000 = 4.44 V.
110001 = 4.46 V.
110010 = 4.48 V.
110011 to 111111 = 4.50 V.
[1:0]
CHG_VLIM[1:0] R/W
00 = 3.2 V
Charging voltage limit programming bus. The values of the charging voltage
limit can be programmed to the following values:
00 = 3.2 V.
01 = 3.4 V.
10 = 3.7 V.
11 = 3.8 V.
Rev. B | Page 29 of 44
ADP5062
Data Sheet
Table 22. Charging Current Settings, Register Address 0x04
Bit No.
Bit Name
Not used
ICHG[4:0]
Access
Default
Description
7
R
[6:2]
R/W
01110 = 750 mA
Fast charge current programming bus. The values of the constant
current charge can be programmed to the the following values:
00000 = 50 mA.
00001 = 100 mA.
00010 = 150 mA.
00011 = 200 mA.
00100 = 250 mA.
00101 = 300 mA.
00110 = 350 mA.
00111 = 400 mA.
01000 = 450 mA.
01001 = 500 mA.
01010 = 550 mA.
01011 = 600 mA.
01100 = 650 mA.
01101 = 700 mA.
01110 = 750 mA.
01111 = 800 mA.
10000 = 850 mA.
10001 = 900 mA.
10010 = 950 mA.
10011 = 1000 mA.
10100 = 1050 mA.
10101 = 1100 mA.
10110 = 1200 mA.
10111 to 11111 = 1300 mA.
[1:0]
ITRK_DEAD[1:0]
R/W
10 = 20 mA
Trickle and weak charge current programming bus. The values of
the trickle and weak charge currents can be programmed to the
following values:
00 = 5 mA.
01 = 10 mA.
10 = 20 mA.
11 = 80 mA.
Table 23. Voltage Thresholds, Register Address 0x05
Bit No.
Bit Name
Access
Default
Description
7
DIS_RCH
R/W
0 = recharge
enabled
0 = recharge enabled.
1 = recharge disabled.
[6:5]
VRCH[1:0]
R/W
11 = 260 mV
Recharge voltage programming bus. The values of the recharge
threshold can be programmed to the following values (note that
the recharge cycle can be disabled in I2C by using the DIS_RCH bit):
00 = 80 mV.
01 = 140 mV.
10 = 200 mV.
11 = 260 mV.
Rev. B | Page 30 of 44
Data Sheet
ADP5062
Bit No.
Bit Name
VTRK_DEAD[1:0]
Access
Default
Description
[4:3]
R/W
01 = 2.5 V
Trickle to fast charge dead battery voltage programming bus. The
values of the trickle to fast charge threshold can be programmed to
the following values:
00 = 2.0 V.
01 = 2.5 V.
10 = 2.6 V.
11 = 2.9 V.
[2:0]
VWEAK[2:0]
R/W
011 = 3.0 V
Weak battery voltage rising threshold.
000 = 2.7 V.
001 = 2.8 V.
010 = 2.9 V.
011 = 3.0 V.
100 = 3.1 V.
101 = 3.2 V.
110 = 3.3 V.
111 = 3.4 V.
Table 24. Timer Settings, Register Address 0x06
Bit No.
[7:6]
5
Bit Name
Not used
EN_TEND
Access
Default
Description
R/W
1
0 = charge complete timer, tEND, disabled. A 31 ms deglitch timer
remains on.
1 = charge complete timer enabled.
4
3
EN_CHG_TIMER
R/W
R/W
1
1
0 = trickle/fast charge timer disabled.
1 = trickle/fast charge timer enabled.
CHG_TMR_PERIOD
Trickle and fast charge timer period.
0 = 30 sec trickle charge timer and 300 minute fast charge timer.
1 = 60 sec trickle charge timer and 600 minute fast charge timer.
2
1
EN_WD
R/W
R/W
0
0
0 = watchdog timer is disabled even when BAT_SNS exceeds VWEAK
1 = watchdog timer safety timer is enabled.
.
WD_PERIOD
Watchdog safety timer period.
0 = 32 sec watchdog timer and 40 minute safety timer.
1 = 64 sec watchdog timer and 40 minute safety timer.
0
RESET_WD
W
0
When RESET_WD is set to logic high by I2C, the watchdog safety
timer is reset.
Table 25. Functional Settings 1, Register Address 0x07
Bit No.
Bit Name
Not used
DIS_IC1
Access
Default
Description
7
6
R/W
0
0
0 = normal operation.
1 = the ADP5062 is disabled; VVINx must be VISO_Bx < VVINx < 5.5 V.
5
4
3
EN_BMON
R/W
0 = when VVINx < VVIN_OK_RISE or VVIN_OK_FALL, the battery monitor is
disabled. When VVINx = 4.0 V to 6.7 V, the battery monitor is enabled
regardless of the EN_BMON state.
1 = the battery monitor is enabled even when the voltage at the
VINx pins is below VVIN_OK
.
EN_THR
R/W
R/W
0
0
0 = when VVINx < VVIN_OK_RISE or VVIN_OK_FALL, the THR current source is
disabled. When VVINx = 4.0 V to 6.7 V, the THR current source is
enabled regardless of the EN_THR state.
1 = THR current source is enabled even when the voltage at the
VINx pins is below VVIN_OK_RISE or VVIN_OK_FALL
.
DIS_LDO
0 = LDO is enabled.
1 = LDO is off. In addition, if EN_CHG = low, the battery isolation
FET is on. If EN_CHG = high, the battery isolation FET is off.
Rev. B | Page 31 of 44
ADP5062
Data Sheet
Bit No.
Bit Name
Access
Default
Description
2
EN_EOC
R/W
1
0 = end of charge not allowed.
1 = end of charge allowed.
1
0
Not used
EN_CHG
R/W
0
0 = battery charging is disabled.
1 = battery charging is enabled.
Table 26. Functional Settings 2, Register Address 0x08
Bit No.
Bit Name
Access
Default
Description
7
EN_JEITA
R/W
0 = JEITA disabled
0 = JEITA compliance of the Li-Ion temperature battery charging
specifications is disabled.
1 = JEITA compliance enabled.
0 = JEITA1 is selected.
1 = JEITA2 is selected.
6
5
JEITA_SELECT
EN_CHG_VLIM
R/W
R/W
0 = JEITA1
0
0 = charging voltage limit disabled.
1 = voltage limit activated. The charger prevents charging until the
battery voltage drops below the VCHG_VLIM threshold.
[4:3]
[2:0]
IDEAL_DIODE[1:0]
VSYSTEM[2:0]
R/W
R/W
00
00 = ideal diode operates constantly when VISO_Sx < VISO_Bx.
01 = ideal diode operates when VISO_Sx < VISO_Bx and VBAT_SNS > VWEAK
10 = ideal diode is disabled.
.
11 = ideal diode is disabled.
See Table 41 for
model specific
default value.
System voltage programming bus. The values of the system voltage
can be programmed to the following values:
000 = 4.3 V.
001 = 4.4 V.
010 = 4.5 V.
011 = 4.6 V.
100 = 4.7 V.
101 = 4.8 V.
110 = 4.9 V.
111 = 5.0 V.
Table 27. Interrupt Enable, Register Address 0x09
Bit No.
Bit Name
Access
Default
Description
7
6
Not used
EN_THERM_LIM_INT R/W
0
0
0
0
0
0
0
0 = isothermal charging interrupt is disabled.
1 = isothermal charging interrupt is enabled.
0 = watchdog alarm interrupt is disabled.
5
4
3
2
1
0
EN_WD_INT
EN_TSD_INT
EN_THR_INT
EN_BAT_INT
EN_CHG_INT
EN_VIN_INT
R/W
R/W
R/W
R/W
R/W
R/W
1 = watchdog alarm interrupt is enabled.
0 = overtemperature interrupt is disabled.
1 = overtemperature interrupt is enabled.
0 = THR temperature thresholds interrupt is disabled.
1 = THR temperature thresholds interrupt is enabled.
0 = battery voltage thresholds interrupt is disabled.
1 = battery voltage thresholds interrupt is enabled.
0 = charger mode change interrupt is disabled.
1 = charger mode change interrupt is enabled.
0 = VINx pin voltage thresholds interrupt is disabled.
1 = VINx pin voltage thresholds interrupt is enabled.
Rev. B | Page 32 of 44
Data Sheet
ADP5062
Table 28. Interrupt Active, Register Address 0x0A
Bit No.
Bit Name
Access Default
Description
7
6
5
Not used
THERM_LIM_INT
WD_INT
R
R
0
0
1 = indicates an interrupt caused by isothermal charging.
1 = indicates an interrupt caused by the watchdog alarm. The
watchdog timer expires within 2 sec or 4 sec, depending on the
watch dog period setting of 32 sec or 64 sec, respectively.
4
3
2
1
0
TSD_INT
THR_INT
BAT_INT
CHG_INT
VIN_INT
R
R
R
R
R
0
0
0
0
0
1 = indicates an interrupt caused by an overtemperature fault.
1 = indicates an interrupt caused by THR temperature thresholds.
1 = indicates an interrupt caused by battery voltage thresholds.
1 = indicates an interrupt caused by a charger mode change.
1 = indicates an interrupt caused by VINx voltage thresholds.
Table 29. Charger Status 1, Register Address 0x0B
Bit No.
Bit Name
Access Default
Description
7
6
5
VIN_OV
R
R
R
N/A
N/A
N/A
1 = the voltage at the VINx pins exceeds VVIN_OV
1 = the voltage at the VINx pins exceeds VVIN_OK_RISE, VVIN_OK_FALL
1 = the current into a VINx pin is limited by the high voltage blocking
FET and the charger is not running at the full programmed ICHG
.
VIN_OK
.
VIN_ILIM
.
4
THERM_LIM
R
R
R
N/A
N/A
N/A
1 = the charger is not running at the full programmed ICHG but is
limited by the die temperature.
3
CHDONE
1 = the end of a charge cycle has been reached. This bit latches on,
in that it does not reset to low when the VRCH threshold is breached.
[2:0]
CHARGER_STATUS[2:0]
Charger status bus.
000 = off.
001 = trickle charge.
010 = fast charge (CC mode).
011 = fast charge (CV mode).
100 = charge complete.
101 = LDO mode.
110 = trickle or fast charge timer expired.
111 = battery detection.
Rev. B | Page 33 of 44
ADP5062
Data Sheet
Table 30. Charger Status 2, Register Address 0x0C
Bit No.
Mnemonic
Access Default
Description
[7:5]
THR_STATUS[2:0]
R
N/A
THR pin status.
000 = off.
001 = battery cold.
010 = battery cool.
011 = battery warm.
100 = battery hot.
111 = thermistor OK.
4
3
Not used
RCH_LIM_INFO
R
R
N/A
The recharge limit information function is activated when DIS_RCH
is logic high and the CHARGER_STATUS[2:0] = 100 (binary). The
status bit informs the system that a recharge cycle is required.
0 = VBAT_SNS > VRCH
1 = VBAT_SNS < VRCH
[2:0]
BATTERY_STATUS[2:0]
Battery status bus.
000 = battery monitor off.
001 = no battery.
010 = VBAT_SNS < VTRK_DEAD
.
011 = VTRK_DEAD ≤ VBAT_SNS < VWEAK
.
100 = VBAT_SNS ≥ VWEAK
.
Table 31. Fault,1 Register Address 0x0D
Bit No.
Bit Name
Not used
BAT_SHR
Not used
TSD 130°C
TSD 140°C
Access Default
Description
[7:4]
3
2
1
0
R/W
R/W
R/W
R/W
0
1 = indicates detection of a battery short.
0
0
1 = indicates an overtemperature (lower) fault.
1 = indicates an overtemperature fault.
1 To reset the fault bits in the fault register, cycle power on VINx or write high to the corresponding I2C bit.
Table 32. Battery Short, Register Address 0x10
Bit No.
Bit Name
Access Default
Description
[7:5]
TBAT_SHR[2:0]
R/W 100 = 30 sec
Battery short timeout timer.
000 = 1 sec.
001 = 2 sec.
010 = 4 sec.
011 = 10 sec.
100 = 30 sec.
101 = 60 sec.
110 = 120 sec.
111 = 180 sec.
[4:3]
[2:0]
Not used
VBAT_SHR[2:0]
R/W
100 = 2.4 V
Battery short voltage threshold level.
000 = 2.0 V.
001 = 2.1 V.
010 = 2.2 V.
011 = 2.3 V.
100 = 2.4 V.
101 = 2.5 V.
110 = 2.6 V.
111 = 2.7 V.
Rev. B | Page 34 of 44
Data Sheet
ADP5062
Table 33. IEND, Register Address 0x11
Bit No. Bit Name
Access Default
Description
[7:5]
IEND[2:0]
R/W
010 = 52.5 mA
Termination current programming bus. The values of the termination current can
be programmed to the following values:
000 = 12.5 mA.
001 = 32.5 mA.
010 = 52.5 mA.
011 = 72.5 mA.
100 = 92.5 mA.
101 = 117.5 mA.
110 = 142.5 mA.
111 = 170.0 mA.
4
3
C/20 EOC
C/10 EOC
R/W
R/W
0
0
The C/20 EOC bit has priority over the other settings (C/5 EOC, C/10 EOC, and
IEND[2:0]).
1 = the termination current is ICHG[4:0] ÷ 20 with the following limitations:
Minimum value = 12.5 mA.
Maximum value = 170 mA.
The C/10 EOC bit has priority over the other termination current settings (C/5 EOC
and IEND[2:0]), but does not have priority over the C/20 EOC setting.
1 = the termination current is ICHG[4:0] ÷ 10, unless C/20 EOC is high. The
termination current is limited to the following values:
Minimum value = 12.5 mA.
Maximum value = 170 mA.
2
C/5 EOC
R/W
0
The C/5 EOC bit has priority over the other termination current settings (IEND[2:0])
but does not have priority over the C/20 EOC setting or the C/10 EOC setting.
1 = the termination current is ICHG[4:0] ÷ 5, unless the C/20 EOC or the C/10 EOC
bit is high. The termination current is limited to the following values:
Minimum value = 12.5 mA.
Maximum value = 170 mA.
1:0
SYS_EN_SET[1:0] R/W
00
Selects the operation of the system enable pin (SYS_EN).
00 = SYS_EN is activated when LDO is active and the system voltage is available.
01 = SYS_EN is activated by the ISO_Bx voltage, the battery charging mode.
10 = SYS_EN is activated and the isolation FET is disabled when the battery drops
1
below VWEAK
.
11 = SYS_EN is active in LDO mode when the charger is disabled. SYS_EN is active
in the charging mode when VISO_Bx ≥ VWEAK
.
1 This option is active when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit 5 (EN_BMON).
Rev. B | Page 35 of 44
ADP5062
Data Sheet
APPLICATIONS INFORMATION
Substituting these values in the equation yields
EFF = 16 μF × (1 − 0.15) × (1 − 0.1) ≈ 12.24 μF
EXTERNAL COMPONENTS
C
ISO_Sx (VOUT) Capacitor Selection
To guarantee the performance of the charger in various operating
modes, including trickle charge, constant current charge, and
constant voltage charge, it is imperative that the effects of dc
bias, temperature, and tolerances on the behavior of the capaci-
tors be evaluated for each application.
To obtain stable operation of the ADP5062 in a safe way, the
combined effective capacitance of the ISO_Sx capacitor and the
system capacitance must not be less than 10 µF and must not
exceed 100 µF at any point during operation.
When choosing the capacitor value, it is also important to account
for the loss of capacitance caused by the output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric that is adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage rating
of 6.3 V or higher are recommended for best performance. Y5V
and Z5U dielectrics are not recommended for use with any dc-
to-dc converter because of their poor temperature and dc bias
characteristics.
Splitting ISO_Sx Capacitance
In many applications, the total ISO_Sx capacitance consists of a
number of capacitors. The system voltage node (ISO_Sx) usually
supplies a single regulator or a number of ICs and regulators,
each of which requires a capacitor close to its power supply
input (see Figure 39).
The capacitance close to the ADP5062 ISO_Sx output should be
at least 5 µF, as long as the total effective capacitance is at least
10 µF at any point during operation.
The worst case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calcu-
lated using the following equation:
ISO_Sx
VIN1
C
> 5µF
ISO_Sx
C
IN1
IC1
ADP5062
C
EFF = COUT × (1 − TEMPCO) × (1 − TOL)
where:
EFF is the effective capacitance at the operating voltage.
SUM OF EFFECTIVE
CAPACITANCES
ON ISO_Sx NODE > 10µF
C
+
C
ISO_Bx
≥10µF
TEMPCO is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
VIN2
IC2
C
IN2
In this example, the worst case temperature coefficient (TEMPCO)
over the range of −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT is 16 μF at 4.2 V, as shown in Figure 38.
60
Figure 39. Splitting ISO_Sx Capacitance
ISO_Bx and ISO_Sx Capacitor Selection
The ISO_Bx and the ISO_Sx effective capacitance (including
temperature and dc bias effects) must not be less than 10 µF at
any point during operation. Typically, a nominal capacitance of
22 µF is required to fullfill the condition at all points of
operation. Suggestions for ISO_Bx and ISO_Sx capacitors are
listed in Table 34.
55
50
45
40
35
30
25
20
CBP Capacitor Selection
The internal supply voltage of the ADP5062 is equipped with a
noise suppressing capacitor at the CBP terminal. Do not allow CBP
capacitance to exceed 14 nF at any point during operation. Do
not connect any external voltage source, any resistive load, or
any other current load to the CBP terminal. Suggestions for a
CBP capacitor are listed in Table 35.
0
1
2
3
4
5
DC BIAS VOLTAGE (V)
Figure 38. Murata GRM31CR61A226KE19 Capacitance vs. Bias Voltage
Rev. B | Page 36 of 44
Data Sheet
ADP5062
VINx Capacitor Selection
Table 34. ISO_Bx and ISO_Sx Capacitor Suggestions
According to the USB 2.0 specification, USB peripherals have a
detectable change in capacitance on VBUS when they are attached
to a USB port. The peripheral device VBUS bypass capacitance
must be at least 1 µF but not larger than 10 µF.
Vendor Part Number
Value
22 μF
22 μF
22 µF
22 µF
Voltage Size
Murata
Murata
TDK
GRM31CR61A226KE19
10 V
6.3 V
6.3 V
6.3 V
1206
1206
1206
1206
GRM31CR60J226ME19
C3216X5R0J226M
JMK316ABJ226KL
The VINx input of the ADP5062 is tolerant of voltages as high
as 20 V; however, if an application requires exposing the VINx
input to voltages of up to 20 V, the voltage range of the capacitor
must also be above 20 V. Suggestions for a VINx capacitor are
given in Table 36.
Taiyo-
Yuden
Table 35. CBP Capacitor Suggestions
Vendor Part Number Value Voltage Size
Murata
TDK
GRM15XR71C103KA86
C1005X7R1C103K
10 nF
10 nF
16 V
16 V
0402
0402
When using ceramic capacitors, a higher voltage range is usually
achieved by selecting a component with larger physical dimensions.
In applications where lower than 20 V at VINx input voltages can
be guaranteed, smaller output capacitors can be used accordingly.
Table 36. VINx Capacitor Suggestions
Vendor Part Number Value Voltage Size
Murata
TDK
GRM21BR61E106MA73 10 µF
C2012X5R1E106K 10 µF
25 V
25 V
0805
0805
Rev. B | Page 37 of 44
ADP5062
Data Sheet
PCB LAYOUT GUIDELINES
VIN = 4V TO 7V
C4
10µF
GRM21BR6E106MA73
8
6
7
VIN1 TO VIN3
ADP5062
20-LEAD LFCSP
ISO_S1 TO ISO_S3
19
CBP
9
C1
10nF
GRM15XR71C103KA8
10
11
C3
22µF
GRM31CR60J226ME19
VDDIO
R1
1.5kΩ
R2
1.5kΩ
CHARGER
CONTROL
BLOCK
1
TO MCU
TO MCU
SCL
SDA
17
12
5
3
2
13
14
TO MCU/NC
DIG_IO1
DIG_IO2
DIG_IO3
TO MCU/NC
TO MCU/NC
CONNECT
CLOSE TO
BATTERY +
ISO_B1 TO ISO_B3
4
BAT_SNS
THR
VDDIO
18
R4
10kΩ
C2
22µF
GRM31CR60J22ME19
R5 NTC 10kΩ
(OPTIONAL)
SYS_EN
ILED
16
15
TO MCU
VLED
AGND
20
Figure 40. Reference Circuit Diagram
C1 – 10nF
16V/X7R
0402
ISO_Bx
PGND
C2 – 22µF
16V/X5R
1206
ISO_Sx
PGND
VINx
PGND
C4 – 10µF
25V/X5R
0805
C3 – 22µF
16V/X5R
1206
Figure 41. Reference PCB Floor Plan
Rev. B | Page 38 of 44
Data Sheet
ADP5062
POWER DISSIPATION AND THERMAL CONSIDERATIONS
is higher and the power dissipation must be calculated using
Equation 3. When the battery voltage level reaches VISO_SFC, the
power dissipation can be calculated using Equation 4.
CHARGER POWER DISSIPATION
When the ADP5062 charger operates at high ambient tempera-
tures and at maximum current charging and loading conditions,
the junction temperature can reach the maximum allowable
operating limit of 125°C.
P
ISOFET = RDSON
where:
DSON_ISO is the on resistance of the battery isolation FET
(typically 110 mΩ during charging).
CHG is the battery charge current.
_
ISO × ICHG
(4)
R
When the junction temperature exceeds 140°C, the ADP5062
turns off, allowing the device to cool down. When the die
temperature falls below 110°C and the TSD 140°C fault bit in
Register 0x0D is cleared by an I2C write, the ADP5062 resumes
normal operation.
I
The thermal control loop of the ADP5062 automatically limits
the charge current to maintain a die temperature below TLIM
(typically 115°C).
This section provides guidelines to calculate the power dissi-
pated in the device to ensure that the ADP5062 operates below
the maximum allowable junction temperature.
The most intuitive and practical way to calculate the power
dissipation in the ADP5062 device is to measure the power
dissipated at the input and all of the outputs. Perform the
measurements at the worst case conditions (voltages, currents,
and temperature). The difference between input and output
power is the power that is dissipated in the device.
To determine the available output current in different operating
modes under various operating conditions, use the following
equations:
PD = PLDOFET + PISOFET
(1)
JUNCTION TEMPERATURE
where:
In cases where the board temperature, TA, is known, the
thermal resistance parameter, θJA, can be used to estimate the
junction temperature rise. TJ is calculated from TA and PD using
the formula
P
P
LDOFET is the power dissipated in the input LDO FET.
ISOFET is the power dissipated in the battery isolation FET.
Calculate the power dissipation in the LDO FET and the battery
isolation FET using Equation 2 and Equation 3.
TJ = TA + (PD × θJA)
(5)
P
P
LDOFET = (VIN – VISO_Sx) × (ICHG + ILOAD
ISOFET = (VISO_Sx – VISO_Bx) × ICHG
)
(2)
(3)
The typical θJA value for the 20-lead LFCSP is 35.6°C/W (see
Table 5). A very important factor to consider is that θJA is based
on a 4-layer, 4 in × 3 in, 2.5 oz. copper board as per JEDEC
standard, and real-world applications may use different sizes
and layers. It is important to maximize the copper to remove the
heat from the device. Copper exposed to air dissipates heat
better than copper used in the inner layers.
where:
VIN is the input voltage at the VINx pins.
VISO_Sx is the system voltage at the ISO_Sx pins.
ISO_Bx is the battery voltage at the ISO_Bx pins.
V
I
I
CHG is the battery charge current.
LOAD is the system load current from the ISO_Sx pins.
If the case temperature can be measured, the junction
temperature is calculated by
LDO Mode
The system regulation voltage is user-programmable from 4.3 V
to 5.0 V. In LDO mode (charging disabled, EN_CHG = low),
calculation of the total power dissipation is simplified, assuming
that all current is drawn from the VINx pins and the battery is
not shared with ISO_Sx.
TJ = TC + (PD × θJC)
(6)
where TC is the case temperature and θJC is the junction-to-case
thermal resistance provided in Table 5.
The reliable operation of the charger can be achieved only if the
estimated die junction temperature of the ADP5062 (Equation 5)
is less than 125°C. Reliability and mean time between failures
(MTBF) are greatly affected by increasing the junction temperature.
Additional information about product reliability can be found in
the ADI Reliability Handbook located at the following URL:
www.analog.com/reliability_handbook.
PD = (VIN – VISO_Sx) × ILOAD
Charging Mode
In charging mode, the voltage at the ISO_Sx pins depends on
the battery level. When the battery voltage is lower than VISO_SFC
(typically 3.8 V), the voltage drop over the battery isolation FET
Rev. B | Page 39 of 44
ADP5062
Data Sheet
FACTORY-PROGRAMMABLE OPTIONS
CHARGER OPTIONS
Table 37 to Table 49 list the factory-programmable options of the ADP5062. In each of these tables, the selection column represents the
default setting of Model ADP5062ACPZ-1-R7 and Model ADP5062ACPZ-2-R7.
Table 37. Default Termination Voltage
Table 41. Default System Voltage
Option
Selection
Option
Selection
000 = 4.20 V
010 = 3.70 V
011 = 3.80 V
100 = 3.90 V
101 = 4.00 V
110 = 4.10 V
111 = 4.40 V
000 = 4.20 V
000 = 4.3 V
001 = 4.4 V
010 = 4.5 V
011 = 4.6 V
100 = 4.7 V
101 = 4.8 V
110 = 4.9 V
111 = 5.0 V
000 = 4.3 V/ADP5062ACPZ-2-R7
111 = 5.0 V/ADP5062ACPZ-1-R7
Table 38. Default Fast Charge Current
Option
Selection
Table 42. Thermistor Resistance
000 = 500 mA
001 = 300 mA
010 = 550 mA
011 = 600 mA
100 = 750 mA
101 = 900 mA
110 = 1300 mA
111 = 1300 mA
Option
Selection
0 = 10 kΩ
1 = 100 kΩ
0 = 10 kΩ
Table 43. Thermistor Beta Value
Option
0100 = 3150
100 = 750 mA
Selection
0100 = 3150
0101 = 3350
0110 = 3500
0111 = 3650
1000 = 3850
Table 39. Default End of Charge Current
Option
Selection
000 = 52.5 mA
001 = 72.5 mA
010 = 12.5 mA
011 = 32.5 mA
100 = 142.5 mA
101 = 167.5 mA
110 = 92.5 mA
111 = 117.5 mA
000 = 52.5 mA
1001 = 4000
1010 = 4200
1011 = 4400
Table 44. DIS_IC1 Mode Select
Option
Selection
0 = DIC_IC1 mode select, VINx current = 280 µA,
ISO_Bx can float, no leak to ISO_Bx
1 = DIC_IC1 mode select, VINx current = 110 µA,
supply switch leaks from VINx to ISO_Bx
0
Table 40. Default Trickle to Fast Charge Threshold
Option
Selection
Table 45. Trickle or Fast Charge Timer Fault Operation
00 = 2.5 V
01 = 2.0 V
10 = 2.9 V
11 = 2.6 V
00 = 2.5 V
Option
Selection
0 = after timeout LDO off, charging off
1 = after timeout LDO mode active, charging off
1 = LDO
mode
active
Rev. B | Page 40 of 44
Data Sheet
ADP5062
I2C REGISTER DEFAULTS
Table 46. I2C Register Default Settings
Bit Name
I2C Register Address, Bit Location
Option
Selection
CHG_VLIM[1:0]
Address 0x03, Bits[1:0]
Address 0x05, Bit 7
Address 0x06, Bit 2
Address 0x07, Bit 6
Address 0x07, Bit 0
Address 0x08, Bit 7
Address 0x08, Bit 6
Address 0x08, Bit 5
0 = limit 3.2 V
1 = limit 3.7 V
0 = limit 3.2 V
DIS_RCH
0 = recharge enabled
1 = recharge disabled
0 = watchdog disabled
1 = watchdog enabled
0 = not activated
0 = recharge enabled
0 = disabled
EN_WD
DIS_IC1
0 = not activated
0 = charging disabled
0 = JEITA disabled
0 = JEITA1 charging
0 = limit disabled
00 = VISO_Sx < VISO_Bx
1 = activated
EN_CHG
0 = charging disabled
1 = charging enabled
0 = JEITA disabled
1 = JEITA enabled
0 = JEITA1 charging
1= JEITA2 charging
0 = limit disabled
EN_JEITA
JEITA_SELECT
EN_CHG_VLIM
1 = limit enabled
IDEAL_DIODE[1:0] Address 0x08, Bits[4:3]
00 = ideal diode operates when VISO_Sx < VISO_Bx
01 = ideal diode operates when VISO_Sx < VISO_Bx
and VBAT_SNS > VWEAK
10 = ideal diode is disabled
11 = ideal diode is disabled
DIGITAL INPUT AND OUTPUT OPTIONS
Table 47. I2C Address 0x11, Bits[1:0] SYS_EN Output Default
Option
Selection (Default)
00 = SYS_EN is activated when LDO is active and system voltage is available
01 = SYS_EN is activated by ISO_Bx voltage; battery charging mode
10 = SYS_EN is activated and the isolation FET is disabled when the battery drops below VWEAK
00
1
11 = SYS_EN is active in LDO mode when the charger is disabled. SYS_EN is active in charging mode when VISO_Bx ≥ VWEAK
1 This option is active when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit D5 (EN_BMON).
Rev. B | Page 41 of 44
ADP5062
Data Sheet
DIG_IO1, DIG_IO2, and DIG_IO3 Options
Table 48. DIG_IO1 Polarity
Option
Selection
0 = DIG_IO1 polarity, high active operation
1 = DIG_IO1 polarity, low active operation
0 = high active
Table 49. DIG_IOx Options
Option DIG_IO1 Function
DIG_IO2 Function
DIG_IO3 Function
Charging disable/enable
Low = charging disable
High = charging enabled
Disable IC1
Low = not activated
High = activated
Fast charge current
Low = ICHG[4:0]
High = ICHG[4:0] ÷ 2
LDO
Low = LDO active
High = LDO disabled
Charging
Low = charging disabled
High = charging enabled
Charging
Selection
0000
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IVINx limit
Disable IC1
0000
Low = 100 mA
High = 500 mA
IVINx limit
Low = 100 mA
High= 500 mA
IVINx limit
Low = 100 mA
High= 500 mA
IVINx limit
Low = 100 mA
High= 500 mA
IVINx limit
Low = 100 mA
High= 500 mA
IVINx limit
Low = 100 mA
High= 500 mA
Charging
Low = charging disabled
High = charging enabled
IVINx limit
Low = 100 mA
High= 500 mA
IVINx limit
Low = 100 mA
High= 500 mA
IVINx limit
Low = 100 mA
High= 500 mA
IVINx limit
Low = 100 mA
High= 500 mA
IVINx limit
Low = 100 mA
High= 500 mA
IVINx limit
Low = not activated
High = activated
IVINx limit
N/A
High = IVINx limit 1500 mA
IVINx limit
N/A
High = IVINx limit 1500 mA
IVINx limit
N/A
High = IVIN limit 1500 mA
IVINx limit
N/A
High = IVINx limit 1500 mA
Recharge
N/A
High = disable recharge
Disable IC1
Low = not activated
High = activated
IVINx limit
Low = charging disabled
High = charging enabled
Recharge
N/A
High = disable recharge
Interrupt output
N/A
N/A
High = IVINx limit 1500 mA
Charging
Low = charging disabled
High = charging enabled
Disable IC1
Low = not activated
High = activated
Recharge
N/A
Interrupt output
N/A
N/A
Interrupt output
N/A
N/A
Interrupt output
N/A
N/A
Interrupt output
N/A
N/A
Interrupt output
N/A
N/A
Interrupt output
N/A
N/A
Interrupt output
N/A
N/A
N/A
High = disable recharge
Fast charge current
Low = ICHG
High = ICHG[4:0] ÷ 2
LDO
Low = LDO active
High = LDO disabled
Charging
Low = charging disabled
High = charging enabled
Charging
Low = 100 mA
High= 500 mA
IVINx limit
N/A
High = IVINx limit 1500 mA
Disable IC1
Low = not activated
High = activated
Low = charging disabled
High = charging enabled
Rev. B | Page 42 of 44
Data Sheet
ADP5062
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
PIN 1
INDICATOR
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.75
2.60 SQ
2.35
11
5
6
10
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 42. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADP5062ACPZ-1-R7
ADP5062ACPZ-2-R7
ADP5062CP-EVALZ
Temperature Range (Junction) Package Description
Package Option
CP-20-8
CP-20-8
–40°C to +125°C
–40°C to +125°C
20-Lead LFCSP_WQ
20-Lead LFCSP_WQ
ADP5062 Evaluation Board
1 Z = RoHS Compliant Part.
2 For additional factory-programmable options, contact an Analog Devices local sales or distribution representative.
Rev. B | Page 43 of 44
ADP5062
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10806-0-10/13(B)
Rev. B | Page 44 of 44
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ADP5065ACBZ-1-R7
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