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ADP5065CB-EVALZ [ADI]

Fast Charge Battery Manager with Power Path and USB Compatibility;
ADP5065CB-EVALZ
型号： ADP5065CB-EVALZ
厂家： ADI    ADI
描述：

Fast Charge Battery Manager with Power Path and USB Compatibility

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Fast Charge Battery Manager with Power  
Path and USB Compatibility  
ADP5065  
Data Sheet  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
3 MHz switch mode charger  
ADP5065  
VBUS  
SYSTEM  
AC  
OR  
USB  
VINx  
SWx  
INDUCTOR  
1.25 A charge current from dedicated charger  
Up to 680 mA charging current from 500 mA USB host  
Operating input voltage from 4.0 V up to 5.5 V  
Tolerant input voltage −0.5 V to +20 V (USB VBUS)  
Dead battery isolation FET between battery and  
charger output  
Battery thermistor input with automatic charger shutdown  
for when battery temperature exceeds limits  
Compliant with the JEITA Li-Ion battery charging  
temperature specification  
3MHz  
BUCK  
PGNDx  
ISO_Sx  
CFILT  
IIN_EXT  
TRK_EXT  
SCL  
ISO_Bx  
CHARGER  
CONTROL  
BLOCK  
BAT_SNS  
SDA  
+
Li-Ion  
THR  
SYS_ON_OK  
V_WEAK_SET  
AGND PGNDx  
SYS_EN_OK flag to hold off system turn-on until battery is at  
minimum required level for guaranteed system startup  
due to minimum battery voltage and/or minimum battery  
charge level requirements  
Figure 1.  
EOC programming with C/20, C/10 and specific current level  
selection  
APPLICATIONS  
Digital still cameras  
Digital video cameras  
Single cell Li-Ion portable equipment  
PDA, audio, GPS devices  
Mobile phones  
GENERAL DESCRIPTION  
The ADP5065 charger is fully compliant with the USB 2.0,  
USB 3.0, and USB Battery Charging Specification 1.1 and  
enables charging via the mini USB VBUS pin from a wall  
charger, car charger, or USB host port.  
Based on the type of USB source, which is detected by an external  
USB detection chip, the ADP5065 can be set to apply the correct  
current limit for optimal charging and USB compliance.  
The ADP5065 comes in a very small and low profile 20-lead  
WLCSP (0.5 mm pitch spacing) package.  
The ADP5065 operates from a 4 V to 5.5 V input voltage range  
but is tolerant of voltages of up to 20 V. This alleviates the  
concerns about the USB bus spiking during disconnect or  
connect scenarios.  
The overall solution requires only five small, low profile external  
components consisting of four ceramic capacitors (one of which  
is the battery filter capacitor), one multilayer inductor. In addition  
to these components, there is one optional dead battery situation  
default setting resistor. This configuration enables a very small  
PCB area to provide an integrated and performance enhancing  
solution to USB battery charging and power rail provision.  
The ADP5065 also features an internal FET between the dc-to-  
dc charger output and the battery. This permits battery isolation  
and, hence, system powering under a dead battery or no battery  
scenario, which allows for immediate system function on  
connection to a USB power supply.  
Rev. D  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 
ADP5065  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Battery Isolation FET................................................................. 19  
Battery Detection ....................................................................... 20  
Battery Pack Temperature Sensing .......................................... 21  
External Resistor for V_WEAK_SET...................................... 22  
I2C Interface ................................................................................ 23  
Charger Operational Flowchart ............................................... 24  
I2C Register Map......................................................................... 25  
Register Bit Descriptions........................................................... 26  
Applications Information .............................................................. 32  
External Components................................................................ 32  
PCB Layout Guidelines.................................................................. 34  
Power Dissipation and Thermal Considerations ....................... 35  
Charger Power Dissipation ....................................................... 35  
Junction Temperature ................................................................ 36  
Factory-Programmable Options .................................................. 37  
Packaging and Ordering Information ......................................... 38  
Outline Dimensions................................................................... 38  
Ordering Guide .......................................................................... 38  
Applications....................................................................................... 1  
Functional Block Diagram .............................................................. 1  
General Description ......................................................................... 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Recommended Input and Output Capacitance........................ 5  
I2C-Compatible Interface Timing Specifications..................... 6  
Absolute Maximum Ratings ....................................................... 7  
Thermal Resistance ...................................................................... 7  
ESD Caution.................................................................................. 7  
Pin Configuration and Function Descriptions............................. 8  
Typical Performance Characteristics ............................................. 9  
Temperature Characteristics..................................................... 11  
Typical Waveforms ..................................................................... 13  
Theory of Operation ...................................................................... 15  
Introduction ................................................................................ 15  
Charger Modes............................................................................ 17  
Thermal Management ............................................................... 19  
REVISION HISTORY  
2/13—Rev. C to Rev. D  
Changed Maximum Duty Cycle from 93% to 96%............................. 3  
Changed Bit[3:0] Default Value from 0100 to 0101, Table 16 .. 26  
Changed Bit 5 and Bit 2 Default Values from 1 to 0, Table 21 ....... 29  
Deleted Disconnecting Supply Voltage at VINx Section ............... 34  
9/12—Rev. B to Rev. C  
Changed Bit[3:0] Default Value from 0011 to 0100, Table 16.........27  
Added Disconnecting Supply Voltage at VINx Section ............ 34  
4/12—Rev. A to Rev. B  
Changes to Features Section and General Description Section........ 1  
Changes to Table 1............................................................................ 3  
Changes to VIN1, VIN2 to PGND1, PGND2 Parameter, Table 4 ... 7  
Changes to Introduction Section.................................................. 15  
11/11—Rev. 0 to Rev. A  
Changes to Figure 10...................................................................... 10  
Changes to Figure 17 and Figure 18............................................. 11  
Changes to Figure 41...................................................................... 36  
10/11—Revision 0: Initial Version  
Rev. D | Page 2 of 40  
 
Data Sheet  
ADP5065  
SPECIFICATIONS  
−40°C < TJ < 125°C, VIN = 5.0 V, VISO_S > 3.0 V, VHOT < VTHR < VCOLD, VBAT_SNS = 3.6 V, CVIN = 2.2 µF, CDCDC = 22 µF, CBAT = 22 µF, CCFILT  
4.7 µF, LOUT = 1 µH, all registers are at default values, unless otherwise noted.  
=
Table 1.  
Parameter  
GENERAL PARAMETERS  
Undervoltage Lockout  
Symbol  
VUVLO  
IVIN  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
2.25  
50  
86  
2.35  
100  
92  
2.45  
150  
100  
150  
300  
V
Falling threshold, higher of VCFILT and VBAT_SNS  
Hysteresis, higher of VCFILT and VBAT_SNS rising  
Nominal USB initialized current level1  
USB super speed  
USB enumerated current level (specification  
for China)  
mV  
mA  
mA  
mA  
Total Input Current  
460  
475  
500  
900  
1500  
mA  
mA  
mA  
USB enumerated current level  
Dedicated charger input  
Dedicated wall charger  
Current Consumption  
VINx  
Battery, Standby  
SWxPin Leakage Current  
CHARGING PARAMETERS  
Fast Charge Current, CC Mode  
IQVIN  
IQISO_B  
−IOUT  
15  
0.22  
mA  
µA  
µA  
No battery, no ISO_Sx load, switching 3 MHz  
TJ = −40°C to +85°C  
VVIN = 0 V, TJ = −40°C to +85°C  
2
2
1, 2  
ICHG  
1250  
mA  
VCFILT > VBAT_SNS + VCCDROP  
(Battery Voltage > VTRK_DEAD  
)
Fast Charge Current Accuracy  
ICHG(TOL)  
−7  
−8  
+5  
+8  
%
%
Tj = 25°C, ICHG = 550 mA to 1250 mA  
ICHG = 550 mA to 1150 mA, fast charge current  
accuracy is guaranteed at temperatures from  
Tj = 0°C to isothermal regulation limit (typically  
Tj = 115°C)  
−17  
16  
+8  
25  
%
ICHG = 1250 mA, Tj = 0°C to isothermal regulation  
limit (typically Tj = 115°C)  
Trickle Charge Current1, 2  
Weak Charge Current  
Dead Battery  
Trickle to Weak Charge Threshold  
Trickle to Weak Charge Threshold  
Hysteresis  
ITRK_DEAD  
ICHG_WEAK  
20  
ICHG + 20  
mA  
mA  
1, 3  
When VTRK_DEAD < VBAT_SNS < VWEAK  
On BAT_SNS1  
VTRK_DEAD  
ΔVTRK_DEAD  
2.4  
2.5  
90  
2.6  
V
mV  
Weak Battery  
Weak to Fast Charge Threshold  
On BAT_SNS1, 3  
VWEAK  
ΔVWEAK  
VTRM  
2.9  
3.0  
90  
4.200  
3.1  
V
mV  
V
%
V
mA  
%
Weak Battery Threshold Hysteresis  
Battery Termination Voltage  
Battery Termination Voltage Accuracy  
Battery Overvoltage Threshold  
Charge Complete Current  
On BAT_SNS, TJ = 0°C to 115°C1  
4.158  
−0.3  
4.242  
+0.3  
On BAT_SNS, TJ = 25°C, IEND = 52.5 mA1  
Relative to CFILT voltage, BAT_SNS rising  
VBATOV  
IEND  
VCFILT − 0.15  
52.5  
1
VBAT_SNS = VTRM  
Charge Complete Current Threshold  
Accuracy  
−25  
+25  
IEND = 72.5 mA or 92.5 mA, TJ = 0°C to 115°C  
−35  
−55  
+35  
+55  
%
%
mV  
V
IEND = 52.5 mA, TJ = 0°C to 115°C  
IEND = 32.5 mA, TJ = 0°C to 115°C  
Relative to VTRM, BAT_SNS falling1  
Recharge Voltage Differential  
Battery Node Short Threshold Voltage1  
CHARGER DC-to-DC CONVERTER  
Switching Frequency  
VRCH  
VBAT_SHR  
260  
2.4  
2.3  
2.8  
2.5  
3.2  
fSWCHG  
DMAX  
3
MHz  
%
mA  
V
Maximum Duty Cycle  
96  
1750  
3.3  
5
Peak Inductor Current  
IL(PK)  
1500  
3.21  
2000  
3.39  
Regulated System Voltage  
Load Regulation  
VISO_STRK  
VBAT_SNS < VTRK_DEAD, trickle charging mode  
mV/A  
DC-to-DC Power  
PMOS On Resistance  
NMOS On Resistance  
RDS(ON)P  
RDS(ON)N  
220  
160  
285  
210  
mΩ  
mΩ  
Rev. D | Page 3 of 40  
 
ADP5065  
Data Sheet  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
BATTERY ISOLATION FET  
Bump to Bump Resistance Between  
ISO_Bx and ISO_Sx Bumps  
RDSONISO  
76  
115  
mΩ  
Includes bump resistances and battery isolation  
PMOS on resistance; on battery supplement  
mode, VIN = 0 V, VISO_B = 3.6 V, IISO_B = 500 mA  
VTRK_DEAD < VBAT_SNS, fast charging CC mode  
VISO_S[1:2] < VISO_B[1:2], VSYS rising  
Regulated System Voltage  
Battery Supplementary Threshold  
VISO_SFC  
VTHISO  
3.15  
0
3.3  
5
3.45  
10  
V
mV  
HIGH VOLTAGE BLOCKING FET  
VINx Input  
High Voltage Blocking FET On  
Resistance  
Current, Suspend Mode  
Input Voltage  
RDSONHV  
ISUSPEND  
340  
1.3  
455  
2.5  
mΩ  
mA  
IIN = 500 mA  
EN_CHG = low  
Good Threshold  
Rising  
Falling  
VVIN_OK_RISE 3.78  
VVIN_OK_FALL  
3.9  
3.6  
5.42  
75  
4.0  
3.67  
5.5  
V
V
V
mV  
Overvoltage Threshold  
Overvoltage Threshold Hysteresis  
VINx Transition Timing  
Minimum Rise Time for VINx from  
5 V to 20 V  
VVIN_OV  
5.35  
tVIN_RISE  
tVIN_FALL  
10  
10  
µs  
µs  
Minimum Fall Time for VINx from  
4 V to 0 V  
THERMAL CONTROL  
Isothermal Charging Temperature  
Thermal Early Warning Temperature  
Thermal Shutdown Temperature  
TLIM  
TSDL  
TSD  
115  
130  
140  
110  
°C  
°C  
°C  
°C  
TJ rising  
TJ falling  
THERMISTOR CONTROL  
Thermistor Current  
10,000 NTC  
100,000 NTC  
INTC_10k  
INTC_100k  
CNTC  
400  
40  
100  
μA  
μA  
pF  
°C  
Thermistor Capacitance  
Cold Temperature Threshold  
Resistance Thresholds  
Cool to Cold Resistance  
Cold to Cool Resistance  
Hot Temperature Threshold  
Resistance Thresholds  
Hot to Typical Resistance  
Typical to Hot Resistance  
JEITA SPECIFICATION4  
JEITA Cold Temperature  
Resistance Thresholds  
Cool to Cold Resistance  
Cold to Cool Resistance  
JEITA Cool Temperature  
TNTC_COLD  
0
No battery charging occurs  
No battery charging occurs  
RCOLD_FALL  
RCOLD_RISE  
TNTC_HOT  
24,050 27,300  
23,100 26,200  
60  
30,600  
29,400  
Ω
Ω
°C  
RHOT_FALL  
RHOT_RISE  
2990  
2730  
3310  
3030  
3640  
3330  
Ω
Ω
TJEITA_COLD  
0
°C  
No battery charging occurs  
RCOLD_FALL  
RCOLD_RISE  
TJEITA_COOL  
24,050 27,300  
23,100 26,200  
10  
30,600  
29,400  
Ω
Ω
°C  
Battery charging occurs at 50% of  
programmed level  
Resistance Thresholds  
Typical to Cool Resistance  
Cool to Typical Resistance  
JEITA Typical Temperature  
RTYP_FALL  
RTYP_RISE  
TJEITA_TYP  
15,200 17,800  
14,500 17,000  
20,400  
19,500  
Ω
Ω
°C  
Normal battery charging occurs at  
default/programmed levels  
Resistance Thresholds  
Warm to Typical Resistance  
Typical to Warm Resistance  
JEITA Warm Temperature  
RWARM_FALL  
RWARM_RISE  
TJEITA_WARM  
4710  
4320  
5400  
4950  
45  
6100  
5590  
Ω
Ω
°C  
Battery termination voltage (VTRM) is reduced  
by 100 mV  
Resistance Thresholds  
Hot to Warm Resistance  
Warm to Hot Resistance  
JEITA Hot Temperature  
RHOT_FALL  
RHOT_RISE  
TJEITA_HOT  
2990  
2730  
3310  
3030  
60  
3640  
3330  
Ω
Ω
°C  
No battery charging occurs  
Rev. D | Page 4 of 40  
Data Sheet  
ADP5065  
Parameter  
BATTERY DETECTION  
Sink Current  
Source Current  
Battery Threshold  
Low  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
ISINK  
ISOURCE  
13  
7
20  
10  
34  
13  
mA  
mA  
VBATL  
VBATH  
VNOBAT  
1.8  
1.9  
3.4  
3.3  
2.0  
V
V
V
High  
No Battery Threshold  
VTRM ≥ 3.7 V, valid after charge complete (see  
Figure 38)  
3.0  
V
VTRM < 3.7 V, valid after charge complete (see  
Figure 38)  
Battery Detection Timer  
TIMERS  
tBATOK  
333  
ms  
Start Charging Delay Timer  
Trickle Charge Timer  
Fast Charge Timer  
Charge Complete Timer  
Deglitch Timer  
Watchdog Timer1  
Safety Timer  
Battery Node Short Timer1  
LOGIC INPUTS  
tSTART  
tTRK  
tCHG  
tEND  
tDG  
tWD  
1
sec  
min  
min  
min  
ms  
sec  
min  
sec  
60  
600  
7.5  
31  
32  
40  
30  
VBAT_SNS = VTRM, ICHG < IEND  
Applies to VTRK, VRCH, IEND, VDEAD, VVIN_OK  
tSAFE  
tBAT_SHR  
36  
44  
Maximum Voltage on Digital Inputs  
Maximum Logic Low Input Voltage  
Minimum Logic High Input Voltage  
Pull-Down Resistance  
VDIN_MAX  
VIL  
VIH  
5.5  
0.5  
V
V
V
kΩ  
Applies to SCL, SDA, TRK_EXT, IIN_EXT  
Applies to SCL, SDA, TRK_EXT, IIN_EXT  
Applies to TRK_EXT, IIN_EXT  
1.2  
215  
350  
610  
1 These values are programmable via I2C. Values are given with default register values.  
2 The output current during charging can be limited by IBUS or by the isothermal charging mode.  
3 Programmable via external resistor programming, if required.  
4 JEITA can be enabled or disabled in I2C.  
RECOMMENDED INPUT AND OUTPUT CAPACITANCE  
Table 2.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
CAPACITANCE  
VINx Capacitance  
1.0  
2.0  
10  
µF  
μF  
µF  
µF  
Effective capacitance  
Effective capacitance  
Effective capacitance  
Effective capacitance  
CFILT Pin Total External Capacitance  
ISO_Sx Pin Total Capacitance  
ISO_Bx Pin Total Capacitance  
4.7  
5.0  
50  
10  
Rev. D | Page 5 of 40  
 
 
ADP5065  
Data Sheet  
I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS  
Table 3.  
Parameter1  
Symbol  
Min  
Typ  
Max  
Unit  
I2C-COMPATIBLE INTERFACE2  
Capacitive Load, Each Bus Line  
SCL Clock Frequency  
SCL High Time  
SCL Low Time  
CS  
fSCL  
400  
400  
pF  
kHz  
µs  
µs  
ns  
µs  
µs  
µs  
µs  
µs  
ns  
ns  
ns  
tHIGH  
tLOW  
tSUDAT  
tHDDAT  
tSUSTA  
tHDSTA  
tBUF  
tSUSTO  
tR  
0.6  
1.3  
100  
0
0.6  
0.6  
1.3  
0.6  
20  
20  
0
Data Setup Time  
Data Hold Time  
0.9  
Setup Time for Repeated Start  
Hold Time for Start/Repeated Start  
Bus Free Time Between a Stop and a Start Condition  
Setup Time for Stop Condition  
Rise Time of SCL/SDA  
300  
300  
50  
Fall Time of SCL/SDA  
Pulse Width of Suppressed Spike  
tF  
tSP  
1 Guaranteed by design.  
2 A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 2, the I2C timing  
diagram.  
Timing Diagram  
SDA  
tF  
tBUF  
tF  
tSP  
tR  
tLOW  
tR  
tSU,DAT  
tHD,STA  
SCL  
tHIGH  
tSU,STA  
tSU,STO  
S
Sr  
P
S
tHD,DAT  
S = START CONDITION  
Sr = REPEATED START CONDITION  
P = STOP CONDITION  
Figure 2. I2C Timing Diagram  
Rev. D | Page 6 of 40  
 
 
 
Data Sheet  
ADP5065  
ABSOLUTE MAXIMUM RATINGS  
THERMAL RESISTANCE  
Table 4.  
Parameter  
θJA is specified for the worst-case conditions, that is, a device  
soldered in a circuit board for surface-mount packages.  
Rating  
VIN1, VIN2 to PGND1, PGND2  
All Other Pins to AGND  
Continuous Drain Current, Battery Supple-  
mentary Mode, from ISO_Bx to ISO_Sx  
TJ ≤ 85°C  
TJ = 125°C  
−0.5 V to +20 V  
−0.3 V to +6 V  
Table 5. Thermal Resistance  
Package Type  
20-Lead WLCSP1  
θJA  
θJC  
θJB  
Unit  
46.8 0.7  
9.2  
°C/W  
2.2 A  
1.1 A  
1
5 × 4 array, 0.5 mm pitch (2.75 mm × 2.08 mm); based on a JEDEC, 2S2P,  
4-layer board with 0 m/sec airflow.  
Storage Temperature Range  
Operating Junction Temperature Range  
Soldering Conditions  
−65°C to +150°C  
−40°C to +125°C  
JEDEC J-STD-020  
Maximum Power Dissipation  
The maximum safe power dissipation in the ADP5065 package  
is limited by the associated rise in junction temperature (TJ) on  
the die. At approximately 150°C, which is the glass transition  
temperature, the plastic changes its properties. Even temporarily  
exceeding this temperature limit may change the stresses that  
the package exerts on the die, permanently shifting the para-  
metric performance of the ADP5065. Exceeding a junction  
temperature of 175°C for an extended period of time can result  
in changes in the silicon devices that potentially cause failure.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
ESD CAUTION  
Rev. D | Page 7 of 40  
 
 
 
 
 
ADP5065  
Data Sheet  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
BALL A1  
CORNER  
1
2
3
4
V_WEAK_SET SCL  
THR  
IIN_EXT  
A
SDA  
TRK_EXT ISO_B1  
ISO_B2  
ISO_S2  
PGND1  
PGND2  
B
C
D
E
BAT_SNS  
AGND  
ISO_S1  
VIN1 SYS_ON_OK SW1  
VIN2  
CFILT  
SW2  
TOP VIEW  
(BALL SIDE DOWN)  
Not to Scale  
Figure 3. Pin Configuration  
Table 6. Pin Function Descriptions  
Pin  
No.  
Mnemonic  
SW1, SW2  
VIN1, VIN2  
PGND1,  
PGND2  
Type1 Description  
D3, E3  
D1, E1  
D4, E4  
I/O  
I/O  
G
DC-to-DC Converter Inductor Connection. These pins are high current outputs when in charging mode.  
Power Connection to USB VBUS. These pins are high current inputs when in charging mode.  
Charger Power Ground. These pins are high current inputs when in charging mode.  
C2  
E2  
AGND  
CFILT  
G
I/O  
Analog Ground.  
4.7 μF Filter Capacitor Connection. This pin is a high current input/output when in charging mode.  
Charger Supply Side Input to Internal Isolation FET/Battery Current Regulation FET.  
Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET.  
C3, C4  
B3, B4  
ISO_S1, ISO_S2 I/O  
ISO_B1,  
ISO_B2  
I/O  
A2  
B1  
A4  
SCL  
SDA  
IIN_EXT  
I
I2C-Compatible Interface Serial Clock.  
I2C-Compatible Interface Serial Data.  
Set Input Current Limit. This pin sets the input current limit directly. When IIN_EXT = low or high-Z, the  
input limit is 100 mA. When IIN_EXT = high, the input limit is 500 mA.  
I/O  
I
B2  
TRK_EXT  
I
Enable Trickle Charge Function. When TRK_EXT = low or high-Z, the trickle charge is enabled. When  
TRK_EXT = high, the trickle charge is disabled.  
A3  
C1  
D2  
THR  
BAT_SNS  
SYS_ON_OK  
I
I
O
Battery Pack Thermistor Connection. If not used, connect a dummy 10 kΩ resistor from THR to GND.  
Battery Voltage Sense Pin.  
Battery Okay Open-Drain Output Flag. Active low. This pin enables the system when the battery  
reaches VWEAK  
.
A1  
V_WEAK_SET  
I/O  
External Resistor Setting Pin for V_WEAK threshold. The use of this pin is optional. When not in use,  
connect to GND.  
1 I is input, O is output, I/O is input/output, and G is ground.  
Rev. D | Page 8 of 40  
 
 
Data Sheet  
ADP5065  
TYPICAL PERFORMANCE CHARACTERISTICS  
100  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
V
INPUT LIMIT 500mA  
INPUT LIMIT 100mA  
IN  
IN  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
V
2.5  
2.9  
3.3  
3.7  
4.1  
4.5  
0.01  
0.1  
1
BATTERY VOLTAGE (V)  
SYSTEM OUTPUT CURRENT (A)  
Figure 4. Battery Charger Efficiency vs. Battery Voltage, VIN = 5.0 V  
Figure 7. System Voltage Efficiency vs. Output Current, VIN = 5.0 V  
3.35  
3.34  
3.33  
3.32  
3.31  
3.30  
3.29  
3.28  
3.27  
3.26  
3.25  
4.5  
4.3  
4.1  
3.9  
3.7  
3.5  
SYSTEM VOLTAGE  
3.3  
3.1  
2.9  
BATTERY VOLTAGE  
2.7  
2.5  
0.001  
0.01  
0.1  
1
2.7  
3.0  
3.3  
3.6  
3.9  
4.2  
SYSTEM OUTPUT CURRENT (A)  
BATTERY VOLTAGE (V)  
Figure 5. System Voltage Regulation vs. Output Current, VIN = 5.0 V  
Figure 8. System Voltage vs. Battery Voltage, VIN = 5.0 V, ILIM = 100 mA  
700  
600  
500  
400  
300  
200  
100  
0
140  
120  
100  
80  
60  
40  
20  
0
2.7  
3.0  
3.3  
3.6  
3.9  
4.2  
2.7  
3.0  
3.3  
3.6  
3.9  
4.2  
BATTERY VOLTAGE (V)  
BATTERY VOLTAGE (V)  
Figure 6. USB Compliant Charge Current vs. Battery Voltage,  
VIN = 5.0 V, ILIM = 500 mA  
Figure 9. USB Limited Battery Charge Current vs. Battery Voltage,  
VIN = 5.0 V, ILIM = 100 mA  
Rev. D | Page 9 of 40  
 
ADP5065  
Data Sheet  
100  
95  
90  
85  
80  
75  
4.4  
4.2  
4.0  
3.8  
3.6  
3.4  
3.2  
3.0  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
V
BAT_SNS  
I
ISO_B  
I
VIN  
70  
2.7  
3.0  
3.3  
3.6  
3.9  
4.2  
0
50  
100  
CHARGE TIME (Minutes)  
150  
BATTERY VOLTAGE (V)  
Figure 10. Battery Isolation FET Resistance vs. Battery Voltage, VIN = 5.0 V,  
Load Current = 1.0 A  
Figure 12. Charge Profile, VIN = 5.0 V, ILIM = 500 mA,  
Battery Capacity = 1320 mAh  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
1
2
3
4
5
6
VIN VOLTAGE (V)  
Figure 11. VINx Current vs. VINx Voltage, Suspend Mode (EN_CHG = 0)  
Rev. D | Page 10 of 40  
Data Sheet  
ADP5065  
TEMPERATURE CHARACTERISTICS  
5.75  
1.0  
0.5  
V
V
V
V
= 3.50V  
= 3.80V  
= 4.20V  
= 4.42V  
TRM  
TRM  
TRM  
TRM  
5.70  
5.65  
5.60  
5.55  
5.50  
5.45  
5.40  
5.35  
5.30  
5.25  
0
–0.5  
–1.0  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
AMBIENT TEMPERATURE (°C)  
AMBIENT TEMPERATURE (°C)  
Figure 13. VINx Overvoltage Protection Rising Threshold vs. Ambient  
Temperature  
Figure 16. Termination Voltage vs. Ambient Temperature, VIN = 5.0 V, VTRM  
Programming 3.50 V, 3.80 V, 4.20 V, and 4.42 V  
3.10  
3.08  
3.06  
3.04  
3.02  
3.00  
2.98  
2.96  
2.94  
2.92  
2.90  
3.315  
3.310  
3.305  
3.300  
3.295  
3.290  
3.285  
3.280  
3.275  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
AMBIENT TEMPERATURE (°C)  
AMBIENT TEMPERATURE (°C)  
Figure 17. Switching Frequency vs. Ambient Temperature, VIN = 5.0 V  
Figure 14. System Voltage vs. Ambient Temperature, VIN = 5.0 V, RLOAD = 33 Ω  
500  
1.10  
1.09  
1.08  
1.07  
1.06  
1.05  
1.04  
1.03  
1.02  
1.01  
1.00  
V
IN  
INPUT LIMIT 500mA  
450  
400  
350  
300  
250  
200  
150  
100  
50  
V
IN  
INPUT LIMIT 100mA  
0
–40  
–20  
0
20  
40  
60  
80  
100  
120  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
AMBIENT TEMPERATURE (°C)  
AMBIENT TEMPERATURE (°C)  
Figure 15. Input Current Limit vs. Ambient Temperature, VIN = 5.0 V  
Figure 18. Fast Charge Current vs. Ambient Temperature,  
VIN = 5.0 V, VISO_B = 3.6 V, ICHG = 1050 mA  
Rev. D | Page 11 of 40  
 
ADP5065  
Data Sheet  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
V
V
V
= 2.7V  
= 3.6V  
= 4.2V  
ISO_B  
ISO_B  
ISO_B  
0
–40  
–20  
0
20  
40  
60  
80  
0
20  
40  
60  
80  
100  
120  
AMBIENT TEMPERATURE (°C)  
AMBIENT TEMPERATURE (°C)  
Figure 19. Battery Leakage Current vs. Ambient Temperature  
Figure 21. Isothermal Regulation of Charge Current vs. Ambient  
Temperature, ICHG = 750 mA, VIN = 5.0 V, VISO_B = 3.6 V  
1.34  
1.32  
1.30  
1.28  
1.26  
1.24  
1.22  
1.20  
1.18  
1.16  
–40  
–20  
0
20  
40  
60  
80  
AMBIENT TEMPERATURE (°C)  
Figure 20. VINx Quiescent Current vs. Temperature, VIN = 5.0 V,  
Suspend Mode (EN_CHG = 0)  
Rev. D | Page 12 of 40  
Data Sheet  
ADP5065  
TYPICAL WAVEFORMS  
T
T
C
INRUSH  
IN  
CURRENT  
I
ISO_B  
I
ISO_B  
3
4
3
4
I
VIN  
I
VIN  
V
V
ISO_S  
ISO_S  
V
IN  
V
IN  
2
1
2
1
CH1 2.0V  
CH3 200mA CH4 200mA  
CH2 2.0V  
100µs  
T
A
CH2  
44mA  
CH1 2.0V  
CH3 200mA CH4 200mA  
CH2 2.0V  
100µs  
T
A
CH3  
44mA  
0.00s  
0.00s  
Figure 22. Typical Waveforms, VINx Connect From High Impedance to  
VBUS, ILIM = 100 mA  
Figure 25. Typical Waveforms, VINx Disconnect from VBUS to High  
Impedance, ILIM = 100 mA  
T
T
I
ISO_B  
I
ISO_B  
3
4
3
4
I
VIN  
I
VIN  
V
V
ISO_S  
ISO_S  
V
IN  
V
IN  
2
1
2
1
CH1 2.0V  
CH3 500mA CH4 500mA  
CH2 2.0V  
20µs  
T
A
CH3  
40mA  
CH1 2.0V  
CH3 500mA CH4 500mA  
CH2 2.0V  
100µs  
T
A
CH3  
40mA  
0.00s  
0.00s  
Figure 23. Mode Change, Fast Charge to Suspend (EN_CHG from High to  
Low), ILIM = 500 mA, RLOAD = 33 Ω  
Figure 26. Mode Change, Suspend to Fast Charge (EN_CHG from Low to  
High), ILIM = 500 mA, RLOAD = 33 Ω  
T
T
V
ISO_S  
2
1
4
I
ISO_B  
SW  
3
4
I
VIN  
V
ISO_S  
V
IN  
2
1
I
SW  
B
CH1 2.0V  
CH3 500mA CH4 500mA  
CH2 2.0V  
100µs  
T
A
CH3  
430mA  
CH1 2.0V CH2 50.0mV  
CH4 500mA  
800ns  
T
A
CH1  
2.16V  
W
0.00s  
–8.0ns  
Figure 24. VINx Current Limit Change from 100 mA to 500 mA,  
EN_CHG = High, VIN = 5.0 V, RLOAD = 33 Ω  
Figure 27. Typical Waveforms, Heavy Load, VIN = 5.0 V, IISO_S = 1000 mA  
Rev. D | Page 13 of 40  
 
ADP5065  
Data Sheet  
T
T
V
ISO_S  
SW  
2
V
ISO_S  
1
1A  
1
4
I
SW  
I
ISO_S  
0A  
4
B
B
W
CH1 100mV  
CH4 500mA  
200µs  
T
A
CH4  
250mA  
CH1 2.0V CH2 50.0mV  
CH4 200mA  
800ns  
T –8.00ns  
A
CH1  
2.16V  
W
600.0µs  
Figure 28. System Voltage Load Transient, VIN = 5.0 V, No Battery  
Figure 30. Typical Waveforms, Light Load, VIN = 5.0 V, IISO_S = 100 mA  
T
C
AND C  
ISO_S  
ISO_B  
INRUSH CURRENT  
I
ISO_B  
3
V
ISO_S  
2
CH2 2.0V  
100µs  
T
A
CH2  
2.76V  
CH3 2.0A  
0.00s  
Figure 29. Battery Connect  
Rev. D | Page 14 of 40  
Data Sheet  
ADP5065  
THEORY OF OPERATION  
The ADP5065 is fully compliant with the USB 3.0 battery charging  
specification and enables charging via the mini USB VBUS pin  
from a wall charger, car charger, or USB host port. Based on the  
type of USB source, which is detected by an external USB  
detection device, the ADP5065 can be set to apply the correct  
current limit for optimal charging and USB compliance. The USB  
charger permits correct operation under all USB compliant  
sources such as, wall chargers, host chargers, hub chargers, and  
standard hosts and hubs.  
INTRODUCTION  
The ADP5065 is a fully I2C-programmable charger for single-  
cell lithium-ion or lithium-polymer batteries suitable for a wide  
range of portable applications.  
The highly efficient switcher dc-to-dc architecture enables higher  
charging currents as well as a lower temperature charging  
operation that results in faster charging times because of the  
following features:  
A processor is able to control the USB charger using the I2C to  
program the charging current and numerous other parameters  
including  
•
•
•
3 MHz switch mode charger.  
1.25 A charge current from dedicated charger.  
Up to 680 mA of charging current from a 500 mA  
USB host.  
•
•
•
•
•
Trickle charge current level.  
The ADP5065 operates from an input voltage from 4 V to 5.5 V  
but is tolerant of voltages of up to 20 V. This alleviates the concern  
about USB bus spiking during disconnection or connection  
scenarios.  
Trickle charge voltage threshold.  
Weak charge (constant current) charge current level.  
Fast charge (constant current) charge current level.  
Fast charge (constant voltage) charge voltage level at 1%  
accuracy.  
The ADP5065 features an internal FET between the dc-to-dc  
charger output and the battery. This permits battery isolation  
and, hence, system powering in a dead battery or no battery  
scenario, which allows for immediate system function on  
connection to a USB power supply.  
•
•
•
•
•
•
•
Fast charge safety timer period.  
Watchdog safety timer parameters.  
Weak battery threshold detection.  
Charge complete threshold.  
Recharge threshold.  
Charge enable/disable.  
Battery pack temperature detection and automatic charger  
shutdown.  
Rev. D | Page 15 of 40  
 
 
ADP5065  
Data Sheet  
E2  
COIL  
CURRENT  
DETECTION  
IND_PEAK_INT  
HIGH VOLTAGE  
BLOCKING FET  
TO USB VBUS  
OR WALL  
ADAPTER  
SW1  
SW2  
VIN1  
VIN2  
D1  
E1  
D3  
E3  
+
–
+
–
HV-FET  
CONTROL  
DC-DC CONTROL  
5.42V  
VIN LIMIT  
VIN  
ISO_S1  
ISO_S2  
C3  
C4  
TO SYSTEM  
LOAD  
OVERVOLTAGE  
3MHz OSC  
BATTERY  
ISOLATION FET  
CFILT  
TRICKLE  
CURRENT  
SOURCE  
+
–
3.9V  
+
VIN GOOD  
–
EOC  
ISO_B1  
ISO_B2  
B3  
B4  
CHARGE CONTROL  
+
–
CV-MODE  
RECHARGE  
2
I C INTERFACE  
SCL  
SDA  
BATTERY  
DETECTION  
SINK  
A2  
B1  
AND  
CONTROL LOGIC  
+
–
WEAK  
+
–
TRICKLE  
IIN_EXT  
A4  
B2  
BATTERY:  
OPEN  
BAT_SNS  
TRK_EXT  
+
–
C1  
SHORT  
3.4V  
1.9V  
BATTERY DETECTION  
+
–
CFILT – 150mV  
V_WEAK_SET  
+
–
BATTERY OVERVOLTAGE  
COLD  
A1  
0.5V  
COOL  
NTC CURRENT  
CONTROL  
WARM  
SYS_ON_OK  
D2  
HOT  
SYSTEM  
VOLTAGE OK  
LOGIC  
THR  
+
–
A3  
0.5V  
THERMAL CONTROL  
C2  
D4 E4  
SINGLE CELL  
Li-Ion  
Figure 31. Block Diagram  
Rev. D | Page 16 of 40  
Data Sheet  
ADP5065  
The ADP5065 also includes a number of significant features to  
optimize charging and functionality, including  
Table 8. Input Current Compatibility with Standard USB Limits  
Mode  
Standard USB Limit  
ADP5065 Function  
USB  
(China  
Only)  
100 mA limit for stan- 100 mA input current limit  
dard USB host or hub or I2C programmed value  
•
•
•
•
Thermal regulation for maximum performance.  
USB host current-limit accuracy: 5 %.  
Termination voltage accuracy: 1 %.  
Battery thermistor input with automatic charger shutdown  
in the event that the battery temperature exceeds limits.  
(Compliant with the JEITA Li-Ion battery charging  
temperature specification.)  
Offloads processor to manage external pin (TRK_EXT)  
control to enable/disable trickle charging.  
300 mA limit for  
Chinese USB  
specification  
300 mA input current limit  
or I2C programmed value  
USB 2.0  
USB 3.0  
100 mA limit for stan-  
dard USB host or hub  
100 mA input current limit  
or I2C programmed value  
500 mA limit for stan- 500 mA input current limit  
dard USB host or hub or I2C programmed value  
•
•
•
150 mA limit for  
super speed USB 3.0  
host or hub  
150 mA input current limit  
or I2C programmed value  
Direct external pin (IIN_EXT) control of 100 mA or  
500 mA input current limit.  
900 mA limit for  
super speed, high  
speed USB host or  
hub charger  
900 mA input current limit  
or I2C programmed value  
Optional external resistor programming input, V_WEAK_  
SET, which is used for setting the VWEAK threshold. When  
the battery reaches the VWEAK threshold, the ADP5065 pulls  
down the SYS_EN_OK open-drain output flag. The flag can  
be used to hold off system turn on until the battery is at the  
minimum required level for a guaranteed system startup.  
Dedicated 1500 mA limit for  
Charger  
1500 mA input current limit  
or I2C programmed value  
dedicated charger or  
low/full speed USB  
host or hub charger  
CHARGER MODES  
Input Current Limit  
Trickle Charge Mode  
A deeply discharged Li-Ion cell may exhibit a very low cell  
voltage making it unsafe to charge the cell at high current rates. The  
ADP5065 charger uses a trickle charge mode to reset the battery  
pack protection circuit and lift the cell voltage to a safe level for fast  
charging. A cell with a voltage below VTRK_DEAD is charged with  
the trickle mode current, ITRK_DEAD. During trickle charging mode,  
the CHARGER_STATUS register is set.  
The VINx input current limit is controlled via an internal I2C  
ILIM register. The input current limit can also be controlled via  
the IIN_EXT pin as outlined in Table 7. Any change in the I2C  
default from 100 mA dominates over the pin setting.  
Table 7. IIN_EXT Operation  
IIN_EXT  
Function  
During trickle charging, the ISO_Sx node is regulated to  
0
1
100 mA input current limit or I2C programmed value  
V
ISO_STRK by the dc-to-dc converter and the battery isolation FET  
500 mA input current limit or I2C programmed value  
(or reprogrammed I2C value from 100 mA default)  
is off, which means the battery is isolated from the system  
power supply.  
USB Compatibility  
Trickle charging can be controlled via the TRK_EXT external  
pin (see Table 9). Note that any change in the I2C EN_TRK bit  
dominates over the pin setting.  
The ADP5065 charger provides support for the following  
connections through the single connector VINx pin.  
The ADP5065 features a programmable input current limit to  
ensure compatibility with the requirements listed in Table 8. The  
current limit defaults to 100 mA to allow compatibility with a  
USB host or hub that is not configured.  
The I2C register default is 100 mA. An I2C write command  
to the ILIM register overrides the IIN_EXT pin and the I2C  
register default value can be reprogrammed for alternative  
requirements.  
Table 9. TRK_EXT Operation  
TRK_EXT  
Function  
0
1
Trickle charge enabled  
Trickle charge disabled  
Trickle Charge Mode Timer  
The duration of trickle charge mode is monitored to ensure the  
battery is revived from its deeply discharged state. If trickle  
charge mode runs for longer than 60 minutes without the cell  
voltage reaching VTRK_DEAD, a fault condition is assumed and  
charging stops. The fault condition is asserted on the  
CHARGER_STATUS register, allowing the user to initiate  
the fault recovery procedure specified in the Fault Recovery  
section.  
When the input current limiting feature is used, the available  
input current may be too low for the charger to meet the pro-  
grammed charging current, ICHG, and the rate of charge is  
reduced. In this case, the VIN_ILIM flag is set.  
When connecting voltage to VINx without having the proper  
voltage level on the battery side, the HV blocking part is in a  
state wherein it draws only 1.3 mA (typical) of current until the  
V
IN has reached the VIN_OK level.  
Rev. D | Page 17 of 40  
 
 
 
 
ADP5065  
Data Sheet  
Weak Charge Mode (Constant Current)  
Fast Charge Mode (Constant Voltage)  
When the battery voltage exceeds VTRK_DEAD but is less than  
As the battery charges, its voltage rises and approaches the termi-  
nation voltage, VTRM. The ADP5065 charger monitors the voltage  
on the BAT_SNS pin to determine when charging should end.  
However, the internal ESR of the battery pack combined with  
PCB and other parasitic series resistances creates a voltage drop  
between the sense point at the BAT_SNS pin and the cell terminal  
itself. To compensate for this and ensure a fully charged cell, the  
ADP5065 enters a constant voltage charging mode when the  
termination voltage is detected on the BAT_SNS pin. The  
ADP5065 reduces charge current gradually as the cell continues to  
charge, maintaining a voltage of VTRM on the BAT_SNS pin. During  
fast charge mode (constant voltage), the CHARGER_ STATUS  
register is set.  
V
WEAK, the charger switches to the intermediate charge mode.  
During the weak charge mode, the battery voltage is too low to  
allow the full system to power-up. Due to the low level of the  
battery, the USB transceiver cannot be powered and, therefore,  
cannot enumerate for more current from a USB host.  
Consequently, the USB limit remains at 100 mA.  
The system microcontroller may or may not be powered by the  
charger output voltage (VISO_SFC) depending upon the amount of  
current required by the microcontroller and/or the system  
architecture. In this case, the battery charge current (ICHG_WEAK  
)
cannot be increased above 20 mA to ensure the microcontroller  
can still operate (if doing so) nor increased above the 100 mA  
USB limit. Thus, set the battery charging current as follows:  
Fast Charge Mode Timer  
The duration of fast charge mode is monitored to ensure that  
the battery is charging correctly. If the fast charge mode runs for  
longer than tCHG without the voltage at the BAT_SNS pin  
reaching VTRM, a fault condition is assumed and charging stops.  
The fault condition is asserted on the CHARGER_STATUS reg-  
ister allowing the user to initiate the fault recovery procedure  
specified in the Fault Recovery section.  
•
Set the default 20 mA via the linear trickle charger branch (to  
ensure that the microprocessor remains alive if powered by  
the main switching charger output, ISO_Sx). Any residual  
current on the main switching charger output, ISO_Sx, is  
used to charge the battery at up to the preprogrammed  
level in the I2C for ICHG (fast charge current limit) or ILIM  
(input current limit).  
If the fast charge mode runs for longer than tCHG, and VTRM has  
been reached on the BAT_SNS pin but the charge current has  
not yet fallen below IEND, charging stops. No fault condition is  
asserted in this circumstance and charging resumes as normal if  
the recharge threshold is breached.  
•
During weak current mode, other features may prevent the  
actual programmed weak charging current from reaching  
its full programmed value. Isothermal charging mode or  
input current limiting for USB compatibility may affect the  
programmed weak charging current value under certain  
operating conditions. During weak charging, the ISO_Sx  
node is regulated to VISO_SFC by the battery isolation FET.  
Watchdog Timer  
The ADP5065 charger features a programmable watchdog timer  
function to ensure charging is under the control of the  
Fast Charge Mode (Constant Current)  
processor. The watchdog timer starts running when the  
ADP5065 charger determines that the processor should be  
operational, that is, when the processor sets the RESET_WD bit  
for the first time or when the battery voltage is greater than the  
weak battery threshold, VWEAK. When the watchdog timer has  
been triggered, it must be reset regularly within the watchdog  
When the battery voltage exceeds VTRK_DEAD and VWEAK, the  
charger switches to fast charge mode, charging the battery with  
the constant current, ICHG. During fast charge mode (constant  
current), the CHARGER_STATUS register is set.  
During constant current mode, other features may prevent the  
current, ICHG, from reaching its full programmed value.  
Isothermal charging mode or input current limiting for USB  
compatibility may affect the value of ICHG under certain oper-  
ating conditions. The voltage on ISO_Sx is regulated to stay at  
timer period, tWD  
.
If the watchdog timer expires without being reset while in  
charger mode, the ADP5065 charger assumes there is a software  
problem and triggers the safety timer, tSAFE. For more infor-  
mation see the Safety Timer section.  
V
ISO_SFC by the battery isolation FET when VISO_B < VISO_SFC.  
Rev. D | Page 18 of 40  
 
Data Sheet  
ADP5065  
Safety Timer  
Thermal Shutdown and Thermal Early Warning  
If the watchdog timer (see the Watchdog Timer section for  
more information) expires while in charger mode, the ADP5065  
charger initiates the safety timer, tSAFE. If the processor has  
programmed charging parameters by this time, the ILIM is set to  
the default value. Charging continues for a period of tSAFE, then  
the charger switches off and sets the CHARGER_STATUS register.  
The ADP5065 switching charger features a thermal shutdown  
threshold detector. If the die temperature exceeds TSD, the  
ADP5065 charger is disabled, and the TSD 140°C bit is set. The  
ADP5065 charger can be reenabled when the die temperature  
drops below the TSD falling limit and the TSD 140°C bit is reset.  
To reset the TSD 140°C bit, write to the I2C Fault Register 0x0D  
or cycle the power.  
Charge Complete  
Before die temperature reaches TSD, the early warning bit is set if  
The ADP5065 charger monitors the charging current while  
in constant voltage fast charge mode. If the current falls  
below IEND and remains below IEND for tEND, charging stops  
and the CHDONE flag is set. If the charging current falls below  
T
SDL is exceeded. This allows the system to accommodate power  
consumption before thermal shutdown occurs.  
Fault Recovery  
I
END for less than tEND and then rises above IEND again, the tEND  
Before performing the following operation, it is important to  
ensure that the cause of the fault has been rectified.  
timer resets.  
Recharge  
To recover from a charger fault (when the CHARGER_STATUS  
equals 110), cycle power on VINx or write high to reset the I2C  
fault bits in the fault register.  
After the detection of charge complete, and the cessation of  
charging, the ADP5065 charger monitors the BAT_SNS pin as  
the battery discharges through normal use. If the BAT_SNS pin  
voltage falls to VRCH, the charger reactivates charging. Under  
most circumstances, triggering the recharge threshold results in  
the charger starting directly into fast charge constant voltage  
mode.  
BATTERY ISOLATION FET  
The ADP5065 charger features an integrated battery isolation  
FET for power path control. The battery isolation FET isolates a  
deeply discharged Li-Ion cell from the system power supply in  
both trickle and fast charge modes, thereby allowing the system  
to be powered at all times.  
Battery Charging Enable/Disable  
The ADP5065 charging function can be disabled by setting the  
I2C EN_CHG bit to low.  
When VINx is below VVIN_OK, the battery isolation FET is in full  
conducting mode.  
THERMAL MANAGEMENT  
Isothermal Charging  
The battery isolation FET is off during trickle charge mode.  
When the battery voltage exceeds VTRK, the battery isolation  
FET switches to the system voltage regulation mode. During  
system voltage regulation mode, the battery isolation FET  
maintains the VISO_SFC voltage on the ISO_Sx pins. When the  
battery voltage exceeds VISO_SFC, the battery isolation FET is in  
full conducting mode.  
To assist with the thermal management of the ADP5065  
charger, the battery charger provides an isothermal charging  
function. As the on-chip power dissipation and die temperature  
increase, the ADP5065 charger monitors die temperature and  
limits output current when the temperature reaches TLIM  
(typically at 115°C). The die temperature is maintained at TLIM  
through the control of the charging current into the battery. A  
reduction in power dissipation or ambient temperature may  
allow the charging current to return to its original value, and  
the die temperature subsequently drops below TLIM. During  
isothermal charging, the THERM_LIM flag is set to high.  
The battery isolation FET supplements the battery to support  
high current functions on the system power supply.  
When voltage on ISO_Sx drops below ISO_Bx, the battery  
isolation FET enters into full conducting mode.  
When voltage on ISO_Sx rises above ISO_Bx, the isolation FET  
enters regulating mode or full conduction mode, depending on the  
Li-Ion cell voltage and the dc-to-dc charger mode.  
Rev. D | Page 19 of 40  
 
 
 
 
ADP5065  
Data Sheet  
Battery (ISO_Bx) Short Detection  
BATTERY DETECTION  
A battery short occurs under a damaged battery condition or  
when the battery protection circuitry is enabled.  
Battery Level Detection  
The ADP5065 charger features a battery detection mechanism to  
detect an absent battery. The charger actively sinks and sources  
current into the ISO_Bx/BAT_SNS node, and voltage vs. time is  
detected. The sink phase is used to detect a charged battery,  
whereas the source phase is used to detect a discharged battery.  
On commencing trickle charging, the ADP5065 charger moni-  
tors the battery voltage. If this battery voltage does not exceed  
VBAT_SHR within the specified timeout period, tBAT_SHR, a fault is  
declared and the charger is stopped by turning the battery  
isolation FET off but the system voltage is maintained at  
The sink phase (see Figure 32) sinks ISINK current from the  
ISO_Bx/ BAT_SNS pins for a time, tBATOK. If the BAT_SNS pin is  
below VBATL when the tBATOK timer expires, the charger assumes no  
battery is present, and starts the source phase. If the BAT_SNS  
exceeds the VBATL voltage when the tBATOK timer expires, the  
charger assumes the battery is present, and begins a new charge  
cycle.  
VISO_STRK by the linear regulator.  
The trickle charge branch is active during the battery short  
scenario, and trickle charge current to the battery is maintained  
until the 60 minute trickle charge mode timer expires.  
After source phase, if the ISO_Bx or BAT_SNS level remains  
below VBATH, either the battery voltage is low or the battery node  
can be shorted. As a result of the battery voltage being low,  
trickle charging mode is initiated (see Figure 33). If the  
BAT_SNS level remains below VBAT_SHR after tBAT_SHR has elapsed,  
the ADP5065 assumes that the battery node is shorted.  
The source phase sources ISOURCE current to ISO_Bx or the  
BAT_SNS pins for a time, tBATOK. If the BAT_SNS pin exceeds  
VBATH before the tBATOK timer expires, the charger assumes that  
no battery is present. If the BAT_SNS does not exceed the VBATH  
voltage when the tBATOK timer expires, the charger assumes that a  
battery is present, and begins a new charge cycle.  
SINK PHASE  
SOURCE PHASE  
V
V
BATH  
LOGIC  
STATUS  
LOGIC  
STATUS  
BATL  
tBAT_OK  
tBAT_OK  
OPEN  
OR  
SHORT  
OPEN  
ISO_Bx  
ISO_Bx  
Figure 32. Battery Detection Sequence  
SINK PHASE  
SOURCE PHASE  
V
TRICKLE CHARGE  
V
V
BATL  
BATH  
BAT_SHR  
LOGIC  
STATUS  
LOGIC  
STATUS  
LOGIC  
STATUS  
tBAT_OK  
tBAT_OK  
tBAT_SHR  
SHORT  
OR  
OPEN  
OR  
SHORT  
SHORT  
LOW  
BATTERY  
ISO_Bx  
ISO_Bx  
ISO_Bx  
Figure 33. Battery Short Detection Sequence  
Rev. D | Page 20 of 40  
 
 
 
Data Sheet  
ADP5065  
The ADP5065 charger monitors the voltage in the THR pin and  
suspends charging if the current is outside the range of less than  
0°C or greater than 60°C. For temperatures greater than 0°C,  
the THR_STATUS register is set accordingly, and for temperatures  
lower than 60°C, the THR_STATUS register is, likewise, set  
accordingly.  
BATTERY PACK TEMPERATURE SENSING  
Battery Thermistor Input  
The ADP5065 charger features battery pack temperature  
sensing that precludes charging when the battery pack  
temperature is outside the specified range. The THR pin  
provides an on and off switching current source, which should  
be connected directly to the battery pack thermistor terminal.  
The activation interval of the THR current source is 167 ms.  
The ADP5065 charger is designed for use with an NTC  
thermistor in the battery pack with a nominal room tempera-  
ture value of either 10 kΩ at 25°C or 100 kΩ at 25°C, which is  
selected by a fuse.  
The battery pack temperature sensing can be controlled by  
I2C using the conditions shown in Table 10. Note that the  
I2C register default setting for EN_THR (Register 0x07) is  
0 = temperature sensing off.  
The ADP5065 charger is designed for use with an NTC  
thermistor in the battery pack with a temperature coefficient  
curve (beta). Fuse-selectable beta programming is supported by  
eight steps covering a range from 3150 to 4400 (see Table 34).  
Table 10. THR Input Function  
Conditions  
JEITA Li-Ion Battery Temperature Charging Specification  
VINx  
VISO_B  
THR Function  
Off  
Off, controlled by I2C  
The ADP5065 is compliant with the JEITA Li-Ion battery  
charging temperature specifications as outlined in Table 11.  
The JEITA function can be enabled via the I2C interface. When  
the ADP5065 detects a JEITA cool condition, charging current  
is reduced according to Table 12.  
Open or VIN = 0 V to 4.0 V <2.5 V  
Open or VIN = 0 V to 4.0 V >2.5 V  
4.0 V to 5.5 V  
Don't care Always on  
If the battery pack thermistor is not connected directly to the  
ADP5065 THR pin, a 10 kΩ (tolerance 20%) dummy resistor  
must be connected between the THR input and GND. Leaving  
the THR pin open results in a false detection of the battery  
temperature being <0°C and charging is disabled.  
When the ADP5065 identifies a hot or cold battery condition,  
the ADP5065 takes the following actions:  
•
•
Stops charging the battery.  
Connects/enables the battery isolation FET such that the  
system power supply node is connected to the battery.  
Table 11. JEITA Li-Ion Battery Charging Specification Defaults  
Parameter  
Symbol  
IJEITA_COLD  
IJEITA_COOL  
Conditions  
Min Max Unit  
JEITA Cold Temperature Limits  
JEITA Cool Temperature Limits  
No battery charging occurs.  
Battery charging occurs at approximately 50% of programmed level.  
See Table 12 for specific charging current reduction levels.  
0
10  
°C  
°C  
0
JEITA Typical Temperature Limits  
JEITA Warm Temperature Limits  
IJEITA_TYP  
Normal battery charging occurs at default/programmed levels.  
10  
45  
45  
60  
°C  
°C  
IJEITA_WARM Battery termination voltage (VTRM) is reduced by 100 mV from  
programmed value.  
JEITA Hot Temperature Limits  
IJEITA_HOT  
No battery charging occurs.  
60  
°C  
Table 12. JEITA Reduced Charge Current Levels  
JEITA Cool Temperature Limit—Reduced Charge Current Levels  
ICHG[2:0] (Default)  
000 = 550 mA  
001 = 650 mA  
010 = 750 mA  
011 = 850 mA  
100 = 950 mA  
101 = 1050 mA  
110 = 1150 mA  
111 = 1250 mA  
ICHG JEITA (mA)  
250  
300  
350  
400  
450  
500  
550  
600  
Rev. D | Page 21 of 40  
 
 
 
 
ADP5065  
Data Sheet  
The VWEAK threshold can be programmed set either by I2C or by  
an external resistor connected between the V_WEAK_SET pin  
and GND. Recommended resistor values for each threshold are  
listed in Table 13.  
EXTERNAL RESISTOR FOR V_WEAK_SET  
The ADP5065 charger features a VWEAK threshold, which can be  
used for enabling the main PMU system. When battery voltage  
at the BAT_SNS pin exceeds the VWEAK level, the ADP5065 pulls  
down the SYS_ON_OK open-drain flag.  
If an external resistor is not used, it is recommended to tie the  
V_WEAK_SET pin to AGND for VWEAK to obtain its default value.  
Table 13. Resistor Values for V_WEAK_SET Pin  
VWEAK Voltage  
VWEAK Voltage  
Target Resistor Value E24 (kΩ)  
Actual Threshold (kΩ)  
(Rising Threshold)  
I2C (3.0 V default)  
2.7 V  
2.8 V  
2.9 V  
3.0 V  
3.1 V  
3.2 V  
(Falling Threshold)  
I2C programmed − 100 mV  
Short to GND  
15  
20  
27  
36  
47  
68  
100  
Open  
Not applicable  
13.2  
17.8  
23.5  
31.0  
41.3  
56.2  
79.7  
122.4  
2.6 V  
2.7 V  
2.8 V  
2.9 V  
3.0 V  
3.1 V  
3.2 V  
3.3 V  
3.3 V  
3.4 V  
Rev. D | Page 22 of 40  
 
 
Data Sheet  
ADP5065  
See Figure 34 for an example of the I2C write sequence to a  
I2C INTERFACE  
single register. The subaddress content selects which one of the  
five ADP5065 registers is written to first. The ADP5065 sends  
an acknowledgement to the master after the 8-bit data byte has  
been written. The ADP5065 increments the subaddress  
automatically and starts receiving a data byte to the following  
register until the master sends an I2C stop as shown in Figure 35.  
Figure 36 shows the I2C read sequence of a single register.  
ADP5065 sends the data from the register denoted by the  
subaddress and increments the subaddress automatically,  
sending data from the next register until the master sends an  
I2C stop condition as shown in Figure 37.  
The ADP5065 includes an I2C-compatible serial interface for  
control of the charging and for a readback of system status  
registers. The I2C chip address is 0x28 in write mode and 0x29  
in read mode.  
Register values are reset to the default values, when the supply  
voltage at the VINx pin falls below the VVIN_OK falling voltage  
threshold. The I2C registers are also reset when the battery is  
disconnected and VIN is 0 V.  
0 = WRITE  
MASTER STOP  
ST  
0
0
1
0
1
0
0
0
0
0
0
SP  
ADP5065 RECEIVES  
DATA  
CHIP ADDRESS  
SUBADDRESS  
Figure 34. I2C Single Register Write Sequence  
0 = WRITE  
MASTER STOP  
ST  
0
0
1
0
1
0
0
0
0
0
0
0
0
SP  
CHIP ADDRESS  
SUBADDRESS  
REGISTER N  
ADP5065 RECEIVES  
DATA TO REGISTER N  
ADP5065 RECEIVES  
DATA TO REGISTER N + 1  
ADP5065 RECEIVES  
DATA TO LAST REGISTER  
Figure 35. I2C Multiple Register Write Sequence  
1 = READ  
0 = WRITE  
ST  
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
ST  
0
0
1
0
1
0
0
1
0
1
SP  
CHIP ADDRESS  
SUBADDRESS  
CHIP ADDRESS  
ADP5065 SENDS DATA  
Figure 36. I2C Single Register Read Sequence  
1 = READ  
MASTER STOP  
0 = WRITE  
S
T
S
T
S
P
0
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
CHIP ADDRESS  
SUBADDRESS  
REGISTER N  
CHIP ADDRESS  
ADP5065 SENDS  
DATA OF REGISTER N  
ADP5065 SENDS  
DATA OF REGISTER  
N + 1  
ADP5065 SENDS  
DATA OF LAST  
REGISTER  
Figure 37. I2C Multiple Register Read Sequence  
Rev. D | Page 23 of 40  
 
 
 
 
 
ADP5065  
Data Sheet  
CHARGER OPERATIONAL FLOWCHART  
POWER ON RESET  
N
Y
RUN  
BATTERY  
DETECTION  
tSTART  
EXPIRED  
N
Y
RESET ALL  
REGISTERS  
VINOK  
POWER  
DOWN  
Y
N
V
<
BAT_SNS  
V
TRK  
TRICKLE  
CHARGE  
FAST CHARGE  
N
N
N
N
VINOK  
Y
VINOK  
Y
IBUSLIM = HIGH  
= I  
V
<
I
< I  
LIM  
BAT_SNS  
VIN  
I
VIN  
LIM  
V
TRK  
Y
Y
WATCHDOG  
EXPIRED  
tWD  
THERMLIM = HIGH  
Y
Y
N
Y
TEMP < T  
Y
EXPIRED  
TEMP = T  
START tSAFE  
LIM  
LIM  
I
= 100mA  
BUS  
N
WATCHDOG  
EXPIRED  
TFAULT/  
BAD BATTERY  
tSAFE/tTRK  
EXPIRED  
tWD  
EXPIRED  
START tSAFE  
I
= 100mA  
BUS  
N
N
TFAULT/  
BAD BATTERY  
(SEE TIMER SECTION)  
Y
tSAFE/tCHG  
EXPIRED  
RUN  
BATTERY  
DETECTION  
Y
N
Y
N
N
CC-MODE  
V
=
BAT_SNS  
N
CHARGING  
V
≤
V
≤
V
BAT_SNS  
BAT_SNS  
TRM  
V
V
NOBAT  
RCH  
Y
CHARGE  
COMPLETE  
Y
N
CV-MODE  
CHARGING  
I
< I  
END  
OUT  
Figure 38. ADP5065 Operational Flowchart  
Rev. D | Page 24 of 40  
 
 
Data Sheet  
ADP5065  
I2C REGISTER MAP  
Table 14. I2C Register Map1  
Register  
Addr. Name  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0x00  
Manufac-  
MANUF  
Model  
turer and  
model ID  
0x01  
0x02  
0x03  
Silicon  
revision  
REV  
ILIM  
VINx pins  
settings  
RFU  
Termina-  
tion  
VTRM  
IEND  
settings  
0x04  
0x05  
0x06  
0x07  
0x08  
0x09  
Charging  
current  
C/20 EOC  
C/10 EOC  
High  
(read only)  
ICHG  
ITRK_DEAD  
Voltage  
threshold  
VRCH  
VTRK_DEAD  
VWEAK  
WD PERIOD RESET_WD  
EN_TRK EN_CHG  
Timer  
settings  
EN_TEND  
EN_BMON  
EN_CHG_TIMER CHG_TMR_PERIOD EN_WD  
EN_THR EN_EOC  
Functional EN_JEITA  
Settings1  
DIS_IPK_SD  
Functional  
Settings2  
Interrupt  
enable  
EN_IND_PEAK_INT EN_THERM_LIM_INT EN_WD_INT EN_TSD_INT  
EN_THR_INT  
THR_INT  
EN_BAT_INT  
BAT_INT  
EN_CHG_INT EN_VIN_INT  
0x0A Interrupt  
active  
IND_PEAK_INT  
VIN_OV  
THERM_LIM_INT  
VIN_OK  
WD_INT  
VIN_ILIM  
TSD_INT  
CHG_INT  
VIN_INT  
0x0B  
Charger  
Status 1  
THERM_LIM  
IPK_STAT  
CHDONE  
CHARGER_STATUS  
BATTERY_STATUS  
0x0C  
Charger  
Status 2  
THR_STATUS  
0x0D Fault  
register  
BAT_SHR  
IND_PEAK_INT TSDL 130°C  
VBAT_SHR  
TSD 140°C  
0x10  
Battery  
short  
TBAT_SHR  
1 Each blank cell indicates a bit that is not used.  
Rev. D | Page 25 of 40  
 
 
ADP5065  
Data Sheet  
REGISTER BIT DESCRIPTIONS  
Table 15. Manufacturer and Model ID, Register Address 0x00 Bit Descriptions  
Bit No.  
Mnemonic  
MANUF[3:0]  
MODEL[3:0]  
Access Default  
Description  
[7:4]  
R
R
0001  
1000  
The 4-bit manufacturer identification bus.  
The 4-bit model identification bus.  
[3:0]  
Table 16. Silicon Revision, Register Address 0x01 Bit Descriptions  
Bit No.  
Mnemonic  
Not Used  
REV[3:0]  
Access Default  
Description  
[7:4]  
R
[3:0]  
R
0101  
The 4-bit silicon revision identification bus.  
Table 17. VINx Settings, Register Address 0x02 Bit Descriptions  
Bit No.  
[7:5]  
4
Mnemonic  
Not Used  
RFU  
Access Default  
Description  
R
R/W  
R/W  
0
Reserved for future use.  
[3:0]  
ILIM[3:0]  
0000 = 100 mA  
VINx pin input current-limit programming bus. The current into VINx  
can be limited to the following programmed values:  
0000 = 100 mA.  
0001 = 150 mA.  
0010 = 200 mA.  
0011 = 300 mA.  
0100 = 400 mA.  
0101 = 500 mA.  
0110 = 600 mA.  
0111 = 700 mA.  
1000 = 800 mA.  
1001 = 900 mA.  
1010 = 1000 mA.  
1011 = 1100 mA.  
1100 = 1200 mA.  
1101 = 1300 mA.  
1110 = 1400 mA.  
1111 = 1500 mA.  
Rev. D | Page 26 of 40  
 
Data Sheet  
ADP5065  
Table 18. Termination Settings, Register Address 0x03 Bit Descriptions  
Bit No.  
Mnemonic  
Access Default  
Description  
[7:2]  
VTRM[5:0]  
R/W 100011 = 4.20 V  
Termination voltage programming bus. The values of the float  
voltage can be programmed as per the following values:  
000000 = 3.50 V.  
000001 = 3.52 V.  
000010 = 3.54 V.  
000011 = 3.56 V.  
000100 = 3.58 V.  
000101 = 3.60 V.  
000110 = 3.62 V.  
000111 = 3.64 V.  
001000 = 3.66 V.  
001001 = 3.68 V.  
001010 = 3.70 V.  
001011 = 3.72 V.  
001100 = 3.74 V.  
001101 = 3.76 V.  
001110 = 3.78 V.  
001111 = 3.80 V.  
010000 = 3.82 V.  
010001 = 3.84 V.  
010010 = 3.86 V.  
010011 = 3.88 V.  
010100 = 3.90 V.  
010101 = 3.92 V.  
010110 = 3.94 V.  
010111 = 3.96 V.  
011000 = 3.98 V.  
011001 = 4.00 V.  
011010 = 4.02 V.  
011011 = 4.04 V.  
011100 = 4.06 V.  
011101 = 4.08 V.  
011110 = 4.10 V.  
011111 = 4.12 V.  
100000 = 4.14 V.  
100001 = 4.16 V.  
100010 = 4.18 V.  
100011 = 4.20 V.  
100100 = 4.22 V.  
100101 = 4.24 V.  
100110 = 4.26 V.  
100111 = 4.28 V.  
101000 = 4.30 V.  
101001 = 4.32 V.  
101010 = 4.34 V.  
101011 = 4.36 V.  
101100 = 4.38 V.  
101101 = 4.40 V.  
101110 to 111111 = 4.42 V.  
Rev. D | Page 27 of 40  
ADP5065  
Data Sheet  
Bit No.  
Mnemonic  
IEND[1:0]  
Access Default  
R/W 01 = 52.5 mA  
Description  
[1:0]  
Termination current programming bus. The values of the termination  
current can be programmed as per the following values:  
00 = 32.5 mA.  
01 = 52.5 mA.  
10 = 72.5 mA.  
11 = 92.5 mA.  
Table 19. Charging Current, Register Address 0x04 Bit Descriptions  
Bit No.  
Mnemonic  
Access Default  
Description  
7
C/20 EOC  
R/W  
The C/20 bit has priority over the other settings (C/10 EOC and IEND).  
When this bit is set to high, C/20 programming is used. 27.5 mA  
minimum value.  
The C/10 bit has priority over the other setting (END) but not C/20  
EOC.  
6
C/10 EOC  
R/W  
When this bit is set to high, C/10 programming is used unless C/20  
EOC is set to high. 27.5 mA minimum value.  
5
Tied high in metal  
ICHG[2:0]  
R
1
[4:2]  
R/W  
111 = 1250 mA  
Fast charge current programming bus. The values of the constant  
current charge can be programmed as per the following values:  
000 = 550 mA.  
001 = 650 mA.  
010 = 750 mA.  
011 = 850 mA.  
100 = 950 mA.  
101 = 1050 mA.  
110 = 1150 mA.  
111 = 1250 mA.  
[1:0]  
ITRK_DEAD[1:0]  
R/W  
10 = 20 mA  
Trickle and weak charge current programming bus. The values of the  
trickle and weak charge currents can be programmed as per the  
following values:  
00 = 5 mA.  
01 = 10 mA.  
10 = 20 mA.  
11 = 20 mA.  
Table 20. Voltage Threshold, Register Address 0x05 Bit Descriptions  
Bit No.  
Mnemonic  
Access Default  
Description  
7
Not used  
R
[6:5]  
VRCH[1:0]  
R/W  
11 = 260 mV  
Recharge voltage programming bus. The values of the recharge  
threshold can be programmed as per the following values:  
00 = 80 mV.  
01 = 140 mV.  
10 = 200 mV.  
11 = 260 mV.  
[4:3]  
VTRK_DEAD[1:0]  
R/W  
01 = 2.5 V  
Trickle to fast charge dead battery voltage programming bus. The  
values of the trickle to fast charge threshold can be programmed as  
per following values:  
00 = 2.4 V.  
01 = 2.5 V.  
10 = 2.6 V.  
11 = 3.3 V.  
Rev. D | Page 28 of 40  
Data Sheet  
ADP5065  
Bit No.  
Mnemonic  
VWEAK[2:0]  
Access Default  
R/W 011 = 3.0 V  
Description  
[2:0]  
Weak battery voltage rising threshold.  
000 = 2.7 V.  
001 = 2.8 V.  
010 = 2.9 V.  
011 = 3.0 V.  
100 = 3.1 V.  
101 = 3.2 V.  
110 = 3.3 V.  
111 = 3.4 V.  
Table 21. Timer Settings, Register Address 0x06 Bit Descriptions  
Bit No.  
[7:6]  
5
Mnemonic  
Access Default  
Description  
Not used  
EN_TEND  
R/W  
0
When low, this bit disables the charge complete timer (tEND), and a 31  
ms deglitch timer remains on this function.  
4
3
EN_CHG_TIMER  
R/W  
R/W  
1
1
When high, the trickle/fast charge timer is enabled.  
Trickle/fast charge timer period.  
CHG_TMR_PERIOD  
0 = 30 sec/300 minutes.  
1 = 60 sec/600 minutes.  
2
1
EN_WD  
R/W  
R/W  
0
0
When high, the watchdog timer safety timer is enabled.  
When low, the watchdog timer is disabled even when BAT_SNS  
exceeds VDEAD  
.
WD PERIOD  
Watchdog safety timer period.  
0 = 32 sec/40 minutes.  
1 = 64 sec/40 minutes.  
0
RESET_WD  
W
0
High resets the watchdog safety timer. Bit is reset automatically.  
Table 22. Functional Settings1, Register Address 0x07 Bit Descriptions  
Bit No.  
Mnemonic  
Access Default  
Description  
7
EN_JEITA  
R/W  
0
When low, this bit disables the JEITA Li-Ion temperature battery  
charging specification.  
6
DIS_IPK_SD  
R/W  
1
When high, this bit disables the automatic shutdown of the device if  
four peak inductor current limits are reached in succession. In  
addition, when high, it only flags the Status Bit IPK_STAT.  
5
4
EN_BMON  
EN_THR  
R/W  
R/W  
0
0
When high, the battery monitor is enabled even when the voltage at  
the VINx pins is below VVIN_OK  
When high, the THR current source is enabled even when the  
voltage at the VINx pins is below VVIN_OK  
.
.
3
2
1
Not used  
EN_EOC  
EN_TRK  
R/W  
R/W  
R/W  
0
1
1
When high, end of charge is allowed.  
When low, trickle charger is disabled and the dc-to-dc converter is  
enabled.  
0
EN_CHG  
R/W  
1
When low, the dc-to-dc converter is disabled.  
Table 23. Functional Settings2, Register Address 0x08 Bit Descriptions  
Bit No.  
Mnemonic  
Access Default  
Description  
[7:0]  
Not used  
R/W  
Table 24. Interrupt Enable, Register Address 0x09 Bit Descriptions  
Bit No.  
Mnemonic  
Access Default  
Description  
7
6
5
4
3
EN_IND_PEAK_INT  
R/W  
0
0
0
0
0
When high, the inductor peak current-limit interrupt is allowed.  
When high, the isothermal charging interrupt is allowed.  
When high, the watchdog alarm interrupt is allowed.  
When high, the overtemperature interrupt is allowed.  
When high, the THR temperature thresholds interrupt is allowed.  
EN_THERM_LIM_INT R/W  
EN_WD_INT  
EN_TSD_INT  
EN_THR_INT  
R/W  
R/W  
R/W  
Rev. D | Page 29 of 40  
ADP5065  
Data Sheet  
Bit No.  
Mnemonic  
Access Default  
Description  
2
1
0
EN_BAT_INT  
EN_CHG_INT  
EN_VIN_INT  
R/W  
R/W  
R/W  
0
0
0
When high, the battery voltage thresholds interrupt is allowed.  
When high, the charger mode change interrupt is allowed.  
When high, the VINx pin voltage thresholds interrupt is allowed.  
Table 25. Interrupt Active, Register Address 0x0A Bit Descriptions  
Bit  
No.  
Mnemonic  
Access Default Description  
7
IND_PEAK_INT  
THERM_LIM_INT  
WD_INT  
R
R
R
0
0
0
When high, this bit indicates an interrupt caused by an inductor peak current limit.  
When high, this bit indicates an interrupt caused by isothermal charging.  
6
5
When high, this bit indicates an interrupt caused by the watchdog alarm. The watchdog  
timer expires within 2 sec or 4 sec depending on the WDPERIOD setting of 32 sec or 64 sec,  
respectively.  
4
3
2
1
0
TSD_INT  
THR_INT  
BAT_INT  
CHG_INT  
VIN_INT  
R
R
R
R
R
0
0
0
0
0
When high, this bit indicates an interrupt caused by an overtemperature fault.  
When high, this bit indicates an interrupt caused by THR temperature thresholds.  
When high, this bit indicates an interrupt caused by battery voltage thresholds.  
When high, this bit indicates an interrupt caused by a charger mode change.  
When high, this bit indicates an interrupt caused by VINx voltage thresholds.  
Table 26. Charger Status 1, Register Address 0x0B Bit Descriptions  
Bit No.  
Mnemonic  
Access Default  
Description  
7
VIN_OV  
R
R
R
Not applicable  
When high, this bit indicates that the voltage at the VINx pins  
exceeds VVIN_OV  
When high, this bit indicates that the voltage at the VINx pins  
exceeds VVIN_OK  
.
6
5
VIN_OK  
Not applicable  
Not applicable  
.
VIN_ILIM  
When high, this bit indicates that the current into a VINx pin is  
limited by the high voltage blocking FET and the charger is not  
running at the full programmed ICHG  
.
4
3
THERM_LIM  
CHDONE  
R
R
Not applicable  
Not applicable  
When high, this bit indicates that the charger is not running at the  
full programmed ICHG but is limited by the die temperature.  
When high, this bit indicates the end of charge cycle has been  
reached. This bit latches on, in that it does not reset to low when the  
VRCH threshold is breached.  
[2:0]  
CHAGER_STATUS[2:0]  
R
Not applicable  
Charger status bus.  
000 = off.  
001 = trickle charge.  
010 = fast charge (CC mode).  
011 = fast charge (CV mode).  
100 = charge complete.  
101 = suspend.  
110 = trickle or fast charge timer expired.  
111 = battery detection.  
Rev. D | Page 30 of 40  
Data Sheet  
ADP5065  
Table 27. Charger Status Register 2, Register Address 0x0C Bit Descriptions  
Bit No.  
Mnemonic  
Access Default  
Description  
[7:5]  
THR_STATUS[2:0]  
R
Not applicable  
THR pin status.  
000 = off.  
001 = battery cold.  
010 = battery cool.  
011 = battery warm.  
100 = battery hot.  
111 = thermistor OK.  
4
IPK_STAT  
R
Not applicable  
Not applicable  
Peak current limit status bit. Set high if four or more peak inductor  
current limits are reached in succession.  
3
Not Used  
R
R
[2:0]  
BATTERY_STATUS[2:0]  
Battery status bus.  
000 = battery monitor off.  
001 = no battery.  
010 = BAT_SNS < VTRK  
.
011 = VTRK ≤ BAT_SNS < VWEAK  
.
100 = BAT_SNS ≥ VWEAK  
.
Table 28. Fault Register, Register Address 0x0D Bit Descriptions1  
Bit No.  
Mnemonic  
Access Default  
Description  
[7:4]  
Not Used  
3
2
1
0
BAT_SHR  
R/W  
R/W  
R/W  
R/W  
0
0
0
0
When high, a battery short detection has occurred.  
When high, an inductor peak current-limit fault has occurred.  
When high, the overtemperature (lower) fault has occurred.  
When high, the overtemperature fault has occurred.  
IND_PEAK_INT  
TSD 130°C  
TSD 140°C  
1 To reset the fault bits in the fault register, cycle power on VINx or write high to the corresponding I2C bit.  
Table 29. Battery Short, Register Address 0x10 Bit Descriptions  
Bit No.  
Mnemonic  
Access Default  
Description  
[7:5]  
TBAT_SHR[2:0]  
R/W  
100 = 30 sec  
Battery short timeout timer:  
000 = 1 sec  
001 = 2 sec  
010 = 4 sec  
011 = 10 sec  
100 = 30 sec  
101 = 60 sec  
110 = 120 sec  
111 = 180 sec  
[4:3]  
[2:0]  
Not used  
R/W  
R/W  
VBAT_SHR[2:0]  
100 = 2.4 V  
Battery short voltage threshold level:  
000 = 2.0 V  
001 = 2.1 V  
010 = 2.2 V  
011 = 2.3 V  
100 = 2.4 V  
101 = 2.5 V  
110 = 2.6 V  
111 = 2.7 V  
Rev. D | Page 31 of 40  
 
ADP5065  
Data Sheet  
APPLICATIONS INFORMATION  
EXTERNAL COMPONENTS  
Inductor Selection  
The worst-case capacitance accounting for capacitor variation  
over temperature, component tolerance, and voltage is calcu-  
lated using the following equation:  
The high switching frequency of the ADP5065 buck converter  
allows for the selection of small chip inductors. Suggested  
inductors are shown in Table 33.  
C
EFF = COUT × (1 − TEMPCO) × (1 − TOL)  
where:  
EFF is the effective capacitance at the operating voltage.  
C
The peak-to-peak inductor current ripple is calculated using  
the following equation:  
TEMPCO is the worst-case capacitor temperature coefficient.  
TOL is the worst-case component tolerance.  
VOUT ×(VIN −VOUT  
)
IRIPPLE  
=
In this example, the worst-case temperature coefficient  
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an  
X5R dielectric. The tolerance of the capacitor (TOL) is assumed  
to be 10%, and COUT is 16 μF at 4.2 V, as shown in Figure 39.  
V
IN × fSW ×L  
where:  
VOUT is the ISO_Sx node output voltage.  
V
IN is the converter input voltage at the CFILT node.  
Substituting these values in the equation yields  
fSW is the switching frequency.  
CEFF = 16 μF × (1 − 0.15) × (1 − 0.1) ≈ 12.24 μF  
L is the inductor value.  
25  
The minimum dc current rating of the inductor must be greater  
than the inductor peak current. The inductor peak current is  
calculated using the following equation:  
20  
15  
10  
5
IRIPPLE  
2
IPEAK = ICHG + ILOAD(MAX)  
+
Inductor conduction losses are caused by the flow of current  
through the inductor, which has an associated internal dc  
resistance (DCR). Larger sized inductors have smaller DCR,  
which may decrease inductor conduction losses. Inductor core  
losses are related to the magnetic permeability of the core material.  
Because the bucks are high switching frequency dc-to-dc  
converters, shielded ferrite core material is recommended for  
its low core losses and low EMI.  
0
0
1
2
3
4
5
6
7
DC BIAS (V)  
Figure 39. Murata GRM31CR60J226ME19C DC Characteristic  
ISO_Sx (VOUT) and ISO_Bx Capacitor Selection  
To guarantee the performance of the charger in various  
operation modes including trickle charge, constant current  
charge, and constant voltage charge, it is imperative that the  
effects of dc bias, temperature, and tolerances on the behavior  
of the capacitors be evaluated for each application.  
To safely obtain stable operation of the ADP5065, the ISO_Sx  
and ISO_Bx effective capacitance (including temperature and  
dc bias effects) must not be less than 10 µF at any point during  
operation. The combined effective capacitance of the ISO_Sx  
capacitor and the system capacitance must not exceed 50 µF at  
any point during operation.  
The peak-to-peak output voltage ripple for the selected output  
capacitor and inductor values is calculated using the following  
equation:  
Higher output capacitor values reduce the output voltage ripple  
and improve load transient response. When choosing this value,  
it is also important to account for the loss of capacitance due to  
output voltage dc bias.  
IRIPPLE  
8× fSW ×COUT  
VIN  
2 ×L×COUT  
VRIPPLE  
=
≈
(
2π× fSW  
)
Ceramic capacitors are manufactured with a variety of dielec-  
trics, each with a different behavior over temperature and  
applied voltage. Capacitors must have a dielectric adequate  
enough to ensure the minimum capacitance over the necessary  
temperature range and dc bias conditions. X5R or X7R dielectrics  
with a voltage rating of 6.3 V or 10 V are recommended for best  
performance. Y5V and Z5U dielectrics are not recommended  
for use with any dc-to-dc converter because of their poor temper-  
ature and dc bias characteristics.  
Capacitors with lower effective series resistance (ESR) are  
preferable to guarantee low output voltage ripple, as shown in  
the following equation:  
VRIPPLE  
ESRCOUT  
≤
IRIPPLE  
Rev. D | Page 32 of 40  
 
 
 
Data Sheet  
ADP5065  
VINx Capacitor Selection  
Table 30. ISO_Sx and ISO_Bx Capacitor Suggestions  
Vendor Part Number Value Voltage Size  
According to the USB 2.0 specification, USB peripherals have a  
detectable change in capacitance on VBUS when they are attached.  
The peripheral device VBUS bypass capacitance must be at least  
1 µF but not larger than 10 µF. The combined capacitance for  
the VINx and CFILT pins must not exceed 10 µF at any tempera-  
ture or dc bias condition. Suggestions for a VINx capacitor is  
given in Table 32.  
Murata  
Murata  
TDK  
GRM31CR61A226KE19  
22 μF  
22 μF  
22 µF  
22 µF  
10 V  
6.3 V  
6.3 V  
6.3 V  
1206  
1206  
1206  
1206  
GRM31CR60J226ME19  
C3216X5R0J226M  
JMK316ABJ226KL  
TAIYO-  
YUDEN  
Table 31. CFILT Capacitor Suggestions  
Vendor Part Number Value Voltage Size  
CFILT Capacitor Selection  
CFILT pin serves the ADP5065 as the step-down dc-to-dc  
converter input capacitor. Maximum input capacitor current  
is calculated using the following equation:  
Murata  
Murata  
TDK  
GRM219R61C475KE15  
4.7 μF 16 V  
4.7 μF 6.3 V  
4.7 μF 6.3 V  
0805  
0603  
0603  
0603  
GRM188R60J475ME84  
C1608X5R0J475K  
V
ISO _ S (VCFILT −VISO _ S )  
TAIYO-  
YUDEN  
JMK107ABJ106MA  
10 µF  
6.3 V  
ICIN ≥ ILOAD+CHG(MAX)  
VCFILT  
Table 32. VINx Capacitor Suggestions  
Vendor Part Number Value Voltage Size  
To minimize supply noise, place the input capacitor as close as  
possible to the CFILT pin of the charger. As with the output  
capacitor, a low ESR capacitor is recommended.  
Murata  
Murata  
TDK  
GRM21BR71E225KA73  
2.2 µF 25  
2.2 µF 25  
2.2 µF 25  
2.2 µF 25  
0805  
0603  
0603  
0603  
GRM188R61E225KA12  
C1608X5R1E225K  
The effective capacitance needed for stability, which includes  
temperature and dc bias effects, is a minimum of 2 µF and a  
maximum of 5 µF. A list of suggested capacitors is shown in  
Table 31.  
TAIYO-  
YUDEN  
TMK107ABJ225MA  
Table 33. 1.0 µH Inductor Suggestions  
Saturation Current  
L −30% Drop  
Vendor  
Murata  
Coilcraft  
Part Number  
DCR (mΩ)  
Size Max L × W × H (mm)  
3.5 × 2.7 × 1.7  
LQH32PN1R0NN0  
XFL3010-102ME  
2.3 A  
45  
43  
2.4 A  
3.2 × 3.2 ×1.1  
Rev. D | Page 33 of 40  
 
 
 
ADP5065  
Data Sheet  
PCB LAYOUT GUIDELINES  
Poor layout can affect ADP5065 performance, causing electro-  
magnetic interference (EMI) and electromagnetic compatibility  
(EMC) problems, ground bounce, and voltage losses. Poor  
layout can also affect regulation and stability. A good layout is  
implemented using the following guidelines:  
Route the output voltage path away from both the inductor  
and SWxnode to minimize noise and magnetic interference.  
Maximize the size of ground metal on the component side  
to help with thermal dissipation.  
Use a ground plane with several vias connecting to the  
component side ground to further reduce noise  
interference on sensitive circuit nodes.  
Place the inductor, input capacitor, and output capacitor  
close to the IC using short tracks. These components carry  
high switching frequencies, and large tracks act as antennas.  
VIN = 4.5V TO 5.5V  
D1  
E1  
VIN1  
VIN2  
ADP5065  
L1 1µH  
LQH32PN1R0NN0  
SW1  
CFILT  
E2  
D3  
E3  
SW2  
ISO_S1  
C3  
C4  
VDDIO  
R2  
CONTROL  
(INPUT CURRENT,  
DC-DC)  
R1  
ISO_S2  
1.5kΩ 1.5kΩ  
A2 SCL  
B1  
TO MCU  
CHARGE CONTROL  
(CHARGE MODE,  
BATTERY ISOLATION)  
ISO_B1  
ISO_B2  
TO MCU  
TO MCU/NC  
TO MCU/NC  
SDA  
A4 IIN_EXT  
B3  
B4  
CONNECT  
CLOSE TO  
BATTERY  
B2  
A1  
TRK_EXT  
+
BAT_SNS C1  
A3  
D2  
THR  
V_WEAK_SET  
VDDIO  
R3/NC  
(OPTIONAL)  
R4  
10kΩ  
SYS_ON_OK  
TO MCU  
C2  
D4  
E4  
Figure 40. Reference Circuit Diagram  
ADP5065  
C
22µF  
PGND  
ISO_B  
V
IN  
PGND  
C
4.7µF  
CFILT  
PGND  
11.5mm  
Figure 41. PCB Layout Suggestion  
Rev. D | Page 34 of 40  
 
Data Sheet  
ADP5065  
POWER DISSIPATION AND THERMAL CONSIDERATIONS  
The ADP5065 is a highly efficient USB compliant charger.  
However, if the device operates at high ambient temperatures  
and maximum current charging and loading conditions, the  
junction temperature can reach the maximum allowable  
operating limit (125°C).  
A second method to estimate the power dissipation uses the  
system voltage and charging efficiency curves provided for the  
ADP5065. When the efficiency is known, use Equation 3b to  
derive the total power lost in the dc-to-dc converter, isolation  
FET and inductor; use Equation 5 to derive the power lost in  
the inductor, and then calculate the power dissipation in the  
buck converter using Equation 4.  
When the temperature exceeds 140°C, the ADP5065 turns off  
allowing the device to cool down. When the die temperature  
falls below 110°C and the TSD 140°C fault bit in Register 0x0D  
is cleared by an I2C write, the ADP5065 resumes normal  
operation.  
Note that the ADP5065 efficiency curves are typical values and  
may not be provided for all possible combinations of VIN, VOUT  
and IOUT. To account for these variations, it is necessary to  
include a safety margin when calculating the power dissipated in  
the charger.  
,
This section provides guidelines to calculate the power dissi-  
pated in the device and ensure that the ADP5065 operates  
below the maximum allowable junction temperature.  
CHARGER POWER DISSIPATION  
The output power of the ADP5065 charger is gived by  
The power loss of the step-down charger is approximated by  
P
OUT = VISO_S × ILOAD + VISO_B × ICHG  
where:  
OUT is the total output power to the system and battery.  
ISO_S is the ISO_Sx pin voltage.  
LOAD is the load current from ISO_Sx node.  
ISO_B is the battery voltage.  
CHG is the charge current.  
(1)  
P
LOSS = PDCHG + PL  
where:  
DCHG is the power dissipation of the ADP5065 charger.  
PL is the inductor power losses.  
(4)  
P
V
I
V
P
The inductor losses are external to the device, and they do not  
have any effect on the die temperature. Equation 5 estimates the  
inductor losses without core losses. Some inductor manufacturers  
provide web tools to estimate power inductor core losses based  
on inductor type, switching frequency, and ripple current. At a  
switching frequency of 3 MHz, the core losses can add inductor  
losses significantly.  
I
The efficiency of the ADP5065 is given by  
POUT  
(2)  
η =  
×100%  
PIN  
where:  
η is the efficiency.  
IN is the input power.  
Power loss is given by  
PL ≈ IOUT(RMS)2 × DCRL  
where:  
DCRL is the inductor series resistance.  
OUT(RMS) is the summary of rms load current and charging  
(5)  
P
I
P
LOSS = PIN − POUT  
(3a)  
(3b)  
current (ILOAD(RMS) + ICHG).  
or  
r
12  
IOUT(RMS) = IOUT × 1+  
(6)  
(7)  
P
LOSS = POUT (1− η)/η  
Power dissipation can be calculated in several ways. The most  
intuitive and practical is to measure the power dissipated at the  
input and both outputs (ISO_Sx and ISO_Bx). Perform the mea-  
surements at the worst-case conditions (voltages, currents, and  
temperature). The difference between input and output power  
is dissipated in the device and the inductor. Use Equation 5  
to derive the power lost in the inductor and, from this, use  
Equation 4 to calculate the power dissipation in the ADP5065  
charger.  
where r is the normalized inductor ripple current.  
r = VOUT × (1 − D)/(IOUT × L × fSW  
where:  
L is the inductance.  
SW is the switching frequency.  
)
f
D is the duty cycle.  
D = VOUT/VIN  
(8)  
Rev. D | Page 35 of 40  
 
 
ADP5065  
Data Sheet  
Maximum junction temperature (TJ) can also be calculated  
from the board temperature (TB) and power dissipation (PD)  
using the formula  
JUNCTION TEMPERATURE  
In cases where the ambient temperature, TA, is known, the  
thermal resistance parameter, θJA, can be used to estimate the  
junction temperature rise. TJ is calculated from TA and PD using  
the formula  
TJ = TA + (PD × θJB)  
(10)  
where θJB is the junction-to-board thermal resistance.  
TJ = TA + (PD × θJA)  
(9)  
The typical value for the 20-bump WLCSP is 9.2°C/W (see  
Table 5). θJB is based on a 4-layer, 4 in × 3 in, 2.5 oz copper  
board, as per the JEDEC standard.  
The typical θJA value for the 20-bump WLCSP is 46.8°C/W (see  
Table 5). A very important factor to consider is that θJA is based  
on a 4-layer, 4 in × 3 in, 2.5 oz copper board as per JEDEC  
standard, and real applications may use different sizes and  
layers. It is important to maximize the copper to remove the heat  
from the device. Copper exposed to air dissipates heat better  
than copper used in the inner layers.  
For a WLCSP device, where possible, remove heat from every  
current carrying bump (PGNDx, VINx, SWx, ISO_Sx, and  
ISO_Bx). For example, thermal vias to the board power planes  
can be placed close to these pins, where available.  
The reliable operation of the charger can be achieved only if the  
estimated die junction temperature of the ADP5065 (Equation 9)  
is less than 125°C. Reliability and mean time between failures  
(MTBF) are highly affected by increasing the junction temper-  
ature. Additional information about product reliability is  
available in the ADI Reliability Handbook at the following URL:  
www.analog.com/reliability_handbook.  
When designing an application for a particular ambient  
temperature range, calculate the expected ADP5065 power  
dissipation (PD). From this power calculation, the junction  
temperature, TJ, can be estimated using Equation 9.  
Rev. D | Page 36 of 40  
 
Data Sheet  
ADP5065  
FACTORY-PROGRAMMABLE OPTIONS  
Table 34. ADP5065 Fuse-Selectable Trim Options  
Parameter  
Value  
10 kΩ  
100 kΩ  
3150  
3350  
3500  
3650  
3850  
4000  
4200  
4400  
ADP5065ACBZ-1-R7 Trim Setting  
NTC Thermistor Type  
10 kΩ  
NTC Beta  
3350  
Rev. D | Page 37 of 40  
 
 
ADP5065  
Data Sheet  
PACKAGING AND ORDERING INFORMATION  
OUTLINE DIMENSIONS  
2.08  
2.04  
2.00  
4
3
2
1
A
B
C
D
E
BALL A1  
IDENTIFIER  
2.75  
2.71  
2.67  
2.00 REF  
0.50  
REF  
BOTTOM VIEW  
(BALL SIDE UP)  
TOP VIEW  
(BALL SIDE DOWN)  
0.390  
0.360  
0.330  
1.50 REF  
0.660  
0.600  
0.540  
SIDE VIEW  
COPLANARITY  
0.04  
SEATING  
PLANE  
0.360  
0.320  
0.280  
0.270  
0.240  
0.210  
Figure 42. 20-Ball Wafer Level Chip Scale Package [WLCSP]  
(CB-20-8)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model1  
Temperature Range (Junction)  
Package Description  
Package Option  
ADP5065ACBZ-1-R7  
ADP5065CB-EVALZ  
−40°C to +125°C  
20-Ball Wafer Level Chip Scale Package [WLCSP]  
ADP5065 Evaluation Board  
CB-20-8  
1 Z = RoHS Compliant Part.  
Rev. D | Page 38 of 40  
 
 
 
 
Data Sheet  
NOTES  
ADP5065  
Rev. D | Page 39 of 40  
ADP5065  
NOTES  
Data Sheet  
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).  
©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D09370-0-2/13(D)  
www.analog.com/ADP5065  
Rev. D | Page 40 of 40  

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