ADP5071ACPZ_技术文档

2 A/1.2 A DC-to-DC Switching Regulator with

Independent Positive and Negative Outputs

Data Sheet

ADP5071

FEATURES

TYPICAL APPLICATION CIRCUIT

Wide input supply voltage range: 2.85 V to 15 V

Generates well regulated, independently resistor

programmable V_POSand V_NEGoutputs

Boost regulator to generate V_POSoutput

Adjustable positive output to 39 V

ADP5071

SS

INBK

R

C1

L1

D1

COMP1

V

POS

C

C1

SW1

FB1

EN1

C

R

VREG

FT1

VREG

Integrated 2.0 A main switch

C

OUT1

R

FB1

Optional single-ended primary-inductor converter

(SEPIC) configuration for automatic step-up/step-down

Inverting regulator to generate V_NEGoutput

Adjustable negative output to V_IN− 39 V

Integrated 1.2 A main switch

True shutdown for both positive and negative outputs

1.2 MHz/2.4 MHz switching frequency with optional external

frequency synchronization from 1.0 MHz to 2.6 MHz

Resistor programmable soft start timer

PVIN1

PVIN2

PVINSYS

V

IN

PGND

VREF

C

IN1

C

VREF

EN2

R

FB2

C

OUT2

R

C2

FB2

COMP2

R

FT2

C

C2

SYNC/FREQ

SLEW

SW2

V

NEG

D2

SEQ

AGND

L2

Slew rate control for lower system noise

Individual precision enable and flexible start-up sequence

control for symmetric start, V_POSfirst, or V_NEGfirst

Out-of-phase operation

Figure 1.

UVLO, OCP, OVP, and TSD protection

4 mm × 4 mm, 20-lead LFCSP and 20-lead TSSOP

−40°C to +125°C junction temperature range

Supported by the ADIsimPower tool set

APPLICATIONS

Bipolar amplifiers, ADCs, DACs, and multiplexers

Charge-coupled device (CCD) bias supply

Optical module supply

RF power amplifier (PA) bias

GENERAL DESCRIPTION

The ADP5071 is a dual high performance dc-to-dc regulator that

generates independently regulated positive and negative rails.

The ADP5071 includes a fixed internal or resistor programmable

soft start timer to prevent inrush current at power-up. During

shutdown, both regulators completely disconnect the loads from

the input supply to provide a true shutdown.

The input voltage range of 2.85 V to 15 V supports a wide variety of

applications. The integrated main switch in both regulators enables

generation of an adjustable positive output voltage up to +39 V

and a negative output voltage down to −39 V below input voltage.

Other key safety features in the ADP5071 include overcurrent

protection (OCP), overvoltage protection (OVP), thermal

shutdown (TSD), and input undervoltage lockout (UVLO).

The ADP5071 operates at a pin selected 1.2 MHz/2.4 MHz

switching frequency. The ADP5071 can synchronize with an

external oscillator from 1.0 MHz to 2.6 MHz to ease noise

filtering in sensitive applications. Both regulators implement

programmable slew rate control circuitry for the MOSFET

driver stage to reduce electromagnetic interference (EMI).

The ADP5071 is available in a 20-lead LFCSP or in a 20-lead

TSSOP and is rated for a −40°C to +125°C junction temperature

range.

Table 1. Family Models

Model

Boost Switch (A)

Inverter Switch (A)

Flexible start-up sequencing is provided with the options of

manual enable, simultaneous mode, positive supply first, and

negative supply first.

ADP5070

ADP5071

1.0

2.0

0.6

1.2

Rev. A

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Tel: 781.329.4700

Technical Support

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ADP5071* Product Page Quick Links

Last Content Update: 11/01/2016

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Evaluation Kits

• ADP5070/ADP5071 Evaluation Board

Design Resources

• ADP5071 Material Declaration

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• Quality And Reliability

• Symbols and Footprints

Documentation

Application Notes

• AN-1366: Using the ADP5070/ADP5071 to Create Positive

and Negative Voltage Rails when VOUT < VIN

• AN-1368: Ferrite Bead Demystified

Data Sheet

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Independent Positive and Negative Outputs Data Sheet

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• UG-758: Evaluating the ADP5070CP/ADP5071CP LFCSP

DC-to-DC Switching Regulators/Converters

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Tools and Simulations

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ADP5071

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Soft Start ...................................................................................... 15

Slew Rate Control....................................................................... 15

Current-Limit Protection ............................................................ 15

Overvoltage Protection.............................................................. 15

Thermal Shutdown .................................................................... 15

Start-Up Sequence...................................................................... 15

Applications Information .............................................................. 17

ADIsimPower Design Tool ....................................................... 17

Component Selection ................................................................ 17

Loop Compensation .................................................................. 20

Common Applications .............................................................. 22

Super Low Noise With Optional LDOs................................... 24

SEPIC Step-Up/Step-Down Operation ................................... 25

Layout Considerations............................................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

Applications....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 14

PWM Mode................................................................................. 14

PSM Mode................................................................................... 14

Undervoltage Lockout (UVLO) ............................................... 14

Oscillator and Synchronization................................................ 14

Internal Regulators..................................................................... 14

Precision Enabling...................................................................... 15

REVISION HISTORY

6/15—Rev. 0 to Rev. A

Added 20-Lead TSSOP ......................................................Universal

Change to Pull-Down Resistance Parameter, Table 2.................. 3

Changes to Table 3 and Table 4....................................................... 5

Added Figure 3, Renumbered Sequentially .................................. 6

Changes to Figure 37 Caption to Figure 39 Caption ................. 13

Changes to Internal Regulators Section ...................................... 14

Change to Soft Start Section.......................................................... 15

Changes to Component Selection Section.................................. 17

Changes to Output Capacitors Section, Soft Start Resistor Section,

and Diodes Section......................................................................... 18

Changes to Figure 52 Caption....................................................... 26

Added Figure 53.............................................................................. 26

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide .......................................................... 27

2/15—Revision 0: Initial Version

Rev. A | Page 2 of 27

Data Sheet

ADP5071

SPECIFICATIONS

PVIN1 = PVIN2 = PVINSYS = 2.85 V to 15 V, V_POS= 15 V, V_NEG= −15 V, f_SW= 1200 kHz, T_J= −40°C to +125°C for minimum/maximum

specifications, and T_A= 25°C for typical specifications, unless otherwise noted.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT SUPPLY VOLTAGE RANGE

QUIESCENT CURRENT

V_IN

2.85

15

V

PVIN1, PVIN2, PVINSYS

Operating Quiescent Current

PVIN1, PVIN2, PVINSYS (Total)

I_Q

3.5

5

4.0

10

mA

µA

No switching, EN1 = EN2 = high,

PVIN1 = PVIN2 = PVINSYS = 5 V

No switching, EN1 = EN2 = low,

PVIN1 = PVIN2 = PVINSYS = 5 V

Shutdown Current

I_SHDN

UVLO

System UVLO Threshold

Rising

Falling

PVINSYS

V_{UVLO_RISING}

V_{UVLO_FALLING}

V_{HYS_1}

2.8

2.55

0.25

2.85

V

2.5

Hysteresis

OSCILLATOR CIRCUIT

Switching Frequency

f_SW

1.130

2.240

1.200

2.400

1.270

2.560

MHz

SYNC/FREQ = low

SYNC/FREQ = high (connect to

VREG)

SYNC/FREQ Input

Input Clock Range

f_SYNC

1.000

100

2.600

1.3

MHz

ns

V

Input Clock Minimum On Pulse Width

Input Clock Minimum Off Pulse Width

Input Clock High Logic

Input Clock Low Logic

t_{SYNC_MIN_ON}

t_{SYNC_MIN_OFF}

V_{H (SYNC)}

V_{L (SYNC)}

0.4

V

PRECISION ENABLING (EN1, EN2)

High Level Threshold

Low Level Threshold

V_{TH_H}

V_{TH_L}

V_{TH_S}

1.125

1.025

0.4

1.15

1.05

1.175

1.075

V

Shutdown Mode

Internal circuitry disabled to

achieve ISHDN

Pull-Down Resistance

INTERNAL REGULATOR

VREG Output Voltage

BOOST REGULATOR

R_EN

1.48

4.25

0.8

MΩ

V

V_REG

V_FB1

Feedback Voltage

V

Feedback Voltage Accuracy

−0.5

−1.5

+0.5

+1.5

0.1

%

µA

V

T_J= 25°C

T_J= −40°C to +125°C

Feedback Bias Current

Overvoltage Protection Threshold

Load Regulation

I_FB1

V_OV1

∆V_FB1/I_LOAD1

∆V_FB1/V_PVIN1

0.86

0.0003

0.002

At FB1 pin

%/mA I_LOAD1¹= 5 mA to 150 mA

1

Line Regulation

%/V

V_PVIN1= 2.85 V to 14.5 V, I_LOAD1

50 mA

=

Error Amplifier (EA) Transconductance

Power FET On Resistance

Power FET Maximum Drain Source Voltage V_{DS (MAX) BOOST}

Input Disconnect Switch On Resistance

Current-Limit Threshold

Minimum On Time

g_M1

R_{DS (ON) BOOST}

270

2.0

300

175

39

210

2.2

50

330

2.4

µA/V

mΩ

V

mΩ

A

R_{DS (ON) INBK}

I_{LIM (BOOST)}

ns

Minimum Off Time

25

ns

Rev. A | Page 3 of 27

ADP5071

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

INVERTING REGULATOR

Reference Voltage

V_REF

1.60

V

Reference Voltage Accuracy

−0.5

−1.5

+0.5

+1.5

%

V

T_J= 25°C

T_J= −40°C to +125°C

Feedback Voltage

V_REF− V_FB2

0.8

Feedback Voltage Accuracy

−0.5

−1.5

+0.5

+1.5

0.1

%

µA

V

T_J= 25°C

T_J= −40°C to +125°C

Feedback Bias Current

Overvoltage Protection Threshold

I_FB2

V_OV2

0.74

At FB2 pin after soft start has

completed

Load Regulation

Line Regulation

∆(V_REF− V_FB2)/

I_LOAD2

∆(V_REF− V_FB2)/

V_PVIN2

0.0004

0.003

%/mA I_LOAD2¹= 5 mA to 75 mA

1

%/V

V_PVIN2= 2.85 V to 14.5 V, I_LOAD2=

25 mA

EA Transconductance

Power FET On Resistance

Power FET Maximum Drain Source Voltage V_{DS (MAX) INVERTER}

g_M2

R_{DS (ON) INVERTER}

270

300

350

39

330

µA/V

mΩ

V

Current-Limit Threshold

Minimum On Time

Minimum Off Time

SOFT START

I_{LIM (INVERTER)}

1200

1320

60

50

1440

mA

ns

Soft Start Timer for Boost and Inverting

Regulators

t_SS

4

ms

SS = open

32

8 × t_SS

ms

SS resistor = 50 kΩ to GND

Hiccup Time

THERMAL SHUTDOWN

Threshold

t_HICCUP

T_SHDN

T_HYS

150

15

°C

Hysteresis

¹I_LOADxis the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).

Rev. A | Page 4 of 27

Data Sheet

ADP5071

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 3.

θ_JAand Ψ_JTare based on a 4-layer printed circuit board (PCB)

(two signal and two power planes) with nine thermal vias

connecting the exposed pad to the ground plane as recommended

in the Layout Considerations section. θ_JCis measured at the top

of the package and is independent of the PCB. The Ψ_JTvalue is

more appropriate for calculating junction to case temperature in

the application.

Parameter

Rating

PVIN1, PVIN2, PVINSYS

INBK

SW1

SW2

PGND, AGND

VREG

−0.3 V to +18 V

−0.3 V to PVIN1 + 0.3 V

−0.3 V to +40 V

PVIN2 − 40 V to PVIN2 + 0.3 V

−0.3 V to +0.3 V

−0.3 V to lower of PVINSYS +

0.3 V or +6 V

Table 4. Thermal Resistance

EN1, EN2, FB1, FB2, SYNC/FREQ −0.3 V to +6 V

COMP1, COMP2, SLEW, SS,

SEQ, VREF

Operating Junction

Temperature Range

Package Type

20-Lead LFCSP

20-Lead TSSOP

θ_JA

θ_JC

Ψ_JT

Unit

°C/W

−0.3 V to VREG + 0.3 V

60.2

58.5

36.5

35.0

0.63

0.60

−40°C to +125°C

Storage Temperature Range

Soldering Conditions

−65°C to +150°C

JEDEC J-STD-020

ESD CAUTION

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. A | Page 5 of 27

ADP5071

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

20 SW2

PGND

SW1

1

2

19 PVIN2

18 PVINSYS

17 PVIN1

16 VREG

15 AGND

INBK

3

SYNC/FREQ

SEQ

4

15 PVIN1

14 VREG

13 AGND

12 VREF

11 FB2

INBK

SYNC/FREQ

SEQ

1

2

3

4

5

ADP5071

5

TOP VIEW

ADP5071

SLEW

FB1

6

TOP VIEW

(Not to Scale)

SLEW

7

14

13

VREF

FB2

FB1

COMP1

EN1

8

9

12 COMP2

11 EN2

SS

10

NOTES

1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.

Figure 2. 20-Lead LFCSP Pin Configuration

Figure 3. 20-Lead TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

LFCSP TSSOP Mnemonic Description

1

2

3

4

INBK

Input Disconnect Switch Output for the Boost Regulator.

SYNC/FREQ Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ

pin high. To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the

switching frequency, connect the SYNC/FREQ pin to an external clock.

3

4

5

6

SEQ

Start-Up Sequence Control. For manual V_POS/V_NEGstartup using an individual precision enabling pin, leave

the SEQ pin open. For simultaneous V_POS/V_NEGstartup when the EN2 pin rises, connect the SEQ pin to VREG

(the EN1 pin can be used to enable the internal references early, if required). For a sequenced startup, pull the

SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence; hold

the other enable pin low.

Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the

fastest slew rate (best efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to

VREG. For the slowest slew rate (best noise performance), connect the SLEW pin to AGND.

SLEW

5

7

FB1

Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost

regulator output capacitor and AGND to program the output voltage.

6

8

COMP1

EN1

Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this

pin and AGND.

Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable

the boost regulator output.

7

9

8

10

11

12

13

14

SS

Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower

soft start time, connect a resistor between the SS pin and AGND.

Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable

the inverting regulator output.

Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between

this pin and AGND.

Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the

inverting regulator output capacitor and VREF to program the output voltage.

9

EN2

10

11

12

COMP2

FB2

VREF

Inverting Regulator Reference Output. Connect a 1.0 μF ceramic filter capacitor between the VREF pin and

AGND.

13

14

15

16

17

15

16

17

18

19

AGND

VREG

PVIN1

PVINSYS

PVIN2

Analog Ground.

Internal Regulator Output. Connect a 1.0 μF ceramic filter capacitor between the VREG pin and AGND.

Power Input for the Boost Regulator.

System Power Supply for the ADP5071.

Power Input for the Inverting Regulator.

Rev. A | Page 6 of 27

Data Sheet

ADP5071

Pin No.

LFCSP TSSOP Mnemonic Description

18

19

20

1

2

SW2

PGND

SW1

Switching Node for the Inverting Regulator.

Power Ground for the Boost and Inverting Regulators.

Switching Node for the Boost Regulator.

EPAD

Exposed Pad. Connect the exposed pad to AGND.

Rev. A | Page 7 of 27

ADP5071

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

Typical performance characteristics are generated using the standard bill of materials for each input/output combination listed in Table 9,

Table 10, and Table 11.

1200

1000

800

600

400

200

0

1000

800

600

400

200

0

V

= 3.3V, L = 3.3µH

= 3.3V, L = 4.7µH

= 5V, L = 3.3µH

= 5V, L = 4.7µH

= 12V, L = 10µH

= 15V, L = 10µH

V

= 3.3V, L = 4.7µH

= 5V, L = 6.8µH

= 5V, L = 10µH

= 12V, L = 6.8µH

= 12V, L = 15µH

= 15V, L = 10µH

= 3.3V, L = 6.8µH

= 15V, L = 22µH

IN

–40

–30

–20

NEG

–10

0

10

20

30

40

50

V

(V)

V

(V)

POS

Figure 4. Boost Regulator Maximum Output Current, f_SW= 1.2 MHz,

_A= 25°C, Based on Target of 70% I_{LIM (BOOST)}

Figure 7. Inverting Regulator Maximum Output Current, f_SW= 1.2 MHz,

_A= 25°C, Based on Target of 70% I_{LIM (INVERTER)}

T

700

600

500

400

300

200

100

0

1000

800

600

400

200

0

V

= 3.3V, L = 3.3µH

V

= 3.3V, L = 2.2µH

= 5V, L = 3.3µH

= 5V, L = 4.7µH

= 12V, L = 6.8µH

= 15V, L = 10µH

= 12V, L = 3.3µH

= 15V, L = 4.7µH

IN

= 3.3V, L = 4.7µH

= 5V, L = 2.2µH

= 5V, L = 4.7µH

= 12V, L = 4.7µH

= 15V, L = 6.8µH

–40

–30

–20

NEG

–10

0

10

20

30

40

50

V

(V)

V

(V)

POS

Figure 5. Boost Regulator Maximum Output Current, f_SW= 2.4 MHz,

_A= 25°C, Based on Target of 70% I_{LIM (BOOST)}

Figure 8. Inverting Regulator Maximum Output Current, f_SW= 2.4 MHz,

_A= 25°C, Based on Target of 70% I_{LIM (INVERTER)}

T

100

80

60

40

20

0

100

80

60

40

20

0

V

= 3.3V, 1.2MHz

= 3.3V, 2.4MHz

V

= 3.3V, 1.2MHz

= 3.3V, 2.4MHz

IN

0.001

0.01

0.1

1

0.001

0.01

0.1

1

LOAD (A)

Figure 6. Boost Regulator Efficiency vs. Current Load, V_IN= 3.3 V,

_POS= 5 V, T_A= 25°C

Figure 9. Inverting Regulator Efficiency vs. Current Load, V_IN= 3.3 V,

_NEG= −5 V, T_A= 25°C

V

Rev. A | Page 8 of 27

Data Sheet

ADP5071

100

80

60

40

20

100

80

60

40

20

0

V

= 3.3V, 1.2MHz

= 3.3V, 2.4MHz

= 5V, 1.2MHz

= 5V, 2.4MHz

V

= 3.3V, 1.2MHz

IN

= 3.3V, 2.4MHz

= 5V, 1.2MHz

= 5V, 2.4MHz

0

0.001

0.01

0.1

1

0.001

0.01

0.1

1

LOAD (A)

Figure 10. Boost Regulator Efficiency vs. Current Load, V_POS= 9 V, T_A= 25°C

Figure 13. Inverting Regulator Efficiency vs. Current Load, V_NEG= −9 V,

T_A= 25°C

100

80

60

40

20

80

60

40

20

V

= 3.3V, 1.2MHz

= 3.3V, 2.4MHz

= 5V, 1.2MHz

= 5V, 2.4MHz

V

= 3.3V, 1.2MHz

= 3.3V, 2.4MHz

= 5V, 1.2MHz

= 5V, 2.4MHz

IN

0

0.001

0.01

0.1

1

0.001

0.01

0.1

1

LOAD (A)

Figure 11. Boost Regulator Efficiency vs. Current Load, V_POS= 15 V,

Figure 14. Inverting Regulator Efficiency vs. Current Load, V_NEG= −15 V,

T

_A= 25°C

T

_A= 25°C

100

80

60

40

20

0

100

80

60

40

20

0

V

= 5V, 1.2MHz

= 5V, 2.4MHz

V

= 5V, 1.2MHz

= 5V, 2.4MHz

IN

0.001

0.01

0.1

1

0.001

0.01

0.1

1

LOAD (A)

Figure 12. Boost Regulator Efficiency vs. Current Load, V_POS= 34 V,

_A= 25°C

Figure 15. Inverting Regulator Efficiency vs. Current Load, V_NEG= −34 V,

_A= 25°C

T

Rev. A | Page 9 of 27

ADP5071

Data Sheet

100

80

60

40

20

100

80

60

40

20

0

T

= +125°C

= +25°C

= –40°C

T

= +125°C

= +25°C

= –40°C

A

0

0.001

0.01

0.1

1

0.001

0.01

0.1

1

LOAD (A)

Figure 16. Boost Regulator Efficiency over Temperature,

Figure 19. Inverting Regulator Efficiency over Temperature,

_IN= 5 V, V_NEG= −15 V, f_SW= 1.2 MHz

V_IN= 5 V, V_POS= 15 V, f_SW= 1.2 MHz

V

0.5

0.3

0.5

0.3

0.1

–0.1

–0.3

–0.5

–0.1

–0.3

–0.5

V

ACCURACY

OUT

REF

FB2

V

ACCURACY

OUT

V

FB1

15

0

5

10

(V)

20

0

5

10

(V)

15

20

V

IN

Figure 17. Boost Regulator Line Regulation, V_POS= 15 V,

_SW= 1.2 MHz, 15 mA Load, T_A= 25°C

Figure 20. Inverting Regulator Line Regulation, V_NEG= −15 V,

_SW= 1.2 MHz, 15 mA Load, T_A= 25°C

f

0.5

0.3

0.5

0.3

0.1

–0.1

–0.3

–0.5

–0.1

–0.3

–0.5

1.2MHz

2.4MHz

1.2MHz

2.4MHz

0

0.1

0.2

0.3

0.4

0.5

0

0.05

0.10

0.15

LOAD (A)

Figure 18. Boost Regulator Load Regulation, V_IN= 5 V, V_POS= 15 V

Figure 21. Inverting Regulator Load Regulation, V_IN= 5 V, V_NEG= −15 V

Rev. A | Page 10 of 27

Data Sheet

ADP5071

0.5

0.3

0.1

–0.1

–0.3

–0.1

–0.3

–0.5

0

0.05

0.10

0.15

0.20

–0.05

0.05

0.15

0.25

0.35

0.45

INVERTING REGULATOR LOAD (A)

BOOST REGULATOR LOAD (A)

Figure 22. Cross Regulation, Boost Regulator V_FB1Regulation over Inverting

Regulator Current Load, V_IN= 5 V, V_POS= 15 V, V_NEG= −15 V,

Figure 25. Cross Regulation, Inverting Regulator V_FB2Regulation over Boost

Regulator Current Load, V_IN= 5 V, V_POS= 15 V, V_NEG= −15 V,

f

_SW= 2.4 MHz, T_A= 25°C, Boost Regulator Run in Continuous Conduction

Mode with Fixed Load for Test

f

_SW= 2.4 MHz, T_A= 25°C, Inverting Regulator Run in Continuous Conduction

Mode with Fixed Load for Test

1.44

2.40

T

= +125°C

= +25°C

= –40°C

T

= +125°C

= +25°C

= –40°C

A

2.35

2.30

2.25

2.20

2.15

2.10

2.05

2.00

1.40

1.36

1.32

1.28

1.22

1.20

0

5

10

(V)

15

20

0

2

4

6

8

10

12

14

16

V

(V)

IN

Figure 23. Boost Regulator Current Limit (I_LIMIT) vs. Input Voltage (V_IN

over Temperature

)

Figure 26. Inverting Regulator Current Limit (I_LIMIT) vs. Input Voltage (V_IN

over Temperature

)

1.27

2.54

T

= +125°C

= +25°C

= –40°C

T

= +125°C

= +25°C

= –40°C

A

1.25

1.23

1.21

1.19

1.17

1.15

1.13

2.49

2.44

2.39

2.34

2.29

2.24

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

V

(V)

V

(V)

IN

Figure 24. Oscillator Frequency vs. Input Voltage (V_IN) over Temperature,

SYNC/FREQ Pin = High

Figure 27. Oscillator Frequency vs. Input Voltage (V_IN) over Temperature,

SYNC/FREQ Pin = Low

Rev. A | Page 11 of 27

ADP5071

Data Sheet

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

14

12

10

8

6

4

T

= +125°C

= +25°C

= –40°C

A

2

T

= +125°C

= +25°C

= –40°C

A

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

V

(V)

IN

V

(V)

IN

Figure 31. Operating Quiescent Current vs. Input Voltage (V_IN) over

Temperature, Both ENx Pins On

Figure 28. Shutdown Quiescent Current vs. Input Voltage (V_IN) over

Temperature, Both ENx Pins Below Shutdown Threshold

T

V

IN

V

IN

V

NEG

2

1

V

POS

2

1

V

FB2

V

3

FB1

3

B

CH1 1V

CH3 5mV

CH2 100mV

W

4.00ms

14.0ms

CH1

5.0V

W

B

CH1 1.0V

CH3 5.0mV

CH2 100mV

4.00ms

W

CH1

5.00V

B

W

T

B

T

14.0ms

W

Figure 32. Inverting Regulator Line Transient, V_IN= 4.5 V to 5.5 V Step,

Figure 29. Boost Regulator Line Transient, V_IN= 4.5 V to 5.5 V Step,

V_NEG= −15 V, R_LOAD2= 300 Ω, f_SW= 2.4 MHz, T_A= 25°C

V_POS= 15 V, R_LOAD1= 300 Ω, f_SW= 2.4 MHz, T_A= 25°C

T

I

LOAD1

I

LOAD2

V

1

2

NEG

2

1

V

POS

V

FB2

3

V

FB1

3

B

CH1 10mA

CH3 5mV

CH2 50mV

W

4.00ms

13.0ms

CH1

50mA

W

B

CH1 20mA

CH3 25mV

CH2 50mV

W

4.00ms

CH1

137mA

B

W

T

B

T

13.160ms

Figure 33. Inverting Regulator Load Transient, V_IN= 5 V Step, V_NEG= −15 V,

_LOAD2= 35 mA to 45 mA Step, f_SW= 2.4 MHz, T_A= 25°C

Figure 30. Boost Regulator Load Transient, V_IN= 5 V Step, V_POS= 15 V,

_LOAD1= 120 mA to 150 mA Step, f_SW= 2.4 MHz, T_A= 25°C

I

Rev. A | Page 12 of 27

Data Sheet

ADP5071

T

I

INDUCTOR

I

INDUCTOR

1

2

SW2

SW1

2

3

V

NEG

POS

3

B

CH2 5V Ω

CH1 200mA

CH3 500mV

CH2 2.5V Ω

2.0µs

34.6%

CH1

0.0A

CH1 100mA

CH3 500mV

2.0µs

17.4%

CH1

0A

W

B

W

B

W

T

W

Figure 34. Boost Regulator Skip Mode Operation Showing Inductor Current

(I_INDUCTOR), Switch Node Voltage, and Output Ripple, V_IN= 5 V,

Figure 37. Inverting Regulator Skip Mode Operation Showing Inductor

Current (I_INDUCTOR), Switch Node Voltage, and Output Ripple, V_IN= 5 V,

V_POS= 15 V, I_LOAD1= 4 mA, f_SW= 2.4 MHz, T_A= 25°C

V_NEG= −5 V, I_LOAD2= 1 mA, f_SW= 2.4 MHz, T_A= 25°C

T

I

INDUCTOR

SW2

I

INDUCTOR

SW1

1

2

3

V

POS

NEG

3

B

CH2 5.0V Ω

CH1 200mA

CH3 500mV

CH2 2.5V Ω

100ns

34.6%

CH1

152mA

CH1 100mA

CH3 500mV

100ns

W

CH1

80mA

W

B

W

B

T

T 17.4%

W

Figure 35. Boost Regulator Discontinuous Conduction Mode Operation

Showing Inductor Current (I_INDUCTOR), Switch Node Voltage, and Output

Ripple, V_IN= 5 V, V_POS= 15 V, I_LOAD1= 35 mA, f_SW= 2.4 MHz, T_A= 25°C

Figure 38. Inverting Regulator Discontinuous Conduction Mode Operation

Showing Inductor Current (I_INDUCTOR), Switch Node Voltage, and Output Ripple,

V_IN= 5 V, V_NEG= −5 V, I_LOAD2= 6 mA, f_SW= 2.4 MHz, T_A= 25°C

T

I

INDUCTOR

1

2

I

INDUCTOR

SW2

SW1

2

3

V

NEG

3

V

POS

B

CH2 5V Ω

CH1 200mA

CH3 500mV

CH2 2.5V Ω

100ns

CH1

152mA

CH1 100mA

CH3 500mV

100ns

17.4%s

CH1

172mA

W

B

W

B

W

T

34.6%

T

W

Figure 39. Inverting Regulator Continuous Conduction Mode Operation

Showing Inductor Current (I_INDUCTOR), Switch Node Voltage, and Output

Ripple, V_IN= 5 V, V_NEG= −5 V, I_LOAD2= 35 mA, f_SW= 2.4 MHz, T_A= 25°C

Figure 36. Boost Regulator Continuous Conduction Mode Operation

Showing Inductor Current (I_INDUCTOR), Switch Node Voltage, and Output

Ripple, V_IN= 5 V, V_POS= 15 V, I_LOAD1= 90 mA, f_SW= 2.4 MHz, T_A= 25°C

Rev. A | Page 13 of 27

ADP5071

Data Sheet

THEORY OF OPERATION

V

IN

CVREG

PVIN1

SYNC/FREQ

PVINSYS

VREG

PVIN2

C

IN

CURRENT SENSE

INVERTER

INBK SWITCH

CONTROL

HV

REGULATOR

INBK

PWM CONTROL

D2

SW2

L2

L1

EN1

EN2

SLEW

HV

BAND GAP

D1

C

V

OUT2

OUT1

SW1

SLEW

C

OUT1

PLL

BOOST PWM

CONTROL

R

FT1

ERROR

AMP

R

REF2

FT2

+

–

OSCILLATOR

PGND

FB1

FB2

CURRENT

SENSE

BOOST_ENABLE

SEQUENCE

CONTROL

R

FB2

ERROR

AMP

–

+

INVERTER_ENABLE

VREF

REF_1V6

REF1

R

REF1

THERMAL

SHUTDOWN

FB1

COMP1

C

VREF

VREG

4µA

COMP2

UVLO

R

C1

REFERENCE

GENERATOR

START-UP

TIMERS

R

C2

REF2

FB1

OVP

REF_1V6

FB2

C

C1

C

C2

SLEW

EN1

EN2 SEQ

SS

AGND

R

(OPTIONAL)

SS

Figure 40. Functional Block Diagram

A phase-locked loop (PLL)-based oscillator generates the internal

clock and offers a choice of two internally generated frequency

options or external clock synchronization. The switching frequency

is configured using the SYNC/FREQ pin options shown in Table 6.

PWM MODE

The boost and inverting regulators in the ADP5071 operate at a

fixed frequency set by an internal oscillator. At the start of each

oscillator cycle, the MOSFET switch turns on, applying a positive

voltage across the inductor. The inductor current increases until

the current sense signal crosses the peak inductor current threshold

that turns off the MOSFET switch; this threshold is set by the error

amplifier output. During the MOSFET off time, the inductor

current declines through the external diode until the next

oscillator clock pulse starts a new cycle. It regulates the output

voltage by adjusting the peak inductor current threshold.

For external synchronization, connect the SYNC/FREQ pin to a

suitable clock source. The PLL locks to an input clock within

the range specified by f_SYNC

.

Table 6. SYNC/FREQ Pin Options

SYNC/FREQ Pin

High

Switching Frequency

2.4 MHz

Low

1.2 MHz

PSM MODE

External Clock

1 × clock frequency

During light load operation, the regulators can skip pulses to

maintain output voltage regulation. Skipping pulses increases

the device efficiency.

INTERNAL REGULATORS

The internal VREG regulator in the ADP5071 provides a stable

power supply for the internal circuitry. The VREG supply can be

used to provide a logic high signal for device configuration pins but

must not be used to supply external circuitry.

UNDERVOLTAGE LOCKOUT (UVLO)

The undervoltage lockout circuitry monitors the PVINSYS pin

voltage level. If the input voltage drops below the V_{UVLO_FALLING}

threshold, both regulators turn off. After the PVINSYS pin voltage

rises above the V_{UVLO_RISING}threshold, the soft start period initiates,

and the regulators are enabled.

The VREF regulator provides a reference voltage for the inverting

regulator feedback network to ensure a positive feedback voltage on

the FB2 pin.

OSCILLATOR AND SYNCHRONIZATION

A current-limit circuit is included for both regulators to protect the

circuit from accidental loading.

The ADP5071 initiates the drive of the boost regulator SW1 pin

and the inverting regulator SW2 pin 180° out of phase to reduce

peak current consumption and noise.

Rev. A | Page 14 of 27

Data Sheet

ADP5071

PRECISION ENABLING

CURRENT-LIMIT PROTECTION

The ADP5071 has an individual enable pin for the boost and

inverting regulators: EN1 and EN2. The enable pins feature a

precision enable circuit with an accurate reference voltage. This

reference allows the ADP5071 to be sequenced easily from other

supplies. It can also be used as a programmable UVLO input by

using a resistor divider.

The boost and inverting regulators in the ADP5071 include

current-limit protection circuitry to limit the amount of forward

current through the MOSFET switch.

When the peak inductor current exceeds the overcurrent limit

threshold for a number of clock cycles during an overload or

short-circuit condition, the regulator enters hiccup mode. The

regulator stops switching and then restarts with a new soft start

cycle after t_HICCUPand repeats until the overcurrent condition is

removed.

The enable pins have an internal pull-down resistor that defaults

each regulator to off when the pin is floating.

When the voltage at the enable pins is greater than the V_{TH_H}

reference level, the regulator is enabled.

OVERVOLTAGE PROTECTION

An overvoltage protection mechanism is present on the FB1

and FB2 pins for the boost and inverting regulators.

SOFT START

Each regulator in the ADP5071 includes soft start circuitry that

ramps the output voltage in a controlled manner during startup,

thereby limiting the inrush current. The soft start time is internally

set to the fastest rate when the SS pin is open.

On the boost regulator, when the voltage on the FB1 pin exceeds

the V_OV1threshold, the switching on SW1 stops until the voltage

falls below the threshold again. This functionality is permanently

enabled on this regulator.

Connecting a resistor between SS and AGND allows the adjust-

ment of the soft start delay. The delay length is common to both

regulators.

On the inverting regulator, when the voltage on the FB2 pin

drops below the V_OV2threshold, the switching stops until the

voltage rises above the threshold. This functionality is enabled

after the soft start period has elapsed.

SLEW RATE CONTROL

The ADP5071 employs programmable output driver slew rate

control circuitry. This circuitry reduces the slew rate of the

switching node as shown in Figure 41, resulting in reduced

ringing and lower EMI. To program the slew rate, connect the

SLEW pin to the VREG pin for normal mode, to the AGND pin

for slow mode, or leave it open for fast mode. This configuration

allows the use of an open-drain output from a noise sensitive

device to switch the slew rate from fast to slow, for example,

during analog-to-digital converter (ADC) sampling.

THERMAL SHUTDOWN

In the event that the ADP5071 junction temperature rises above

T

_SHDN, the thermal shutdown circuit turns off the IC. Extreme

junction temperatures can be the result of prolonged high current

operation, poor circuit board design, and/or high ambient temper-

ature. Hysteresis is included so that when thermal shutdown occurs,

the ADP5071 does not return to operation until the on-chip

temperature drops below T_SHDNminus T_HYS. When resuming from

thermal shutdown, a soft start is performed on each enabled

channel.

Note that slew rate control causes a trade-off between efficiency

and low EMI.

START-UP SEQUENCE

The ADP5071 implements a flexible start-up sequence to meet

different system requirements. Three different enabling modes

can be implemented via the SEQ pin, as explained in Table 7.

FASTEST

SLOWEST

Table 7. SEQ Pin Settings

SEQ Pin

Open

VREG

Low

Description

Manual enable mode

Simultaneous enable mode

Sequential enable mode

To configure the manual enable mode, leave the SEQ pin open.

The boost and inverting regulators are controlled separately from

their respective precision enable pins.

Figure 41. Switching Node at Various Slew Rate Settings

Rev. A | Page 15 of 27

ADP5071

Data Sheet

V

POS

To configure the simultaneous enable mode, connect the SEQ pin

to the VREG pin. Both regulators power up simultaneously

when the EN2 pin is taken high. The EN1 pin enable can be

used to enable the internal references ahead of enabling the

outputs, if desired. The simultaneous enable mode timing is

shown in Figure 42.

V

IN

DISCONNECT

SWITCH TURN ON

TIME

V

POS

V

NEG

1. V

POS

FOLLOWED BY V

NEG

V

(SEQ = LOW, EN1 = HIGH, EN2 = LOW)

IN

DISCONNECT

SWITCH TURN ON

POS

TIME

V

IN

DISCONNECT

SWITCH TURN ON

V

NEG

TIME

SIMULTANEOUS ENABLE MODE

(SEQ = HIGH, EN2 = HIGH)

Figure 42. Simultaneous Enable Mode

V

NEG

To configure the sequential enable mode, pull the SEQ pin low.

In this mode, either V_POSor V_NEGcan be enabled first by using

the respective EN1 pin or EN2 pin. Keep the other pin low. The

secondary supply is enabled when the primary supply completes

soft start and its feedback voltage reaches approximately 85% of

the target value. The sequential enable mode timing is shown in

Figure 43.

2. V

NEG

FOLLOWED BY V

POS

(SEQ = LOW, EN2 = HIGH, EN1 = LOW)

SEQUENTIAL ENABLE MODE

Figure 43. Sequential Enable Mode

Rev. A | Page 16 of 27

Data Sheet

ADP5071

APPLICATIONS INFORMATION

Set the positive output for the boost regulator by

ADIsimPOWER DESIGN TOOL

The ADP5071 is supported by the ADIsimPower design toolset.

ADIsimPower is a collection of tools that produce complete

power designs optimized to a specific design goal. These tools

allow the user to generate a full schematic, bill of materials, and

calculate performance in minutes. ADIsimPower can optimize

designs for cost, area, efficiency, and parts count while taking

into consideration the operating conditions and limitations of

the IC and all real external components. The ADIsimPower tool

can be found at www.analog.com/adisimpower, and the user

can request an unpopulated board through the tool.





R



^FT1

V_POS= V_FB1× 1+







R_FB1



where:

V

R

_POSis the positive output voltage.

_FB1is the FB1 reference voltage.

_FT1is the feedback resistor from V_POSto FB1.

_FB1is the feedback resistor from FB1 to AGND.

Set the negative output for the inverting regulator by

R

FT2

FB2

COMPONENT SELECTION

Feedback Resistors

V_NEG= V_FB2

where:

V

R

V

−

(

V_REF−V_FB2

)

R

The ADP5071 provides an adjustable output voltage for both boost

and inverting regulators. An external resistor divider sets the output

voltage where the divider output must equal the appropriate

feedback reference voltage, V_FB1or V_FB2. To limit the output voltage

accuracy degradation due to feedback bias current, ensure that the

_NEGis the negative output voltage.

_FB2is the FB2 reference voltage.

_FT2is the feedback resistor from V_NEGto FB2.

_FB2is the feedback resistor from FB2 to VREF.

_REFis the VREF pin reference voltage.

current through the divider is at least 10 times I_FB1or I_FB2

.

Table 8. Recommended Feedback Resistor Values

Boost/SEPIC Regulator

Inverting Regulator

Calculated

Desired Output

Voltage (V)

Calculated

R_FT1(MΩ)

0.143

0.316

0.357

0.432

0.604

1.24

1.4

2.1

2.43

2.15

R_FB1(kΩ)

115

102

115

121

100

137

100

107

100

137

Output Voltage (V)

R_FT2(MΩ)

0.332

0.475

0.523

0.715

1.15

1.62

1.15

2.8

2.32

R_FB2(kΩ)

Output Voltage (V)

1.8

3

3.3

4.2

5

1.795

2.998

3.283

4.188

5.002

8.998

12.000

13.063

14.990

18.000

19.865

23.903

30.000

35.253

102

100

102

115

158

133

71.5

162

118

113

102

107

−1.804

−3.000

−3.302

−4.174

−5.023

−8.944

−12.067

−13.027

−14.929

−18.103

−20.014

−23.984

−30.004

−34.748

9

12

13

15

18

20

24

30

35

2.67

2.94

3.16

4.12

2.55

3.09

3.65

5.9

5.11

115

Rev. A | Page 17 of 27

ADP5071

Data Sheet

Output Capacitors

VREF Capacitor

Higher output capacitor values reduce the output voltage ripple

and improve load transient response. When choosing this value,

it is also important to account for the loss of capacitance due to

the output voltage dc bias.

A 1.0 µF ceramic capacitor (C_VREF) is required between the VREF

pin and AGND.

Soft Start Resistor

A resistor can be connected between the SS pin and the AGND pin

to increase the soft start time. The soft start time can be set by the

resistor between 4 ms (268 kΩ) and 32 ms (50 kΩ). Leaving the

SS pin open selects the fastest time of 4 ms. Figure 44 shows the

behavior of this operation. Calculate the soft start time using the

following formula:

Ceramic capacitors are manufactured with a variety of dielectrics,

each with a different behavior over temperature and applied

voltage. Capacitors must have a dielectric adequate to ensure the

minimum capacitance over the necessary temperature range and

dc bias conditions. X5R or X7R dielectrics with a voltage rating of

25 V or 50 V (depending on output) are recommended for best

performance. Y5V and Z5U dielectrics are not recommended

for use with any dc-to-dc converter because of their poor

temperature and dc bias characteristics.

t

_SS= 38.4 × 10⁻³− 1.28 × 10⁻⁷× R_SS(Ω)

where 50 kΩ ≤ R_SS≤ 268 kΩ.

SOFT START

TIMER

Calculate the worst-case capacitance accounting for capacitor

variation over temperature, component tolerance, and voltage

using the following equation:

32ms

C

_EFFECTIVE= C_NOMINAL× (1 − TEMPCO) × (1 − DCBIASCO) ×

(1 − Tolerance)

where:

4ms

SS PIN OPEN

R1

SOFT START

RESISTOR

C_EFFECTIVEis the effective capacitance at the operating voltage.

C_NOMINALis the nominal data sheet capacitance.

R2

Figure 44. Soft Start Behavior

TEMPCO is the worst-case capacitor temperature coefficient.

DCBIASCO is the dc bias derating at the output voltage.

Tolerance is the worst-case component tolerance.

Diodes

A Schottky diode with low junction capacitance is recommended

for D1 and D2. At higher output voltages and especially at higher

switching frequencies, the junction capacitance is a significant

contributor to efficiency. Higher capacitance diodes also generate

more switching noise. As a guide, a diode with less than 40 pF

junction capacitance is preferred when the output voltage is

above 5 V.

To guarantee the performance of the device, it is imperative that

the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

Capacitors with lower effective series resistance (ESR) and

effective series inductance (ESL) are preferred to minimize

output voltage ripple.

Inductor Selection for the Boost Regulator

Note that the use of large output capacitors can require a slower

soft start to prevent current limit during startup. A 10 µF capacitor

is suggested as a good balance between performance and size.

The inductor stores energy during the on time of the power

switch, and transfers that energy to the output through the

output rectifier during the off time. To balance the tradeoffs

between small inductor current ripple and efficiency, inductance

values in the range of 1 µH to 22 µH are recommended. In general,

lower inductance values have higher saturation current and

lower series resistance for a given physical size. However, lower

inductance results in a higher peak current that can lead to reduced

efficiency and greater input and/or output ripple and noise. A

peak-to-peak inductor ripple current close to 30% of the maximum

dc input current for the application typically yields an optimal

compromise.

Input Capacitor

Higher value input capacitors help to reduce the input voltage

ripple and improve transient response.

To minimize supply noise, place the input capacitor as close as

possible to the PVINSYS pin, PVIN1 pin, and PVIN2 pin. A low

ESR capacitor is recommended.

The effective capacitance needed for stability is a minimum of 10 µF.

If the power pins are individually decoupled, it is recommended

to use an effective minimum of a 5.6 µF capacitor on the PVIN1

and PVIN2 pins and a 3.3 µF capacitor on the PVINSYS pin. The

minimum values specified exclude dc bias, temperature, and

tolerance effects that are application dependent and must be

taken into consideration.

VREG Capacitor

A 1.0 µF ceramic capacitor (C_VREG) is required between the VREG

pin and AGND.

Rev. A | Page 18 of 27

Data Sheet

ADP5071

For the inductor ripple current in continuous conduction mode

(CCM) operation, the input (V_IN) and output (V_POS) voltages

determine the switch duty cycle (DUTY₁) by the following

equation:

Inductor Selection for the Inverting Regulator

The inductor stores energy during the on time of the power

switch, and transfers that energy to the output through the

output rectifier during the off time. To balance the tradeoffs

between small inductor current ripple and efficiency, inductance

values in the range of 1 µH to 22 µH are recommended. In

general, lower inductance values have higher saturation current

and lower series resistance for a given physical size. However,

lower inductance results in a higher peak current that can lead

to reduced efficiency and greater input and/or output ripple and

noise. A peak-to-peak inductor ripple current close to 30% of

the maximum dc current in the inductor typically yields an

optimal compromise.









^DIODE1



V

_POS−V_IN+V

DUTY =

1

V^POS+V^DIODE1



where V_DIODE1is the forward voltage drop of the Schottky diode

(D1).

The dc input current in CCM (I_IN) can be determined by the

following equation:

I_OUT1

(1− DUTY )

I_IN

=

For the inductor ripple current in continuous conduction mode

(CCM) operation, the input (V_IN) and output (V_NEG) voltages

determine the switch duty cycle (DUTY₂) by the following

equation:

1

Using the duty cycle (DUTY₁) and switching frequency (f_SW),

determine the on time (t_ON1) using the following equation:

DUTY

f_SW

1

t_ON1

=









|V_NEG| + V^DIODE2



DUTY

=

2

V_IN+ |V_NEG| + V

^DIODE2

The inductor ripple current (∆I_L1) in steady state is calculated by

V_IN×t_ON1

where V_DIODE2is the forward voltage drop of the Schottky diode

(D2).

∆I_L1

=

L1

The dc current in the inductor in CCM (I_L2) can be determined

by the following equation:

Solve for the inductance value (L1) using the following equation:

V_IN× t_ON1

L1 =

I_OUT2

(1− DUTY )

I_L2

=

∆I_L1

2

Assuming an inductor ripple current of 30% of the maximum

dc input current results in

Using the duty cycle (DUTY₂) and switching frequency (f_SW),

determine the on time (t_ON2) by the following equation:

V_IN× t_ON1× (1− DUTY

1)

DUTY

f_SW

2

L1 =

t_ON2

=

0.3

×

I

^OUT1

Ensure that the peak inductor current (the maximum input

current plus half the inductor ripple current) is below the rated

saturation current of the inductor. Likewise, ensure that the

maximum rated rms current of the inductor is greater than the

maximum dc input current to the regulator.

The inductor ripple current (∆I_L2) in steady state is calculated by

V_IN×t_ON2

∆I_L2

=

L2

Solve for the inductance value (L2) by the following equation:

When the ADP5071 boost regulator is operated in CCM at duty

cycles greater than 50%, slope compensation is required to stabilize

the current mode loop. This slope compensation is built in to

the ADP5071 For stable current mode operation, ensure that

the selected inductance is equal to or greater than the minimum

calculated inductance, L_MIN1, for the application parameters in

the following equation:

V_IN× t_ON2

L2 =

∆I_L2

Assuming an inductor ripple current of 30% of the maximum

dc current in the inductor results in

V_IN× t_ON2×(1− DUTY )

2

L2 =

0.3

×

I

OUT2













0.13

(1 − DUTY )

(µH)

Ensure that the peak inductor current (the maximum input current

plus half the inductor ripple current) is below the rated saturation

current of the inductor. Likewise, ensure that the maximum rated

rms current of the inductor is greater than the maximum dc

input current to the regulator.

L1 > L_MIN1=V_IN×

− 0.16

1

Table 10 suggests a series of inductors to use with the ADP5071

boost regulator.

Rev. A | Page 19 of 27

ADP5071

Data Sheet

When the ADP5071 inverting regulator is operated in CCM at

duty cycles greater than 50%, slope compensation is required to

stabilize the current mode loop. For stable current mode operation,

ensure that the selected inductance is equal to or greater than

the minimum calculated inductance, L_MIN2, for the application

parameters in the following equation:

G

_CS1is the current sense transconductance gain (the inductor

current divided by the voltage at COMP1), which is internally

set by the ADP5071and is 12.5 A/V.

Z_OUT1is the impedance of the load in parallel with the output

capacitor.

To determine the crossover frequency (f_C1), it is important to

note that, at that frequency, the compensation impedance (Z_COMP1

is dominated by a resistor (R_C1), and the output impedance (Z_OUT1

is dominated by the impedance of an output capacitor (C_OUT1).

Therefore, when solving for the crossover frequency, the equation

(by definition of the crossover frequency) is simplified to

)













0.13

(1 − DUTY

(µH)

L2 > L_MIN2=V_IN×

− 0.16

2

)

Table 11 suggests a series of inductors to use with the ADP5071

inverting regulator.

V_FB1V_IN

V_POSV_POS

LOOP COMPENSATION

A_VL1

=

×

×G_M1× R_C1×G_CS1×

The ADP5071 uses external components to compensate the

regulator loop, allowing the optimization of the loop dynamics

for a given application. It is recommended to use the ADIsimPower

tool to calculate compensation components.

1

=1

2π × f_C1×C_OUT1

where f_C1is the crossover frequency.

Boost Regulator

To solve for R_C1, use the following equation:

The boost converter produces an undesirable right half plane

zero in the regulation feedback loop. This feedback loop requires

compensating the regulator such that the crossover frequency

occurs well below the frequency of the right half plane zero. The

right half plane zero is determined by the following equation:

2

2π × f_C1×C_OUT1×(V_POS

)

R_C1

=

V_FB1×V_IN×G_M1×G_CS1

where G_CS1= 12.5 A /V.

2

Using typical values for V_FB1and G_M1results in

R

_LOAD1(1− DUTY

1)

f_Z1(RHP) =

where:

2

2094 × f_C1×C_OUT1×(V_POS

)

2

π ×

L1

R_C1

=

V_IN

f_Z1(RHP) is the right half plane zero frequency.

_LOAD1is the equivalent load resistance or the output voltage

divided by the load current.

For better accuracy, it is recommended to use the value of output

capacitance, C_OUT1, expected for the dc bias conditions under

which it operates under in the calculation for R_C1.

R









^DIODE1



V

_POS−V_IN+V

After the compensation resistor is known, set the zero formed

by the compensation capacitor and resistor to one-fourth of the

crossover frequency, or

DUTY =

1

VPOS +VDIODE1



where V_DIODE1is the forward voltage drop of the Schottky

2

diode (D1).

C_C1

=

π × f_C1× R_C1

To stabilize the regulator, ensure that the regulator crossover

frequency is less than or equal to one-tenth of the right half

plane zero frequency.

where C_C1is the compensation capacitor value.

ERROR

AMPLIFIER

FB1

The boost regulator loop gain is

COMP1

g

M1

REF1

V_FB1V_IN

V_POSV_POS

R

C1

A_VL1

=

×

× G_M1× R_OUT1||Z_COMP1× G_CS1× Z_OUT1

C

B1

C

C1

where:

A

V

G

_VL1is the loop gain.

Figure 45. Compensation Components

_FB1is the feedback regulation voltage

_POSis the regulated positive output voltage.

_INis the input voltage.

The capacitor, C_B1, is chosen to cancel the zero introduced by

the output capacitor ESR. Solve for C_B1as follows:

_M1is the error amplifier transconductance gain.

ESR × C_OUT1

CB1 =

R

Z

_OUT1is the output impedance of the error amplifier and is 33 MΩ.

_COMP1is the impedance of the series RC network from

R_C1

COMP1 to AGND.

Rev. A | Page 20 of 27

Data Sheet

ADP5071

For low ESR output capacitance such as with a ceramic capacitor,

To determine the crossover frequency, it is important to note

that, at that frequency, the compensation impedance (Z_COMP2) is

C

_B1is optional. For optimal transient performance, R_C1and C_C1

may need to be adjusted by observing the load transient response

of the ADP5071. For most applications, R_C1must be within the

range of 1 kΩ to 200 kΩ, and C_C1must be within the range of

1 nF to 68 nF.

dominated by a resistor, R_C2, and the output impedance (Z_OUT2

)

is dominated by the impedance of the output capacitor, C_OUT2

.

Therefore, when solving for the crossover frequency, the equation

(by definition of the crossover frequency) is simplified to

Inverting Regulator

V_FB2

V_IN

A

=

×

× G_M2×

VL2

|V_NEG| (V_IN+ 2 ×|V_NEG|)

The inverting converter, like the boost converter, produces an

undesirable right half plane zero in the regulation feedback loop.

This feedback loop requires compensating the regulator such that

the crossover frequency occurs well below the frequency of the

right half plane zero. The right half plane zero frequency is

determined by the following equation:

1

R_C2× G_CS2 ×

=1

2π × f_C2× C_OUT2

where f_C2is the crossover frequency.

To solve for R_C2, use the following equation:

2

R_LOAD2(1− DUTY

2π × L2 × DUTY

2

)

2π × f_C2× C_OUT2×|V_NEG|×(V_IN+ (2 ×|V_NEG|)

V_FB2×V_IN× G_M2× G_CS2

f_Z2(RHP) =

R_C2=

2

where:

f_Z2(RHP) is the right half plane zero frequency.

_LOAD2is the equivalent load resistance or the output voltage

divided by the load current.

where G_CS2= 12.5 A /V.

Using typical values for V_FB2and G_M2results in

R

2094× f_C2×C_OUT2×|V_NEG|× (V_IN+ (2 ×|V_NEG|)

R_C2

=

V_IN









|V_NEG|+V^DIODE2

V_IN+|V_NEG|+ V



DUTY =

2

For better accuracy, it is recommended to use the value of output

capacitance, C_OUT2, expected under the dc bias conditions that it

operates under in the calculation for R_C2.

^DIODE2

where V_DIODE2is the forward voltage drop of the Schottky diode

(D2).

After the compensation resistor is known, set the zero formed

by the C_C2and R_C2to one-fourth of the crossover frequency, or

To stabilize the regulator, ensure that the regulator crossover

frequency is less than or equal to one-tenth of the right half

plane zero frequency.

2

CC2 =

π × f_C2× RC2

The inverting regulator loop gain is

where C_C2is the compensation capacitor.

V_FB2

V_IN

ERROR

A

=

×

× G_M2×

VL2

AMPLIFIER

FB2

|V_NEG

|

(V_IN+ 2 × |V_NEG|)

COMP2

g

M2

REF2

R

C2

C

B2

R_OUT2||Z_COMP2× G_CS2× Z_OUT2

where:

C

C2

A

V

G

_VL2is the loop gain.

_FB2is the feedback regulation voltage.

_NEGis the regulated negative output voltage.

_INis the input voltage.

Figure 46. Compensation Component

The capacitor, C_B2, is chosen to cancel the zero introduced by

output capacitance, ESR.

_M2is the error amplifier transconductance gain.

Solve for C_B2as follows:

R

Z

_OUT2is the output impedance of the error amplifier and is 33 MΩ.

_COMP2is the impedance of the series RC network from COMP2

ESR × C_OUT2

CB2 =

to AGND.

_CS2is the current sense transconductance gain (the inductor

R_C2

For low ESR output capacitance, such as with a ceramic capacitor,

_B2is optional. For optimal transient performance, R_C2and C_C2

may need to be adjusted by observing the load transient response

of the ADP5071. For most applications, R_C2must be within the

range of 1 kΩ to 200 kΩ, and C_C2must be within the range of

1 nF to 68 nF.

G

current divided by the voltage at COMP2), which is internally

set by the ADP5071 and is 12.5 A/V.

C

Z_OUT2is the impedance of the load in parallel with the output

capacitor.

Rev. A | Page 21 of 27

ADP5071

Data Sheet

Figure 47 shows the schematic referenced by Table 9 through

Table 11 with example component values for +5 V to 15 V

generation. Table 9 shows the components common to all of the

COMMON APPLICATIONS

Table 9 through Table 11 list a number of common component

selections for typical V_INand V_OUTconditions. These have been

bench tested and provide an off the shelf solution. Note that when

pairing a boost and inverting regulator bill of materials, choose

the same V_INand switching frequency. To optimize components

for an application, it is recommend to use the ADIsimPower

toolset.

V

_INand V_OUTconditions.

Table 9. Recommended Common Components Selections

REF Value Part Number

C_IN110 µF TMK316B7106KL-TD

Manufacturer

Taiyo Yuden

C_VREG1 µF

C_VREF1 μF

GRM188R71A105KA61D Murata

ADP5071

R

5.6kΩ

L1

3.3µH

SS

INBK

C1

V

+15V

D1

DFLS240

POS

COMP1

C

47nF

C1

SW1

FB1

EN1

R

FT1

2.43MΩ

C

OUT1

VREG

10µF

R

C

FB1

VREG

137kΩ

1µF

PVIN1

PVIN2

PVINSYS

V

+5V

IN

PGND

VREF

C

IN1

10µF

C

VREF

1µF

EN2

R

FB2

C

R

12kΩ

OUT2

C2

118kΩ

10µF

FB2

COMP2

R

FT2

C

C2

47nF

2.32MΩ

SYNC/FREQ

SLEW

SW2

V

NEG

D2

SEQ

–15V

AGND

DFLS240

L2

6.8µH

Figure 47. Typical +5 V to 15 V Application

Rev. A | Page 22 of 27

Data Sheet

ADP5071

Table 10. Recommended Boost Regulator Components

V_INV_POSFreq.

(V) (V) (MHz) (µH) Part

L1

L1, Coilcraft®

C_OUT1

(µF)

D1, Diodes,

Inc. Part

R_FT1

(MΩ)

R_FB1

(kΩ)

C_C1

(nF)

R_C1

(kΩ)

C_OUT1, Murata Part

3.3

3.3 15

3.3 24

3.3 34

5

9

1.2

2.4

1.2

2.4

1.2

2.4

1.2

2.4

1.2

2.4

1.2

2.4

1.2

2.4

1.2

2.4

1.2

2.4

1.2

2.4

2.2

1

XAL4020-222ME_

XAL4020-102ME_

XAL4020-222ME_

XAL4020-152ME_

XAL4030-332ME_

XAL4020-152ME_

XAL4030-332ME_

XAL4030-472ME_

XAL4030-332ME_

XAL4020-152ME_

XAL4030-332ME_

XAL4020-222ME_

XAL4030-472ME_

XAL4030-332ME_

XAL4030-472ME_

XAL4030-682ME_

XAL4030-332ME_

10

GRM32ER71H106KA12L DFLS240L

GRM32ER71H106KA12L DFLS240

0.604

1.24

2.43

3.09

4.22

1.24

2.43

3.09

4.22

3.09

115

121

137

107

102

121

137

107

102

107

47

4.7

3.3

14

18

33

2.2

1.5

3.3

1.5

3.3

4.7

3.3

1.5

3.3

2.2

4.7

3.3

4.7

6.8

3.3

33

9

1.8

2.2

5.6

8.2

10

12

4.7

15

24

34

24

12

Table 11. Recommended Inverting Regulator Components

V_INV_NEGFreq.

L2

(MHz) (µH) L2, Coilcraft Part

C_OUT2

(µF)

D2, Diodes,

Inc. Part

R_FT2

(MΩ)

R_FB2

(kΩ)

C_C2

(nF)

R_C2

(kΩ)

(V) (V)

3.3 −5

3.3 −9

C_OUT2, Murata Part

1.2

2.4

1.2

2.4

3.3

2.2

4.7

2.2

4.7

2.2

4.7

3.3

6.8

4.7

6.8

3.3

6.8

3.3

10

XAL4030-332ME_

XAL4020-222ME_

XAL4030-472ME_

XAL4020-222ME_

XAL4030-472ME_

XAL4020-222ME_

XAL4030-472ME_

XAL4030-332ME_

XAL4030-682ME_

XAL4030-472ME_

XAL4030-682ME_

XAL4030-332ME_

XAL4030-682ME_

XAL4030-332ME_

XAL4040-103ME_

XAL4030-472ME_

XAL4040-103ME_

XAL4030-472ME_

XAL4040-153ME_

XAL4030-682ME_

10

GRM32ER71H106KA12L DFLS240L

GRM32ER71H106KA12L DFLS240

1.15

1.62

2.32

3.16

4.99

1.62

2.32

3.16

4.99

3.16

158

133

118

102

115

133

118

102

115

102

47

68

47

8.2

10

15

18

39

47

33

5.6

12

27

39

15

3.3 −15 1.2

3.3 −15 2.4

3.3 −24 1.2

3.3 −24 2.4

3.3 −34 1.2

3.3 −34 2.4

5

−9

1.2

2.4

5

12

−15 1.2

−15 2.4

−24 1.2

−24 2.4

−34 1.2

−34 2.4

−24 1.2

−24 2.4

4.7

10

4.7

15

6.8

Rev. A | Page 23 of 27

ADP5071

Data Sheet

SUPER LOW NOISE WITH OPTIONAL LDOS

Low dropout regulators (LDOs) can be added to the ADP5071

output to provide super low noise supplies for high performance

ADCs, digital-to-analog converters (DACs), and other precision

applications. Table 12 shows recommended companion devices,

and Figure 48 shows a typical application schematic for 15 V

generation from a +5 V supply.

ADP5071

R

5.6kΩ

L1

3.3µH

SS

INBK

C1

D1

COMP1

ADP7142

VIN VOUT

DFLS240

V

= +15V

POS

C

+16V

C

1µF

C1

SW1

FB1

47nF

R

20kΩ

C

1µF

EN1

FT3

NR3

IN3

R

C

FT1

2.15MΩ

OUT3

ADJ

(5V)

2.2µF

C

R

1kΩ

OUT1

10µF

FB3

NR3

VREG

R

10kΩ

C

FB1

VREG

EN

SS

113kΩ

1µF

PVIN1

PVIN2

PVINSYS

GND

V

IN

PGND

VREF

C

1nF

+5V

C

SS3

IN1

10µF

C

VREF

1µF

ADP7182

EN VOUT

V

= –15V

NEG

EN2

C

R

OUT2

10µF

FB2

R

FT4

52.3kΩ

C

C2

NR4

47µF

100kΩ

C

OUT4

12kΩ

FB2

2.2µF

ADJ

COMP2

R

FT2

2.1MΩ

R

5.9kΩ

FB4

NR4

C

C2

SYNC/FREQ

SLEW

5.9kΩ

–16V

47nF

SW2

VIN

GND

C

IN4

D2

DFLS240

SEQ

2.2µF

AGND

L2

6.8µH

Figure 48. Super Low Noise 15 V Generation with Post Regulation by the ADP7142 (+40 V, +200 mA, Low Noise LDO) and ADP7182 (−28 V, −200 mA, Low Noise LDO)

Table 12. Recommended LDOs for Super Low Noise Operation

Parameter

V_INRange

Fixed V_OUT

Adjustable V_OUT

I_OUT

I_Qat No Load

I_SHDNTypical

Soft Start

PGOOD

ADP7102

3.3 V to 20 V

1.5 V to 9 V

1.22 V to 19 V

300 mA

400 µA

40 µA

No

Yes

ADP7104

3.3 V to 20 V

1.5 V to 9 V

1.22 V to 19 V

500 mA

400 µA

40 µA

No

Yes

ADP7105

3.3 V to 20 V

1.8 V, 3.3 V, 5 V

1.22 V to 19 V

500 mA

400 µA

40 µA

Yes

ADP7118

2.7 V to 20 V

1.2 V to 5 V

1.2 V to 19 V

200 mA

50 µA

2 µA

Yes

No

ADP7142

2.7 V to 40 V

1.2 V to 5 V

1.2 V to 39 V

200 mA

50 µA

2 µA

Yes

No

ADP7182

−2.7 V to −28 V

−1.8 V to −5 V

−1.22 V to−27 V

−200 mA

−33 µA

−2 µA

No

Noise (Fixed), 10 Hz 15 µV rms

to 100 kHz

15 µV rms

11 µV rms

18 µV rms

PSRR (100 kHz)

PSRR (1 MHz)

Package

60 dB

40 dB

8-lead LFCSP,

8-lead SOIC

60 dB

40 dB

8-lead LFCSP,

8-lead SOIC

60 dB

40 dB

8-lead LFCSP,

8-lead SOIC

68 dB

50 dB

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

68 dB

50 dB

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

45 dB

6-lead LFCSP, 8-lead

LFCSP, 5-lead TSOT

Rev. A | Page 24 of 27

Data Sheet

ADP5071

SEPIC STEP-UP/STEP-DOWN OPERATION

SEPIC operation allows the positive output channel to produce

a voltage higher or lower than V_IN. Both standalone and coupled

inductors are supported for this application. SEPIC designs are

supported in the ADIsimPower toolset.

ADP5071

SS

INBK

STANDALONE OR

L1A

L1B

D1

COUPLED-INDUCTOR

R

C1

COMP1

+5V/400mA

C

C1

SW1

FB1

EN1

C

S1

C

R

VREG

FT1

VREG

C

OUT1

R

FB1

1µF

PVIN1

V

= +12V

PVIN2

PVINSYS

IN

PGND

VREF

C

IN1

10µF

C

VREF

EN2

1µF

R

FB2

C

OUT2

R

C2

FB2

COMP2

R

FT2

C

C2

SYNC/FREQ

SLEW

SW2

–5V/400mA

D2

SEQ

AGND

L2

Figure 49. SEPIC Application for +12 V in to 5 V Output Generation

Rev. A | Page 25 of 27

ADP5071

Data Sheet

LAYOUT CONSIDERATIONS

Layout is important for all switching regulators but is particularly

important for regulators with high switching frequencies. To

achieve high efficiency, good regulation, good stability, and low

noise, a well-designed PCB layout is required. Follow these

guidelines when designing PCBs:

•

Keep the input bypass capacitor, C_IN1, close to the PVIN1 pin,

the PVIN2 pin, and the PVINSYS pin. Route each of these

pins individually to the pad of this capacitor to minimize noise

coupling between the power inputs rather than connecting the

three pins at the device. A separate capacitor can be used on

the PVINSYS pin for the best noise performance.

•

Keep the high current paths as short as possible. These

paths include the connections between CIN1, L1, L2, D1,

D2, COUT1, COUT2, and PGND and their connections to

the ADP5071.

Keep AGND and PGND separate on the top layer of the

board. This separation avoids pollution of AGND with

switching noise. Do not connect PGND to the EPAD on

the top layer of the layout. Connect both AGND and PGND

to the board ground plane with vias. Ideally, connect PGND

to the plane at a point between the input and output

capacitors. Connect the EPAD on its own to this ground

layer with vias and connect AGND as near to the pin as

possible between the CVREF and CVREG capacitors.

Keep high current traces as short and wide as possible to

minimize parasitic series inductance, which causes spiking

and electromagnetic interference (EMI).

Figure 50. Suggested LFCSP Layout; Vias Connected to the PCB Ground

Plane, Not to Scale

•

Avoid routing high impedance traces near any node con-

nected to the SW1 and SW2 pins or near Inductors L1and

L2 to prevent radiated switching noise injection.

•

Place the feedback resistors as close to the FB1 and FB2 pins as

possible to prevent high frequency switching noise injection.

Place the top of the upper feedback resistors, RFT1 and RFT2,

or route traces to them from as close as possible to the top

of COUT1 and COUT2 for optimum output voltage sensing.

Place the compensation components as close as possible

to COMP1 and COMP2. Do not share vias to the ground

plane with the feedback resistors to avoid coupling high

frequency noise into the sensitive COMP1 and COMP2 pins.

Place the CVREF and CVREG capacitors as close to the

VREG and VREF pins as possible. Ensure that short traces

•

Figure 51. Suggested TSSOP Layout; Vias Connected to the PCB Ground

Plane, Not to Scale

are used between VREF and R_FB2

.

Rev. A | Page 26 of 27

Data Sheet

ADP5071

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

16

15

20

0.50

BSC

1

EXPOSED

PAD

2.75

2.60 SQ

2.35

11

5

6

BOTTOM VIEW

10

0.50

0.40

0.30

0.25 MIN

TOP VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 52. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-8)

Dimensions shown in millimeters

4.25

4.20

4.15

6.60

6.50

6.40

20

11

3.05

3.00

2.95

4.50

4.40

4.30

EXPOSED

PAD

(Pins Up)

TOP

VIEW

6.40

BSC

1

10

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.65 BSC

1.05

1.00

0.80

1.20 MAX

SECTION OF THIS DATA SHEET.

8°

0°

0.20

0.09

0.15

0.05

0.30

0.19

0.75

0.60

0.45

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-ACT

Figure 53. 20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]

(RE-20-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADP5071ACPZ

ADP5071ACPZ-R7

ADP5071AREZ

ADP5071AREZ-R7

ADP5071CP-EVALZ

ADP5071RE-EVALZ

Temperature Range

−40°C to +125°C

Package Description

Package Option

20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]

Evaluation Board for the LFCSP_WQ

CP-20-8

RE-20-1

Evaluation Board for the TSSOP_EP

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D12069-0-6/15(A)

Rev. A | Page 27 of 27


型号：	ADP5071ACPZ
厂家：	ADI
描述：	Independent Positive and Negative Outputs
文件：	总28页 (文件大小：1002K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP5071ACPZ [ADI]

相关型号：

ADP5071ACPZ-R7

ADP5071AREZ

ADP5071AREZ-R7

ADP5071CP-EVALZ

ADP5071RE-EVALZ

ADP5072

ADP5072ACBZ-R7

ADP5072CB-EVALZ

ADP5073

ADP5073ACPZ-R7

ADP5073CP-EVALZ

ADP5074