ADP5073 [ADI]
2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs;
| 型号： | ADP5073 |
| 厂家： | 
ADI |
| 描述： | 2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| 文件： | 总23页 (文件大小：715K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 A/1.2 A DC-to-DC Switching Regulator with
Independent Positive and Negative Outputs
Data Sheet
ADP5076
The ADP5076 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up.
FEATURES
Input supply voltage range: 2.85 V to 5.5 V
Generates well regulated, independently resistor
programmable VPOS and VNEG outputs
Boost regulator to generate VPOS output
Adjustable positive output to 35 V
Other key safety features in the ADP5076 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The ADP5076 is available in a 20-ball wafer level chip scale
package (WLCSP) and is rated for a −40°C to +125°C junction
temperature range.
Integrated 2.0 A main switch
Inverting regulator to generate VNEG output
Adjustable negative output to −30 V
Integrated 1.20 A main switch
Table 1. Family Models
Boost
Inverter
1.2 MHz or 2.4 MHz switching frequency with optional
external frequency synchronization from 1.0 MHz to
2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Individual precision enable and flexible start-up sequence
control for symmetric start, VPOS first, or VNEG first
Out of phase operation
Model
Switch (A) Switch (A) Package
ADP5070 1.0
0.6
1.2
0.6
1.2
2.4
0.8
1.2
20-lead LFCSP (4 mm ×
4 mm) and 20-lead TSSOP
20-lead LFCSP (4 mm ×
4 mm) and 20-lead TSSOP
20-ball WLCSP
(1.61 mm × 2.18 mm)
16-lead LFCSP (3 mm ×
3 mm)
16-lead LFCSP (3 mm ×
3 mm)
12-ball WLCSP
(1.61 mm × 2.18 mm)
ADP5071 2.0
ADP5072 1.0
ADP5073 N/A1
ADP5074 N/A1
ADP5075 N/A1
ADP5076 2.0
UVLO, OCP, OVP, and TSD protection
1.61 mm × 2.18 mm, 20-ball WLCSP
−40°C to +125°C junction temperature range
APPLICATIONS
Bipolar amplifiers, ADCs, DACs, and multiplexers
Charge coupled device (CCD) bias supply
Optical module supply
20-ball WLCSP
(1.61 mm × 2.18 mm)
1 N/A means not applicable.
RF power amplifier bias
Time of flight module supply
FUNCTIONAL BLOCK DIAGRAM
V
IN
GENERAL DESCRIPTION
ADP5076
L1
D1
SS
The ADP5076 is a dual, high performance, dc-to-dc regulator that
generates independently regulated positive and negative rails. The
input voltage range of 2.85 V to 5.5 V supports a wide variety of
applications. The integrated main switch in both regulators enables
generation of an adjustable positive output voltage up to +35 V and
a negative output voltage down to −30 V.
V
POS
R
C1
SW1
SW1
COMP1
EN1
C
C1
R
FT1
FB1
R
FB1
C
OUT1
OUT2
PVIN
PVIN
AVIN
V
IN
PGND
PGND
VREF
C
IN
C
VREF
The ADP5076 operates at a pin selected 1.2 MHz or 2.4 MHz
switching frequency. The ADP5076 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
filtering in sensitive applications. Both regulators implement
programmable slew rate control circuitry for the metal-oxide
semiconductor field effect transistor (MOSFET) driver stage to
reduce electromagnetic interference (EMI). Flexible start-up
sequencing is provided with the options of manual enable,
simultaneous mode, positive supply first, and negative supply first.
EN2
C
R
FB2
R
C2
FB2
COMP2
R
FT2
C
C2
SYNC
SLEW
SEQ
SW2
V
NEG
D2
AGND
L2
Figure 1.
Rev. A
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2019 Analog Devices, Inc. All rights reserved.
www.analog.com
ADP5076
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Precision Enabling ..................................................................... 14
Soft Start ...................................................................................... 14
Slew Rate Control....................................................................... 14
Current-Limit Protection.......................................................... 14
Overvoltage Protection.............................................................. 14
Thermal Shutdown .................................................................... 14
Startup Sequence ........................................................................ 14
Applications Information.............................................................. 16
Component Selection ................................................................ 16
Output Capacitors...................................................................... 17
Loop Compensation .................................................................. 18
Common Applications .............................................................. 20
Layout Considerations............................................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 13
Pulse Width Modulation (PWM) Mode ................................. 13
Pulse Skip Modulation Mode ................................................... 13
UVLO........................................................................................... 13
Oscillator and Synchronization................................................ 13
Internal Regulator ...................................................................... 13
REVISION HISTORY
12/2019—Rev. 0 to Rev. A
Replaced Figure 1 ............................................................................. 1
Replaced Figure 39 ......................................................................... 13
8/2019—Revision 0: Initial Version
Rev. A | Page 2 of 23
Data Sheet
ADP5076
SPECIFICATIONS
PVIN = AVIN = +2.85 V to +5.5 V, adjustable positive output voltage (VPOS) = +15 V, adjustable negative output voltage (VNEG) = −15 V,
switching frequency (fSW) = 1200 kHz, junction temperature (TJ) = −40°C to +125°C for minimum and maximum specifications, and
ambient temperature (TA) = +25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT SUPPLY VOLTAGE
QUIESCENT CURRENT
Operating Quiescent Current
Sum of PVIN and AVIN
VIN
2.85
5.5
V
PVIN pin, AVIN pin
IQ
3.5
4.0
2.2
mA
mA
No switching, EN1 pin =
EN2 pin = high
No switching, EN1 pin =
EN2 pin = low
Standby Current
ISTNDBY
2.05
UVLO
System UVLO Threshold
Rising
Falling
AVIN pin
VUVLO_RISING
VUVLO_FALLING
VHYS_1
2.8
2.55
0.25
2.85
V
V
V
2.5
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
fSW
1.130
2.240
1.200
2.400
1.270
2.560
MHz
MHz
SYNC pin = low
SYNC pin = high (connect to
AVIN pin)
SYNC Input
Input Clock Range
Input Clock Minimum On Pulse Width
Input Clock Minimum Off Pulse Width tSYNC_MIN_OFF
fSYNC
tSYNC_MIN_ON
1.000
100
100
2.600
1.3
MHz
ns
ns
V
Input Clock High Logic
Input Clock Low Logic
PRECISION ENABLING (EN1, EN2)
High Level Threshold
Low Level Threshold
Shutdown Mode
VH (SYNC)
VL (SYNC)
0.4
V
VTH_H
VTH_L
VTH_S
1.125
1.025
0.4
1.15
1.05
1.175
1.075
V
V
V
Internal circuitry disabled to
achieve ISTNDBY
Pull-Down Resistance
BOOST REGULATOR
Adjustable Positive Output Voltage
Feedback Voltage
REN
1.48
0.8
MΩ
VPOS
VFB1
35
V
V
Feedback Voltage Accuracy
−0.5
−1.5
+0.5
+1.5
0.1
%
%
μA
V
TJ = 25°C
TJ = −40°C to +125°C
Feedback Bias Current
Overvoltage Protection Threshold
Load Regulation
Line Regulation
Error Amplifier (EA) Transconductance
Power Field Effect Transistor (FET) On
Resistance
Power FET Maximum Drain Source
Voltage
Current-Limit Threshold, Main Switch
Minimum On Time
Minimum Off Time
IFB1
VOV1
0.86
At FB1 pin
%/mA ILOAD11 = 5 mA to 150 mA
(∆VFB1/VFB1)/ΔILOAD1
(∆VFB1/VFB1)/ΔVPVIN
GM1
0.0003
0.002
300
%/V
μA/V
mΩ
ILOAD1 = 50 mA
260
2.0
340
2.4
RDS (ON) BOOST
175
VDS (MAX) BOOST
ILIM (BOOST)
39
V
2.2
50
25
A
ns
ns
Rev. A | Page 3 of 23
ADP5076
Data Sheet
Parameter
Symbol
Min
Typ
1.60
0.8
Max
Unit
Test Conditions/Comments
INVERTING REGULATOR
Adjustable Negative Output Voltage
Reference Voltage
VNEG
VREF
−30
V
V
%
%
V
Reference Voltage Accuracy
−0.5
−1.5
+0.5
+1.5
TJ = 25°C
TJ = −40°C to +125°C
VFB2 is the FB2 reference
Feedback Voltage
VREF − VFB2
voltage
Feedback Voltage Accuracy
−0.5
−1.5
+0.5
+1.5
0.1
%
%
μA
V
TJ = 25°C
TJ = −40°C to +125°C
Feedback Bias Current
Overvoltage Protection Threshold
IFB2
VOV2
0.74
At FB2 pin after soft start has
completed
Load Regulation
Line Regulation
(∆(VREF − VFB2)/(VREF
−
−
0.0004
0.003
%/mA
%/V
I
LOAD2 = 5 mA to 75 mA
V
FB2))/∆ILOAD2
(∆(VREF − VFB2)/(VREF
FB2))/ΔVPVIN
I
LOAD2 = 25 mA
V
EA Transconductance
Power FET On Resistance
Power FET Maximum Drain Source
Voltage
GM2
RDS (ON) INVERTER
VDS (MAX) INVERTER
260
300
350
39
340
μA/V
mΩ
V
Current-Limit Threshold, Main Switch
Minimum On Time
Minimum Off Time
ILIM (INVERTER)
1.20
1.32
60
50
1.44
A
ns
ns
SOFT START
Soft Start Timer for DC-DC Regulators
tSS
4
32
8 × tSS
ms
ms
ms
SS pin = open
SS resistor = 50 kΩ to GND
Hiccup Time
THERMAL SHUTDOWN
Threshold
tHICCUP
TSHDN
THYS
150
15
°C
°C
Hysteresis
1 ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).
Rev. A | Page 4 of 23
Data Sheet
ADP5076
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
PVIN, AVIN
SW1
Rating
−0.3 V to +6 V
−0.3 V to +40 V
PVIN − 40 V to PVIN + 0.3 V
−0.3 V to +0.3 V
−0.3 V to +6 V
SW2
θJA is the natural convection junction-to-ambient thermal
PGND, AGND
EN1, EN2, FB1, FB2, SYNC
COMP1, COMP2, SLEW, SS,
SEQ, VREF
Operating Junction
Temperature Range
Storage Temperature Range
Soldering Conditions
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction-to-case thermal resistance. ΨJT is the junction-to-
top of package thermal characterization parameter.
−0.3 V to AVIN + 0.3 V
θJA and ΨJT are based on a 4-layer PCB (two signal and two
−40°C to +125°C
power planes). θJC is measured at the top of the package and is
independent of the PCB. The ΨJT value is more appropriate for
calculating junction to case temperature in the application.
−65°C to +150°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4. Thermal Resistance
Package Type
θJA
θJC
ΨJT
Unit
CB-20-14
50
0.54
0.13
C/W
ESD CAUTION
Rev. A | Page 5 of 23
ADP5076
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
A
B
C
D
E
PVIN
SW2
SW1
PGND
AVIN
EN2
PVIN
SW1
SEQ
SS
PGND
EN1
SYNC
AGND SLEW
COMP2 FB2
FB1
VREF COMP1
Figure 2. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
A1, B2
A2
A3, B3
A4, B4
B1
Mnemonic
Description
PVIN
SW2
SW1
PGND
AVIN
Power Input for the Inverter Regulator.
Switching Node for the Inverting Regulator.
Switching Node for the Boost Regulator.
Power Ground for the Boost Regulator.
System Power Supply for the ADP5076.
C1
EN2
Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable
the inverting regulator output.
C2
C3
SYNC
SEQ
Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC pin
high. To set the switching frequency to 1.2 MHz, pull the SYNC pin low. To synchronize the switching frequency,
connect the SYNC pin to an external clock.
Start-Up Sequence Control. For manual VPOS/VNEG startup using an individual precision enabling pin, leave the
SEQ pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to the AVIN pin.
(The EN1 pin can be used to enable the internal references early, if required.) For a sequenced startup, pull
the SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence. Hold
the other enable pin low.
C4
EN1
Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable the
boost regulator output.
D1
D2
AGND
SLEW
Analog Ground.
Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the fastest
slew rate (best efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to the AVIN pin. For
the slowest slew rate (best noise performance), connect the SLEW pin to the AGND pin.
D3
D4
E1
E2
E3
E4
SS
Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft
start time, connect a resistor between the SS pin and the AGND pin.
Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost
regulator output capacitor and the AGND pin to program the output voltage.
Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this
pin and the AGND pin.
Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the
inverting regulator output capacitor and the VREF pin to program the output voltage.
Inverting Regulator Reference Output. Connect a 1.0 μF ceramic filter capacitor between the VREF pin and
the AGND pin.
Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this pin
and the AGND pin.
FB1
COMP2
FB2
VREF
COMP1
Rev. A | Page 6 of 23
Data Sheet
ADP5076
TYPICAL PERFORMANCE CHARACTERISTICS
1200
500
450
400
350
300
250
200
150
100
50
V
V
V
V
= 3.3V, L1 = 3.3µH
= 3.3V, L1 = 4.7µH
= 5.0V, L1 = 3.3µH
= 5.0V, L1 = 4.7µH
V
V
V
V
= 3.3V, L2 = 4.7µH
= 3.3V, L2 = 6.8µH
= 5V, L2 = 10µH
= 5V, L2 = 6.8µH
IN
IN
IN
IN
IN
IN
IN
IN
1000
800
600
400
200
0
0
0
5
10
15
20
25
30
35
40
–35
–30
–25
–20
–15
(V)
–10
–5
0
V
(V)
POS
V
NEG
Figure 3. Boost Regulator Maximum Output Current, fSW = 1.2 MHz,
TA = 25°C, Based on Target of 70% ILIM (BOOST)
Figure 6. Inverting Regulator Maximum Output Current, fSW = 1.2 MHz,
TA = 25°C, Based on Target of 70% ILIM (INVERTER)
900
700
V
V
V
V
= 3.3V, L1 = 3.3µH
= 3.3V, L1 = 4.7µH
= 5V, L1 = 2.2µH
= 5V, L1 = 4.7µH
IN
IN
IN
IN
V
V
V
= 3.3V, L2 = 2.2µH
= 5V, L2 = 3.3µH
= 5V, L2 = 4.7µH
IN
IN
IN
800
700
600
500
400
300
200
100
0
600
500
400
300
200
100
0
0
5
10
15
20
25
30
35
40
–35
–30
–25
–20
V
–15
(V)
–10
–5
0
V
(V)
POS
NEG
Figure 7. Inverting Regulator Maximum Output Current, fSW = 2.4 MHz,
TA = 25°C, Based on Target of 70% ILIM (INVERTER)
Figure 4. Boost Regulator Maximum Output Current, fSW = 2.4 MHz,
TA = 25°C, Based on Target of 70% ILIM (BOOST)
100
90
80
70
60
50
40
30
20
100
V
V
= 3.3V, fSW = 2.4MHz
= 3.3V, fSW = 1.2MHz
IN
IN
90
80
70
60
50
40
30
20
10
0
10
V
V
= 3.3V, fSW = 2.4MHz
= 3.3V, fSW = 1.2MHz
IN
IN
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
CURRENT LOAD (A)
CURRENT LOAD (A)
Figure 8. Inverting Regulator Efficiency vs. Current Load, VIN = +3.3 V,
VNEG = −5 V, TA = 25°C
Figure 5. Boost Regulator Efficiency vs. Current Load,
VIN = 3.3 V, VPOS = 5 V, TA = 25°C
Rev. A | Page 7 of 23
ADP5076
Data Sheet
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
V
V
V
V
= 3.3V, fSW = 1.2MHz
V
V
V
V
= 3.3V, fSW = 1.2MHz
= 3.3V, fSW = 2.4MHz
= 5V, fSW = 1.2MHz
= 5V, fSW = 2.4MHz
IN
IN
IN
IN
IN
IN
IN
IN
= 3.3V, fSW = 2.4MHz
= 5.0V, fSW = 1.2MHz
= 5.0V, fSW = 2.4MHz
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
CURRENT LOAD (A)
CURRENT LOAD (A)
Figure 9. Boost Regulator Efficiency vs. Current Load, VPOS = 9 V, TA = 25°C
Figure 12. Inverting Regulator Efficiency vs. Current Load, VNEG = −9 V,
TA = 25°C
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
V
V
V
V
= 3.3V, fSW = 1.2MHz
= 3.3V, fSW = 2.4MHz
= 5V, fSW = 1.2MHz
= 5V, fSW = 2.4MHz
20
10
0
V
V
V
V
= 3.3V, fSW = 1.2MHz
= 3.3V, fSW = 2.4MHz
= 5V, fSW = 1.2MHz
= 5V, fSW = 2.4MHz
IN
IN
IN
IN
IN
IN
IN
IN
10
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
CURRENT LOAD (A)
CURRENT LOAD (A)
Figure 10. Boost Regulator Efficiency vs. Current Load, VPOS = 15 V, TA = 25°C
Figure 13. Inverting Regulator Efficiency vs. Current Load, VNEG = −15 V,
TA = 25°C
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
V
V
V
= 3.3V, fSW = 1.2MHz
= 5V, fSW = 1.2MHz
= 5V, fSW = 2.4MHz
V
V
V
= 3.3V, fSW = 1.2MHz
= 5V, fSW = 1.2MHz
= 5V, fSW = 2.4MHz
IN
IN
IN
IN
IN
IN
10
10
0
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
CURRENT LOAD (A)
CURRENT LOAD (A)
Figure 14. Inverting Regulator Efficiency vs. Current Load, VNEG = −30 V,
TA = 25°C
Figure 11. Boost Regulator Efficiency vs. Current Load, VPOS = 35 V,
TA = 25°C
Rev. A | Page 8 of 23
Data Sheet
ADP5076
100
90
80
70
60
50
40
30
20
10
0
100
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
90
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 15. Boost Regulator Efficiency over Temperature,
VIN = 5 V, VPOS = 15 V, fSW = 1.2 MHz
Figure 18. Inverting Regulator Efficiency over Temperature,
VIN = 5 V, VNEG = −15 V, fSW = 1.2 MHz
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
V
V
V
ACCURACY
ACCURACY
ACCURACY
NEG
REF
FB2
V
V
ACCURACY
ACCURACY
POS
FB1
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
IN
V
IN
Figure 16. Boost Regulator Line Regulation, VPOS = 15 V,
fSW = 1.2 MHz, 15 mA Load, TA = 25°C
Figure 19. Inverting Regulator Line Regulation, VNEG = −15 V,
fSW = 1.2 MHz, 15 mA Load, TA = 25°C
0.5
0.5
0.4
0.3
0.2
0.1
0
1.2MHz
2.4MHz
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
1.2MHz
2.4MHz
0
0.05
0.10
0.15
0.20
0
0.05
0.10
0.15
0.20
0.25
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 17. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V
Figure 20. Inverting Regulator Load Regulation, VIN = +5 V, VNEG = −15 V
Rev. A | Page 9 of 23
ADP5076
Data Sheet
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12
BOOST REGULATOR LOAD (A)
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12
INVERTING REGULATOR LOAD (A)
Figure 24. Cross Regulation, Inverting Regulator VFB2 Regulation over Boost
Regulator Current Load, VIN = +5 V, VPOS = +15 V, VNEG = −15 V, fSW = 2.4 MHz,
TA = 25°C, Inverting Regulator Run in Continuous Conduction Mode with
Fixed Load for Test
Figure 21. Cross Regulation, Boost Regulator VFB1 Regulation over Inverting
Regulator Current Load, VIN = +5 V, VPOS = +15 V, VNEG = −15 V, fSW = 2.4 MHz,
TA = 25°C, Boost Regulator Run in Continuous Conduction Mode with Fixed
Load for Test
1.44
2.40
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
1.40
1.36
1.32
1.28
1.24
1.20
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
V
(V)
IN
IN
Figure 25. Inverting Regulator Current Limit (ILIMIT2) vs. VIN over Temperature
Figure 22. Boost Regulator Current Limit (ILIMIT1) vs. VIN over Temperature
2.54
1.27
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
1.25
1.23
1.21
1.19
1.17
1.15
1.13
2.49
2.44
2.39
2.34
2.29
2.24
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
IN
Figure 26. Oscillator Frequency vs. VIN over Temperature, SYNC Pin = Low
Figure 23. Oscillator Frequency vs. VIN over Temperature, SYNC Pin = High
Rev. A | Page 10 of 23
Data Sheet
ADP5076
3.0
2.5
2.0
1.5
1.0
0.5
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
2.7
3.2
3.7
4.2
(V)
4.7
5.2
5.7
2.7
3.2
3.7
4.2
(V)
4.7
5.2
5.7
V
IN
V
IN
Figure 30. Operating Quiescent Current vs. VIN over Temperature,
ENx Pins On
Figure 27. Standby Current vs. VIN over Temperature, ENx Pins Below
Shutdown Threshold
V
V
IN
IN
V
POS
2
1
3
V
V
NEG
2
1
V
FB2
FB1
3
CH1 1.00V
CH3 20.0mV
CH2 200mV
M2.00ms A CH1
5.772000ms
5.16V
CH2 50.0mV
CH1 1.00V
CH3 10.0mV
M1.00ms A CH1
1.906000ms
4.96V
T
T
Figure 28. Boost Regulator Line Transient, VIN = 4.5 V to 5.5 V Step, VPOS = 15 V,
Resistor Load for Boost Regulator (RLOAD1) = 300 Ω, fSW = 2.4 MHz, TA = 25°C
Figure 31. Inverting Regulator Line Transient, VIN = +4.5 V to +5.5 V Step,
VNEG = −15 V, Resistor Load for Inverting Regulator (RLOAD2) = 300 Ω,
fSW = 2.4 MHz, TA = 25°C
I
LOAD1
I
LOAD2
4
1
4
1
V
V
V
NEG
POS
V
FB2
FB1
3
3
CH1 100mV
CH3 10.0mV
M1.00ms A CH4
20.30%
48.0mA
CH1 50.0mV
CH3 10.0mV
M100µs A CH4
20.30%
140mA
CH4 20.0mA
T
CH4 50.0mA
T
Figure 32. Inverting Regulator Load Transient, VIN = +5 V Step, VNEG = −15 V,
ILOAD2 = 35 mA to 45 mA Step, fSW = 2.4 MHz, TA = 25°C
Figure 29. Boost Regulator Load Transient, VIN = 5 V Step, VPOS = 15 V,
ILOAD1 = 120 mA to 150 mA Step, fSW = 2.4 MHz, TA = 25°C
Rev. A | Page 11 of 23
ADP5076
Data Sheet
I
INDUCTOR
3
I
INDUCTOR
SW2
3
2
SW1
2
1
V
NEG
V
POS
1
B
B
CH1 50.0mV
CH2 5.00V
M4.00µs A CH3
12.00000µs
35.0mA
W
W
CH1 500mV
CH2 10.0V
M2.00µs A CH3
7.960000µs
82.0mA
B
CH3 50.0mA
T
W
CH3 100mA
T
Figure 33. Boost Regulator Skip Mode Operation Showing Inductor Current
(IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VPOS = 15 V,
ILOAD1 = 4 mA, fSW = 2.4 MHz, TA = 25°C
Figure 36. Inverting Regulator Skip Mode Operation Showing IINDUCTOR, Switch
Node Voltage, and Output Ripple, VIN = +5 V,
VNEG = −5 V, ILOAD2 = 0 mA, fSW = 2.4 MHz, TA = 25°C
I
I
INDUCTOR
INDUCTOR
3
3
SW1
SW2
2
2
V
V
NEG
POS
1
1
CH1 500mV
CH2 5.00V
M200ns A CH3
24.46000µs
42.0mA
CH1 500mV
CH2 10.0V
M200ns A CH3
7.960000µs
100mA
CH3 50mA
CH3 200mA
T
T
Figure 34. Boost Regulator Discontinuous Conduction Mode Operation
Showing IINDUCTOR, Switch Node Voltage, and Output Ripple, VIN = 5 V,
VPOS = 15 V, ILOAD1 = 6 mA, fSW = 2.4 MHz, TA = 25°C
Figure 37. Inverting Regulator Discontinuous Conduction Mode Operation
Showing IINDUCTOR, Switch Node Voltage, and Output Ripple, VIN = +5 V,
VNEG = −5 V, ILOAD2 = 6 mA, fSW = 2.4 MHz, TA = 25°C
I
INDUCTOR
I
INDUCTOR
3
3
SW1
SW2
2
1
2
1
V
V
NEG
POS
B
B
CH1 50.0mV
CH2 5.00V
M100ns A CH3
24.46000µs
84.0mA
CH1 500mV
CH2 10.0V
M200ns A CH4
7.960000µs
310mA
W
W
B
CH3 50mA
T
CH3 500mA
W
T
Figure 35. Boost Regulator Continuous Conduction Mode Operation
Showing IINDUCTOR, Switch Node Voltage, and Output Ripple, VIN = 5 V,
VPOS = 15 V, ILOAD1 = 90 mA, fSW = 2.4 MHz, TA = 25°C
Figure 38. Inverting Regulator Continuous Conduction Mode Operation
Showing IINDUCTOR, Switch Node Voltage, and Output Ripple, VIN = +5 V,
VNEG = −5 V, ILOAD2 = 35 mA, fSW = 2.4 MHz, TA = 25°C
Rev. A | Page 12 of 23
Data Sheet
ADP5076
THEORY OF OPERATION
V
IN
C
IN
SYNC
AVIN
PVIN
CURRENT SENSE
L1
INVERTER
PWM CONTROL
D1
V
POS
SW1
SLEW
D2
V
SW2
L2
NEG
C
OUT1
SLEW
BOOST PWM
CONTROL
R
FT1
REFERENCES
C
OUT2
PGND
FB1
CURRENT
SENSE
PLL
R
ERROR
AMP
FT2
REF2
ERROR
+
–
+
AMP
OSCILLATOR
FB2
–
R
REF1
FB1
COMP1
BOOST_ENABLE
SEQUENCE
CONTROL
R
FB2
R
INVERTER_ENABLE
C1
VREF
REF_1V6
THERMAL
SHUTDOWN
C
VREF
COMP2
C
C1
4µA
UVLO
SLEW
TRI-STATE
BUFFER
REF1
REF2
1.5MΩ
1.5MΩ
START-UP
TIMERS
REFERENCE
GENERATOR
R
C2
FB1
OVP
FB2
REF_1V6
C
C2
SS
SLEW
EN1
EN2 SEQ
R
(OPTIONAL)
SS
AGND
Figure 39. Typical Application Circuit
PULSE WIDTH MODULATION (PWM) MODE
OSCILLATOR AND SYNCHRONIZATION
In PWM mode, the boost and inverting regulators in the
ADP5076 operate at a fixed frequency set by an internal
oscillator. At the start of each oscillator cycle, the MOSFET
switch turns on, applying a positive voltage across the inductor.
The inductor current increases until the current sense signal
crosses the peak inductor current threshold that turns off the
MOSFET switch. This threshold is set by the error amplifier
output. During the MOSFET off time, the inductor current
declines through the external diode until the next oscillator
clock pulse starts a new cycle. The ADP5076 regulates the output
voltage by adjusting the peak inductor current threshold.
The ADP5076 initiates the drive of the boost regulator SW1 pin
and the inverting regulator SW2 pin 180° out of phase to reduce
peak current consumption and noise.
A phase-locked loop (PLL)-based oscillator generates the
internal clock and offers a choice of two internally generated
frequency options or external clock synchronization. The
switching frequency is configured using the SYNC pin options
shown in Table 6.
For external synchronization, connect the SYNC pin to a
suitable clock source. The PLL locks to an input clock within
the range specified by fSYNC
.
PULSE SKIP MODULATION MODE
Table 6. SYNC Pin Options
In pulse skip modulation operation during light load, the
regulators can skip pulses to maintain output voltage regulation.
Skipping pulses increases the device efficiency.
SYNC Pin
High
Switching Frequency
2.4 MHz
Low
1.2 MHz
UVLO
External Clock
1 × clock frequency
The undervoltage lockout circuitry monitors the AVIN pin
voltage level. If the input voltage drops below the VUVLO_FALLING
threshold, both regulators turn off. After the AVIN pin voltage
rises above the VUVLO_RISING threshold, the soft start period initiates,
and the regulators are enabled.
INTERNAL REGULATOR
The VREF regulator provides a reference voltage for the inverting
regulator feedback network to ensure a positive feedback voltage on
the FB2 pin.
A current-limit circuit is included for the VREF regulator to protect
the circuit from accidental loading.
Rev. A | Page 13 of 23
ADP5076
Data Sheet
short-circuit condition, the regulator enters hiccup mode. The
regulator stops switching and then restarts with a new soft start
cycle after tHICCUP and repeats until the overcurrent condition is
removed.
PRECISION ENABLING
The ADP5076 has an individual enable pin for the boost
regulator (EN1) and inverting regulator (EN2). These enable
pins feature a precision enable circuit with an accurate reference
voltage. This reference allows the ADP5076 to be sequenced
easily from other supplies. It can also be used as a programmable
UVLO input by using a resistor divider.
OVERVOLTAGE PROTECTION
An overvoltage protection mechanism is present on the FB1
and FB2 pins for the boost and inverting regulators.
The enable pins have an internal pull-down resistor that defaults
each regulator to off when the pin is floating.
On the boost regulator, when the voltage on the FB1 pin exceeds
the VOV1 threshold, the switching on SW1 stops until the voltage
falls below the threshold again. This functionality is permanently
enabled on this regulator.
When the voltage of the enable pins is greater than the VTH_H
reference level, the regulator is enabled.
On the inverting regulator, when the voltage on the FB2 pin
drops below the VOV2 threshold, the switching stops until the
voltage rises above the threshold. This functionality is enabled
after the soft start period has elapsed.
SOFT START
Each regulator in the ADP5076 includes soft start circuitry that
ramps the output voltage in a controlled manner during startup,
limiting the inrush current. The soft start time is internally set to
the fastest rate when the SS pin is open.
THERMAL SHUTDOWN
Connecting a resistor between the SS pin and the AGND pin
allows the adjustment of the soft start delay. The delay length is
common to both regulators.
In the event that the ADP5076 junction temperature rises above
TSHDN, the thermal shutdown circuit turns off the integrated
circuit (IC). Extreme junction temperatures can be the result of
prolonged high current operation, poor circuit board design,
and/or high ambient temperature. Hysteresis is included so that
when thermal shutdown occurs, the ADP5076 does not return to
SLEW RATE CONTROL
The ADP5076 employs programmable output driver slew rate
control circuitry. This circuitry reduces the slew rate of the
switching node as shown in Figure 40, resulting in reduced
ringing and lower EMI. To program the slew rate, connect the
SLEW pin to the AVIN pin for normal mode, to the AGND pin
for slow mode, or leave it open for fast mode. This configuration
allows the use of an open-drain output from a noise sensitive
device to switch the slew rate from fast to slow, for example,
during ADC sampling.
operation until the on-chip temperature drops below TSHDN − THYS
When resuming from thermal shutdown, a soft start is performed
on each enabled channel.
.
STARTUP SEQUENCE
The ADP5076 implements a flexible startup sequence to meet
different system requirements. Three different enabling modes
can be implemented via the SEQ pin, as explained in Table 7.
Slew rate control causes a trade-off between efficiency and low
EMI.
Table 7. SEQ Pin Settings
SEQ Pin
Open
AVIN
Description
Manual enable mode
Simultaneous enable mode
Sequential enable mode
Low
FASTEST
To configure the manual enable mode, leave the SEQ pin open.
The boost and inverting regulators are controlled separately from
their respective precision enable pins.
SLOWEST
To configure the simultaneous enable mode, connect the SEQ pin
to the AVIN pin. Both regulators power up simultaneously
when the EN2 pin is taken high. The EN1 pin enable can be
used to enable the internal references ahead of enabling the
outputs, if desired. The simultaneous enable mode timing is
shown in Figure 41.
Figure 40. Switching Node at Various Slew Rate Settings
CURRENT-LIMIT PROTECTION
The boost and inverting regulators in the ADP5076 include
current-limit protection circuitry to limit the amount of forward
current through the MOSFET switch.
When the peak inductor current exceeds the overcurrent limit
threshold for a number of clock cycles during an overload or
Rev. A | Page 14 of 23
Data Sheet
ADP5076
V
V
POS
POS
V
V
IN
IN
TIME
TIME
V
V
V
NEG
NEG
1. V
FOLLOWED BY V
NEG
SIMULTANEOUS ENABLE MODE
(SEQ = HIGH, EN2 = HIGH)
POS
(SEQ = LOW, EN1 = HIGH, EN2 = LOW)
Figure 41. Simultaneous Enable Mode
POS
To configure the sequential enable mode, pull the SEQ pin low.
In this mode, either VPOS or VNEG can be enabled first by using
the respective EN1 pin or EN2 pin. Keep the other pin low. The
secondary supply is enabled when the primary supply completes
soft start and its feedback voltage reaches approximately 85% of
the target value. The sequential enable mode timing is shown in
Figure 42.
V
IN
TIME
V
NEG
2. V
FOLLOWED BY V
POS
NEG
(SEQ = LOW, EN2 = HIGH, EN1 = LOW)
Figure 42. Sequential Enable Mode
Rev. A | Page 15 of 23
ADP5076
Data Sheet
APPLICATIONS INFORMATION
COMPONENT SELECTION
Feedback Resistors
V
R
R
FB1 is the FB1 reference voltage.
FT1 is the feedback resistor from VPOS to FB1.
FB1 is the feedback resistor from FB1 to AGND.
The ADP5076 provides an adjustable output voltage for both boost
and inverting regulators. An external resistor divider sets the
output voltage where the divider output must equal the
appropriate feedback reference voltage, VFB1 or VFB2. To limit the
output voltage accuracy degradation due to feedback bias current,
ensure that the current through the divider is at least 10 × IFB1 or
Set the negative output for the inverting regulator by
RFT2
VNEG VFB2
where:
V
V
V
VFB2
REF
RFB2
NEG is the negative output voltage.
FB2 is the FB2 reference voltage.
10 × IFB2
.
Set the positive output for the boost regulator by
R
R
FT2 is the feedback resistor from VNEG to FB2.
FB2 is the feedback resistor from FB2 to VREF.
RFT1
VPOS VFB1 1
V
REF is the VREF pin reference voltage.
RFB1
where:
POS is the positive output voltage.
Table 8. Recommended Feedback Resistor Values for Boost Regulator
V
Boost Regulator
Desired Output Voltage (V)
RFT1 (MΩ)
0.432
0.604
1.24
RFB1 (kΩ)
102
115
Calculated Output Voltage (V)
+4.2
+5
+9
4.188
5.002
8.998
121
+12
+13
+15
+18
+20
+24
+30
1.4
2.1
2.43
2.15
2.55
3.09
3.65
100
137
137
100
107
107
100
12.000
13.063
14.990
18.000
19.865
23.903
30.000
Table 9. Recommended Feedback Resistor Values for Inverting Regulator
Inverting Regulator
Desired Output Voltage (V)
RFT2 (MΩ)
0.332
0.475
0.523
0.715
1.15
1.62
1.15
2.8
2.32
RFB2 (kΩ)
102
100
102
115
158
133
71.5
162
118
Calculated Output Voltage (V)
−1.8
−3
−3.3
−4.2
−5
−1.804
−3.000
−3.302
−4.174
−5.023
−8.944
−12.067
−13.027
−14.929
−18.103
−20.014
−23.984
−30.004
−9
−12
−13
−15
−18
−20
−24
−30
2.67
2.94
3.16
4.12
113
113
102
107
Rev. A | Page 16 of 23
Data Sheet
ADP5076
Soft Start Resistor
OUTPUT CAPACITORS
A resistor can be connected between the SS pin and the AGND pin
to increase the soft start time. The soft start time can be set by the
resistor between 4 ms (268 kΩ) and 32 ms (50 kΩ). Leaving the
SS pin open selects the fastest time of 4 ms. Figure 43 shows the
behavior of this operation. Calculate the soft start time using the
following formula:
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
the output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure the
minimum capacitance over the necessary temperature range and
dc bias conditions. X5R or X7R dielectrics with a voltage rating of
25 V or 50 V (depending on output) are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any dc-to-dc converter because of their poor
temperature and dc bias characteristics.
t
SS = 38.4 × 10−3 − 1.28 × 10−7 × RSS (ꢀ)
where 50 kꢀ ≤ RSS ≤ 268 kꢀ.
SOFT START
TIMER
32ms
Calculate the worst-case capacitance accounting for capacitor
variation over temperature, component tolerance, and voltage
using the following equation:
4ms
SS PIN OPEN
R1
SOFT START
RESISTOR
C
EFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×
(1 − Tolerance)
where:
R2
Figure 43. Soft Start Behavior
Diodes
C
C
EFFECTIVE is the effective capacitance at the operating voltage.
NOMINAL is the nominal data sheet capacitance.
Use a Schottky diode with low junction capacitance for diode 1
(D1) and diode 2 (D2). At higher output voltages and especially at
higher switching frequencies, the junction capacitance is a
significant contributor to efficiency. Higher capacitance diodes
also generate more switching noise. As a guide, a diode with less
than 40 pF junction capacitance is preferred when the output
voltage is above 5 V.
TEMPCO is the worst-case capacitor temperature coefficient.
DCBIASCO is the dc bias derating at the output voltage.
Tolerance is the worst-case component tolerance.
To guarantee the performance of the device, it is imperative that
the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Inductor Selection for the Boost Regulator
Capacitors with lower effective series resistance (ESR) and
effective series inductance (ESL) are preferred to minimize
output voltage ripple.
The inductor stores energy during the on time of the power
switch and transfers that energy to the output through the
output rectifier during the off time. To balance the tradeoffs
between small inductor current ripple and efficiency, inductance
values in the range of 1 μH to 22 μH are recommended. In general,
lower inductance values have higher saturation current and
lower series resistance for a given physical size. However, lower
inductance results in a higher peak current that can lead to reduced
efficiency and greater input and/or output ripple and noise. A
peak-to-peak inductor ripple current that is close to 30% of the
maximum dc input current for the application typically yields
an optimal compromise.
The use of large output capacitors can require a slower soft start
to prevent current limit during startup. A 10 μF capacitor is
suggested as a good balance between performance and size.
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response.
To minimize supply noise, place the input capacitor as close as
possible to the AVIN pin and the PVIN pin. A low ESR capacitor
is recommended.
For the inductor ripple current in continuous conduction mode
(CCM) operation, the VIN and output voltage (VPOS) determine
the switch duty cycle (DUTY1) using the following equation:
The effective capacitance needed for stability is a minimum of 10 μF.
If the power pins are individually decoupled, it is recommended
to use an effective minimum of a 5.6 μF capacitor on the PVIN pin
and a 3.3 μF capacitor on the AVIN pin. The minimum values
specified exclude dc bias, temperature, and tolerance effects that
are application dependent and must be taken into
consideration.
DIODE1
VPOS VIN V
DUTY
1
V
POS VDIODE1
where VDIODE1 is the forward voltage drop of D1.
VREF Capacitor
A 1.0 μF ceramic capacitor (CVREF) is required between the
VREF pin and the AGND pin.
Rev. A | Page 17 of 23
ADP5076
Data Sheet
The dc input current in CCM (IIN) can be determined using the
following equation:
For the inductor ripple current in CCM operation, the VIN and
output voltage (VNEG) determine the switch duty cycle (DUTY2)
using the following equation:
IOUT1
IIN
(1 DUTY1)
|VNEG | VDIODE2
VIN |VNEG | V
DUTY
2
DIODE2
Using the DUTY1 and fSW, determine the on time (tON1) using
the following equation:
where VDIODE2 is the forward voltage drop of D2.
DUTY1
The dc current in the inductor in CCM (IL2) can be determined
using the following equation:
tON1
fSW
The inductor ripple current (IL1) in steady state is calculated
using the following equation:
IOUT2
IL2
(1 DUTY2)
VIN tON1
Using the DUTY2 and fSW, determine the on time (tON2) using
the following equation:
IL1
L1
Solve for the inductor (L1) using the following equation:
DUTY2
tON2
VIN tON1
L1
fSW
IL1
The inductor ripple current (IL2) in steady state is calculated
using the following equation:
Assuming an inductor ripple current of 30% of the maximum
dc input current, solve for L1 using the following equation:
VIN tON2
IL2
VIN tON1 (1 DUTY1)
L1
L2
0.3 IOUT1
Solve for the inductor (L2) using the following equation:
Ensure that the peak inductor current (the maximum input
current plus half the inductor ripple current) is below the rated
saturation current of the inductor. Likewise, ensure that the
maximum rated rms current of the inductor is greater than the
maximum dc input current to the regulator.
VIN tON2
L2
IL2
Assuming an inductor ripple current of 30% of the maximum
dc current in the inductor, solve for L2 using the following
equation:
When the ADP5076 boost regulator is operated in CCM at duty
cycles greater than 50%, slope compensation is required to stabilize
the current mode loop. This slope compensation is built in to
the ADP5076. For stable current mode operation, ensure that
the selected inductance is equal to or greater than the minimum
calculated inductance (LMIN1) for the application parameters in
the following equation:
VIN tON2 (1 DUTY2)
L2
0.3 IOUT2
Ensure that the peak inductor current (the maximum input current
plus half the inductor ripple current) is below the rated saturation
current of the inductor. Likewise, ensure that the maximum rated
rms current of the inductor is greater than the maximum dc
input current to the regulator.
0.13
L1 LMIN1 VIN
0.16 µH
(1 DUTY1)
When the ADP5076 inverting regulator is operated in CCM at
duty cycles greater than 50%, slope compensation is required to
stabilize the current mode loop. For stable current mode operation,
ensure that the selected inductance is equal to or greater than
the minimum calculated inductance (LMIN2) for the application
parameters in the following equation:
Table 11 suggests a series of inductors to use with the ADP5076
boost regulator.
Inductor Selection for the Inverting Regulator
The inductor stores energy during the on time of the power
switch and transfers that energy to the output through the
output rectifier during the off time. To balance the tradeoffs
between small inductor current ripple and efficiency, inductance
values in the range of 1 μH to 22 μH are recommended. In
general, lower inductance values have higher saturation current
and lower series resistance for a given physical size. However,
lower inductance results in a higher peak current that can lead
to reduced efficiency and greater input and/or output ripple and
noise. A peak-to-peak inductor ripple current that is close to
30% of the maximum dc current in the inductor typically yields
an optimal compromise.
0.13
L2 LMIN2 VIN
0.16 µH
(1 DUTY2)
Table 12 suggests a series of inductors to use with the ADP5076
inverting regulator.
LOOP COMPENSATION
The ADP5076 uses external components to compensate the
regulator loop, allowing the optimization of the loop dynamics
for a given application.
Rev. A | Page 18 of 23
Data Sheet
ADP5076
Using typical values for VFB1 and GM1 (see the Specifications
section) results in
Boost Regulator
The boost converter produces an undesirable right half plane
zero in the regulation feedback loop. This feedback loop requires
compensating the regulator so that the crossover frequency is
less than the frequency of the right half plane zero. The right
half plane zero frequency is determined by the following
equation:
2
2094 fC1 COUT1 (VPOS
)
RC1
VIN
For better accuracy, it is recommended to use the COUT1 value
expected under the dc bias conditions that the COUT1 value
operates under in the calculation for RC1.
R
LOAD1(1 DUTY1)2
2 L1
fZ1(RHP)
After the compensation resistor is known, set the zero formed
by the compensation capacitor and resistor to one-fourth of the
crossover frequency, or
where:
fZ1(RHP) is the right half plane zero frequency.
LOAD1 is the equivalent resistor load for boost regulator, which
2
R
CC1
π fC1 RC1
is also equal to the output voltage divided by the load current.
where CC1 is the compensation capacitor value.
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
ERROR
AMPLIFIER
FB1
COMP1
g
M1
The boost regulator loop gain is
REF1
R
C1
VFB1 VIN
AVL1
GM1 ROUT1 ||Z COMP1 GCS1 ZOUT1
C
C1
VPOS VPOS
where:
Figure 44. Compensation Components
A
V
V
V
G
VL1 is the loop gain.
Inverting Regulator
FB1 is the feedback regulation voltage.
POS is the regulated positive output voltage.
IN is the input voltage.
The inverting converter, like the boost converter, produces an
undesirable right half plane zero in the regulation feedback loop.
This feedback loop requires compensating the regulator so that
the crossover frequency is less than the frequency of the right half
plane zero. The right half plane zero frequency is determined by
the following equation:
M1 is the error amplifier transconductance gain.
R
OUT1 is the output impedance of the error amplifier and is 33 Mꢀ.
Z
COMP1 is the impedance of the series RC network from the
COMP1 pin to the AGND pin.
CS1 is the current sense transconductance gain (the inductor
G
RLOAD2 (1 DUTY2)2
2π L2 DUTY2
fZ2(RHP)
current divided by the voltage at the COMP1 pin), which is
internally set by the ADP5076 and is 12.5 A/V.
where:
Z
OUT1 is the impedance of the load in parallel with the output
capacitor.
fZ2(RHP) is the right half plane zero frequency.
R
LOAD2 is the equivalent resistor load for inverting regulator,
At crossover frequency (fC1), the ZCOMP1 is dominated by a resistor
(RC1), and the ZOUT1 is dominated by the impedance of an output
capacitor (COUT1). Therefore, when solving for the fC1, the equation
(by definition of the crossover frequency) is simplified to
which is also equal to the output voltage divided by the load
current.
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
VFB1 VIN
VPOS VPOS
AVL1
GM1 RC1 GCS1
The inverting regulator loop gain is
1
1
VFB2
VIN
2π fC1 COUT1
A
GM2
VL2
|VNEG
|
(VIN 2 |VNEG|)
To solve for RC1, use the following equation:
ROUT2 ||ZCOMP2 GCS2 ZOUT2
2
2 fC1 COUT1 (VPOS
)
RC1
where:
VFB1 VIN GM1 GCS1
A
V
V
V
G
VL2 is the loop gain.
FB2 is the FB2 reference voltage.
NEG is the regulated negative output voltage.
IN is the input voltage.
M2 is the error amplifier transconductance gain.
OUT2 is the output impedance of the error amplifier and is 33 Mꢀ.
where GCS1 = 12.5 A/V.
R
Rev. A | Page 19 of 23
ADP5076
Data Sheet
Z
COMP2 is the impedance of the series RC network from the
COMP2 pin to the AGND pin.
CS2 is the current sense transconductance gain (the inductor
COMMON APPLICATIONS
Table 10, Table 11, and Table 12 list a number of common
component selections for typical VIN and VOUT conditions.
These have been bench tested and provide an off the shelf solution.
When pairing a boost and inverting regulator bill of materials,
G
current divided by the voltage at COMP2), which is internally
set by the ADP5076 and is 12.5 A/V.
Z
OUT2 is the impedance of the load in parallel with the output
choose the same VIN and fSW
.
capacitor.
V
IN
+5V
At crossover frequency (fC2), the ZCOMP2 is dominated by a
resistor (RC2), and the ZOUT2 is dominated by the impedance of the
output capacitor (COUT2). Therefore, when solving for the fC2, the
equation (by definition of the crossover frequency) is simplified to
ADP5076
R
SS
C1
L1
3.3µH
102kΩ
V
D1
POS
COMP1
EN1
PD3S140
+15V
C
1nF
C1
SW1
SW1
FB1
R
FT1
2.43MΩ
VFB2
VIN
C
OUT1
A
GM2
VL2
10µF
R
FB1
|VNEG | (VIN 2|VNEG |)
137kΩ
PVIN
PVIN
AVIN
V
+5V
IN
1
PGND
PGND
VREF
C
C
IN
10µF
RC2 GCS 2
1
VREF
1µF
2π fC2 COUT2
To solve for RC2, use the following equation:
EN2
R
FB2
C
R
OUT2
C2
61.9kΩ
118kΩ
10µF
FB2
COMP2
R
FT2
2.32MΩ
2π fC2 COUT2 |VNEG |(VIN (2 |VNEG |)
VFB2 VIN GM2 GCS2
V
C
IN
C2
2.2nF
SYNC
SLEW
SEQ
RC2
+5V
SW2
V
NEG
D2
PD3S140
L2
6.8µF
–15V
AGND
where GCS2 = 12.5 A/V.
Using typical values for VFB2 and GM2 results in
Figure 46. Typical +5 V to 15 V Application
2094 fC2 COUT2 |VNEG | (VIN (2 |VNEG |)
Figure 46 shows the schematic referenced by Table 10, Table 11,
and Table 12 with example component values for +5 V to 15 V
generation. Table 10 shows the components common to all of
the VIN and VOUT conditions.
RC2
VIN
See the Specifications section for the typical values for VFB2 and
M2. The typical value for VFB2 can be obtained by subtracting
(VREF − VFB2) from VREF
G
.
Table 10. Recommended Common Components Selections
For better accuracy, it is recommended to use the COUT2 value
expected under the dc bias conditions that the COUT2 value
operates under in the calculation for RC2.
Reference
Value Part Number
Manufacturer
Input
10 μF GRM21BZ71C106KE15L Murata
Capacitor
CVREF
1 ꢀF
GRM188R71C105KA12C Murata
After the compensation resistor is known, set the zero formed
by the CC2 and RC2 to one-fourth of the crossover frequency, or
Figure 47 shows the efficiency curves for the boost and inverting
regulator using the recommended small-sized components in
Table 10, Table 11, and Table 12 for VPOS = +15 V and VNEG
2
CC2
=
π fC2 RC2
−15 V at VIN = +5 V.
where CC2 is the compensation capacitor.
100
V
V
V
V
= +15V, 2.4MHz
= +15V, 1.2MHz
= –15V, 1.2MHz
= –15V, 2.4MHz
POS
POS
NEG
NEG
ERROR
90
80
70
60
50
40
30
20
10
0
AMPLIFIER
FB2
COMP2
g
M2
REF2
R
C2
C
C2
Figure 45. Compensation Component
0.001
0.01
0.1
1
LOAD CURRENT (A)
Figure 47. Boost Regulator and Inverting Regulator Efficiency vs. Current
Load, TA = 25°C
Rev. A | Page 20 of 23
Data Sheet
ADP5076
Table 11 and Table 12 are based on the smallest sized
It is important to verify the thermal performance of the small
sized inductor at higher ambient temperatures in the actual
application.
components. The maximum output current is limited by the
saturation current (ISAT) rating of the 2 mm × 2 mm inductor. A
higher output current is possible by using larger inductors with
higher ISAT ratings, as long as the inductor peak current remains
below the appropriate current limit specifications.
Table 11. Recommended Boost Regulator Small Sized Components
VIN
(V)
VPOS
(V)
ILOAD1 (MAX) Frequency
L1
(μH)
L1 Manufacturer Part
No. (Coilcraft)
RFT1
(MΩ)
RFB1
(kΩ)
CC1
(nF)
RC1
(kΩ)
(mA)
370
500
170
270
90
(MHz)
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
COUT1, Murata Part No.1
GRM21BR71A106KA73L
GRM21BR71A106KA73L
GRM21BZ71C106KE15L
GRM21BZ71C106KE15L
GRM31CR71E106MA12L
GRM31CR71E106MA12L
GRM32ER7YA106MA12L
GRM32ER7YA106MA12L
GRM21BZ71C106KE15L
GRM21BZ71C106KE15L
GRM31CR71E106MA12L
GRM31CR71E106MA12L
GRM32ER7YA106MA12L
GRM32ER7YA106MA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
D1
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5
5
2.2
1
EPL2014-222ML_
EPL2014-102ML_
EPL2014-222ML_
EPL2014-152ML_
EPL2014-332ML_
EPL2014-152ML_
EPL2014-332ML_
EPL2014-332ML_
EPL2014-332ML_
EPL2014-152ML_
EPL2014-332ML_
EPL2014-222ML_
EPL2014-472ML_
EPL2014-332ML_
EPL2014-472ML_
EPL2014-472ML_
PMEG2005AELD 0.604
PMEG2005AELD 0.604
PMEG2005AELD 1.24
PMEG2005AELD 1.24
115
115
121
121
137
137
107
107
121
121
137
137
107
107
102
102
0.47
0.39
0.82
0.68
2.2
21
5
22.1
16.5
6.81
12.1
9.53
28
9
2.2
1.5
3.3
1.5
3.3
3.3
3.3
1.5
3.3
2.2
4.7
3.3
4.7
4.7
9
15
15
24
24
9
PD3S140
PD3S140
PD3S140
PD3S140
2.43
2.43
3.09
3.09
150
50
1.2
1.8
70
1.8
12.7
15.8
13.3
16.2
11.5
19.1
12.4
118
13.3
230
390
100
180
50
PMEG2005AELD 1.24
PMEG2005AELD 1.24
0.56
0.47
1
5
9
5
15
15
24
24
34
34
PD3S140
PD3S140
PD3S140
PD3S140
PD3S140
PD3S140
2.43
2.43
3.09
3.09
4.22
4.22
5
0.82
1.5
5
5
100
30
1.2
5
0.56
1.5
5
60
1 COUT1 = 10 ꢀF
Table 12. Recommended Inverting Regulator Small Sized Components
VIN
(V)
VNEG
(V)
ILOAD2 (MAX) Frequency
L2
(μH)
L2 Manufacturer Part
No. (Coilcraft)
RFT2
(MΩ)
RFB2
(kΩ)
CC2
(nF)
RC2
(kΩ)
(mA)
190
230
100
150
60
(MHz)
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
C
OUT2, Murata Part No.1
D2
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5
−5
3.3
2.2
4.7
2.2
4.7
2.2
4.7
3.3
6.8
3.3
6.8
3.3
10
EPL2014-332ML_
EPL2014-222ML_
EPL2014-472ML_
EPL2014-222ML_
EPL2014-472ML_
EPL2014-222ML_
EPL2014-472ML_
EPL2014-332ML_
EPL2014-682ML_
EPL2014-332ML_
EPL2014-682ML_
EPL2014-332ML_
EPL2014-103ML_
EPL2014-472ML_
EPL2014-103ML_
EPL2014-472ML_
GRM21BR71A106KA73L
GRM21BR71A106KA73L
GRM21BZ71C106KE15L
GRM21BZ71C106KE15L
GRM31CR71E106MA12L
GRM31CR71E106MA12L
GRM32ER7YA106MA12L
GRM32ER7YA106MA12L
GRM21BZ71C106KE15L
GRM21BZ71C106KE15L
GRM31CR71E106MA12L
GRM31CR71E106MA12L
GRM32ER7YA106MA12L
GRM32ER7YA106MA12L
GRM32ER71H106KA12L
GRM32ER71H106KA12L
PMEG2005AELD 1.15
PMEG2005AELD 1.15
PMEG2005AELD 1.62
PMEG2005AELD 1.62
158
158
133
133
118
118
102
102
133
133
118
118
102
102
75
5.6
2.2
4.7
2.7
4.7
2.2
6.8
2.7
12
6.65
8.66
6.81
6.04
6.04
7.15
9.09
10
−5
−9
−9
−15
−15
−24
−24
−9
PD3S140
PD3S140
PD3S140
PD3S140
2.32
2.32
3.16
3.16
100
40
60
120
190
70
PMEG2005AELD 1.62
PMEG2005AELD 1.62
6.81
4.64
6.81
5.36
10
5
−9
2.2
2.7
2.2
4.7
4.7
3.9
2.2
5
−15
−15
−24
−24
−30
−30
PD3S140
PD3S140
PD3S140
PD3S140
PD3S140
PD3S140
2.32
2.32
3.16
3.16
4.99
4.99
5
120
40
5
5
70
4.7
10
5.74
15.8
8.87
5
30
5
50
4.7
75
1 COUT2 = 10 ꢀF
Rev. A | Page 21 of 23
ADP5076
Data Sheet
Place the tops of the upper feedback resistors (RFT1 and RFT2) or
route traces to them from as close as possible to the tops of
LAYOUT CONSIDERATIONS
Layout is important for all switching regulators but is particularly
important for regulators with high switching frequencies. To
achieve high efficiency, good regulation, good stability, and low
noise, a well-designed PCB layout is required. Follow these
guidelines when designing PCBs:
COUT1 and COUT2 for optimum output voltage sensing.
Place the compensation components (RC1, CC1, RC2, and
CC2) as close as possible to the COMP1 and COMP2 pins.
Do not share vias to the ground plane with the feedback
resistors to avoid coupling high frequency noise into the
sensitive COMP1 and COMP2 pins.
Keep the input bypass capacitor (CIN) near to the PVIN pin
and the AVIN pin.
Place the CVREF capacitor as close to the VREF pin as
possible. Ensure that short traces are used between the
Keep the high current paths as short as possible. These
paths include the connections between CIN, L1, D1, COUT1
and the PGND pin for the boost regulator, and L2, D2,
VREF pin and RFB2
.
R
FT1
R
COUT2, and the PGND pin for the inverting regulator and
V
FB1
POS
their connections to the ADP5076.
R
C1
Keep the AGND pin and the PGND pin separate on the
top layer of the board. This separation avoids pollution of
the AGND pin with switching noise. Connect both the
AGND and PGND pins to the board ground plane with
vias. Ideally, connect the PGND pin to the plane at a point
between the input and output capacitors.
Keep high current traces as short and wide as possible to
minimize parasitic series inductance, which causes spiking
and EMI.
Avoid routing high impedance traces near any node
connected to the SW1 and SW2 pins or near inductors L1
and L2 to prevent radiated switching noise injection.
Place the feedback resistors (RFT1, RFB1, RFT2, and RFB2) as close
as possible to the FB1 and FB2 pins to prevent high frequency
switching noise injection.
C
OUT1
C
C1
C
VREF
R
FB2
FT2
R
V
NEG
C
IN
C
R
C2 C2
C
OUT2
V
NEG
Figure 48. Suggested Layout for VIN = +3.3 V, VPOS = +15 V, ILOAD1 = 90 mA and
VNEG = −15 V, ILOAD2 = 60 mA, Not to Scale
Rev. A | Page 22 of 23
Data Sheet
ADP5076
OUTLINE DIMENSIONS
1.650
1.610
1.570
0.310
0.290
0.270
4
3
2
1
A
B
BALL A1
IDENTIFIER
2.220
2.180
2.140
1.60 REF
C
D
E
0.40
BSC
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
0.225
1.20 REF
0.205
0.185
0.330
0.300
0.270
0.560
0.500
0.440
SIDE VIEW
COPLANARITY
0.04
0.300
0.260
0.220
SEATING
PLANE
0.230
0.200
0.170
Figure 49. 20-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-20-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CB-20-14
ADP5076ACBZ-R7
ADP5076CB-EVALZ
−40°C to +125°C
20-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D20402-0-12/19(A)
Rev. A | Page 23 of 23
相关型号：
ADP5076ACBZ-R7
2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs
ADI
ADP5076CB-EVALZ
2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs
ADI
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