ADP5304 [ADI]
Ultralow Power Step-Down Regulator for Energy Harvesting;
| 型号： | ADP5304 |
| 厂家： | 
ADI |
| 描述： | Ultralow Power Step-Down Regulator for Energy Harvesting |
| 文件： | 总17页 (文件大小：556K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Power Step-Down Regulator
for Energy Harvesting
ADP5304
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
2.2µH
V
= 2.15V TO 6.5V
V
OUT
Input supply voltage range: 2.15 V to 6.50 V
Operation down to 2.00 V typical
IN
PVIN
SW
10µF
ADP5304
10µF
Ultralow, 260 nA typical quiescent current with no load
Selective output voltage from 1.2 V to 3.6 V (or 0.8 V to 5.0 V)
2.5ꢀ output accuracy over the full temperature range
Output current up to 50 mA in hysteresis mode
VINOK flag to monitor the input voltage
ON
EN
PGND
OFF
MODE
FB
NC
VINOK
VID0: 1.2V VID8: 2.5V
VID1: 1.5V VID9: 2.6V
VID2: 1.8V VID10: 2.7V
VID3: 2.0V VID11: 2.8V
VID4: 2.1V VID12: 2.9V
VID5: 2.2V VID13: 3.0V
VID6: 2.3V VID14: 3.3V
VID7: 2.4V VID15: 3.6V
100ꢀ duty cycle operation mode
Quick output discharge (QOD) option
Undervoltage lockout (UVLO), overcurrent protection (OCP),
and thermal shutdown (TSD) protection
AGND
VID
R0
EPAD
10-lead, 3 mm × 3 mm LFCSP package
−40°C to +125°C operating junction temperature range
Figure 1.
APPLICATIONS
Energy (gas, water) metering
Energy harvesting applications
Portable and battery-powered equipment
Medical applications
Keep-alive power supply
GENERAL DESCRIPTION
The ADP5304 is a high efficient, ultralow quiescent current
step-down regulator that draws only 260 nA of quiescent
current to regulate the output at no load.
energy harvester to charge up the conventional capacitor or
super capacitor.
The ADP5304 integrates an ultralow power comparator with a
factory programmable voltage reference to monitor the voltage
of the input power source. The voltage reference, with hysteresis, is
the threshold for the stopping and the starting of the switching,
allowing the use of the high impedance power source.
The ADP5304 runs from an input voltage range of 2.15 V to
6.50 V, allowing the use of the multiple alkaline, NiMH, and
Lithium cells, or the use of a high impedance power source. The
output voltage is selectable from 0.8 V to 5.0 V by an external
VID resistor to ground. The total solution requires only four
tiny external components.
Other key features of the ADP5304 include separate enabling
and a QOD. Safety features, such as OCP, TSD, and input
UVLO are also included.
The ADP5304 operates in hysteresis mode via connecting the
MODE pin to ground. In hysteresis mode, the regulator
achieves excellent efficiency at a power of less than 1 mW and
provides up to 50 mA of output load. The device enables very
efficient power management to achieve the collection of small
amounts of energy from the high impedance battery or the
The ADP5304 is available in 10-lead, 3 mm × 3 mm LFCSP
package rated for the −40°C to +125°C junction temperature range.
Rev. 0
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ADP5304
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Current Limit.............................................................................. 12
Short-Circuit Protection............................................................ 12
Soft Start ...................................................................................... 12
Startup with Precharged Output .............................................. 12
100% Duty Operation................................................................ 12
Active Discharge......................................................................... 12
Thermal Shutdown .................................................................... 12
Applications Information.............................................................. 13
External Component Selection ................................................ 13
Selecting the Inductor................................................................ 13
Output Capacitor........................................................................ 13
Input Capacitor........................................................................... 14
Layout Recommendations ........................................................ 14
Typical Application Circuits ......................................................... 15
Factory Programmable Options................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Detailed Functional Block Diagram .............................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Buck Regulator Operational Mode .......................................... 11
Adjustable and Fixed Output Voltages .................................... 11
Undervoltage Lockout (UVLO) ............................................... 11
Enable/Disable ............................................................................ 11
VINOK Function........................................................................ 11
REVISION HISTORY
10/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 17
Data Sheet
ADP5304
DETAILED FUNCTIONAL BLOCK DIAGRAM
PVIN
SW
PVIN
DRIVER
VINOK
VINOK_TH
PVIN
NC
I
LIM_HYS
CONTROL
LOGIC
0A (HYS)
PVIN
DRIVER
VINOK
PGND
STANDBY
0.808V
0.8V
FB
INTERNAL
FEEDBACK
RESISTOR
DIVIDER
VID
1.2V
0.4V
AGND
EN
BAND GAP BIAS
AND
HOUSEKEEPING
PVIN
UVLO
2.06V
2.00V
1.2V
0.4V
2MHz
OSC
MODE
KEEP ALIVE BLOCK
Figure 2.
Rev. 0 | Page 3 of 17
ADP5304
Data Sheet
SPECIFICATIONS
VIN = 3.6 V, VOUT = 2.5 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.
Table 1.
Parameter
Symbol
VIN
Min
Typ
Max
6.50
40
Unit
V
Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE
SHUTDOWN CURRENT
2.15
ISHUTDOWN
18
18
nA
nA
VEN = 0 V, −40°C ≤ TJ ≤ +85°C
VEN = 0 V, −40°C ≤ TJ ≤ +125°C
130
QUIESCENT CURRENT
Operating Quiescent Current
IQ
260
260
640
360
500
1500
nA
nA
nA
−40°C ≤ TJ ≤ +85°C
−40°C ≤ TJ ≤ +125°C
100% duty cycle operation, VIN = 3.0 V,
VOUT set as 3.3 V
UNDERVOLTAGE LOCKOUT
UVLO
UVLO Threshold
Rising
Falling
VUVLO_RISING
VUVLO_FALLING
2.06
2.00
2.14
V
V
1.90
1.2
EN PIN
Input Voltage Threshold
High
VIH
V
Low
VIL
IEN_LEAKAGE
0.4
25
V
nA
Input Leakage Current
FB PIN
Output Options by VID Resistor
Fixed VID Code Threshold Accuracy from Active VFB_FIX
Mode to Standby Mode
VOUT_OPT
0.8
−0.75
5.0
+0.75
V
%
0.8 V to 5.0 V in different factory option
TJ = 25°C
−2.5
−3
+2.5
+3
%
%
−40°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
Adjustable VID Code Threshold Accuracy from
Active Mode to Standby Mode
Hysteresis of Threshold Accuracy from Active
Mode to Standby Mode
VFB_ADJ
VFB (HYS)
IFB
1
%
Feedback Bias Current
66
25
95
45
nA
nA
Output Option 0, VOUT = 2.5 V
Output Option 1, VOUT = 1.3 V
SW PIN
High-Side Power FET On Resistance
Low-Side Power FET On Resistance
Peak Current
RDS (ON) H
RDS (ON) L
ILIM
386
299
265
40
520
470
mΩ
mΩ
mA
ns
Pin to pin measurement
Pin to pin measurement
Minimum On Time
tMIN_ON
70
VINOK PIN
VINOK Monitor Threshold Range
VINOK Monitor Accuracy Range
VVINOK (RISE)
2.05
−1.5
−3
5.15
+1.5
+3
V
%
%
Factory programmable
TJ = 25°C
−40°C ≤ TJ ≤ +125°C
VINOK Monitor Threshold Hysteresis
VINOK Rising Delay
VINOK Falling Delay
Leakage Current for the VINOK Pin
Output Low Voltage for the VINOK Pin
SOFT START
VVINOK (HYS)
tVINOK_RISE
tVINOK_FALL
IVINOK_LEAKAGE
VVINOK_LOW
1.5
190
130
0.1
50
%
μs
μs
μA
mV
1
100
IVINOK = 100 μA
Default Soft Start Time
Start-Up Delay
tSS
350
2
μs
ms
Ω
Factory trim, 1 bit (350 μs, 2800 μs)
Delay from the EN pin being pulled high
tSTART_DELAY
RDIS
COUT DISCHARGE SWITCH ON RESISTANCE
THERMAL SHUTDOWN
Threshold
290
TSHDN
THYS
142
127
C
C
Hysteresis
Rev. 0 | Page 4 of 17
Data Sheet
ADP5304
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
PVIN to PGND
SW to PGND
FB to AGND
VID to AGND
EN to AGND
VINOK to AGND
MODE to AGND
NC to AGND
PGND to AGND
Storage Temperate Range
−0.3 V to +7 V
−0.3 V to PVIN + 0.3 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−65°C to +150°C
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
10-Lead, 3 mm × 3 mm LFCSP
57
0.86
°C/W
ESD CAUTION
Operating Junction Temperature Range −40°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 5 of 17
ADP5304
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EN 1
10 PVIN
NC 2
9
8
7
6
SW
ADP5304
MODE 3
VID 4
PGND
AGND
VINOK
TOP VIEW
(Not to Scale)
FB 5
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LARGE
EXTERNAL COPPER GROUND PLANE UNDERNEATH THE
IC FOR THERMAL DISSIPATION.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
EN
NC
MODE
VID
Enable Input for the Regulator. A logic low on this pin disables the regulator.
No Connect. Connect this pin to ground.
Operating Mode Pin. Connect this pin to ground; the regulator operates in hysteresis mode.
Voltage Configuration Pin. Connect one resistor from this pin to ground to configure the output voltage of the
regulator.
5
FB
Feedback Sensing Input for the Regulator.
6
7
8
9
VINOK
AGND
PGND
SW
PVIN
EPAD
Input Power-Good Signal. This open-drain output is the power-good signal for the input voltage.
Analog Ground.
Power Ground.
Switching Node Output for the Regulator.
Power Input for the Regulator.
10
Exposed Pad. Solder the exposed pad to a large external copper ground plane underneath the IC for thermal
dissipation.
Rev. 0 | Page 6 of 17
Data Sheet
ADP5304
TYPICAL PERFORMANCE CHARACTERISTICS
VIN =3.6 V, VOUT = 2.5 V, L1 = 2.2 μH, CIN = COUT = 10 ꢀF, fSW = 2 MHz, TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
V
V
V
V
V
V
= 2.5V
= 3.0V
= 3.6V
= 4.2V
= 5.0V
= 6.0V
V
V
V
V
V
V
= 2.5V
= 3.0V
= 3.6V
= 4.2V
= 5.0V
= 6.0V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 4. Hysteresis Efficiency vs. Load Current, VOUT = 1.2 V
Figure 7. Hysteresis Efficiency vs. Load Current, VOUT = 1.5 V
100
100
90
80
70
60
50
90
80
70
60
V
V
V
V
V
V
= 2.5V
= 3.0V
= 3.6V
= 4.2V
= 5.0V
= 6.0V
IN
IN
IN
IN
IN
IN
V
V
V
V
V
= 3.0V
= 3.6V
= 4.2V
= 5.0V
= 6.0V
IN
IN
IN
IN
IN
40
0.001
50
0.001
0.01
0.1
1
10
0.01
0.1
1
10
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 5. Hysteresis Efficiency vs. Load Current, VOUT = 1.8 V
Figure 8. Hysteresis Efficiency vs. Load Current, VOUT = 2.5 V
100
2.10
2.08
2.06
2.04
2.02
2.00
1.98
1.96
90
80
70
60
RISING
V
V
V
V
= 3.6V
= 4.2V
= 5.0V
= 6.0V
IN
IN
IN
IN
FALLING
50
0.001
0.01
0.1
1
10
–40
25
85
125
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 6. Hysteresis Efficiency vs. Load Current, VOUT = 3.3 V
Figure 9. UVLO Threshold, Rising and Falling vs. Temperature
Rev. 0 | Page 7 of 17
ADP5304
Data Sheet
160
140
120
100
80
350
300
250
200
150
100
–40ºC
+25ºC
+85ºC
+125ºC
–40ºC
+25ºC
+85ºC
+125ºC
60
40
20
0
2.3
2.9
3.5
4.1
V
4.7
(V)
5.3
5.9
6.5
2.3
2.9
3.5
4.1
V
4.7
(V)
5.3
5.9
6.5
IN
IN
Figure 10. Shutdown Current vs. VIN, EN = Low
Figure 13. Quiescent Current vs. VIN
700
600
500
400
300
200
100
400
350
300
250
200
150
100
–40ºC
+25ºC
+125ºC
–40ºC
+25ºC
+125ºC
2.3
2.9
3.5
4.1
V
4.7
(V)
5.3
5.9
6.5
2.3
2.9
3.5
4.1
V
IN
4.7
(V)
5.3
5.9
6.5
IN
Figure 14. Low-Side RDS (ON) L vs. VIN
Figure 11. High-Side RDS (ON) H vs. VIN
810
808
806
804
802
800
798
796
794
792
V
OUT
ACTIVE TO STANDBY
STANDBY TO ACTIVE
1
SW
2
4
I
L
CH1 100mV
CH2 2.00V
CH4 500mA Ω
M 200µs A CH4
39.60%
140mA
–40
25
85
125
T
TEMPERATURE (°C)
Figure 15. Steady Waveform, ILOAD = 1 mA (IL is the Inductor Current)
Figure 12. Feedback Voltage vs. Temperature
Rev. 0 | Page 8 of 17
Data Sheet
ADP5304
V
V
V
IN
IN
3
1
3
1
OUT
V
OUT
I
L
I
L
4
2
4
2
SW
SW
CH1 1.00V
CH3 2.00V
CH2 5.00V
CH4 500mA Ω
M 100µs A CH1
T 40.40%
1.40V
CH1 1.00V
CH3 2.00V
CH2 5.00V
CH4 200mA Ω
M 100µs A CH1
T 40.40%
1.40V
Figure 16. Soft Start, ILOAD = 50 mA
Figure 19. Soft Start with Precharge Function
1
V
(AC)
OUT
V
V
(AC)
OUT
IN
1
4
2
I
I
OUT
L
4
SW
CH1 50.0mV
M 200µs A CH4
T 20.80%
111mA
CH1 50.0mV
CH3 2.00V
CH2 5.00V
CH4 500mA Ω
M 2.00ms A CH3
30.00%
4.72V
CH4 50.0mA Ω
T
Figure 17. Load Transient, ILOAD from 0 mA to 50 mA
Figure 20. Line Transient, ILOAD = 10 μA
V
IN
1
V
OUT
1
2
3
I
L
4
CH1 1.00V
CH3 1.00V
M 10.0ms A CH3
T 40.20%
4.80V
B
B
B
CH2 1.00V
W
CH1 2.00V
CH3 1.00V
M 4.00ms A CH3
T 20.20%
980mV
W
W
CH4 200mA Ω
Figure 21. VINOK Function at a 3.0 V VINOK Threshold
Figure 18. Input Voltage Ramp-Up and Ramp-Down
Rev. 0 | Page 9 of 17
ADP5304
Data Sheet
V
OUT
V
L
OUT
1
1
I
I
L
SW
4
2
4
2
SW
CH1 1.00V
CH2 5.00V
CH4 200mA Ω
M 10µs
T 40.40%
A CH1
1.40V
CH1 1.00V
CH2 5.00V
CH4 200mV Ω
M 200µs A CH2
T 40.20%
1.68V
Figure 22. Output Short Protection
Figure 24. Output Short Recovery
V
V
IN
EN
OUT
3
V
OUT
3
1
I
L
SW
1
2
SW
2
CH1 1.00V
CH3 1.00V
CH2 2.00V
CH4 2.00V Ω
M 20.0ms A CH2
T 40.20%
1.56V
CH1 1.00V
CH3 2.00V
CH2 2.00V
M 4.00ms A CH3
T 40.00%
1.64V
Figure 23. 260 μA Current Source Charge Up, 100 μF Output Capacitor with
100 μA Load Current, and 3.0 V VINOK Threshold
Figure 25. Quick Output Discharge Function
Rev. 0 | Page 10 of 17
Data Sheet
ADP5304
THEORY OF OPERATION
The ADP5304 is a high efficient, ultralow quiescent current
step-down regulator in a 10-lead LFCSP package, designed to
meet demanding performance and board space requirements.
The device enables direct connection to a wide input voltage
range of 2.15 V to 6.50 V, allowing the use of high impedance
power sources or energy harvester sources.
Table 5. Output Voltage Options by the VID Pin
VID
Configuration
VOUT
Factory Option 0 (V) Factory Option 1 (V)
,
VOUT,
Short to ground
Short to PVIN
RVID = 499 kΩ
RVID = 316 kΩ
RVID = 226 kΩ
RVID = 174 kΩ
RVID = 127 kΩ
RVID = 97.6 kΩ
RVID = 76.8 kΩ
RVID = 56.2 kΩ
RVID = 43 kΩ
3.0
2.5
3.6
3.3
2.9
2.8
2.7
2.6
2.4
2.3
2.2
2.1
2.0
1.8
1.5
1.2
3.1
1.3
5.0
4.5
4.2
3.9
3.4
3.2
1.9
1.7
1.6
1.4
1.1
1.0
0.9
0.8
BUCK REGULATOR OPERATIONAL MODE
The ADP5304 buck regulator operates in hysteresis mode and
charges the output voltage slightly higher than its nominal
output voltage with PWM pulses via the regulation of constant
peak inductor current. When the output voltage increases until
the output sense signal exceeds the hysteresis upper threshold,
the regulator enters the standby mode. In standby mode, the
high-side and low-side MOSFET and a majority of the circuitry
are disabled to allow a low quiescent current, as well as high
efficiency performance. During standby mode, the output
capacitor supplies the energy into the load and the output
voltage decreases until it falls below the hysteresis comparator
lower threshold. Then, the buck regulator wakes up into active
mode and generates the PWM pulses to charge the output again.
RVID = 32.4 kΩ
RVID = 25.5 kΩ
RVID = 19.6 kΩ
RVID = 15 kΩ
RVID = 11.8 kΩ
UNDERVOLTAGE LOCKOUT (UVLO)
The buck regulator is forced to operate in hysteresis mode via
connecting the MODE pin to ground. The regulator only draws
260 nA of quiescent current to regulate the output under zero load,
which allows the regulator to act as keep-alive power supply in
battery-powered applications or energy harvesting systems.
The undervoltage lockout circuitry monitors the input voltage
level on the PVIN pin. If input voltage falls below 2.00 V
(typical), the regulator turns off. After the input voltage rises
above 2.06 V (typical), the soft start period initiates, and when
the EN pin is high, the regulator enables.
ADJUSTABLE AND FIXED OUTPUT VOLTAGES
ENABLE/DISABLE
The ADP5304 provides adjustable output voltage settings via
the connection of one resistor through the VID pin to AGND.
The VID detection circuitry works in the start-up period, and
the voltage ID code is sampled and held into the internal
register and does not change until the next power recycle.
Furthermore, the ADP5304 provides a fixed output voltage
programmed via the factory fuse. In this condition, connect
the VID pin to the PVIN pin.
The ADP5304 includes a separate enable (EN) pin. A logic high
on the EN pin starts the regulator. Due to the low quiescent current
design, it is typical for the regulator to start switching after a
delay of a few milliseconds from the EN pin being pulled high.
A logic low on the EN pin immediately disables the regulator
and brings the regulator into extremely low current consumption.
VINOK FUNCTION
For output voltage settings, the feedback resistor divider is built
in to the ADP5304, and the feedback pin (FB) must be tied
directly to the output. An ultralow power voltage reference and
an integrated high impedance (50 MΩ, typical) feedback
divider network contribute to low quiescent current. Table 5
lists the output voltage options by the VID pin configurations. It
is recommended to use a 1% resistor.
The ADP5304 includes an open-drain VINOK output that can
be used to indicate the input voltage status. The VINOK output
becomes active high when the input voltage on the PVIN pin is
above the reference threshold. When the input voltage falls below
the reference threshold, the VINOK pin goes low. Note that a
relatively long validation time of 130 μs typical exists for the
VINOK output status to change due to the ultralow power
comparator design.
Rev. 0 | Page 11 of 17
ADP5304
Data Sheet
The ADP5304 VINOK threshold also determines the time
when the buck regulator starts and stops switching. When the
input voltage is below the threshold, the regulator stops switching
in hysteresis mode. After the input source charges the input
capacitor voltage above a hysteresis from the threshold, the
regulator resumes switching. The regulator operates the input
voltage in a hysteresis window around the threshold considered
as the maximum power point tracking (MPPT). The high
impedance input power source or small input power application
employs the ADP5304 to charge the large output capacitor via
trickle charging.
STARTUP WITH PRECHARGED OUTPUT
The buck regulators in the ADP5304 include a precharged
start-up feature to protect the low-side FETs from damage
during startup. If the output voltage is precharged before the
regulator is turned on, the regulator prevents reverse inductor
current—which discharges the output capacitor—until the
internal soft start reference voltage exceeds the precharged
voltage on the feedback pin.
100% DUTY OPERATION
When the input voltage approaches the output voltage, the
ADP5304 stops switching and enters 100% duty cycle operation. It
connects the output via the inductor and the internal high-side
power switch to the input. When the input voltage is charged
again and the required duty cycle falls to 95% typical, the buck
immediately restarts switching and regulation without allowing
overshoot on the output voltage. The ADP5304 draws an ultralow
quiescent current of only 640 nA typical during 100% duty cycle
operation.
Different VINOK thresholds are factory programmable from
2.05 V to 5.15 V in 50 mV steps. To order a device with options
other than the default options, contact your local Analog
Devices, Inc., sales or distribution representative.
CURRENT LIMIT
The buck regulators in the ADP5304 have protection circuitry
that limits the direction and the amount of current to a certain
level that flows through the high-side MOSFET and the low-side
MOSFET in cycle by cycle mode. The positive current limit on
the high-side MOSFET limits the amount of current that can
flow from the input to the output. The negative current limit on
the low-side MOSFET prevents the inductor current from
reversing direction and flowing out of the load.
ACTIVE DISCHARGE
The regulator in the ADP5304 integrates an optional, factory
programmable discharge switch from the switching node to
ground. This switch turns on when its associated regulator is
disabled, which helps discharge the output capacitor quickly.
The typical value of the discharge switch is 290 Ω for the regulator.
SHORT-CIRCUIT PROTECTION
By default, the discharge function is not enabled. The active
discharge function can be enabled by the factory fuse
The buck regulators in the ADP5304 include frequency foldback to
prevent current runaway on a hard short. When the output voltage
at the feedback pin (FB) falls below 0.3 V typical, indicating the
possibility of a hard short at the output, the switching frequency
in active mode reduces to half of the internal oscillator frequency.
The reduction in the switching frequency allows more time for
the inductor to discharge, preventing a runaway of output current.
THERMAL SHUTDOWN
If the ADP5304 junction temperature exceeds 142C, the thermal
shutdown circuit turns the IC off, except for the internal linear
regulator. Extreme junction temperatures can be the result of
high current operation, poor circuit board design, or high ambient
temperature. A 15C hysteresis is included so that the ADP5304
does not return to operation after thermal shutdown until the
junction temperature falls below 127C. When the device exits
thermal shutdown, a soft start is initiated for each enabled channel.
SOFT START
The ADP5304 has an internal soft start function that ramps the
output voltage in a controlled limitation upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the device. The typical soft start
time or the regulator is 350 μs.
A different soft start time (2800 μs) can be programmed for
ADP5304 via the factory fuse (see Table 11).
Rev. 0 | Page 12 of 17
Data Sheet
ADP5304
APPLICATIONS INFORMATION
This section describes the external components selection for the
ADP5304. The typical application circuit is shown in Figure 26.
A minimum requirement of the dc current rating of the inductor
is for it to be equal to the maximum load current plus half of the
inductor current ripple (ΔIL), as shown by the following equations:
V
=
IN
2.2µH
V
= 1.8V
OUT
2.15V TO 6.50V
PVIN
SW
VOUT
10µF
MLCC
1–
ADP5304
10µF
MLCC
VIN
IL VOUT
L fSW
EN
PGND
R2
1MΩ
I
2
MODE
NC
FB
L
I
PK = ILOAD (MAX) +
VINOK
VID
where IPK is the peak inductor current.
AGND
Use the inductor series from the different vendors shown in Table 6.
OUTPUT CAPACITOR
R1
19.6kΩ
EPAD
Output capacitance is required to minimize the voltage overshoot,
the voltage undershoot, and the ripple voltage present on the
output. Capacitors with low equivalent series resistance (ESR)
values produce the lowest output ripple. Furthermore, use
capacitors such as X5R and X7R dielectric capacitors. Do not
use Y5V and Z5U capacitors, because they are unsuitable
choices due to their large capacitance variation over temperature
and their dc bias voltage changes. Because ESR is important,
select the capacitor using the following equation:
Figure 26. Typical Application Circuit
EXTERNAL COMPONENT SELECTION
The ADP5304 is optimized for operation with a 2.2 ꢀH inductor
and 10 ꢀF output capacitors for various output voltages using
the closed-loop compensation and adaptive slope compensation
circuits. The selection of components depends on the efficiency,
the load current transient, and other application requirements.
The trade-offs among performance parameters, such as
efficiency and transient response, are made by varying the
choice of external components.
VRIPPLE
ESRCOUT
ΔIL
SELECTING THE INDUCTOR
where:
ESRCOUT is the ESR of the chosen capacitor.
RIPPLE is the peak-to-peak output voltage ripple.
The high switching frequency of the ADP5304 allows the use of
small surface-mount power inductors. The dc resistance (DCR)
value of the selected inductor affects efficiency. In addition, it is
recommended to select a multilayer inductor rather than a
magnetic iron inductor because the high switching frequency
increases the core temperature rise and enlarges the core loss.
V
Increasing the output capacitor value has no effect on stability
and may reduce output ripple and enhance load transient response.
ADP5304 can charge up the conventional capacitor or super
capacitor. When choosing the output capacitor value, it is
important to account for the loss of capacitance due to output
voltage dc bias.
Use the capacitor series from the different vendors shown in Table 7.
Table 6. Recommended Inductors
Vendor
Model
Inductance (μH)
Dimensions (mm)
2.0 × 1.6 × 0.85
2.5 × 2.0 × 1.2
DCR (mΩ)
280
250
ISAT1 (A)
1.0
1.7
1.5
TDK
Wurth
Coilcraft
MLP2016V2R2MT0S1
74479889222
LPS3314-222MR
2.2
2.2
2.2
3.3 × 3.3 × 1.3
100
1 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current.
Table 7. Input and Output Capacitors
Vendor
Murata
Murata
Murata
Model
Capacitance (μF)
Size
GRM188D71A106MA73
GRM21BR71A106KE51
GRM31CR60J107ME39
10
10
100
0603
0805
1206
Rev. 0 | Page 13 of 17
ADP5304
Data Sheet
Use the following equation to determine the rms input current:
INPUT CAPACITOR
An input capacitor is required to reduce the input voltage
ripple, input ripple current, and source impedance. Place the
input capacitor as close as possible to the PVIN pin. A low ESR
X7R or X5R capacitor is highly recommended to minimize the
input voltage ripple.
VOUT
VIN VOUT
VIN
I RMS I LOAD ( MAX
)
For most applications, a 10 μF capacitor is sufficient. The input
capacitor can be increased without any limit for better input
voltage filtering.
LAYOUT RECOMMENDATIONS
Figure 27 shows the typical printed circuit board (PCB) layout
for the ADP5304.
10µF
10V/XR5
0603
EN
NC
1
2
10PVIN
9
8
7
6
SW
ADP5304
TOP VIEW
MODE3
PGND
AGND
VINOK
5.7
VID
FB
4
5
10µF
6.3V/XR5
0603
100kΩ
0201
4.6
Figure 27. PCB Layout for the ADP5304
Rev. 0 | Page 14 of 17
Data Sheet
ADP5304
TYPICAL APPLICATION CIRCUITS
The ADP5304 can be used as a keep-alive, ultralow power step-
down regulator to extend the battery life and load pulse current
capability with super capacitors (see Figure 28), and as a
battery-powered equipment or wireless sensor network
controlled by a microcontroller or a processor (see Figure 29).
The VINOK function can achieve the maximum power point
tracking.
V
= 2.0V TO 3.0V
10µF
2.2µH
V
= 1.8V
OUT
IN
PVIN
SW
ADC/RF/AFE
CR2032
ADP5304
1mF
EN
PGND
FB
R2
1MΩ
VID
R1
19.6kΩ
1%
MCU
(ALWAYS ON)
VINOK
NC
MODE
AGND
Figure 28. Typical ADP5304 Application with a Coin Cell Battery (CR2032)
PIEZOELECTRIC
HARVESTER
2.2µH
V
= 1.8V
OUT
PVIN
EN
SW
ADC/RF/AFE
ADP5304
10mF
10µF
PGND
FB
R2
1MΩ
VID
MCU
(ALWAYS ON)
R1
19.6kΩ
1%
VINOK
NC
MODE
AGND
Figure 29. Typical ADP5304 Application with a Piezoelectric Harvester
Rev. 0 | Page 15 of 17
ADP5304
Data Sheet
FACTORY PROGRAMMABLE OPTIONS
To order a device with options other than the default options,
contact your local Analog Devices sales or distribution
representative.
Table 10. Output Discharge Functionality Options
Option
Description
Option 0
Output discharge function disabled for buck
regulator (default)
Table 8. Output Voltage VID Setting Options
Option 1
Output discharge function enabled form buck
regulator
Option
Description
Option 0 VID resistor to set the output voltage as follows:
1.2 V, 1.5 V, 1.8 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V,
2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.3 V, 3.6 V, 3.3 V (default)
Option 1 VID resistor to set the output voltage as follows:
0.8 V, 0.9 V, 1.0 V, 1.1 V, 1.3 V, 1.4 V, 1.6 V, 1.7 V, 1.9 V,
3.1 V, 3.4 V, 3.9 V, 4.2 V, 4.5 V, 5.0 V
Table 11. Soft Start Timer Options
Option
Description
350 μs (default)
2800 μs
Option 0
Option 1
Table 9. VINOK Monitor Threshed Options
Option
Option 0
Option 1
Option 2
Option 3
…
VINOK Monitor Threshold (V)
2.05
2.10
2.15
2.20
…
Option 20
…
3.00 (default)
…
Option 62
Option 63
5.10
5.15
Rev. 0 | Page 16 of 17
Data Sheet
ADP5304
OUTLINE DIMENSIONS
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
EXPOSED
PAD
1.74
1.64
1.49
AREA
0.50
0.40
0.30
0.20 MIN
1
5
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 30. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADP5304ACPZ-1-R7
−40°C to +125°C
10-Lead Lead Frame Chip Scale Package [LFCSP_WD] Without
Output Discharge, VINOK Threshold = 3.00 V
CP-10-9
ADP5304ACPZ-2-R7
−40°C to +125°C
10-Lead Lead Frame Chip Scale Package [LFCSP_WD] Without
Output Discharge, VINOK Threshold = 4.00 V
CP-10-9
ADP5304-EVALZ
Evaluation Board
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13493-0-10/15(0)
Rev. 0 | Page 17 of 17
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