ADP7112_技术文档

20 V, 200 mA, Low Noise,

CMOS LDO Linear Regulator

ADP7112

Data Sheet

FEATURES

TYPICAL APPLICATION CIRCUITS

Low noise: 11 μV rms independent of fixed output voltage

PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz,

ADP7112

V

= 6V

V

= 5V

OUT

IN

VIN

VOUT

V_OUT= 5 V, V_IN= 7 V

C

OUT

2.2µF

IN

2.2µF

Input voltage range: 2.7 V to 20 V

Maximum output current: 200 mA

Initial accuracy: 0.8ꢀ

Accuracy over line, load, and temperature

1.8ꢀ, T_J= −40°C to +125°C

SENSE/ADJ

ON

EN

SS

C

GND

SS

OFF

1nF

Figure 1. ADP7112 with Fixed Output Voltage, 5 V

Low dropout voltage: 200 mV (typical) at a 200 mA load,

V

_OUT= 5 V

ADP7112

V

= 7V

V

= 6V

User-programmable soft start

Low quiescent current, I_GND= 50 ꢁA (typical) with no load

Low shutdown current

IN

OUT

VIN

VOUT

C

OUT

2.2µF

IN

2kΩ

2.2µF

SENSE/ADJ

10kΩ

ON

1.8 ꢁA at V_IN= 5 V

3.0 ꢁA at V_IN= 20 V

Stable with a small 2.2 μF ceramic output capacitor

Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, and 5.0 V

15 standard voltages between 1.2 V and 5.0 V are

available

EN

SS

C

1nF

GND

SS

OFF

Figure 2. ADP7112 with 5 V Output Adjusted to 6 V

Adjustable output from 1.2 V to V_IN– V_DO, output can be

adjusted above initial set point

Precision enable

1 mm × 1.2 mm, 6-ball WLCSP

APPLICATIONS

Regulation to noise sensitive applications

ADC and DAC circuits, precision amplifiers, power for

VCO V_TUNEcontrol

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation

GENERAL DESCRIPTION

The ADP7112 is a CMOS, low dropout (LDO) linear regulator

that operates from 2.7 V to 20 V and provides up to 200 mA of

output current. This high input voltage LDO is ideal for the

regulation of high performance analog and mixed-signal circuits

operating from 19 V down to 1.2 V rails. Using an advanced

proprietary architecture, the device provides high power supply

rejection, low noise, and achieves excellent line and load transient

response with a small 2.2 μF ceramic output capacitor. The

ADP7112 regulator output noise is 11 ꢀV rms, independent of

the output voltage for the fixed options of 5 V or less.

The ADP7112 is available in 15 fixed output voltage options.

The following voltages are available from stock: 1.2 V

(adjustable), 1.8 V, 2.5 V, 3.3 V, and 5.0 V. Additional voltages

available by special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V,

2.8 V, 2.85 V, 3.8 V, 4.2 V, and 4.6 V.

Each fixed output voltage can be adjusted above the initial set

point with an external feedback divider. This allows the ADP7112

to provide an output voltage from 1.2 V to V_IN− V_DOwith high

PSRR and low noise.

A user-programmable soft start with an external capacitor is

available in the ADP7112. The ADP7112 is available in a 6-ball

1 mm × 1.2 mm WLCSP, making it a very compact solution.

Rev. D

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ADP7112

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Theory of Operation ...................................................................... 13

Applications Information ............................................................. 14

Capacitor Selection .................................................................... 14

Programable Precision Enable ................................................. 15

Soft Start ...................................................................................... 15

Noise Reduction of the ADP7112 in Adjustable Mode........ 16

Current-Limit and Thermal Overload Protection ................ 16

Effect of Noise Reduction on Start-Up Time......................... 16

Thermal Considerations ........................................................... 17

PCB Layout Considerations.......................................................... 19

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Applications ...................................................................................... 1

Typical Application Circuits........................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications .................................................................................... 3

Input and Output Capacitance, Recommended Specifications

......................................................................................................... 4

Absolute Maximum Ratings ........................................................... 5

Thermal Data................................................................................ 5

Thermal Resistance...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions ............................ 6

Typical Performance Characteristics............................................. 7

REVISION HISTORY

3/2020—Rev. C to Rev. D

12/2014—Rev. A to Rev. B

Change to General Description Section........................................ 1

Changes to Shutdown Current Parameter, Table 1..................... 3

Changes to Theory of Operation Section.................................... 13

Change to Effect of Noise Reduction on Start-Up Time Section...16

Changes to Table 7 ......................................................................... 20

Changed EN to GND Parameter from −0.3 V to VIN to −0.3 V

to +24 V, Table 3 ...............................................................................5

12/2014—Rev. 0 to Rev. A

Changes to Figure 34 to Figure 39 ............................................... 12

Changes to Figure 42 ..................................................................... 14

7/2016—Rev. B to Rev. C

Changes to Figure 40 ..................................................................... 13

Changes to Programmable Precision Enable Section and Soft

Start Section..................................................................................... 15

Added Effect of Noise Reduction on Start-Up Time Section .. 16

9/2014—Revision 0: Initial Version

Rev. D | Page 2 of 21

Data Sheet

ADP7112

SPECIFICATIONS

V_IN= V_OUT+ 1 V or 2.7 V, whichever is greater, V_OUT= 5 V, EN = V_IN, I_OUT= 10 mA, C_IN= C_OUT= 2.2 μF, C_SS= 0 pF, T_A= 25°C for typical

specifications, T_J= −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IN

Test Conditions/Comments

Min

Typ

Max

Unit

V

INPUT VOLTAGE RANGE

MAXIMUM OUTPUT CURRENT

OPERATING SUPPLY CURRENT

2.7

20

I_{LOAD_MAX}

I_GND

200

50

80

180

1.8

3.0

mA

μA

I_OUT= 0 μA

140

190

320

I_OUT= 10 mA

I_OUT= 200 mA

EN = GND

SHUTDOWN CURRENT

I_GND-SD

EN = GND, V_IN= 20 V

10

OUTPUT VOLTAGE ACCURACY

Output Voltage Accuracy

V_OUT

I_OUT= 10 mA, T_J= 25°C

100 ꢀA < I_OUT< 200 mA, V_IN= (V_OUT+ 1 V) to 20 V

–0.8

–1.8

–0.02

+0.8

+1.8

+0.02

%

LINE REGULATION

∆V_OUT/∆V_INV_IN= (V_OUT+ 1 V) to 20 V

∆V_OUT/∆I_OUTI_OUT= 100 ꢀA to 200 mA

%/V

%/mA

nA

LOAD REGULATION¹

SENSE INPUT BIAS CURRENT

DROPOUT VOLTAGE²

0.002 0.004

SENSE_I-BIAS

V_DROPOUT

100 ꢀA < I_OUT< 200 mA V_IN= (V_OUT+ 1 V) to 20 V

10

1000

60

420

I_OUT= 10 mA

I_OUT= 200 mA

V_OUT= 5 V

30

mV

μs

200

380

1.15

360

START-UP TIME³

T_START-UP

SS_I-SOURCE

I_LIMIT

SOFT START SOURCE CURRENT

CURRENT-LIMIT THRESHOLD⁴

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

UNDERVOLTAGE THRESHOLDS

Input Voltage Rising

SS = GND

μA

250

460

2.69

0.4

mA

TS_SD

TS_SD-HYS

T_Jrising

150

15

°C

UVLO_RISE

UVLO_FALL

UVLO_HYS

V

mV

Input Voltage Falling

Hysteresis

2.2

1.0

230

EN INPUT STANDBY

EN Input Logic High

EN Input Logic Low

EN Input Logic Hysteresis

EN INPUT PRECISION

EN Input Logic High

2.7 V ≤ V_IN≤ 20 V

EN_STBY-HIGH

EN_STBY-LOW

EN_STBY-HYS

V

mV

150

EN_HIGH

EN_LOW

EN_HYS

I_EN-LKG

t_EN-DLY

1.15

1.06

1.22

1.12

100

0.04

80

1.30

1.18

V

mV

μA

ꢀs

EN Input Logic Low

EN Input Logic Hysteresis

EN Input Leakage Current

EN Input Delay Time

EN = V_INor GND

1

From EN rising from 0 V to V_INto 0.1 × V_OUT

10 Hz to 100 kHz, all output voltage options

1 MHz, V_IN= 7 V, V_OUT= 5 V

100 kHz, V_IN= 7 V, V_OUT= 5 V

10 kHz, V_IN= 7 V, V_OUT= 5 V

OUTPUT NOISE

OUT_NOISE

11

μV rms

dB

POWER SUPPLY REJECTION RATIO PSRR

50

68

88

¹Based on an endpoint calculation using 100 ꢀA and 200 mA loads. See Figure 5 for typical load regulation performance for loads less than 1 mA.

²Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output

voltages greater than 2.7 V.

³Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.

⁴Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V or 4.5 V.

Rev. D | Page 3 of 21

ADP7112

Data Sheet

INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

INPUT AND OUTPUT CAPACITANCE

Minimum Capacitance¹

Capacitor Effective Series Resistance (ESR)

C_MIN

R_ESR

T_A= −40°C to +125°C

1.5

0.001

μF

Ω

0.3

¹The minimum input and output capacitance must be greater than 1.5 ꢀF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,

whereas Y5V and Z5U capacitors are not recommended for use with any LDO.

Rev. D | Page 4 of 21

Data Sheet

ADP7112

ABSOLUTE MAXIMUM RATINGS

θ_JAof the package is based on modeling and calculation using a

4-layer board. The θ_JAis highly dependent on the application

and board layout. In applications where high maximum power

dissipation exists, close attention to thermal board design is

required. The value of θ_JAcan vary, depending on PCB material,

layout, and environmental conditions. The specified values of θ_JA

are based on a 4-layer, 4 in. × 3 in. circuit board. See JESD51-7 and

JESD51-9 for detailed information on the board construction.

Table 3.

Parameter

Rating

VIN to GND

VOUT to GND

EN to GND

SENSE/ADJ to GND

SS to GND

−0.3 V to +24 V

−0.3 V to VIN

−0.3 V to +24 V

−0.3 V to +6 V

−0.3 V to VIN or +6 V

(whichever is less)

Storage Temperature Range

−65°C to +150°C

Ψ

_JBis the junction-to-board thermal characterization parameter

Operating Junction Temperature −40°C to +125°C

(T_J) Range

Operating Ambient Temperature −40°C to +85°C

(T_A) Range

with units of °C/W. The Ψ_JBof the package is based on

modeling and calculation using a 4-layer board. The JESD51-12,

Guidelines for Reporting and Using Electronic Package Thermal

Information, states that thermal characterization parameters are

not the same as thermal resistances. Ψ_JBmeasures the component

power flowing through multiple thermal paths rather than a

single path as in thermal resistance (θ_JB). Therefore, Ψ_JBthermal

paths include convection from the top of the package as well as

radiation from the package, factors that make Ψ_JBmore useful in

real-world app-lications. Maximum T_Jis calculated from the

board temperature (T_B) and P_Dusing the formula

Soldering Conditions

JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

T_J= T_B+ (P_D× Ψ_JB)

(2)

See JESD51-8 and JESD51-12 for more detailed information

about Ψ_JB.

THERMAL DATA

Absolute maximum ratings apply individually only, not in

combination. The ADP7112 can be damaged when the junction

temperature limits are exceeded. Monitoring ambient temperature

does not guarantee that T_Jis within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature can

have to be derated.

THERMAL RESISTANCE

θ_JA, θ_JC, and Ψ_JBare specified for the worst-case conditions, that

is, a device soldered in a circuit board for surface-mount

packages.

Table 4. Thermal Resistance

Package Type

θ_JA

θ_JC

Ψ_JB

Unit

In applications with moderate power dissipation and low

printed circuit board (PCB) thermal resistance, the maximum

ambient temperature can exceed the maximum limit as long as

the junction temperature is within specification limits. The

junction temperature of the device is dependent on the ambient

temperature, the power dissipation (P_D) of the device, and the

junction-to-ambient thermal resistance of the package (θ_JA).

6-Ball WLCSP

260

4

58

°C/W

ESD CAUTION

Maximum T_Jis calculated from the T_Aand P_Dusing the

formula

T_J= T_A+ (P_D× θ_JA)

(1)

Rev. D | Page 5 of 21

ADP7112

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1

INDICATOR

1

2

A

B

C

VIN

SS

VOUT

SENSE/

ADJ

EN

GND

ADP7112

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

A1

B1

Mnemonic Description

VIN

SS

Regulator Input Supply. Bypass VIN to GND with a 2.2 μF or greater capacitor.

Soft Start. An external capacitor connected to this pin determines the soft start time. Leave this pin open

for a typical 380 ꢀs start-up time. Do not ground this pin.

C1

EN

The enable pin controls the operation of the LDO. Drive EN high to turn on the regulator. Drive EN low

to turn off the regulator. For automatic startup, connect EN to VIN.

A2

B2

VOUT

Regulated Output Voltage. Bypass VOUT to GND with a 2.2 μF or greater capacitor.

SENSE/ADJ Sense Input (SENSE). Connect to load.

Adjustable Model (ADJ). The adjustable model has a fixed output set to 1.2 V. The output can be set to a

voltage higher than 1.2 V by connecting an external resistor divider to the ADJ pin.

C2

GND

Ground.

Rev. D | Page 6 of 21

Data Sheet

ADP7112

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= V_OUT+ 1 V or 2.7 V, whichever is greater, V_OUT= 5 V, I_LOAD= 10 mA, C_IN= C_OUT= 2.2 μF, T_A= 25°C, unless otherwise noted.

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

300

250

200

150

100

50

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

0

–40

–5

25

85

125

–40

–5

25

85

125

JUNCTION TEMPERATURE (°C)

Figure 4. Output Voltage (V_OUT) vs. Junction Temperature

Figure 7. Ground Current vs. Junction Temperature

5.05

200

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

180

160

140

120

100

80

60

40

20

0

0.1

1

10

(mA)

100

1000

0.1

1

10

(mA)

100

1000

I

LOAD

Figure 5. Output Voltage (V_OUT) vs. Load Current (I_LOAD

)

Figure 8. Ground Current vs. Load Current (I_LOAD)

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

300

250

200

150

100

50

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

0

5

10

15

20

5

10

15

20

V

(V)

V

(V)

IN

Figure 6. Output Voltage (V_OUT) vs. Input Voltage (V_IN

)

Figure 9. Ground Current vs. Input Voltage (V_IN)

Rev. D | Page 7 of 21

ADP7112

Data Sheet

2.5

2.0

1.5

1.0

0.5

1000

900

800

700

600

500

400

300

200

100

0

LOAD = 5mA

V

= 2.7V

= 3V

= 5V

= 6V

= 10V

= 20V

IN

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

0

4.8

5.0

5.2

(V)

5.4

5.6

–50

–25

0

25

50

75

100

125

V

TEMPERATURE (°C)

IN

Figure 10. Shutdown Current vs. Temperature at Various Input Voltages

Figure 13. Ground Current vs. Input Voltage (V_IN) in Dropout, V_OUT= 5 V

250

3.35

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

200

150

100

50

3.33

3.31

3.29

3.27

3.25

0

–40

–5

25

85

125

1

10

100

1000

JUNCTION TEMPERATURE (°C)

I

(mA)

LOAD

Figure 14. Output Voltage (V_OUT) vs. Junction Temperature, V_OUT= 3.3 V

Figure 11. Dropout Voltage vs. Load Current (I_LOAD), V_OUT= 5 V

3.35

5.05

5.00

4.95

4.90

4.85

4.80

3.33

3.31

3.29

3.27

3.25

4.75

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

4.70

4.65

4.60

4.8

0.1

1

10

(mA)

100

1000

5.0

5.2

(V)

5.4 5.6

I

LOAD

V

IN

Figure 12. Output Voltage (V_OUT) vs. Input Voltage (V_IN) in Dropout, V_OUT= 5 V

Figure 15. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= 3.3 V

Rev. D | Page 8 of 21

Data Sheet

ADP7112

3.35

300

250

200

150

100

50

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

3.33

3.31

3.29

3.27

3.25

0

5

10

(V)

15

20

0

5

10

(V)

15

20

V

IN

Figure 16. Output Voltage (V_OUT) vs. Input Voltage (V_IN), V_OUT= 3.3 V

Figure 19. Ground Current vs. Input Voltage (V_IN), V_OUT= 3.3 V

300

250

200

150

100

50

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

250

LOAD = 200mA

200

150

100

50

0

–40

–5

25

85

125

1

10

100

1000

JUNCTION TEMPERATURE (°C)

I

(mA)

LOAD

Figure 17. Ground Current vs. Junction Temperature, V_OUT= 3.3 V

Figure 20. Dropout Voltage vs. Load Current (I_LOAD), V_OUT= 3.3 V

200

180

160

140

120

100

80

3.4

3.3

3.2

3.1

3.0

60

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

40

2.9

20

LOAD = 150mA

LOAD = 200mA

0

0.1

2.8

3.1

1

10

(mA)

100

1000

3.3

3.5

(V)

3.7 3.9

I

V

LOAD

IN

Figure 18. Ground Current vs. Load Current (I_LOAD), V_OUT= 3.3 V

Figure 21. Output Voltage (V_OUT) vs. Input Voltage (V_IN) in Dropout,

V_OUT= 3.3 V

Rev. D | Page 9 of 21

ADP7112

Data Sheet

700

600

500

400

300

200

100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

0

0.2

0.6

1.0

1.4

1.8

2.2

2.6

3.0

3.1

3.3

3.5

(V)

3.7

3.9

HEADROOM VOLTAGE (V)

V

IN

Figure 22. Ground Current vs. Input Voltage (V_IN) in Dropout, V_OUT= 3.3 V

Figure 25. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

V_OUT= 1.8 V, for Different Frequencies

300

0

–20

–40

–60

V

= 2.7V

= 5.0V

= 10V

= 20V

IN

250

200

150

100

50

3.0V

2.0V

1.6V

1.4V

1.2V

1.0V

800mV

700mV

600mV

500mV

–80

–100

–120

0

–40

–5

25

85

125

10

100

1k

10k

100k

1M

10M

TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency, V_OUT= 3.3 V,

for Various Headroom Voltages

Figure 23. Soft Start (SS) Current vs. Temperature, Multiple Input Voltages,

V_OUT= 5 V

0

10Hz

3.0V

100Hz

1kHz

2.0V

1.6V

–10

1.4V

1.2V

10kHz

100kHz

–20

1.0V

1MHz

10MHz

–30

–40

–50

–60

–70

–80

–90

–100

800mV

700mV

600mV

–40

–50

–60

–70

–80

–90

–100

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

1

10

100

1k

10k

100k

1M

10M

HEADROOM VOLTAGE (V)

FREQUENCY (Hz)

Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

V_OUT= 3.3 V, for Different Frequencies

Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency, V_OUT= 1.8 V,

for Various Headroom Voltages

Rev. D | Page 10 of 21

Data Sheet

ADP7112

0

10k

1k

100

10

1

–20

–40

–60

3.0V

2.0V

1.6V

–80

1.4V

1.2V

1.0V

800mV

700mV

600mV

500mV

–100

–120

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency, V_OUT= 5 V,

for Various Headroom Voltages

Figure 31. Output Noise Spectral Density vs. Frequency, I_LOAD= 10 mA

0

100k

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

100µA

1mA

10mA

100mA

200mA

–10

–20

10k

–30

–40

–50

–60

–70

–80

–90

1k

100

10

1

–100

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

1

10

100

1k

10k

100k

1M

10M

HEADROOM VOLTAGE (V)

FREQUENCY (Hz)

Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

V_OUT= 5 V, for Different Frequencies

Figure 32. Output Noise Spectral Density vs. Frequency, for Different Loads

20

100k

10Hz TO 100kHz

1.8V

3.3V

5.0V

100Hz TO 100kHz

16

10k

1k

100

10

1

12

8

4

0

1

10

100

1000

1

10

100

1k

10k

100k

1M

10M

LOAD CURRENT (mA)

FREQUENCY (Hz)

Figure 33. Output Noise Spectral Density vs. Frequency, for

Different Output Voltages

Figure 30. RMS Output Noise vs. Load Current

Rev. D | Page 11 of 21

ADP7112

Data Sheet

T

1

2

1

B

CH1 200mA Ω

CH2 20mV

M20µs A CH1

W

1000mA

CH1 1V

CH2 2mV

M4µs

10.2%

A

CH4

1.84V

W

T

10.2%

T

Figure 34. Load Transient Response, I_LOAD= 1 mA to 200 mA,

V_OUT= 5 V, V_IN= 7 V, CH1 Load Current, CH2 V_OUT

Figure 37. Line Transient Response, I_LOAD= 200 mA,

V_OUT= 3.3 V, CH1 V_IN, CH2 V_OUT

T

1

2

1

2

B

CH1 2V

CH2 2mV

M4.0µs

10.2%

A

CH4

1.84V

CH1 200mA

Ω

CH2 20mV

M20µs

W

T 10.2%

A

CH1

84mA

W

T

Figure 35. Line Transient Response, I_LOAD= 200 mA,

V_OUT= 5 V, CH1 V_IN, CH2 V_OUT

Figure 38. Load Transient Response, I_LOAD= 1 mA to 200 mA,

V_OUT= 1.8 V, V_IN= 3 V, CH1 Load Current, CH2 V_OUT

T

1

2

1

2

B

W

B

CH1 200mA Ω

CH2 20mV

M20µs

A

CH1

148mA

CH1 1V

CH2 5mV

M4.0µs

93.4%

A

CH4

2.08V

W

T

10.4%

T

Figure 36. Load Transient Response, I_LOAD= 1 mA to 200 mA,

V_OUT= 3.3 V, V_IN= 5 V, CH1 Load Current, CH2 V_OUT

Figure 39. Line Transient Response, I_LOAD= 200 mA,

V_OUT= 1.8 V, CH1 V_IN, CH2 V_OUT

Rev. D | Page 12 of 21

Data Sheet

ADP7112

THEORY OF OPERATION

The ADP7112 is a low quiescent current, LDO linear

regulator that operates from 2.7 V to 20 V and provides up to

200 mA of output current. Drawing a low 180 ꢀA of quiescent

current (typical) at full load makes the ADP7112 ideal for

portable equipment. Typical shutdown current consumption

is around 3.0 ꢀA at room temperature.

any fixed output voltage to be set to a higher voltage with an

external voltage divider. For example, a fixed 5 V output can be

set to a 6 V output according to the following equation:

V

_OUT= 5 V(1 + R1/R2)

(3)

where R1 and R2 are the resistors in the output voltage divider

shown in Figure 41.

Optimized for use with small 2.2 μF ceramic capacitors, the

ADP7112 provides excellent transient performance.

ADP7112

V

= 7V

V

= 6V

IN

OUT

VIN

EN

VOUT

C

2.2µF

R1

C

OUT

2.2µF

IN

VIN

VOUT

2kΩ

SENSE/ADJ

R2

10kΩ

SENSE/

ADJ

SHORT-CIRCUIT,

THERMAL

PROTECTION

ON

GND

SS

GND

C

SS

OFF

REFERENCE

1nF

Figure 41. Typical Adjustable Output Voltage Application Schematic

EN

SHUTDOWN

It is recommended that the R2 value be less than 200 kΩ to

minimize errors in the output voltage caused by the SENSE/

ADJ pin input current. For example, when R1 and R2 each equal

200 kΩ and the default output voltage is 1.2 V, the adjusted output

voltage is 2.4 V. The output voltage error introduced by the

SENSE/ADJ pin input current is 1 mV or 0.04%, assuming a

typical SENSE/ADJ pin input current of 10 nA at 25°C.

Figure 40. Internal Block Diagram

Internally, the ADP7112 consists of a reference, an error amplifier,

and a PMOS pass transistor. Output current is delivered via the

PMOS pass device, which is controlled by the error amplifier. The

error amplifier compares the reference voltage with the feedback

voltage from the output and amplifies the difference. If the

feedback voltage is lower than the reference voltage, the gate of the

PMOS device is pulled lower, allowing more current to pass and

increasing the output voltage. If the feedback voltage is higher than

the reference voltage, the gate of the PMOS device is pulled higher,

allowing less current to pass and decreasing the output voltage.

The ADP7112 uses the EN pin to enable and disable the

VOUT pin under normal operating conditions. When EN is

high, VOUT turns on, and when EN is low, VOUT turns off.

For automatic startup, tie EN to VIN.

The ADP7112 is available in 15 fixed output voltage options,

ranging from 1.2 V to 5.0 V. The ADP7112 architecture allows

Rev. D | Page 13 of 21

ADP7112

Data Sheet

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

Figure 43 depicts the capacitance vs. voltage bias characteristic

of a 0805, 2.2 μF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the

X5R dielectric is ~ 15ꢀ over the −40°C to +85°C temperature

range and is not a function of package or voltage rating.

2.5

The ADP7112 is designed for operation with small, space-saving

ceramic capacitors, but functions with general-purpose capacitors

as long as care is taken with regard to the effective series resistance

(ESR) value. The ESR of the output capacitor affects the stability

of the LDO control loop. A 2.2 μF capacitance with an ESR of

0.3 Ω or less is recommended to ensure the stability of the

ADP7112. Transient response to changes in load current is also

affected by output capacitance. Using a larger value of output

capacitance improves the transient response of the ADP7112 to

large changes in load current. Figure 42 shows the transient

responses for an output capacitance value of 2.2 μF.

2.0

1.5

1.0

0.5

0

T

1

0

2

4

6

8

10

12

DC BIAS VOLTAGE (V)

2

Figure 43. Capacitance vs. Voltage Characteristic

Use Equation 1 to determine the worst-case capacitance

accounting for capacitor variation over temperature, component

tolerance, and voltage.

B

CH1 200mA Ω

CH2 20mV

M20µs

W

A

CH1

100mA

C_EFF= C_BIAS× (1 − TEMPCO) × (1 − TOL)

(4)

W

T

10.2%

where:

Figure 42. Output Transient Response, V_OUT= 5 V, C_OUT= 2.2 μF, CH1 Load

Current, CH2 V_OUT

C_BIASis the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

Input Bypass Capacitor

Connecting a 2.2 μF capacitor from VIN to GND reduces

the circuit sensitivity to the PCB layout, especially when long

input traces or high source impedance is encountered. If

greater than 2.2 μF of output capacitance is required, increase

the input capacitor to match it.

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15ꢀ for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10ꢀ, and C_BIASis 2.09 ꢁF at 5 V, as shown in Figure 43.

These values in Equation 1 yield

Input and Output Capacitor Properties

C

_EFF= 2.09 ꢁF × (1 − 0.15) × (1 − 0.1) = 1.59 ꢁF

(5)

Any good quality ceramic capacitors can be used with the

ADP7112, as long as they meet the minimum capacitance and

maximum ESR requirements. Ceramic capacitors are manufac-

tured with a variety of dielectrics, each with different behavior

over temperature and applied voltage. Capacitors must have a

dielectric adequate to ensure the minimum capacitance over

the necessary temperature range and dc bias conditions. X5R or

X7R dielectrics with a voltage rating of 6.3 V to 100 V are

recommended. Y5V and Z5U dielectrics are not recommended,

due to their poor temperature and dc bias characteristics.

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over temper-

ature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP7112, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

Rev. D | Page 14 of 21

Data Sheet

ADP7112

PROGRAMABLE PRECISION ENABLE

SOFT START

The ADP7112 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. As shown in Figure 44,

when a rising voltage on EN crosses the upper threshold,

nominally 1.2 V, VOUT turns on. When a falling voltage on EN

crosses the lower threshold, nominally 1.1 V, VOUT turns off.

The hysteresis of the EN threshold is typically 100 mV.

3.5

The ADP7112 uses an internal soft start (SS pin open) to limit the

inrush current when the output is enabled. The start-up time for

the 3.3 V option is approximately 380 ꢀs from the time the EN

active threshold is crossed to when the output reaches 90% of

the final value. As shown in Figure 46, the start-up time is

dependent on the output voltage setting.

6

V

EN

= 1.8V

= 3.3V

= 5.0V

OUT

3.0

2.5

2.0

1.5

1.0

5

4

3

2

1

0

0.5

0

–40°C

+25°C

+125°C

1.05

1.10

1.15

1.20

1.25

1.30

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

V

(V)

EN

TIME (ms)

Figure 44. Typical V_OUTResponse to EN Pin Operation

Figure 46. Typical Start-Up Behavior

The upper and lower thresholds are user programmable and can be

set higher than the nominal 1.2 V threshold by using two resistors.

The resistance values, R_EN1and R_EN2, can be determined from

An external capacitor connected to the SS pin determines the

soft start time. This SS pin can be left open for a typical 380 ꢀs

start-up time. Do not ground this pin. When an external soft

start capacitor (C_SS) is used, the soft start time is determined by

the following equation:

R

_EN2= nominally 10 kΩ to 100 kΩ

(6)

(7)

_EN1= R_EN2× (V_IN− 1.2 V)/1.2 V

SS_TIME(sec) = t_{START-UP at 0 pF}+ (0.6 × C_SS)/I_ss

where:

_{START-UP at 0 pF}is the start-up time at C_SS= 0 pF (typically 380 ꢀs).

_SSis the soft start capacitor (F).

(8)

where V_INis the desired turn-on voltage.

The hysteresis voltage increases by the factor (R_EN1+ R_EN2)/R_EN2

For the example shown in Figure 45, the enable threshold is

3.6 V with a hysteresis of 300 mV.

.

t

C

I_ssis the soft start current (typically 1.15 ꢀA).

3.5

ADP7112

V

= 8V

V

= 6V

IN

OUT

VIN

VOUT

3.0

2.5

2.0

1.5

1.0

0.5

0

C

2.2µF

R1

C

OUT

2.2µF

IN

2kΩ

SENSE/ADJ

R2

10kΩ

R

EN1

ON

200kΩ

EN

GND

R

OFF

EN2

100kΩ

Figure 45. Typical EN Pin Voltage Divider

V

EN

NO SS CAP

1nF

2nF

4.7nF

6.8nF

10nF

Figure 44 shows the typical hysteresis of the EN pin. This pre-

vents on/off oscillations that can occur due to noise on the EN pin

as it passes through the threshold points.

0

1

2

3

4

5

6

7

8

9

10

TIME (ms)

Figure 47. Typical Soft Start Behavior, Different C_SS

Rev. D | Page 15 of 21

ADP7112

Data Sheet



RMS noise of the adjustable LDO without noise reduction

of 22 μV rms

RMS noise of the adjustable LDO with noise reduction

(assuming 11 μV rms for fixed voltage option) of 12 μV rms

NOISE REDUCTION OF THE ADP7112 IN

ADJUSTABLE MODE

The ultralow output noise of the ADP7112 is achieved by

keeping the LDO error amplifier in unity gain and setting the

reference voltage equal to the output voltage. This architecture

does not work for an adjustable output voltage LDO in the

conventional sense. However, the ADP7112 architecture allows

any fixed output voltage to be set to a higher voltage with an

external voltage divider. For example, a fixed 5 V output can be

set to a 6 V output according to Equation 3 (see Figure 2).

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADP7112 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADP7112 is designed to current limit when the

output load reaches 360 mA (typical). When the output load

exceeds 360 mA, the output voltage is reduced to maintain a

constant current limit.

V

_OUT= 5 V(1 + R1/R2)

The disadvantage in using the ADP7112 in this manner is that

the output voltage noise is proportional to the output voltage.

Therefore, it is best to choose a fixed output voltage that is close

to the target voltage to minimize the increase in output noise.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and/or

high power dissipation) when the junction temperature starts

to rise above 150°C, the output is turned off, reducing the

output current to zero. When the junction temperature drops

below 135°C, the output is turned on again, and output current

is restored to the operating value.

The adjustable LDO circuit can be modified to reduce the

output voltage noise to levels close to that of the fixed output

ADP7112. The circuit shown in Figure 48 adds two additional

components to the output voltage setting resistor divider. C_NR

and R_NRare added in parallel with R1 to reduce the ac gain of

the error amplifier. R_NRis chosen to be small with respect to R2.

If R_NRis 1% to 10% of the value of R2, the minimum ac gain of

the error amplifier is approximately 0.1 dB to 0.8 dB. The actual

gain is determined by the parallel combination of R_NRand R1.

This gain ensures that the error amplifier always operates at

slightly greater than unity gain.

Consider the case where a hard short from VOUT to ground

occurs. At first, the ADP7112 current limits, so that only 360

mA is conducted into the short. If self heating of the junction

is great enough to cause the temperature to rise above 150°C,

thermal shutdown activates, turning off the output and reducing

the output current to zero. As the junction temperature cools

and drops below 135°C, the output turns on and conducts

360 mA into the short, again causing the junction

temperature to rise above 150°C. This thermal oscillation

between 135°C and 150°C causes a current oscillation

between 360 mA and 0 mA that continues as long as the short

remains at the output.

C_NRis chosen by setting the reactance of C_NRequal to R1 − R_NR

at a frequency between 1 Hz and 50 Hz. This setting places the

frequency where the ac gain of the error amplifier is 3 dB down

from the dc gain.

V

= 10V

VIN

VOUT

V

= 12V

OUT

+

C

OUT

IN

R1

100kΩ

+

C

2.2µF

IN

+

C

NR

2.2µF

1µF

SENSE/ADJ

Current-limit and thermal limit protections protect the device

against accidental overload conditions. For reliable operation,

device power dissipation must be externally limited so that the

junction temperature does not exceed 125°C.

R

10kΩ

NR

ON

200kΩ

100kΩ

R2

100kΩ

OFF

EN

GND

EFFECT OF NOISE REDUCTION ON START-UP TIME

The start-up time of the ADP7112 is affected by the noise

reduction network and must be considered in applications

where power supply sequencing is critical.

Figure 48. Noise Reduction Modification

The noise of the adjustable LDO is found by using the

following formula, assuming the noise of a fixed output LDO is

approximately 11 ꢀV.

The noise reduction circuit adds a pole in the feedback loop,

slowing down the start-up time. The start-up time for an

adjustable model with a noise reduction network can be

approximated using the following equation:

Noise = 11 ꢀV × (R_PAR+ R2)/R2

(9)

where R_PARis a parallel combination of R1 and R_NR

.

SSNR_TIME(sec) = 5.5 × C_NR× (R_NR+ R₁)

Based on the component values shown in Figure 48, the

ADP7112 has the following characteristics:

For a C_NR, R_NR, and R₁combination of 1 μF, 10 kΩ, and 100 kΩ

as shown in Figure 48, the start-up time is approximately 0.6 sec.

When SSNR_TIMEis greater than SS_TIME, SSNR_TIMEdictates the

length of the start-up time instead of the soft start capacitor.



DC gain of 2 (6 dB)

3 dB roll-off frequency of 1.59 Hz

High frequency ac gain of 1.09 (0.75 dB)

Noise reduction factor of 1.83 (5.25 dB)

Rev. D | Page 16 of 21

Data Sheet

ADP7112

Power dissipation due to ground current is quite small and can

be ignored. Therefore, the junction temperature equation

simplifies to the following:

THERMAL CONSIDERATIONS

In applications with a low input-to-output voltage differential,

the ADP7112 does not dissipate much heat. However, in

applications with high ambient temperature and/or high input

voltage, the heat dissipated in the package can become large

enough to cause the junction temperature of the die to exceed

the maximum junction temperature of 125°C.

T_J= T_A+ (((V_IN− V_OUT) × I_LOAD) × θ_JA)

(11)

As shown in Equation 4, for a given ambient temperature, input-

to-output voltage differential, and continuous load current,

there exists a minimum copper size requirement for the PCB

to ensure that the junction temperature does not rise above 125°C.

Figure 49 to Figure 51 show junction temperature calculations

for different ambient temperatures, power dissipation, and

areas of PCB copper.

When the junction temperature exceeds 150°C, the converter

enters thermal shutdown. It recovers only after the junction

temperature has decreased below 135°C to prevent any permanent

damage. Therefore, thermal analysis for the chosen application

is very important to guarantee reliable performance over all

conditions. The junction temperature of the die is the sum of

the ambient temperature of the environment and the temperature

rise of the package due to the power dissipation, as shown in

Equation 1.

In the case where the board temperature is known, use the

thermal characterization parameter, Ψ_JB, to estimate the

junction temperature rise (see Figure 52). Calculate the

maximum junction temperature by using Equation 2.

T_J= T_B+ (P_D× Ψ_JB)

To guarantee reliable operation, the junction temperature of

the ADP7112 must not exceed 125°C. To ensure that the

junction temperature stays below this maximum value, the user

must be aware of the parameters that contribute to junction

temperature changes. These parameters include ambient

temperature, power dissipation in the power device, and thermal

resistances between the junction and ambient air (θ_JA). The θ_JA

number is dependent on the package assembly compounds that

are used and the amount of copper solders the package GND pin

to the PCB.

The typical value of Ψ_JBis 58°C/W for the 6-ball WLCSP package.

145

135

125

115

105

95

85

75

65

2

25mm

55

45

35

25

2

100mm

500mm

Table 6 shows typical θ_JAvalues of the 6-ball WLCSP package

for various PCB copper sizes. The typical Ψ_JBvalue for the

6-ball WLCSP package is 58°C/W.

T

MAX

J

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Table 6. Typical θ_JAValues

TOTAL POWER DISSIPATION (W)

Copper Size (mm)

θ_JA(°C/W) for WLCSP

Figure 49. WLCSP, T_A= 25°C

25¹

50

100

500

260

159

157

151

140

130

120

110

100

90

¹Device soldered to minimum size pin traces.

To calculate the junction temperature of the ADP7112, use

Equation 1.

T_J= T_A+ (P_D× θ_JA)

80

where:

2

25mm

70

2

100mm

500mm

MAX

T_Ais the ambient temperature.

P_Dis the power dissipation in the die, given by

60

T

J

50

P_D= ((V_IN− V_OUT) × I_LOAD) + (V_IN× I_GND

where:

_INand V_OUTare input and output voltages, respectively.

)

(10)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

TOTAL POWER DISSIPATION (W)

Figure 50. WLCSP, T_A= 50°C

V

I

_LOADis the load current.

_GNDis the ground current.

Rev. D | Page 17 of 21

ADP7112

Data Sheet

140

120

100

80

135

125

115

105

95

60

T

= 25°C

= 50°C

= 65°C

= 85°C

MAX

B

J

40

2

25mm

2

100mm

500mm

MAX

20

T

J

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

TOTAL POWER DISSIPATION (W)

Figure 52. WLCSP Junction Temperature Rise, Different Board Temperatures

Figure 51. WLCSP, T_A= 85°C

Rev. D | Page 18 of 21

Data Sheet

ADP7112

PCB LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by increasing

the amount of copper attached to the pins of the ADP7112.

However, as listed in Table 6, a point of diminishing returns is

eventually reached, beyond which an increase in the copper size

does not yield significant heat dissipation benefits.

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Use of 0805 or 1206 size capacitors and

resistors achieves the smallest possible footprint solution on

boards where area is limited.

Figure 53. Example WLCSP PCB Layout

Rev. D | Page 19 of 21

ADP7112

Data Sheet

Table 7. Recommended LDOs for Super Low Noise Operation

Noise

(Fixed)

I_Qat

I_OUT

(μA)

I_GND-SD

Max

(μA)

10 Hz to PSRR

100 kHz 100 kHz 1 MHz

P_GOOD(μV rms) (dB)

PSRR

Device

Number

V_IN

Range (V)

V_OUT

Fixed (V) (V)

V_OUTAdjust I_OUT

Soft

Start

(mA)

(dB)

Package

ADP7102 3.3 to 20

ADP7104 3.3 to 20

ADP7105 3.3 to 20

1.5 to 9

1.22 to 19

300

750

900

75

No

Yes

15

60

40

3 mm ×

3 mm

8-lead LFCSP,

8-lead SOIC

3 mm ×

3 mm

8-lead LFCSP,

8-lead SOIC

3 mm ×

3 mm

1.22 to 19

500

40

1.8, 3.3, 5 1.22 to 19

8-lead LFCSP,

8-lead SOIC

ADP7112 2.7 to 20

ADP7118 2.7 to 20

1.2 to 5

1.2 to 19

200

180

10

Yes

No

11

68

50

1 mm ×

1.2 mm

6-ball WLCSP

2 mm ×

2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7142 2.7 to 40

1.2 to 5

1.2 to 39

200

180

10

−8

Yes

No

11

18

68

45

50

45

2 mm ×

2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7182 −2.7 to −28 −1.8 to −5 −1.22 to −27 −200

−650

2 mm ×

2 mm

6-lead LFCSP,

3 × 3 mm

8-lead LFCSP,

5-lead TSOT

Table 8. Related Devices

Model

Input Voltage (V)

2.7 to 20

2.7 to 40

Output Current (mA)

Package

ADP7118ACP

ADP7118ARD

ADP7118AUJ

ADP7142ACP

ADP7142ARD

ADP7142AUJ

200

6-lead LFCSP

8-lead SOIC

5-lead TSOT

6-lead LFCSP

8-lead SOIC

5-lead TSOT

2.7 to 40

Rev. D | Page 20 of 21

Data Sheet

ADP7112

OUTLINE DIMENSIONS

0.990

0.950

0.910

BOTTOM VIEW

(BALL SIDE UP)

2

1

A

B

BALL A1

IDENTIFIER

1.200

1.160

1.120

0.80

REF

C

0.40

BSC

TOP VIEW

(BALL SIDE DOWN)

0.40 BSC

0.330

0.300

0.270

0.560

0.500

0.440

SIDE VIEW

COPLANARITY

0.04

0.300

0.260

0.220

0.230

0.200

0.170

SEATING

PLANE

Figure 54. 6-Ball Wafer Level Chip Scale Package [WLCSP]

1.00 mm × 1.20 mm Body

(CB-6-15)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +125°C

Output Voltage (V)^{2, 3}

Package Description

6-Ball WLCSP

Package Option

CB-6-15

Branding

ADP7112ACBZ-1.2-R7

ADP7112ACBZ-1.8-R7

ADP7112ACBZ-2.5-R7

ADP7112ACBZ-3.3-R7

ADP7112ACBZ-5.0-R7

ADP7112CB-EVALZ

Adjustable (1.2)

CQ

CR

CS

CT

CU

1.8

2.5

3.3

5.0

3.3

6-Ball WLCSP

WLCSP Evaluation Board

CB-6-15

¹Z = RoHS Compliant Part.

²For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.

³The evaluation boards are preconfigured with an adjustable ADP7112.

registered trademarks are the property of their respective owners.

D12508-3/20(D)

Rev. D | Page 21 of 21


型号：	ADP7112
厂家：	ADI
描述：	20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator
文件：	总21页 (文件大小：584K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP7112 [ADI]

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