ADP7118ARDZ-3.3_技术文档

20 V, 200 mA, Low Noise,

CMOS LDO Linear Regulator

ADP7118

Data Sheet

FEATURES

TYPICAL APPLICATION CIRCUITS

Low noise: 11 µV rms independent of fixed output voltage

PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz,

ADP7118

V

= 6V

V

= 5V

OUT

IN

VIN

VOUT

C

V_OUT≤ 5 V, V_IN= 7 V

IN

OUT

2.2µF

Input voltage range: 2.7 V to 20 V

Maximum output current: 200 mA

Initial accuracy: 0.8%

Accuracy over line, load, and temperature

−1.2% to +1.5%, T_J= −40°C to +85°C

1.8%, T_J= −40°C to +125°C

SENSE/ADJ

ON

EN

SS

C

GND

SS

1nF

OFF

Figure 1. ADP7118 with Fixed Output Voltage, 5 V

Low dropout voltage: 200 mV (typical) at a 200 mA load,

ADP7118

V

= 7V

V

= 6V

V_OUT= 5 V

IN

OUT

VIN

VOUT

User programmable soft start (LFCSP and SOIC only)

Low quiescent current, I_GND= 50 μA (typical) with no load

Low shutdown current: 1.8 μA at V_IN= 5 V, 3.0 μA at V_IN= 20 V

Stable with a small 2.2 µF ceramic output capacitor

Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, 4.5 V, and 5.0 V

16 standard voltages between 1.2 V and 5.0 V are available

Adjustable output from 1.2 V to V_IN– V_DO, output can be

adjusted above initial set point

C

OUT

2.2µF

IN

2kΩ

2.2µF

SENSE/ADJ

10kΩ

ON

EN

SS

C

GND

SS

1nF

OFF

Figure 2. ADP7118 with 5 V Output Adjusted to 6 V

Precision enable

2 mm × 2 mm, 6-lead LFCSP, 8-Lead SOIC, 5-Lead TSOT

AEC-Q100 qualified for automotive applications

APPLICATIONS

Regulation to noise sensitive applications

ADC and DAC circuits, precision amplifiers, power for

VCO V_TUNEcontrol

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation

Supported by ADIsimPower tool

GENERAL DESCRIPTION

The ADP7118 is a CMOS, low dropout (LDO) linear regulator

that operates from 2.7 V to 20 V and provides up to 200 mA of

output current. This high input voltage LDO is ideal for the

regulation of high performance analog and mixed-signal circuits

operating from 19 V down to 1.2 V rails. Using an advanced

proprietary architecture, the device provides high power supply

rejection, low noise, and achieves excellent line and load transient

response with a small 2.2 µF ceramic output capacitor. The

ADP7118 regulator output noise is 11 μV rms independent of

the output voltage for the fixed options of 5 V or less.

Additional voltages available by special order are 1.5 V, 1.85 V,

2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V, 3.8 V, 4.2 V, and 4.6 V.

Each fixed output voltage can be adjusted above the initial set

point with an external feedback divider. This allows the ADP7118

to provide an output voltage from 1.2 V to V_IN− V_DOwith high

PSRR and low noise.

User programmable soft start with an external capacitor is

available in the LFCSP and SOIC packages.

The ADP7118 is available in a 6-lead, 2 mm × 2 mm LFCSP

making it not only a very compact solution, but it also provides

excellent thermal performance for applications requiring up to

200 mA of output current in a small, low profile footprint. The

ADP7118 is also available in a 5-lead TSOT and an 8-lead SOIC.

The ADP7118 is available in 16 fixed output voltage options.

The following voltages are available from stock: 1.2 V

(adjustable), 1.8 V, 2.5 V, 3.3 V, 4.5 V, and 5.0 V.

Rev. F

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ADP7118

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications Information ............................................................. 14

ADIsimPower Design Tool ...................................................... 14

Capacitor Selection .................................................................... 14

Programable Precision Enable ................................................. 15

Soft Start ...................................................................................... 15

Noise Reduction of the ADP7118 in Adjustable Mode........ 16

Effect of Noise Reduction on Start-Up Time......................... 16

Current-Limit and Thermal Overload Protection ................ 17

Thermal Considerations ........................................................... 17

Printed Circuit Board Layout Considerations ........................... 20

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 23

Automotive Products ................................................................ 24

Applications ...................................................................................... 1

Typical Application Circuits........................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications .................................................................................... 3

Input and Output Capacitance, Recommended Specifications.. 4

Absolute Maximum Ratings ........................................................... 5

Thermal Data................................................................................ 5

Thermal Resistance...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions........................... 6

Typical Performance Characteristics............................................. 7

Theory of Operation ...................................................................... 13

REVISION HISTORY

9/2020—Rev. E to Rev. F

11/2016—Rev. B to Rev. C

Change to General Description Section........................................ 1

Changes to Shutdown Current Parameter, Table 1..................... 3

Change to Theory of Operation Section ..................................... 13

Change to Figure 50....................................................................... 16

Changes to Current-Limit and Thermal Overload

Protection Section .......................................................................... 17

Changes to Table 8 ......................................................................... 21

Changes to Ordering Guide.......................................................... 23

Changes to Features Section and General Description Section .......1

Changes to Ordering Guide...................................................................23

7/2016—Rev. A to Rev. B

Change to Table 5..............................................................................6

Change to Figure 42....................................................................... 13

Changes to Programmable Precision Enable Section and Soft

Start Section .................................................................................... 15

Added Effect of Noise Reduction on Start-Up Time Section .. 16

9/2019—Rev. D to Rev. E

Changes to Features Section ........................................................... 1

Change to Package Column, Table 9........................................... 21

Changes to Ordering Guide.......................................................... 23

Added Automotive Products Section.......................................... 24

12/2014—Rev. 0 to Rev. A

Changes to Figure 36 to Figure 41 ............................................... 12

Changes to Figure 44 ..................................................................... 14

9/2014—Revision 0: Initial Version

4/2018—Rev. C to Rev. D

Changes to Features Section ........................................................... 1

Updated Outline Dimensions....................................................... 22

Changes to Ordering Guide.......................................................... 23

Rev. F | Page 2 of 24

Data Sheet

ADP7118

SPECIFICATIONS

V_IN= V_OUT+ 1 V or 2.7 V, whichever is greater, V_OUT= 5 V, EN = V_IN, I_OUT= 10 mA, C_IN= C_OUT= 2.2 µF, C_SS= 0 pF, T_A= 25°C for typical

specifications, T_J= −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IN

Test Conditions/Comments

Min

Typ

Max

20

Unit

V

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

2.7

I_GND

I_OUT= 0 µA

50

80

180

1.8

3.0

140

190

320

µA

I_OUT= 10 mA

I_OUT= 200 mA

EN = GND

SHUTDOWN CURRENT

I_GND-SD

EN = GND, V_IN= 20 V

10

OUTPUT VOLTAGE ACCURACY

Output Voltage Accuracy

V_OUT

I_OUT= 10 mA, T_J= 25°C

100 μA < I_OUT< 200 mA, V_IN= (V_OUT+ 1 V) to 20 V,

T_J= −40°C to +85°C

–0.8

–1.2

+0.8

+1.5

%

100 μA < I_OUT< 200 mA, V_IN= (V_OUT+ 1 V) to 20 V

–1.8

+1.8

%

LINE REGULATION

∆V_OUT/∆V_INV_IN= (V_OUT+ 1 V) to 20 V

∆V_OUT/∆I_OUTI_OUT= 100 μA to 200 mA

–0.015

+0.015 %/V

LOAD REGULATION¹

SENSE INPUT BIAS CURRENT

DROPOUT VOLTAGE²

0.002 0.004

%/mA

nA

SENSE_I-BIAS

V_DROPOUT

100 μA < I_OUT< 200 mA V_IN= (V_OUT+ 1 V) to 20 V

10

1000

60

420

I_OUT= 10 mA

I_OUT= 200 mA

V_OUT= 5 V

30

mV

µs

200

380

1.15

360

START-UP TIME³

t_START-UP

SS_I-SOURCE

I_LIMIT

SOFT START SOURCE CURRENT

CURRENT-LIMIT THRESHOLD⁴

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

UNDERVOLTAGE THRESHOLDS

Input Voltage Rising

Input Voltage Falling

Hysteresis

SS = GND

µA

250

2.2

460

mA

TS_SD

T_Jrising

150

15

°C

TS_SD-HYS

UVLO_RISE

UVLO_FALL

UVLO_HYS

2.69

V

mV

230

PRECISION EN INPUT

Logic High

Logic Low

Logic Hysteresis

Leakage Current

2.7 V ≤ V_IN≤ 20 V

EN_HIGH

EN_LOW

EN_HYS

I_EN-LKG

t_EN-DLY

1.15

1.06

1.22

1.12

100

0.04

80

1.30

1.18

V

mV

µA

μs

EN = V_INor GND

1

Delay Time

From EN rising from 0 V to V_INto 0.1 × V_OUT

10 Hz to 100 kHz, all output voltage options

1 MHz, V_IN= 7 V, V_OUT= 5 V

100 kHz, V_IN= 7 V, V_OUT= 5 V

10 kHz, V_IN= 7 V, V_OUT= 5 V

OUTPUT NOISE

OUT_NOISE

11

µV rms

dB

POWER SUPPLY REJECTION RATIO PSRR

50

68

88

¹Based on an endpoint calculation using 100 μA and 200 mA loads. See Figure 7 for typical load regulation performance for loads less than 1 mA.

²Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output

voltages above 2.7 V.

³Start-up time is defined as the time between the rising edge of EN to OUT being at 90% of the nominal value.

⁴Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V or 4.5 V.

Rev. F | Page 3 of 24

ADP7118

Data Sheet

INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

INPUT AND OUTPUT CAPACITANCE

Minimum Capacitance¹

Capacitor Effective Series Resistance (ESR)

C_MIN

R_ESR

T_A= −40°C to +125°C

1.5

0.001

µF

Ω

0.3

¹The minimum input and output capacitance must be greater than 1.5 μF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,

while Y5V and Z5U capacitors are not recommended for use with any LDO.

Rev. F | Page 4 of 24

Data Sheet

ADP7118

ABSOLUTE MAXIMUM RATINGS

θ_JAof the package is based on modeling and calculation using a

Table 3.

4-layer board. The θ_JAis highly dependent on the application

and board layout. In applications where high maximum power

dissipation exists, close attention to thermal board design is

required. The value of θ_JAmay vary, depending on PCB material,

layout, and environmental conditions. The specified values of θ_JA

are based on a 4-layer, 4 inches × 3 inches circuit board. See

JESD51-7 and JESD51-9 for detailed information on the board

construction.

Parameter

Rating

VIN to GND

VOUT to GND

EN to GND

SENSE/ADJ to GND

SS to GND

–0.3 V to +24 V

–0.3 V to VIN

–0.3 V to +24 V

–0.3 V to +6 V

–0.3 V to VIN or

+6 V (whichever is

less)

Storage Temperature Range

Junction Temperature (T_J)

–65°C to +150°C

150°C

Ψ

_JBis the junction-to-board thermal characterization parameter

with units of °C/W. The Ψ_JBof the package is based on

–40°C to +125°C

modeling and calculation using a 4-layer board. The JESD51-12,

Guidelines for Reporting and Using Electronic Package Thermal

Information, states that thermal characterization parameters are

not the same as thermal resistances. Ψ_JBmeasures the component

power flowing through multiple thermal paths rather than a

single path as in thermal resistance (θ_JB). Therefore, Ψ_JBthermal

paths include convection from the top of the package as well as

radiation from the package, factors that make Ψ_JBmore useful

in real-world applications. Maximum T_Jis calculated from the

board temperature (T_B) and P_Dusing the formula

Operating Ambient Temperature (T_A)

Range

Soldering Conditions

JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

T_J= T_B+ (P_D× Ψ_JB)

(2)

THERMAL DATA

See JESD51-8 and JESD51-12 for more detailed information

about Ψ_JB.

Absolute maximum ratings apply individually only, not in

combination. The ADP7118 can be damaged when the junction

temperature limits are exceeded. Monitoring ambient temperature

does not guarantee that T_Jis within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature may

have to be derated.

THERMAL RESISTANCE

θ_JA, θ_JC, and Ψ_JBare specified for the worst-case conditions, that

is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type

6-Lead LFCSP

8-Lead SOIC

5-Lead TSOT

θ_JA

θ_JC

Ψ_JB

47.1

32.7

43

Unit

°C/W

In applications with moderate power dissipation and low

printed circuit board (PCB) thermal resistance, the maximum

ambient temperature can exceed the maximum limit as long as

the junction temperature is within specification limits. The

junction temperature of the device is dependent on the ambient

temperature, the power dissipation (P_D) of the device, and the

junction-to-ambient thermal resistance of the package (θ_JA).

72.1

52.7

170

42.3

41.5

N/A¹

¹N/A means not applicable.

ESD CAUTION

Maximum T_Jis calculated from the T_Aand P_Dusing the

formula

T_J= T_A+ (P_D× θ_JA)

(1)

Rev. F | Page 5 of 24

ADP7118

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VOUT

SENSE/ADJ

GND

1

2

3

6

5

4

VIN

ADP7118

SS

TOP VIEW

(Not to Scale)

EXPOSED PAD

EN

NOTES

1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE

ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE

PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED

PAD CONNECT TO THE GROUND PLANE ON THE BOARD.

Figure 3. 6-Lead LFCSP Pin Configuration

1

2

3

5

VIN

GND

EN

VOUT

ADP7118

TOP VIEW

(Not to Scale)

4

SENSE/ADJ

Figure 4. 5-Lead TSOT Pin Configuration

VOUT

1

2

3

4

8

7

6

5

VIN

SS

ADP7118

TOP VIEW

(Not to Scale)

SENSE/ADJ

GND

EN

NOTES

1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE

ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE

PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED

PAD CONNECT TO THE GROUND PLANE ON THE BOARD.

Figure 5. 8-Lead SOIC Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

6-Lead LFCSP

8-Lead SOIC

5-Lead TSOT

Mnemonic Description

1

1, 2

5

VOUT

Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or greater

capacitor.

2

3

4

SENSE/ADJ Sense Input (SENSE). Connect to load. An external resistor divider may

also set the output voltage higher than the fixed output voltage (ADJ).

3

4

5

2

3

GND

EN

Ground.

The enable pin controls the operation of the LDO. Drive EN high to turn

on the regulator. Drive EN low to turn off the regulator. For automatic

startup, connect EN to VIN.

5

6

Not applicable SS

Soft Start. An external capacitor connected to this pin determines the

soft-start time. Leave this pin open for a typical 380 μs start-up time. Do

not ground this pin.

Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater

capacitor.

7, 8

1

VIN

Not applicable EP

Exposed Pad. The exposed pad on the bottom of the package enhances

thermal performance and is electrically connected to GND inside the

package. It is recommended that the exposed pad connect to the

ground plane on the board.

Rev. F | Page 6 of 24

Data Sheet

ADP7118

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= V_OUT+ 1 V or 2.7 V, whichever is greater, V_OUT= 5 V, I_OUT= 10 mA, C_IN= C_OUT= 2.2 µF, T_A= 25°C, unless otherwise noted.

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

300

250

200

150

100

50

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

0

–40

–5

25

85

125

–40

–5

25

85

125

JUNCTION TEMPERATURE (°C)

Figure 6. Output Voltage (V_OUT) vs. Junction Temperature

Figure 9. Ground Current vs. Junction Temperature

5.05

200

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

180

160

140

120

100

80

60

40

20

0

0.1

1

10

(mA)

100

1000

0.1

1

10

(mA)

100

1000

I

LOAD

Figure 7. Output Voltage (V_OUT) vs. Load Current (I_LOAD

)

Figure 10. Ground Current vs. Load Current (I_LOAD)

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

300

250

200

150

100

50

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

0

5

10

15

20

5

10

15

20

V

(V)

V

(V)

IN

Figure 8. Output Voltage (V_OUT) vs. Input Voltage (V_IN

)

Figure 11. Ground Current vs. Input Voltage (V_IN)

Rev. F | Page 7 of 24

ADP7118

Data Sheet

2.5

1000

900

800

700

600

500

400

300

200

100

0

LOAD = 5mA

V

= 2.7V

= 3V

= 5V

= 6V

= 10V

= 20V

IN

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

2.0

1.5

1.0

0.5

0

–50

–25

0

25

50

75

100

125

4.8

5.0

5.2

(V)

5.4

5.6

TEMPERATURE (°C)

V

IN

Figure 12. Shutdown Current vs. Temperature at Various Input Voltages

Figure 15. Ground Current vs. Input Voltage (V_IN) in Dropout, V_OUT= 5 V

250

3.35

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

200

150

100

50

3.33

3.31

3.29

3.27

3.25

0

1

10

100

1000

–40

–5

25

85

125

I

(mA)

JUNCTION TEMPERATURE (°C)

LOAD

Figure 16. Output Voltage (V_OUT) vs. Junction Temperature, V_OUT= 3.3 V

Figure 13. Dropout Voltage vs. Load Current (I_LOAD), V_OUT= 5 V

3.35

5.05

5.00

4.95

4.90

4.85

4.80

3.33

3.31

3.29

3.27

3.25

4.75

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

4.70

4.65

4.60

4.8

0.1

1

10

(mA)

100

1000

5.0

5.2

(V)

5.4 5.6

I

LOAD

V

IN

Figure 14. Output Voltage(V_OUT) vs. Input Voltage (V_IN) in Dropout, V_OUT= 5 V

Figure 17. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= 3.3 V

Rev. F | Page 8 of 24

Data Sheet

ADP7118

3.35

300

250

200

150

100

50

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

3.33

3.31

3.29

3.27

3.25

0

5

10

(V)

15

20

0

5

10

(V)

15

20

V

IN

Figure 18. Output Voltage (V_OUT) vs. Input Voltage (V_IN), V_OUT= 3.3 V

Figure 21. Ground Current vs. Input Voltage (V_IN), V_OUT= 3.3 V

300

250

200

150

100

50

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

250

LOAD = 200mA

200

150

100

50

0

1

10

100

1000

–40

–5

25

85

125

I

(mA)

JUNCTION TEMPERATURE (°C)

LOAD

Figure 19. Ground Current vs. Junction Temperature, V_OUT= 3.3 V

Figure 22. Dropout Voltage vs. Load Current (I_LOAD), V_OUT= 3.3 V

200

180

160

140

120

100

80

3.4

3.3

3.2

3.1

3.0

60

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

40

2.9

20

LOAD = 150mA

LOAD = 200mA

0

0.1

2.8

3.1

1

10

(mA)

100

1000

3.3

3.5

(V)

3.7 3.9

I

V

LOAD

IN

Figure 20. Ground Current vs. Load Current (I_LOAD), V_OUT= 3.3 V

Figure 23. Output Voltage (V_OUT) vs. Input Voltage (V_IN) in Dropout,

V_OUT= 3.3 V

Rev. F | Page 9 of 24

ADP7118

Data Sheet

700

600

500

400

300

200

100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

0

3.1

3.3

3.5

(V)

3.7

3.9

0.2

0.6

1.0

1.4

1.8

2.2

2.6

3.0

V

HEADROOM VOLTAGE (V)

IN

Figure 24. Ground Current vs. Input Voltage (V_IN) in Dropout, V_OUT= 3.3 V

Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

V_OUT= 1.8 V,for Different Frequencies

300

0

–20

–40

–60

V

= 2.7V

= 5.0V

= 10V

= 20V

IN

250

200

150

100

50

3.0V

2.0V

1.6V

1.4V

1.2V

1.0V

800mV

700mV

600mV

500mV

–80

–100

–120

0

–40

–5

25

85

125

10

100

1k

10k

100k

1M

10M

TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency, V_OUT= 3.3 V,

for Various Headroom Voltages

Figure 25. Soft Start (SS) Current vs. Temperature, Multiple Input Voltages,

V_OUT= 5 V

0

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

3.0V

2.0V

1.6V

1.4V

1.2V

1.0V

800mV

–10

–20

–30

700mV

600mV

–40

–50

–60

–70

–80

–90

–40

–50

–60

–70

–80

–90

–100

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

1

10

100

1k

10k

100k

1M

10M

HEADROOM VOLTAGE (V)

FREQUENCY (Hz)

Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

V_OUT= 3.3 V, for Different Frequencies

Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency, V_OUT= 1.8 V,

for Various Headroom Voltages

Rev. F | Page 10 of 24

Data Sheet

ADP7118

0

10k

1k

100

10

1

–20

–40

–60

3.0V

2.0V

1.6V

–80

1.4V

1.2V

1.0V

800mV

700mV

600mV

500mV

–100

–120

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 33. Output Noise Spectral Density vs. Frequency, I_LOAD= 10 mA

Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency, V_OUT= 5 V,

for Various Headroom Voltages

0

100k

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

100µA

1mA

10mA

100mA

200mA

–10

–20

10k

–30

–40

–50

–60

–70

–80

–90

1k

100

10

1

–100

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

1

10

100

1k

10k

100k

1M

10M

HEADROOM VOLTAGE (V)

FREQUENCY (Hz)

Figure 34. Output Noise Spectral Density vs. Frequency, for Different Loads

Figure 31. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

V_OUT= 5 V, for Different Frequencies

20

100k

1.8V

10Hz TO 100kHz

3.3V

5.0V

100Hz TO 100kHz

16

10k

1k

100

10

1

12

8

4

0

1

10

100

1000

1

10

100

1k

10k

100k

1M

10M

LOAD CURRENT (mA)

FREQUENCY (Hz)

Figure 35. Output Noise Spectral Density vs. Frequency for

Different Output Voltages

Figure 32. RMS Output Noise vs. Load Current

Rev. F | Page 11 of 24

ADP7118

Data Sheet

T

1

2

1

B

W

CH1 1V

CH2 2mV

M4µs

10.2%

A

CH4

1.84V

B

W

CH1 200mA Ω

CH2 20mV

M20µs A CH1

T 10.2%

1000mA

W

T

Figure 36. Load Transient Response, I_LOAD= 1 mA to 200 mA,

V_OUT= 5 V, V_IN= 7 V, CH1 Load Current, CH2 V_OUT

Figure 39. Line Transient Response, I_LOAD= 200 mA,

V_OUT= 3.3 V, CH1 V_IN, CH2 V_OUT

T

1

2

1

2

B

W

B

W

CH1 2V

CH2 2mV

M4.0µs

10.2%

A

CH4

1.84V

CH1 200mA

Ω

CH2 20mV

M20µs

A

CH1

84mA

W

T

10.2%

Figure 37. Line Transient Response, I_LOAD= 200 mA,

V_OUT= 5 V, CH1 V_IN, CH2 V_OUT

Figure 40. Load Transient Response, I_LOAD= 1 mA to 200 mA,

V_OUT= 1.8 V, V_IN= 3 V, CH1 Load Current, CH2 V_OUT

T

1

2

1

2

B

CH1 200mA Ω

CH2 20mV

M20µs

A

CH1

148mA

B

CH1 1V

W

CH2 5mV

M4.0µs

93.4%

A

CH4

2.08V

W

T

10.4%

T

Figure 38. Load Transient Response, I_LOAD= 1 mA to 200 mA,

V_OUT= 3.3 V, V_IN= 5 V, CH1 Load Current, CH2 V_OUT

Figure 41. Line Transient Response, I_LOAD= 200 mA,

V_OUT= 1.8 V, CH1 V_IN, CH2 V_OUT

Rev. F | Page 12 of 24

Data Sheet

ADP7118

THEORY OF OPERATION

The ADP7118 is a low quiescent current, LDO linear regulator

that operates from 2.7 V to 20 V and provides up to 200 mA of

output current. Drawing a low 180 μA of quiescent current

(typical) at full load makes the ADP7118 ideal for portable

equipment. Typical shutdown current consumption is less than

3 µA at room temperature.

The ADP7118 is available in 16 fixed output voltage options,

ranging from 1.2 V to 5.0 V. The ADP7118 architecture allows

any fixed output voltage to be set to a higher voltage with an

external voltage divider. For example, a fixed 5 V output can be

set to a 6 V output according to the following equation:

V

_OUT= 5 V(1 + R1/R2)

(3)

Optimized for use with small 2.2 µF ceramic capacitors, the

ADP7118 provides excellent transient performance.

where R1 and R2 are the resistors in the output voltage divider

shown in Figure 43.

VOUT

To set the output voltage of the adjustable ADP7118, replace

5 V in Equation 3 with 1.2 V.

VIN

SENSE/

ADJ

SHORT-CIRCUIT,

THERMAL

PROTECTION

GND

ADP7118

V

= 7V

V

= 6V

OUT

IN

VIN

VOUT

REFERENCE

C

2.2µF

R1

C

OUT

2.2µF

IN

2kΩ

SENSE/ADJ

R2

10kΩ

EN

SHUTDOWN

ON

Figure 42. Internal Block Diagram

EN

SS

GND

C

1nF

SS

OFF

Internally, the ADP7118 consists of a reference, an error

amplifier, and a PMOS pass transistor. Output current is

delivered via the PMOS pass device, which is controlled by the

error amplifier. The error amplifier compares the reference

voltage with the feedback voltage from the output and amplifies

the difference. If the feedback voltage is lower than the

reference voltage, the gate of the PMOS device is pulled lower,

allowing more current to pass and increasing the output

voltage. If the feedback voltage is higher than the reference

voltage, the gate of the PMOS device is pulled higher, allowing

less current to pass and decreasing the output voltage.

Figure 43. Typical Adjustable Output Voltage Application Schematic

It is recommended that the R2 value be less than 200 kΩ to

minimize errors in the output voltage caused by the SENSE/ADJ

pin input current. For example, when R1 and R2 each equal

200 kΩ and the default output voltage is 1.2 V, the adjusted output

voltage is 2.4 V. The output voltage error introduced by the

SENSE/ADJ pin input current is 1 mV or 0.04%, assuming a

typical SENSE/ADJ pin input current of 10 nA at 25°C.

The ADP7118 uses the EN pin to enable and disable the

VOUT pin under normal operating conditions. When EN is

high, VOUT turns on, and when EN is low, VOUT turns off.

For automatic startup, EN can be tied to VIN.

Rev. F | Page 13 of 24

ADP7118

Data Sheet

APPLICATIONS INFORMATION

with a variety of dielectrics, each with different behavior over

temperature and applied voltage. Capacitors must have a dielectric

adequate to ensure the minimum capacitance over the necessary

temperature range and dc bias conditions. X5R or X7R dielectrics

with a voltage rating of 6.3 V to 100 V are recommended. Y5V

and Z5U dielectrics are not recommended, due to their poor

temperature and dc bias characteristics.

ADIsimPOWER DESIGN TOOL

The ADP7118 is supported by the ADIsimPower™ design tool

set. ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials, and

calculate performance in minutes. ADIsimPower can optimize

designs for cost, area, efficiency, and parts count, taking into

consideration the operating conditions and limitations of the IC

and all real external components. For more information about,

and to obtain ADIsimPower design tools, visit

Figure 45 depicts the capacitance vs. voltage bias characteristic

of an 0805, 2.2 µF, 10 V, X5R capacitor. The voltage stability of

a capacitor is strongly influenced by the capacitor size and

voltage rating. In general, a capacitor in a larger package or

higher voltage rating exhibits better stability. The temperature

variation of the X5R dielectric is ~ 15% over the −40°C to

+85°C temperature range and is not a function of package or

voltage rating.

www.analog.com/ADIsimPower.

CAPACITOR SELECTION

Output Capacitor

The ADP7118 is designed for operation with small, space-saving

ceramic capacitors, but functions with general-purpose capacitors

as long as care is taken with regard to the effective series resistance

(ESR) value. The ESR of the output capacitor affects the stability

of the LDO control loop. A minimum of 2.2 µF capacitance with

an ESR of 0.3 Ω or less is recommended to ensure the stability of

the ADP7118. Transient response to changes in load current is

also affected by output capacitance. Using a larger value of output

capacitance improves the transient response of the ADP7118 to

large changes in load current. Figure 44 shows the transient

responses for an output capacitance value of 2.2 µF.

2.5

2.0

1.5

1.0

0.5

0

T

0

2

4

6

8

10

12

1

DC BIAS VOLTAGE (V)

Figure 45. Capacitance vs. Voltage Characteristic

Use Equation 1 to determine the worst-case capacitance

accounting for capacitor variation over temperature, component

tolerance, and voltage.

2

C

_EFF= C_BIAS× (1 − TEMPCO) × (1 − TOL)

where:

_BIASis the effective capacitance at the operating voltage.

(4)

C

B

CH1 200mA Ω

CH2 20mV

M20µs

W

A

CH1

100mA

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

W

T

10.2%

Figure 44. Output Transient Response, V_OUT= 5 V, C_OUT= 2.2 µF, CH1 Load

Current, CH2 V_OUT

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and C_BIASis 2.09 μF at 5 V, as shown in Figure 45.

Input Bypass Capacitor

Connecting a 2.2 µF capacitor from VIN to GND reduces the

circuit sensitivity to the PCB layout, especially when long input

traces or high source impedance is encountered. If greater than

2.2 µF of output capacitance is required, increase the input

capacitor to match it.

These values in Equation 1 yield

C_EFF= 2.09 μF × (1 − 0.15) × (1 − 0.1) = 1.59 μF

(5)

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over temper-

ature and tolerance at the chosen output voltage.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADP7118, as long as they meet the minimum capacitance and

maximum ESR requirements. Ceramic capacitors are manufactured

To guarantee the performance of the ADP7118, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

Rev. F | Page 14 of 24

Data Sheet

ADP7118

PROGRAMABLE PRECISION ENABLE

SOFT START

The ADP7118 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. As shown in Figure 46,

when a rising voltage on EN crosses the upper threshold,

nominally 1.2 V, VOUT turns on. When a falling voltage on EN

crosses the lower threshold, nominally 1.1 V, VOUT turns off.

The hysteresis of the EN threshold is approximately 100 mV.

3.5

The ADP7118 uses an internal soft start (SS pin open) to limit the

inrush current when the output is enabled. The start-up time for

the 3.3 V option is approximately 380 µs from the time the EN

active threshold is crossed to when the output reaches 90% of

the final value. As shown in Figure 48, the start-up time is

independent on the output voltage setting.

6

V

EN

= 1.8V

= 3.3V

= 5.0V

OUT

3.0

2.5

2.0

1.5

1.0

5

4

3

2

1

0

0.5

0

–40°C

+25°C

+125°C

1.05

1.10

1.15

1.20

1.25

1.30

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

V

(V)

TIME (ms)

EN

Figure 48. Typical Start-Up Behavior

Figure 46. Typical V_OUTResponse to EN Pin Operation

An external capacitor connected to the SS pin determines the

soft start time. This SS pin can be left open for a typical 380 µs

start-up time. Do not ground this pin. When an external soft

start capacitor (C_SS) is used, the soft start time is determined by

the following equation:

The upper and lower thresholds are user programmable and

can be set higher than the nominal 1.2 V threshold by using

two resistors. The resistance values, R_EN1and R_EN2, can be

determined from the following:

R

_EN2= nominally 10 kΩ to 100 kΩ

(6)

(7)

SS_TIME(sec) = t_{START-UP at 0 pF}+ (0.6 × C_SS)/I_SS

where:

_{START-UP at 0 pF}is the start-up time at C_SS= 0 pF (typically 380 µs).

_SSis the soft start capacitor (F).

(8)

_EN1= R_EN2× (V_IN− 1.2 V)/1.2 V

where:

t

C

V

_INis the desired turn-on voltage.

The hysteresis voltage increases by the factor (R_EN1+ R_EN2)/R_EN2

For the example shown in Figure 47, the enable threshold is

3.6 V with a hysteresis of 300 mV.

.

I

_SSis the soft start current (typically 1.15 µA).

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

ADP7118

V

= 8V

V

= 6V

OUT

IN

VIN

VOUT

C

R1

C

OUT

2.2µF

IN

10kΩ

2.2µF

SENSE/ADJ

R2

20kΩ

R

EN1

ON

200kΩ

EN

GND

R

OFF

EN2

V

EN

100kΩ

NO SS CAP

1nF

2nF

4.7nF

6.8nF

10nF

Figure 47. Typical EN Pin Voltage Divider

Figure 46 shows the typical hysteresis of the EN pin. This pre-

vents on/off oscillations that can occur due to noise on the

EN pin as it passes through the threshold points.

0

1

2

3

4

5

6

7

8

9

10

TIME (ms)

Figure 49. Typical Soft Start Behavior, Different C_SS

Rev. F | Page 15 of 24

ADP7118

Data Sheet

•

Measured rms noise of the adjustable LDO without noise

reduction is 70 µV rms

Measured rms noise of the adjustable LDO with noise

reduction is 12 µV rms

NOISE REDUCTION OF THE ADP7118 IN

ADJUSTABLE MODE

The ultralow output noise of the ADP7118 is achieved by keeping

the LDO error amplifier in unity gain and setting the reference

voltage equal to the output voltage. This architecture does not

work for an adjustable output voltage LDO in the conventional

sense. However, the ADP7118 architecture allows any fixed

output voltage to be set to a higher voltage with an external

voltage divider. For example, a fixed 5 V output can be set to a

10 V output according to Equation 3 (see Figure 50):

Measured noise reduction of approximately 15.3 dB

Note that the measured noise reduction is less than the theoretical

noise reduction. Figure 51 shows the noise spectral density of an

adjustable ADP7118 set to 6 V and 12 V with and without the

noise reduction network. The output noise with the noise

reduction network is approximately the same for both voltages,

especially beyond 100 Hz. The noise of the 6 V and 12 V outputs

without the noise reduction network differs by a factor of 2 up to

approximately 20 kHz. Above 40 kHz, the closed loop gain of

the error amplifier is limited by the open loop gain characteristic.

Therefore, the noise contribution from 20 kHz to 100 kHz is

less than what it is if the error amplifier had infinite bandwidth.

This is also the reason why the noise is less than what might be

expected simply based on the dc gain, that is, 70 µV rms vs.

110 µV rms.

V

_OUT= 5 V(1 + R1/R2)

The disadvantage in using the ADP7118 in this manner is that

the output voltage noise is proportional to the output voltage.

Therefore, it is best to choose a fixed output voltage that is close

to the target voltage to minimize the increase in output noise.

The adjustable LDO circuit can be modified to reduce the

output voltage noise to levels close to that of the fixed output

ADP7118. The circuit shown in Figure 50 adds two additional

components to the output voltage setting resistor divider. C_NR

and R_NRare added in parallel with R1 to reduce the ac gain of

the error amplifier. R_NRis chosen to be small with respect to R2.

If R_NRis 1% to 10% of the value of R2, the minimum ac gain of

the error amplifier is approximately 0.1 dB to 0.8 dB. The actual

gain is determined by the parallel combination of R_NRand R1.

This gain ensures that the error amplifier always operates at

slightly greater than unity gain.

100k

12V NOISE REDUCTION

12V NO NOISE REDUCTION

6V NOISE REDUCTION

10k

1k

100

10

1

6V NO NOISE REDUCTION

C_NRis chosen by setting the reactance of C_NRequal toR1 − R_NR

at a frequency between 1 Hz and 50 Hz. This setting places the

frequency where the ac gain of the error amplifier is 3 dB down

from the dc gain.

1

10

100

1k

10k

100k

1M

10M

V

= 10V

VIN

VOUT

V

= 12V

OUT

2.2µF

IN

R1

+

C

2.2µF

FREQUENCY (Hz)

IN

+

C

100kΩ

NR

1µF

SENSE/ADJ

Figure 51. 6 V and 12 V Output Voltage with and Without Noise Reduction

Network

R

NR

10kΩ

ON

200kΩ

100kΩ

R2

100kΩ

OFF

EN

EFFECT OF NOISE REDUCTION ON START-UP TIME

The start-up time of the ADP7118 is affected by the noise

reduction network and must be considered in applications

where power supply sequencing is critical.

GND

Figure 50. Noise Reduction Modification

The noise reduction circuit adds a pole in the feedback loop,

slowing down the start-up time. To approximate the start-up time

for an adjustable model with a noise reduction network using the

following equation:

The noise of the adjustable LDO is found by using the

following formula, assuming the noise of a fixed output LDO is

approximately 11 μV.

Noise = 11 μV × (R_PAR+ R2)/R2

(9)

SSNR_TIME(sec) = 5.5 × C_NR× (R_NR+ R_FB1

)

where R_PARis a parallel combination of R1 and R_NR

.

For a C_NR, R_NR, and R1 combination of 1 µF, 10 kΩ, and 100 kΩ,

as shown in Figure 50, the start-up time is approximately 0.6 sec.

When SSNR_TIMEis greater than SS_TIME, SSNR_TIMEdictates the

length of the start-up time instead of the soft start capacitor.

Based on the component values shown in Figure 50, the ADP7118

has the following characteristics:

•

DC gain of 10 (20 dB)

3 dB roll-off frequency of 1.75 Hz

High frequency ac gain of 1.099 (0.82 dB)

Theoretical noise reduction factor of 9.1 (19.2 dB)

Rev. F | Page 16 of 24

Data Sheet

ADP7118

temperature changes. These parameters include ambient

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

temperature, power dissipation in the power device, and

thermal resistances between the junction and ambient air (θ_JA).

The θ_JAnumber is dependent on the package assembly

compounds that are used and the amount of copper used to

solder the package GND pins to the PCB.

The ADP7118 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADP7118 is designed to current limit when the

output load reaches 360 mA (typical). When the output load

exceeds 360 mA, the output voltage is reduced to maintain a

constant current limit.

Table 6 shows typical θ_JAvalues of the 8-lead SOIC, 6-lead LFCSP,

and 5-lead TSOT packages for various PCB copper sizes. Table 7

shows the typical Ψ_JBvalues of the 8-lead SOIC, 6-lead LFCSP,

and 5-lead TSOT.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and/or

high power dissipation) when the junction temperature starts

to rise above 150°C, the output is turned off, reducing the

output current to zero. When the junction temperature drops

below 135°C, the output is turned on again, and output current

is restored to the operating value.

Table 6. Typical θ_JAValues

θ

_JA(°C/W)

Copper Size (mm²)

25¹

LFCSP

182.8

N/A²

142.6

83.9

SOIC

N/A²

181.4

145.4

89.3

TSOT

N/A²

152

146

131

N/A²

50

100

500

1000

6400

Consider the case where a hard short from VOUT to ground

occurs. At first, the ADP7118 current limits, so that only 360 mA

is conducted into the short. If self heating of the junction is

great enough to cause the temperature to rise above 150°C,

thermal shutdown activates, turning off the output and reducing

the output current to zero. As the junction temperature cools

and drops below 135°C, the output turns on and conducts

360 mA into the short, again causing the junction

71.7

57.4

77.5

63.2

¹Device soldered to minimum size pin traces.

²N/A means not applicable.

Table 7. Typical Ψ_JBValues

Model

Ψ_JB(°C/W)

temperature to rise above 150°C. This thermal oscillation

between 135°C and 150°C causes a current oscillation

between 360 mA and 0 mA that continues as long as the short

remains at the output.

6-Lead LFCSP

8-Lead SOIC

5-Lead TSOT

24

38.8

43

To calculate the junction temperature of the ADP7118, use

Equation 1.

Current and thermal limit protections protect the device

against accidental overload conditions. For reliable operation,

device power dissipation must be externally limited so that the

junction temperature does not exceed 125°C.

T_J= T_A+ (P_D× θ_JA)

where:

THERMAL CONSIDERATIONS

T_Ais the ambient temperature.

P_Dis the power dissipation in the die, given by

In applications with a low input-to-output voltage differential,

the ADP7118 does not dissipate much heat. However, in

applications with high ambient temperature and/or high input

voltage, the heat dissipated in the package may become large

enough to cause the junction temperature of the die to exceed

the maximum junction temperature of 125°C.

P_D= [(V_IN− V_OUT) × I_LOAD] + (V_IN× I_GND

where:

_INand V_OUTare input and output voltages, respectively.

)

(10)

V

I

_LOADis the load current.

I

_GNDis the ground current.

When the junction temperature exceeds 150°C, the converter

enters thermal shutdown. It recovers only after the junction

temperature has decreased below 135°C to prevent any permanent

damage. Therefore, thermal analysis for the chosen application is

very important to guarantee reliable performance over all

conditions. The junction temperature of the die is the sum of

the ambient temperature of the environment and the temperature

rise of the package due to the power dissipation, as shown in

Equation 2.

Power dissipation due to ground current is quite small and can

be ignored. Therefore, the junction temperature equation

simplifies to the following:

T_J= T_A+ {[(V_IN− V_OUT) × I_LOAD] × θ_JA}

(11)

As shown in Equation 4, for a given ambient temperature, input-

to-output voltage differential, and continuous load current,

there exists a minimum copper size requirement for the PCB

to ensure that the junction temperature does not rise above 125°C.

Figure 52 to Figure 60 show junction temperature calculations

for different ambient temperatures, power dissipation, and

areas of PCB copper.

To guarantee reliable operation, the junction temperature of

the ADP7118 must not exceed 125°C. To ensure that the

junction temperature stays below this maximum value, the user

must be aware of the parameters that contribute to junction

Rev. F | Page 17 of 24

ADP7118

Data Sheet

140

120

100

80

145

135

125

115

105

95

85

60

75

65

40

T

= 25°C

= 50°C

= 65°C

= 85°C

MAX

55

B

J

2

6400mm

45

2

500mm

20

2

25mm

35

T

MAX

J

25

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

TOTAL POWER DISSIPATION (W)

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

TOTAL POWER DISSIPATION (W)

Figure 52. LFCSP, T_A= 25°C

Figure 55. SOIC, T_A= 25°C

140

130

120

110

100

90

140

130

120

110

100

90

80

70

2

6400mm

2

500mm

60

2

25mm

50mm

T

MAX

1.6

T

MAX

1.2

J

50

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.8

0

0.2

0.4

0.6

0.8

1.0

TOTAL POWER DISSIPATION (W)

Figure 53. LFCSP, T_A= 50°C

Figure 56. SOIC, T_A= 50°C

140

130

120

110

100

90

145

135

125

115

105

95

80

85

70

2

6400mm

2

500mm

75

60

2

25mm

50mm

T

MAX

1.6

T

MAX

J

50

65

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.8

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

TOTAL POWER DISSIPATION (W)

Figure 54. LFCSP, T_A= 85°C

Figure 57. SOIC, T_A= 85°C

Rev. F | Page 18 of 24

Data Sheet

ADP7118

145

135

125

115

105

95

The typical value of Ψ_JBis 24°C/W for the 8-lead LFCSP package,

38.8°C/W for the 8-lead SOIC package, and 43°C/W for the 5-lead

TSOT package.

140

120

100

80

85

75

65

55

2

500mm

100mm

50mm

45

60

2

35

T

MAX

J

25

40

T

= 25°C

= 50°C

= 65°C

= 85°C

MAX

B

J

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

TOTAL POWER DISSIPATION (W)

20

0

Figure 58. TSOT, T_A= 25°C

140

130

120

110

100

90

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

TOTAL POWER DISSIPATION (W)

Figure 61. LFCSP Junction Temperature Rise, Different Board Temperatures

140

120

100

80

70

2

500mm

100mm

50mm

60

2

T

MAX

J

40

50

T

= 25°C

= 50°C

= 65°C

= 85°C

MAX

B

J

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

TOTAL POWER DISSIPATION (W)

20

0

Figure 59. TSOT, T_A= 50°C

145

135

125

115

105

95

0

0.5

1.0

1.5

2.0

2.5

3.0

TOTAL POWER DISSIPATION (W)

Figure 62. SOIC Junction Temperature Rise, Different Board Temperatures

140

120

100

80

85

2

500mm

100mm

50mm

60

75

2

T

MAX

J

40

65

T

= 25°C

= 50°C

= 65°C

= 85°C

MAX

B

J

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

TOTAL POWER DISSIPATION (W)

20

0

Figure 60. TSOT, T_A= 85°C

0

0.5

1.0

1.5

2.0

2.5

In the case where the board temperature is known, use the thermal

characterization parameter, Ψ_JB, to estimate the junction

temperature rise (see Figure 61, Figure 62, and Figure 63).

Calculate the maximum junction temperature by using

Equation 2.

TOTAL POWER DISSIPATION (W)

Figure 63. TSOT Junction Temperature Rise, Different Board Temperatures

T_J= T_B+ (P_D× Ψ_JB)

Rev. F | Page 19 of 24

ADP7118

Data Sheet

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by increasing

the amount of copper attached to the pins of the ADP7118.

However, as listed in Table 6, a point of diminishing returns is

eventually reached, beyond which an increase in the copper size

does not yield significant heat dissipation benefits.

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Use of 0805 or 1206 size capacitors and

resistors achieves the smallest possible footprint solution on

boards where area is limited.

Figure 64. Example LFCSP PCB Layout

Figure 65. Example SOIC PCB Layout

Rev. F | Page 20 of 24

Data Sheet

ADP7118

Figure 66. Example TSOT PCB Layout

Table 8. Recommended LDOs for Very Low Noise Operation

Noise

(Fixed)

10 Hz to

100 kHz

(µV rms)

V_OUT

Adjust

I

_Qat

I_GND-SD

Max

(µA)

PSRR

100 kHz

(dB)

Device

Number

V_IN

V_OUT

I_OUT

(mA)

I_OUT

(µA)

Soft

Start

PSRR

1 MHz

Range (V) Fixed (V) (V)

P_GOOD

Package

ADP7102

ADP7104

ADP7105

ADP7112

ADP7118

3.3 to 20

2.7 to 20

1.5 to 9

1.22 to

19

300

500

200

750

900

180

75

10

No

Yes

15

11

60

68

40 dB

50 dB

3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

1.5 to 9

1.22 to

19

No

Yes

No

3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

1.8, 3.3, 5 1.22 to

19

Yes

3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

1.2 to 5

1.2 to 19

1 mm ×

1.2 mm

6-ball WLCSP

2 mm × 2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7142

ADP7182

2.7 to 40

1.2 to 5

1.2 to 39

200

180

10

−8

Yes

No

11

18

68

45

50 dB

45 dB

2 mm × 2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

−2.7 to

−28

−1.8 to

−5

−1.22 to

−27

−200

−650

2 mm × 2 mm

6-lead LFCSP,

3 mm × 3 mm

8-lead LFCSP,

5-lead TSOT

Table 9. Related Devices

Model

Input Voltage (V)

2.7 to 40

2.7 to 20

Output Current (mA)

Package

ADP7142ACP

ADP7142ARD

ADP7142AUJ

200

6-Lead LFCSP

8-Lead SOIC

5-Lead TSOT

6-Ball WLCSP

ADP7112ACB

Rev. F | Page 21 of 24

ADP7118

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

1.70

1.60

1.50

2.10

2.00 SQ

1.90

0.65 BSC

6

4

PIN 1 INDEX

EXPOSED

PAD

1.10

1.00

0.90

AREA

0.425

0.350

0.275

0.15 MIN

PIN 1

3

1

INDICATOR AR EA OP

(SEE DETAIL A)

TIONS

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.60

0.55

0.50

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.35

0.30

0.25

SEATING

PLANE

0.20 REF

Figure 67. 6-Lead Lead Frame Chip Scale Package [LFCSP]

2.00 mm × 2.00 mm Body and 0.55 mm Package Height

(CP-6-3)

Dimensions shown in millimeters

5.00

4.90

4.80

2.29

0.356

5

4

6.20

8

1

4.00

6.00

3.90

3.80

2.29

5.80

0.457

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

BOTTOM VIEW

45°

1.27 BSC

3.81 REF

TOP VIEW

SECTION OF THIS DATA SHEET.

1.65

1.25

1.75

1.35

0.50

0.25

0.17

0.10 MAX

0.05 NOM

SEATING

PLANE

8°

0°

0.51

0.31

1.04 REF

COPLANARITY

0.10

1.27

0.40

COMPLIANT TO JEDEC STANDARDS MS-012-AA

Figure 68. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-1)

Dimensions shown in millimeters

Rev. F | Page 22 of 24

Data Sheet

ADP7118

3.05

2.90

2.75

TOP VIEW

5

1

4

3

3.05

2.80

2.55

1.75

1.60

1.45

2

0.95 BSC

1.90 REF

0.90

0.70

SIDE VIEW

END VIEW

1.00 MAX

0.20

0.08

8°

4°

0°

SEATING

PLANE

0.10 MAX

0.50

0.30

0.60

0.45

0.30

COMPLIANT TO JEDEC STANDARDS MO-193-AB

Figure 69. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

Temperature Range

−40°C to +125°C

Output Voltage (V)^{3, 4}

Package Description

6-Lead LFCSP

Package Option Marking Code

ADP7118ACPZN-R7

ADP7118ACPZN1.8-R7

ADP7118ACPZN2.5-R7

ADP7118ACPZN3.3-R7

ADP7118ACPZN5.0-R7

ADP7118ARDZ

Adjustable (1.2 V)

1.8

2.5

3.3

CP-6-3

RD-8-1

UJ-5

LP9

LPA

LPB

LPC

LPD

5

6-Lead LFCSP

Adjustable (1.2 V)

1.8

2.5

3.3

8-Lead SOIC_N_EP

5-Lead TSOT

ADP7118ARDZ-R7

ADP7118ARDZ-1.8

ADP7118ARDZ-1.8-R7

ADP7118ARDZ-2.5

ADP7118ARDZ-2.5-R7

ADP7118ARDZ-3.3

ADP7118ARDZ-3.3-R7

ADP7118ARDZ-5.0

ADP7118ARDZ-5.0-R7

ADP7118AUJZ-R2

5

Adjustable (1.2 V)

LP9

LPA

LPB

LPC

LUU

LPD

LVL

LVM

LVN

LV8

ADP7118AUJZ-R7

UJ-5

ADP7118AUJZ-1.8-R7

ADP7118AUJZ-2.5-R7

ADP7118AUJZ-3.3-R7

ADP7118AUJZ-4.5-R7

ADP7118AUJZ-5.0-R7

ADP7118WAUJZ-1.8-R7

ADP7118WAUJZ-2.5-R7

ADP7118WAUJZ-3.3-R7

ADP7118WAUJZ-5.0-R7

ADP7118UJ-EVALZ

ADP7118CP-EVALZ

ADP7118RD-EVALZ

1.8

2.5

3.3

4.5

5

1.8

2.5

3.3

5

UJ-5

5-Lead TSOT

TSOT Evaluation Board

LFCSP Evaluation Board

SOIC Evaluation Board

¹Z = RoHS Compliant Part.

²W = Qualified for Automotive Applications.

³For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.

⁴The evaluation boards are preconfigured with an adjustable ADP7118.

Rev. F | Page 23 of 24

ADP7118

Data Sheet

AUTOMOTIVE PRODUCTS

The ADP7118W model is available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

registered trademarks are the property of their respective owners.

D11849-9/20(F)

Rev. F | Page 24 of 24


型号：	ADP7118ARDZ-3.3
厂家：	ADI
描述：	20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator
文件：	总24页 (文件大小：915K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP7118ARDZ-3.3 [ADI]

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