ADP7185ACPZN1.0-R7_技术文档

−500 mA, Ultralow Noise, High PSRR,

Low Dropout Linear Regulator

ADP7185

Data Sheet

FEATURES

TYPICAL APPLICATION CIRCUITS

Input voltage range: −2.0 V to −5.5 V

Maximum output current: −500 mA

EP

V

= –3.8V

VIN

VOUT

V

= –3.3V

IN

OUT

C

4.7µF

C

Fixed output voltage options: −0.5 V to −4.5 V

Adjustable output from −0.5 V to −V_IN+ 0.5 V

Low output noise: 4 μV rms from 100 Hz to 100 kHz

Noise spectral density: 20 nV/√Hz, 10 kHz to 1 MHz

PSRR at −500 mA load

IN

OUT

4.7µF

SENSE

ADP7185

+1.25V

0V

VA

C

1µF

C

OFF

EN

A

AFB

10nF

–1.3V

ON

VAFB

VREG

GND

68 dB at 10 kHz

50 dB at 100 kHz

C

REG

1µF

40 dB at 1 MHz

Figure 1. ADP7185 with Fixed Output Voltage, −3.3 V

Low dropout voltage: −190 mV typical at −500 mA load

Initial output voltage (V_OUT) accuracy: 0.5ꢀ

Output voltage accuracy over line, load, and temperature:

2.2ꢀ

Operating supply current (I_GND): −0.6 mA typical at no load

Low shutdown current: −2 μA typical at V_IN= −5.5 V

Stable with small 4.7 μF ceramic input and output capacitor

Positive or negative enable logic

EP

V

= –3V

OFF

VIN

EN

VOUT

V

= –2.5V

IN

OUT

C

4.7µF

C

IN

OUT

4.7µF

SENSE

ADP7185

+1.25V

0V

VA

R1

100kΩ

C

A

1µF

C

AFB

10nF

–1.3V

ON

VAFB

R2

24.9kΩ

Current-limit and thermal overload protection

8-lead, 2 mm × 2 mm LFCSP package

Supported by ADIsimPOWER voltage regulator design tool

VREG

GND

C

REG

1µF

Figure 2. ADP7185 with Adjustable Output Voltage, V_OUT= −2.5 V

APPLICATIONS

Regulation to noise sensitive applications: analog-to-digital

converters (ADCs), digital-to-analog converters (DACs),

precision amplifiers

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation

GENERAL DESCRIPTION

The ADP7185 is a complementary metal oxide semiconductor

(CMOS), low dropout (LDO) linear regulator that operates

from −2.0 V to −5.5 V and provides up to −500 mA of output

current. This high output current LDO is ideal for regulation of

high performance analog and mixed signal circuits operating

from −0.5 V down to −4.5 V. Using an advanced proprietary

architecture, the ADP7185 provides high power supple rejection

ratio (PSRR) and low noise, and it achieves excellent line and load

transient response with a small 4.7 μF ceramic output capacitor.

Additional voltages available by special order are −0.8 V, −0.9 V,

−1.3 V, −2.8 V, −4.2 V, and −4.5 V. An adjustable version is also

available which allows output voltages that range from −0.5 V to

−V_IN+ 0.5 V with an external feedback divider.

The enable logic feature is capable of interfacing with positive

or negative logic levels for maximum flexibility.

The ADP7185 regulator output noise is 4 μV rms independent

of the output voltage. The ADP7185 is available in an 8-lead,

2 mm × 2 mm LFCSP, making it not only a very compact

solution but also providing excellent thermal performance for

applications requiring up to −500 mA of output current in a

small, low profile footprint.

The ADP7185 is available in 15 fixed output voltage options.

The following voltages are available from stock: −0.5 V, −1.0 V,

−1.2 V, −1.5 V, −1.8 V, −2.0 V, −2.5 V, −3.0 V, and −3.3 V.

Rev. 0

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rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADP7185

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 13

Adjustable Mode Operation ..................................................... 13

Enable Pin Operation ................................................................ 13

Start-Up Time............................................................................. 14

Applications Information.............................................................. 15

ADIsimPower Design Tool ....................................................... 15

Capacitor Selection .................................................................... 15

Undervoltage Lockout (UVLO) ............................................... 16

Current-Limit and Thermal Overload Protection................. 16

Thermal Considerations............................................................ 17

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Applications....................................................................................... 1

Typical Application Circuits............................................................ 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Input and Output Capacitor Recommended Specifications... 4

Absolute Maximum Ratings............................................................ 5

Thermal Data................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

REVISION HISTORY

5/2017—Revision 0: Initial Version

Rev. 0 | Page 2 of 19

Data Sheet

ADP7185

SPECIFICATIONS

V_IN= (V_OUT− 0.5 V) or −2 V (whichever is more negative), EN = V_IN, I_OUT= −10 mA, C_IN= C_OUT= 4.7 μF, C_AFB= 10 nF, C_A= C_REG= 1 μF, T_A=

25°C for typical specifications, and T_J= −40°C to +125°C for minimum/maximum speciﬁcations, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IN

Test Conditions/Comments

Min

Typ

Max

−5.5

−500

−0.90

−7.0

−7

Unit

INPUT VOLTAGE RANGE

LOAD CURRENT

−2.0

V

I_LOAD

mA

OPERATING SUPPLY CURRENT

I_GND

I_OUT= 0 μA

I_OUT= −500 mA

−0.6

−5.5

−2

7

5

6

mA

SHUTDOWN CURRENT

OUTPUT NOISE¹

I_GND-SD

EN = GND, V_IN= −5.5 V

10 Hz to 100 kHz, C_AFB= 1 nF

10 Hz to 100 kHz, C_AFB= 10 nF

100 Hz to 100 kHz, C_AFB= 1 nF

100 Hz to 100 kHz, C_AFB= 10 nF

100 Hz, C_AFB= 1 nF

100 Hz, C_AFB= 10 nF

10 kHz to 1 MHz, C_AFB=1 nF to 1 ꢀF

I_OUT= −500 mA, V_OUT= −3.3 V, V_IN= −3.8 V

At 1 kHz

μA

OUT_NOISE

μV rms

nV/√Hz

4

NOISE SPECTRAL DENSITY¹

OUT_NSD

PSRR

300

100

20

POWER SUPPLY REJECTION RATIO¹

80

68

50

40

dB

V

At 10 kHz

At 100 kHz

At 1 MHz

OUTPUT VOLTAGE

Accuracy

V_OUT

–0.5

–4.5

+0.5

+2.2

I_OUT= −10 mA, T_A= 25°C

−1 mA < I_OUT< −500 mA, V_IN= (V_OUT− 0.5 V) –2.2

to −5.5 V

%

OUTPUT VOLTAGE REFERENCE FEEDBACK

V_AFBAccuracy

V_AFB

Adjustable model voltage reference

Adjustable model, −1 mA < I_OUT< −500 mA, −2.2

V_IN= (V_OUT− 0.5 V) to −5.5 V

−0.489 −0.5

−0.511

+2.2

V

%

LINE REGULATION

LOAD REGULATION²

INPUT BIAS CURRENT

SENSE

ΔV_OUT/∆V_INV_IN= (V_OUT− 0.5 V) to −5.5 V

∆V_OUT/∆I_OUTI_OUT= −1 mA to −500 mA

−0.1

+0.3

1.8

%/V

%/A

0.6

SENSE_I-BIAS

V_AFB-BIAS

−1 mA < I_OUT< −500 mA, V_IN= (V_OUT− 0.5 V)

to −5.5 V

−1 mA < I_OUT< −500 mA, V_IN= (V_OUT− 0.5 V)

to −5.5 V

−10

−30

nA

V_AFB

DROPOUT VOLTAGE³

V_DROPOUT

I_OUT= −100 mA

−60

−190 −360

mV

I_OUT= −500 mA

PULL-DOWN RESISTANCE

Output Voltage

Regulated Input Supply Voltage

Low-Noise Reference Voltage

START-UP TIME⁴

V_EN= 0 V

V_OUT= −1 V

V_REG= −1 V

V_A= −1 V

V_OUT-PULL

V_REG-PULL

V_A-PULL

280

1.3

61

15

55

4

Ω

kΩ

Ω

T_START-UP

V_OUT= −4.5 V, C_AFB= 1 nF, C_A= 1 μF

V_OUT= −4.5 V, C_AFB= 10 nF, C_A= 1 μF

V_OUT= −1.2 V, C_AFB= 1 nF, C_A= 1 μF

V_OUT= −1.2 V, C_AFB= 10 nF, C_A= 1 μF

V_OUT= −0.5 V, no C_AFB, C_A= 1 μF

ms

10

1.5

CURRENT-LIMIT THRESHOLD⁵

THERMAL SHUTDOWN

Threshold

I_LIMIT

−600

−900 −1100 mA

TS_SD

TS_SD-HYS

T_Jrising

150

15

°C

Hysteresis

Rev. 0 | Page 3 of 19

ADP7185

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

UNDERVOLTAGE LOCKOUT THRESHOLDS

Input Voltage

Rising

UVLO_RISE

UVLO_FALL

UVLO_HYS

−1.77

V

mV

Falling

Hysteresis

−1.58

−1.3

90

EN INPUT (NEGATIVE)

Logic High

Logic Low

−2 V ≤ V_IN≤ −5.5 V

V_OUT= off to on

V_OUT= on to off

V_EN-NEG-HIGH

V_{EN-NEG_LOW}

EN_HYS-NEG

I_EN-LKG

−1.16

V

mV

μA

−0.96 -0.88

191

Hysteresis

Leakage Current

EN INPUT (POSITIVE)

Logic High

Logic Low

Leakage Current

EN = V_INor GND

−2 V ≤ V_IN≤ −5.5 V

V_OUT= off to on

V_OUT= on to off

V_EN= 5 V, V_IN= −5.5 V

−0.25

V_EN-POS-HIGH

V_EN-POS-LOW

I_EN-LKG

0.96

0.89

4.0

1.25

6.0

V

μA

0.5

¹Guaranteed by characterization but not production tested.

²Based on an endpoint calculation using −1 mA and −500 mA loads.

³Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output

voltages below −2 V.

⁴Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.

⁵Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit threshold for a

−3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of −3.0 V, or −2.7 V.

INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

CAPACITANCE

T_A= −40°C to +125°C

Minimum C_INand C_OUTCapacitance¹

Minimum C_Aand C_REGCapacitance²

Minimum C_AFBCapacitance³

Capacitor Equivalent Series Resistance (ESR)

C_IN, C_OUT

C_A, C_REG

C_AFB

3.3

0.7

4.7

1

10

μF

nF

Ω

R_ESR

0.1

¹The minimum input and output capacitance must be greater than 3.3 μF over the full range of operating conditions. X7R and X5R type capacitors are recommended;

Y5V and Z5U capacitors are not recommended for use with any LDO.

²The minimum C_Aand C_REGcapacitance must be greater than 0.7 μF over the full range of operating conditions. X7R and X5R type capacitors are recommended; Y5V

and Z5U capacitors are not recommended for use with any LDO.

³The minimum C_AFBcapacitance must be greater than 0.7 nF over the full range of operating conditions. X7R and X5R type capacitors are recommended; Y5V and Z5U

capacitors are not recommended for use with any LDO.

Rev. 0 | Page 4 of 19

Data Sheet

ADP7185

ABSOLUTE MAXIMUM RATINGS

Table 3.

temperature (T_J) of the device is dependent on the ambient

temperature (T_A), the power dissipation of the device (P_D), and

the junction to ambient thermal resistance of the package (θ_JA).

Parameter

Rating

VIN to GND

VOUT to GND

+0.3 V to −6 V

+0.3 V to −V_IN

Use the following equation to calculate the junction temperature

(T_J) from the ambient temperature (T_A) and power dissipation (P_D):

EN to GND

VA to GND

VAFB to GND

VREG to GND

+5.0 V to −6 V

+0.3 V to −6 V

+0.3 V to −2.16 V

+0.3 V to −6 V

−65°C to +150°C

−40°C to +125°C

JEDEC J-STD-020

T_J= T_A+ (P_D× θ_JA)

The junction to ambient thermal resistance (θ_JA) of the package

is based on modeling and calculation using a 4-layer board. The

junction to ambient thermal resistance is highly dependent on

the application and board layout. In applications where high

maximum power dissipation exists, close attention to thermal

board design is required. The θ_JAvalue may vary, depending on

the PCB material, layout, and environmental conditions. The

specified θ_JAvalues are based on a 4-layer, 4 in. × 3 in. circuit board.

SENSE to GND

Storage Temperature Range

Operating Junction Temperature Range

Soldering Conditions

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Table 4. Thermal Resistance

THERMAL DATA

Package Type

θ_JA

θ_JC

Unit

Absolute maximum ratings apply individually only, not in

combination. The ADP7185 can be damaged when the junction

temperature limits are exceeded. Monitoring ambient temperature

does not guarantee that T_Jis within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature may

have to be derated.

CP-8-27

68.8

10.0

°C/W

ESD CAUTION

In applications with moderate power dissipation and low printed

circuit board (PCB) thermal resistance, the maximum ambient

temperature can exceed the maximum limit as long as the

junction temperature is within specification limits. The junction

Rev. 0 | Page 5 of 19

ADP7185

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VOUT

SENSE

VA

1

2

3

4

8

7

6

5

VIN

VREG

GND

EN

ADP7185

TOP VIEW

(Not to Scale)

VAFB

NOTES

1. EXPOSED PAD. THE EXPOSED PAD ENHANCES THE

THERMAL PERFORMANCE AND IS ELECTRICALLY

CONNECTED TO VIN INSIDE THE PACKAGE. IT IS

RECOMMENDED THAT THE EXPOSED PAD CONNECT

TO THE INPUT VOLTAGE PLANE ON THE BOARD.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

VOUT

SENSE

VA

Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor.

Sense Input. Connect this pin to VOUT.

Low Noise Reference Voltage. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground.

Output Voltage Reference Feedback (Adjust Mode). Connect a 1 nF to 1 μF capacitor between the VAFB pin and

the VA pin to reduce noise. Start-up time is increased as a function of the capacitance. Connect an external resistor

divider between the VA pin and the VAFB pin to set the output voltage in adjust mode.

VAFB

5

EN

Enable. Drive EN at least +1.25 V above or −1.3 V below ground to enable the regulator or drive EN to ground to

turn the regulator off. For automatic startup, connect EN to VIN.

6

7

GND

VREG

Ground.

Regulated Input Supply to the LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not

connect a load to ground.

8

VIN

EP

Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor.

Exposed pad. The exposed pad enhances the thermal performance and is electrically connected to VIN inside the

package. It is recommended that the exposed pad connect to the input voltage plane on the board.

Rev. 0 | Page 6 of 19

Data Sheet

ADP7185

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= −3.8 V, V_OUT= −3.3 V, I_OUT= −10 mA, C_IN= C_OUT= 4.7 μF, C_AFB= 10 nF, C_A= C_REG= 1 μF, and T_A= 25°C, unless otherwise noted.

–1.186

–1.191

–1.196

–1.201

–1.206

–1.211

–1.216

0

–1

–2

–3

–4

–5

–6

–7

–8

NO LOAD

I

= –10mA

= –100mA

= –300mA

= –500mA

LOAD

NO LOAD

I

= –10mA

LOAD

= –100mA

= –300mA

= –500mA

–60 –40 –20

0

20

40

60

80

100 120 140

–40

–15

10

35

60

85

110

135

TEMPERATURE (°C)

JUNCTION TEMPERATURE (°C)

Figure 4. Output Voltage (V_OUT) vs. Junction Temperature, V_OUT= −1.2 V

Figure 7. Ground Current vs. Junction Temperature (T_J), V_OUT= −1.2 V

–1.186

–1.191

–1.196

–1.201

–1.206

–1.211

–1.216

0

–1

–2

–3

–4

–5

–6

–1000

–100

(mA)

–10

–500 –450 –400 –350 –300 –250 –200 –150 –100 –50

0

I

LOAD

I

(mA)

LOAD

Figure 5. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= −1.2 V

Figure 8. Ground Current vs. Load Current (I_LOAD), V_OUT= −1.2 V

–1.186

–1.196

–1.206

–1.216

0

–1

–2

–3

–4

–5

–1.226

NO LOAD

–6

–7

–8

NO LOAD

I

= –10mA

= –100mA

= –300mA

= –500mA

LOAD

I

= –10mA

–1.236

–1.246

LOAD

= –100mA

= –300mA

= –500mA

–5.5

–5.0

–4.5

–4.0

–3.5

(V)

–3.0

–2.5

–2.0

–5.5

–5.0

–4.5

–4.0

–3.5

(V)

–3.0

–2.5

–2.0

V

IN

V

IN

Figure 6. Output Voltage (V_OUT) vs. Input Voltage (V_IN), V_OUT= −1.2 V

Figure 9. Ground Current vs. Input Voltage (V_IN), V_OUT= −1.2 V

Rev. 0 | Page 7 of 19

ADP7185

Data Sheet

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–2.435

–2.455

–2.475

–2.495

–2.515

–2.535

–2.555

–2.575

V

= –2.0V

= –2.5V

= –3.0V

= –3.5V

= –4.0V

= –4.5V

= –5.0V

= –5.5V

IN

NO LOAD

I

= –10mA

= –100mA

= –300mA

= –500mA

LOAD

–5.0

–40

–15

10

35

60

85

110

135

–5.5

–5.0

–4.5

–4.0

–3.5

–3.0

JUNCTION TEMPERATURE (°C)

V

(V)

IN

Figure 10. Shutdown Current vs. Junction Temperature at Various Input Voltages,

V_OUT= −1.2 V

Figure 13. Output Voltage (V_OUT) vs. Input Voltage (V_IN), V_OUT= −2.5 V

–2.435

0

–1

–2

–3

–4

–5

–6

NO LOAD

I

= –10mA

= –100mA

= –300mA

= –500mA

LOAD

–2.455

–2.475

–2.495

–2.515

–2.535

–2.555

–60 –40 –20

0

20

40

60

80

100 120 140

–500 –450 –400 –350 –300 –250 –200 –150 –100 –50

0

TEMPERATURE (°C)

I

(mA)

LOAD

Figure 11. Output Voltage (V_OUT) vs. Junction Temperature (T_J), V_OUT= −2.5 V

Figure 14. Ground Current vs. Load Current (I_LOAD), V_OUT= −2.5 V

–2.455

0

–1

–2

–3

–4

–5

–2.475

–2.495

–2.515

–2.535

–2.555

–6

–7

–8

I

= –10mA

LOAD

= –100mA

= –200mA

= –300mA

= –500mA

–1000

–100

(mA)

–10

–5.5

–5.0

–4.5

–4.0

–3.5

–3.0

I

LOAD

V

(V)

IN

Figure 12. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= −2.5 V

Figure 15. Ground Current vs. Input Voltage (V_IN), V_OUT= −2.5 V

Rev. 0 | Page 8 of 19

Data Sheet

ADP7185

–3.249

–3.269

–3.289

–3.309

–3.329

–3.349

–3.369

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

–1000

–100

(mA)

–10

–1000

–100

(mA)

–10

I

LOAD

Figure 16. Dropout Voltage vs Load Current (I_LOAD), V_OUT= −2.5 V

Figure 19. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= −3.3 V

–2.24

–3.26

NO LOAD

–2.26

–2.28

–2.30

–2.32

–2.34

–2.36

–2.38

–2.40

–2.42

–2.44

–2.46

–2.48

–2.50

–2.52

I

= –10mA

I

= –10mA

LOAD

= –100mA

= –300mA

= –500mA

= –100mA

= –300mA

= –500mA

–3.28

–3.30

–3.32

–3.34

–3.36

–3.38

–3.1

–3.0

–2.9

–2.8

–2.7

(V)

–2.6

–2.5

–2.4

–5.5

–5.3

–5.1

–4.9

–4.7

–4.5

–4.3

–4.1

–3.9

V

(V)

IN

Figure 17. Output Voltage (V_OUT) vs. Input Voltage (V_IN) in Dropout at

Various Loads, V_OUT= −2.5 V

Figure 20. Output Voltage (V_OUT) vs. Input Voltage (V_IN), V_OUT= −3.3 V

–3.239

0

–1

–2

–3

–4

–5

NO LOAD

I

= –10mA

= –100mA

= –300mA

= –500mA

LOAD

–3.259

–3.279

–3.299

–3.319

–3.339

–3.359

–6

–7

–8

NO LOAD

I

= –10mA

= –100mA

= –300mA

= –500mA

LOAD

–60 –40 –20

0

20

40

60

80

100 120 140

–40

–15

10

35

60

85

110

135

TEMPERATURE (°C)

JUNCTION TEMPERATURE (°C)

Figure 18. Output Voltage (V_OUT) vs. Junction Temperature (T_J), V_OUT= −3.3 V

Figure 21. Ground Current vs. Junction Temperature (T_J), V_OUT= −3.3 V

Rev. 0 | Page 9 of 19

ADP7185

Data Sheet

0

–20

0

–1

–2

–3

–4

–5

–6

–40

–60

–80

–100

–120

–140

–160

–180

–200

–500 –450 –400 –350 –300 –250 –200 –150 –100 –50

0

–1000

–100

(mA)

–10

I

(mA)

I

LOAD

Figure 22. Ground Current vs. Load Current (I_LOAD), V_OUT= −3.3 V

Figure 25. Dropout Voltage vs. Load Current (I_LOAD), V_OUT= −3.3 V

0

–1

–2

–3

–4

–5

–3.14

NO LOAD

–3.16

–3.18

–3.20

–3.22

–3.24

–3.26

–3.28

–3.30

–3.32

I

= –10mA

= –100mA

= –300mA

= –500mA

LOAD

–6

–7

–8

NO LOAD

I

= –10mA

= –100mA

= –300mA

= –500mA

LOAD

–5.5

–5.3

–5.1

–4.9

–4.7

–4.5

–4.3

–4.1

–3.9

–3.8

–3.7

–3.6

–3.5

(V)

–3.4

–3.3

–3.2

V

(V)

V

IN

Figure 23. Ground Current vs. Input Voltage (V_IN), V_OUT= −3.3 V

Figure 26. Output Voltage (V_OUT) vs. Input Voltage (V_IN) in Dropout at

Various Loads, V_OUT= −3.3 V

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

0

–5

–10

–15

V

= –3.8V

= –4.0V

= –4.5V

= –5.0V

= –5.5V

IN

–4.0

–4.5

–5.0

–20

–25

I

= –10mA

= –100mA

= –300mA

= –500mA

LOAD

–40

–20

0

20

40

60

80

100

120

140

–3.9

–3.7

–3.5

–3.3

(V)

–3.1

–2.9

–2.7

JUNCTION TEMPERATURE (°C)

V

IN

Figure 24. Shutdown Current vs. Junction Temperature at

Various Input Voltages, V_OUT= −3.3 V

Figure 27. Ground Current vs. Input Voltage (V_IN) in Dropout at

Various Loads, V_OUT= −3.3 V

Rev. 0 | Page 10 of 19

Data Sheet

ADP7185

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

V

= –2.0V

= –2.1V

= –2.2V

= –2.3V

= –2.4V

= –2.5V

I

= –10mA

IN

LOAD

= –100mA

= –200mA

= –300mA

= –500mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Input Voltages, V_OUT= −1.2 V, I_LOAD= −500 mA

Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Loads, V_OUT= −1.2 V, V_IN= −2 V

0

V

= –3.0V

= –3.1V

= –3.2V

= –3.3V

= –3.4V

= –3.5V

IN

I

= –10mA

LOAD

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

= –100mA

= –200mA

= –300mA

= –500mA

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Input Voltages, V_OUT= −2.5 V, I_LOAD= −500 mA

Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Loads, V_OUT= −2.5 V, V_IN= −3 V

0

V

= –3.8V

= –3.9V

= –4.0V

= –4.1V

= –4.2V

= –4.3V

IN

I

= –10mA

LOAD

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–10

–20

= –100mA

= –200mA

= –300mA

= –500mA

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Input Voltages, V_OUT= −3.3 V, I_LOAD= −500 mA

Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Loads, V_OUT= −3.3 V, V_IN= −3.8 V

Rev. 0 | Page 11 of 19

ADP7185

Data Sheet

4.40

4.35

4.30

4.25

4.20

4.15

4.10

4.05

4.00

3.95

3.90

3.85

10Hz TO 100kHz

100Hz TO 100kHz

V

IN

1

V

OUT

2

3.80

–1000

CH1 995mV CH2 –20.5mV 5.0µs/DIV

500mV/DIV 2.0mV 1MS 20GS/s

STOP 40mV

EDGE POSITIVE

–100

LOAD CURRENT (mA)

–10

Figure 37. Line Transient Response, 500 mV Step, V_OUT= −3.3 V, I_LOAD= −500 mA

Figure 34. RMS Noise vs. Load Current (I_LOAD) at Various Frequencies,

V_IN= −3.8 V, V_OUT= −3.3 V

10k

–1.2V

–2.5V

–3.3V

–4.5V

V

OUT

1k

100

10

–4.5V ADJ

2

1

I

LOAD

1

0.1

10

CH1 –475mA CH2 5.0mV

500mA/DIV 9.9mV

10.0µs/DIV

2MS 20GS/s

STOP –220mA

EDGE POSITIVE

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 38. Load Transient Response, V_OUT= −1.2 V, I_LOAD= −10 mA to −500 mA

Figure 35. Noise Spectral Density (NSD) vs. Frequency at Various Output Voltages,

V_IN= −3.8 V, V_OUT= −3.3 V

V

IN

V

OUT

1

2

V

OUT

1

2

I

LOAD

CH1 –215.0mA CH2 3.6mV 10.0µs/DIV

200mA/DIV 2.0mV 2MS 20GS/s

STOP –222mA

EDGE POSITIVE

CH1 995mV CH2 –2.00mV 5.0µs/DIV

500mV/DIV 2.0mV 1MS 20GS/s

STOP 40mV

EDGE POSITIVE

Figure 39. Load Transient Response, V_OUT= −2.5 V, I_LOAD= −10 mA to −500 mA

Figure 36. Line Transient Response, 500 mV Step, V_OUT= −1.2 V, I_LOAD= −500 mA

Rev. 0 | Page 12 of 19

Data Sheet

ADP7185

THEORY OF OPERATION

The ADP7185 is a low quiescent current, LDO linear regulator

that operates from −2.0 V to −5.5 V and can provide up to

−500 mA of output current. Total integrated output noise is

4 μV rms independent of the output voltage, making it ideal for

high performance and noise sensitive applications. Shutdown

current consumption is −7 μA (maximum).

R2 resistors that are connected across the VA and VAFB pins.

Because the reference voltage to the LDO regulator already

adjusts according to the desired V_OUT, the LDO regulator now

connects in a buffer configuration for improved noise performance.

If the load draws higher current, the LDO regulator pulls the gate

of the NMOS device higher towards GND to allow more current

to pass. If the load draws less current, the LDO regulator pulls

the gate of the NMOS device lower toward −V_INto restrict the

amount of current passing through the device.

The ADP7185 is optimized for use with a 4.7 μF ceramic

capacitor for excellent transient performance. Using advanced

proprietary architecture, the ADP7185 provides ultralow noise

and high power supply rejection up to high frequencies of

operation. Figure 40 shows the fixed output voltage internal block

diagram of the ADP7185, and Figure 41 shows the adjustable

output voltage internal block diagram of the ADP7185.

ADJUSTABLE MODE OPERATION

The adjustable mode version of the ADP7185 has an output that

can be set to from −0.5 V to −4.5 V by an external voltage divider.

To calculate the output voltage, use the following equation:

V

_OUT= −0.5 V(1 + R1/R2)

(1)

R2

VAFB

VA

Figure 42 shows an example of an adjustable setting where R1 =

280 kΩ and R2 = 49.9 kΩ, setting the output voltage to −3.3 V.

SENSE

VOUT

R1

R2 must be at least 10 kΩ to maximize PSRR performance.

–0.5V

REFERENCE

G

M

EP

V

= –3.8V

VIN

VOUT

V

= –3.3V

OUT

GND

IN

C

4.7µF

OUT

OVER CURRENT

THERMAL

PROTECTION

C

4.7µF

VREG

SENSE

IN

VREG

EN

C

REG

1µF

ADP7185

GND

EN

VA

REG

EN

R1

280kΩ

C

A

1µF

C

AFB

10nF

+1.25V

0V

VAFB

OFF

VIN

R2

49.9kΩ

–1.3V

ON

Figure 40. Fixed Output Voltage Internal Block Diagram

Figure 42. Setting the Adjustable Output Voltage

R2

R1

VAFB

VA

ENABLE PIN OPERATION

The ADP7185 uses the EN pin to enable and disable the VOUT pin

under normal operating conditions. When EN is +1.25 V above or

−1.3 V below with respect to GND, VOUT turns on, and when

EN is at 0 V, VOUT turns off, as shown in Figure 43. For

automatic startup, connect EN to VIN.

SENSE

VOUT

–0.5V

REFERENCE

G

M

GND

OVER CURRENT

THERMAL

PROTECTION

VREG

EN

REG

EN

VIN

Figure 41. Adjustable Output Voltage Internal Block Diagram

2

Internally, the ADP7185 consists of a regulator block, reference

block, G_Mamplifier, feedback voltage divider, LDO regulator, and an

N-channel MOSFET pass transistor. The regulator block produces

an internal voltage rail (V_REG) of −1.8 V to serve as the supply

voltage for the succeeding internal blocks. The G_Mamplifier

produces a reference voltage (V_A) used as a reference to the

LDO regulator.

V

OUT

CH1 1.0V

–15mV

CH2 1.0V

0mV

200ms/DIV

A

CH2

40mV

2MS 1MS/s

Figure 43. Typical EN Pin Operation

For fixed option models, the VA voltage is generated through the

resistor divider ratio depending on the V_OUToption. For adjustable

models, the V_Avoltage generates externally through the R1 and

Rev. 0 | Page 13 of 19

ADP7185

Data Sheet

0.5

0

START-UP TIME

EN

C

= 1nF

AFB

= 10nF

= 100nF

= 1µF

When the output is enabled, the ADP7185 uses an internal soft

start to limit the inrush current. The start-up time for a −1.2 V

output is approximately 12 ms from the time the EN active

threshold is crossed to the time when the output reaches 90%

of its final value (see Figure 44). As shown in Figure 44 and

Figure 45, the start-up time is dependent upon the output

voltage option and the value of the C_AFBcapacitor.

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

1

EN

V

= –4.5V

= –3.3V

= –2.5V

= –1.2V

OUT

0

–1

–2

–3

–4

–5

–6

10

30

50

70

90 110 130 150 170 190 210 230

TIME (ms)

Figure 45. Start-Up Time at Various C_AFBCapacitor Values, C_A= 1 μF

A second time constant, τ₂, is dependent mainly on C_AFB. Figure 45

shows how the C_AFBvalue affects the start-up time. Estimate τ₂by

τ₂≈ C_AFB× R1

(3)

The R1 value scales vs. the V_OUToption. Table 6 shows the R1

value depending on the fixed output voltage option, whereas R2

is constant at 500 kΩ. For example, at a fixed V_OUT= −3.3 V, R1

equals 2.8 MΩ. To keep τ₂at a minimum, it is recommended that

C_AFBbe in the approximately nanofarad range. A typical setup for

the ADP7185 is C_AFB= 10 nF; therefore, τ₂= 28 ms. The total

time constant, τ_TOTAL, is the sum of τ₁and τ₂. At 2.2 × τ_TOTAL, VA is

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

TIME (ms)

Figure 44. Start-Up Time at Various Output Voltages, C_AFB= 10 nF, C_A= 1 μF

The total start-up time depends mostly on the C_Aand C_AFB

values expressed by the τ₁and τ₂equations (see Equation 2 and

Equation 3). During startup, an internal circuit, G_{M_START}, turns

on and helps charge C_Aup to 90% of the final value. Estimate the

first time constant, τ₁, due to C_Aby

equal to ~90% of the final value. Therefore, for a fixed V_OUT

−3.3 V, the output voltage is ~90% of the final value after 63.8 ms.

=

Table 6. R1 and R2 Values for the Fixed Output Options

Output Voltage (V)

τ₁≈ C_A× ((R1 + R2)//Z_OUT

)

(2)

R1 (Ω)

700 k

2 M

2.8 M

4 M

R2 (kΩ)

During this time, keep Z_OUTlow to approximately 1 kΩ to allow

quick start-up times, keeping τ₁in the order of 1 ms.

−1.2

−2.5

−3.3

−4.5

500

Note that τ₁and τ₂are estimates only and do not take into account

that G_Mand Z_OUTdynamically change. It is an accurate estimate

of ~90% of the start-up time for the C_AFB< 10 nF recommended

setup, where ~100% of the settling time can easily be achieved.

Note that for setups with C_AFB>> 10 nF, the equation may not

hold true anymore. However, it is still a convenient estimate on

the amount of time needed to achieve ~100% of the settling time.

Rev. 0 | Page 14 of 19

Data Sheet

ADP7185

APPLICATIONS INFORMATION

C_Aand C_AFBCapacitors

ADIsimPOWER DESIGN TOOL

The ultralow output noise of the ADP7185 is achieved by

keeping the LDO error amplifier in unity gain and setting the

reference voltage equal to the output voltage. In this architecture,

the resistor driven by the G_Mamplifier adjusts the reference

voltage to the selected output voltage. To ensure the G_Mamplifier

stability, the C_Acapacitor is needed to generate the dominant

pole and to keep the G_Mamplifier stable across all conditions.

C_Aalso serves as a dampening capacitor to the inputs of the

LDO error amplifier for improved PSRR. However, the LDO

output noise scales by the G_Mamplifier amount of gain as a

function of the output voltage. To minimize the output voltage

noise contributed by the G_Mamplifier, the C_AFBcapacitor must

be connected between the VA and VAFB pins to keep the ac

gain of the G_Mamplifier in unity.

The ADIsimPower™ design tool set supports the ADP7185.

ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials,

and calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and parts count,

taking into consideration the operating conditions and

limitations of the IC and all external components. For more

information about, and to obtain ADIsimPower design tools,

visit www.analog.com/ADIsimPower.

CAPACITOR SELECTION

Output Capacitor

The ADP7185 operates with small, space-saving ceramic

capacitors; however, it also functions with general-purpose

capacitors as long as care is taken with regard to the effective

series resistance (ESR) value. The ESR of the output capacitor

affects the stability of the LDO regulator control loop. A

minimum of 4.7 μF capacitance with an ESR of 0.05 Ω or less is

recommended to ensure the stability of the ADP7185. Output

capacitance affects the transient response to changes in load

currents. Using a larger value for the output capacitance improves

the transient response of the ADP7185 to large changes in load

current. Figure 46 shows the transient response for an output

capacitance value (C_OUT) of 4.7 μF.

GND

R2

C

A

VAFB

VA

C

R1

AFB

G

M

REFERENCE

Figure 47. C_Aand C_AFBConnection to the G_MAmplifier

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADP7185 if they meet the minimum capacitance and maximum

ESR requirements. Ceramic capacitors are manufactured with a

variety of dielectrics, each with different behavior over temperature

and applied voltage. Capacitors must have a dielectric adequate to

ensure the minimum capacitance over the necessary temperature

range and dc bias conditions. X5R and X7R dielectrics with a

voltage rating from 6.3 V to 10 V are recommended. Due to their

poor temperature and dc bias characteristics, Y5V and Z5U

dielectrics are not recommended.

V

OUT

2

1

I

LOAD

CH1 –475mA CH2 5.0mV

500mA/DIV 9.9mV

10.0µs/DIV

2MS 20GS/s

STOP –220mA

EDGE POSITIVE

Figure 46. Output Transient Response, C_OUT= 4.7 ꢀF, V_OUT= −1.2 V

Input Bypass Capacitor

Connecting a 4.7 μF or greater capacitor from VIN to GND

reduces the circuit sensitivity to the PCB layout, especially when

long input traces or high source impedance are encountered.

When more than 4.7 μF of output capacitance is required,

increase the input capacitance to match it.

Rev. 0 | Page 15 of 19

ADP7185

Data Sheet

Figure 48 shows the change in capacitance vs. the dc bias voltage

characteristics of a 0805 case, 4.7 μF, 10 V, X5R capacitor. The

capacitor size and voltage ratings strongly influence the voltage

stability of a capacitor. In general, a capacitor in a larger package

or with a higher voltage rating exhibits improved stability. The

temperature variation of the X5R dielectric is about 15% over

the −55°C to +85°C temperature range and is not a function of

package size or voltage rating.

A typical hysteresis of 90 mV within the UVLO circuitry prevents

the device from oscillating due to the noises from VIN.

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

–0.35

–0.40

–0.45

–0.50

–0.55

5.64

4.70

3.76

2.82

1.88

0.94

0

–1.74

–1.72

–1.70

–1.68

VIN (V)

–1.66

–1.64

–1.62

–1.60

Figure 49. Typical UVLO Behavior, VOUT = −0.5 V

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADP7185 is protected against damage due to excessive

power dissipation by current-limit and thermal overload

protection circuits. The ADP7185 is designed to reach current

limit when the output load reaches −900 mA (typical). When

the output load exceeds −900 mA, the output voltage is reduced

to maintain a constant current limit.

0

2

4

6

8

10

12

DC BIAS VOLTAGE (V dc)

Figure 48. Change in Capacitance vs. DC Bias Voltage

Use Equation 4 to determine the worst-case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and

power dissipation) when the junction temperature begins to rise

above 150°C, the output is turned off, reducing the output

current to zero. When the junction temperature drops below

135°C (typical), the output is turned on again, and the output

current is restored to its nominal value.

C

_EFF= C_OUT× (1 − TEMPCO) × (1 − TOL)

(4)

where:

C

_EFFis the effective capacitance at the operating voltage.

_OUTis the output capacitor.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient

(TEMPCO) over −55°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and C_OUT= 4.7 μF at 1.0 V.

Consider the case where a hard short from VOUT to GND occurs.

At first, the ADP7185 reaches current limit so that only −900 mA

is conducted into the short. If self-heating of the junction becomes

great enough to cause its temperature to rise above 150°C, thermal

shutdown activates, turning off the output and reducing the

output current to zero. As the junction temperature cools and

drops below 135°C, the output turns on and conducts −900 mA

into the short, again causing the junction temperature to rise

above 150°C. This thermal oscillation between 135°C and

150°C causes a current oscillation between −900 mA and 0 A

that continues as long as the short remains at the output. Current-

limit and thermal overload protections protect the device

against accidental overload conditions. For reliable operation,

externally limit device power dissipation so that junction

temperatures do not exceed 125°C.

Substituting these values in Equation 4 yields

C_EFF= 4.7 μF × (1 − 0.15) × (1 − 0.1) = 3.6 μF

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over temperature

and tolerance at the chosen output voltage.

To guarantee the performance of the ADP7185, it is imperative

to evaluate the effects of dc bias, temperature, and tolerances on

the behavior of the capacitors for each application.

UNDERVOLTAGE LOCKOUT (UVLO)

The UVLO circuitry protects the system from power supply

brownouts. If the input voltage on VIN is more positive than

the minimum −1.58 V UVLO falling threshold, the LDO output

shuts down. The LDO enables again when the voltage to VIN is

more negative than the maximum −1.77 V UVLO rising threshold.

Rev. 0 | Page 16 of 19

Data Sheet

ADP7185

As shown in Equation 7, for a given ambient temperature, input

to output voltage differential, and continuous load current,

there exists a minimum copper size requirement for the PCB to

ensure that the junction temperature does not rise above 125°C.

THERMAL CONSIDERATIONS

In applications with a low input to output voltage differential,

the ADP7185 does not dissipate much heat. However, in

applications with high ambient temperature and/or high input

voltage, the heat dissipated in the package may become large

enough to cause the junction temperature of the die to exceed

the maximum junction temperature of 125°C.

Figure 50 to Figure 52 show the junction temperature calculations

for the different ambient temperatures, power dissipation, and

areas of the PCB copper.

140

When the junction temperature exceeds 150°C, the converter

enters thermal shutdown. The converter recovers only after the

junction temperature decreases below 135°C to prevent any

permanent damage. Therefore, thermal analysis for the chosen

application is important to guarantee reliable performance over all

conditions. The junction temperature of the die is the sum of the

ambient temperature of the environment and the temperature

rise of the package due to the power dissipation, as shown in

Equation 5.

120

100

80

60

T

MAX

40

20

0

J

2

6400mm

1000mm

500mm

100mm

25mm

To guarantee reliable operation, the junction temperature of the

ADP7185 must not exceed 125°C. To ensure that the junction

temperature stays below this maximum value, the user must be

aware of the parameters that contribute to junction temperature

changes. These parameters include ambient temperature, power

dissipation in the power device, and thermal resistances between

the junction and ambient air (θ_JA). The θ_JAnumber is dependent

on the package assembly compounds that are used, and the amount

of copper used to solder the package VIN pins to the PCB.

2

0

0.5

1.0

1.5

2.0

2.5

POWER DISSIPATION (W)

Figure 50. Junction Temperature vs. Total Power Dissipation, T_A= −25°C

140

120

100

80

Table 7 shows the typical θ_JAvalues for the 8-lead LFCSP

package and for various PCB copper sizes.

Table 7. Typical θ_JAValues

Copper Size (mm²)

60

θ_JA(°C/W), 8-Lead LFCSP

T

MAX

25

146.6

105.4

75.38

65.16

53.5

40

20

0

J

2

6400mm

1000mm

500mm

100mm

25mm

100

500

1000

6400

2

0

0.5

1.0

1.5

2.0

2.5

POWER DISSIPATION (W)

Calculate the junction temperatures of the ADP7185 by

Figure 51. Junction Temperature vs. Total Power Dissipation, T_A= −50°C

T_J= T_A+ (P_D× θ_JA)

(5)

(6)

140

where:

120

100

80

T_Ais the ambient temperature.

P_Dis the power dissipation in the die, given by

P_D= ((V_IN− V_OUT) × I_LOAD) + (V_IN× I_GND

where:

V_INand V_OUTare the input and output voltages, respectively.

)

60

I

_LOADis the load current.

_GNDis the ground current.

T

MAX

40

20

0

J

2

6400mm

1000mm

500mm

100mm

25mm

2

Power dissipation due to ground current is quite small and can

be ignored. Therefore, the junction temperature equation

simplifies to

2

0

0.5

1.0

1.5

2.0

2.5

POWER DISSIPATION (W)

T_J= T_A+ (((V_IN− V_OUT) × I_LOAD) × θ_JA)

(7)

Figure 52. Junction Temperature vs. Total Power Dissipation, T_A= −85°C

Rev. 0 | Page 17 of 19

ADP7185

Data Sheet

PCB LAYOUT CONSIDERATIONS

Place the input capacitor (C_IN) as close as possible to the VIN

and GND pins. Place the output capacitor (C_OUT) as close as

possible to the VOUT and GND pins. Place bypass capacitors

(C_Aand C_REG) close to their respective pins (VA and VREG) and

GND. Use of 0805 or 0603 size capacitors and resistors achieves

the smallest possible footprint solution on boards where area is

limited. Connect the exposed pad to VIN.

Figure 54. Typical Board Layout, Top Side

Figure 53. Evaluation Board

Figure 55. Typical Board Layout, Bottom Side

Rev. 0 | Page 18 of 19

Data Sheet

ADP7185

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

1.60

1.50

2.10

2.00 SQ

1.90

1.40

0.50 BSC

5

8

PIN 1 INDEX

1.10

1.00

0.90

AREA

EXPOSED

PAD

0.30

0.25

0.20

PIN 1

TIONS

INDIC ATOR AREA OP

(SEE DETAIL A)

4

1

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.60

0.55

0.50

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.25

0.20

SEATING

PLANE

0.152 REF

Figure 56. 8-Lead Lead Frame Chip Scale Package [LFCSP]

2 mm × 2 mm Body and 0.55 mm Package Height

(CP-8-27)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +125°C

Output Voltage (V)²

Package Description

8-Lead LFCSP

Package Option

CP-8-27

Branding

LTS

LTT

LTU

LTV

LTW

LTX

LTY

LTZ

LU0

LU1

ADP7185ACPZN0.5-R7

ADP7185ACPZN1.0-R7

ADP7185ACPZN1.2-R7

ADP7185ACPZN1.5-R7

ADP7185ACPZN1.8-R7

ADP7185ACPZN2.0-R7

ADP7185ACPZN2.5-R7

ADP7185ACPZN3.0-R7

ADP7185ACPZN3.3-R7

ADP7185ACPZN-R7

ADP7185-3.3-EVALZ

−0.5

−1.0

−1.2

−1.5

−1.8

−2.0

−2.5

−3.0

−3.3

Adjustable

−3.3

CP-8-27

Evaluation Board for the

Fixed Voltage Option

ADP7185-ADJ-EVALZ

−2.5

Evaluation Board for the

Adjustable Voltage Option

¹Z = RoHS Compliant Part.

²For additional voltage options, contact a local Analog Devices Inc., sales or distribution representative.

registered trademarks are the property of their respective owners.

D13932-0-5/17(0)

Rev. 0 | Page 19 of 19


型号：	ADP7185ACPZN1.0-R7
厂家：	ADI
描述：	â500 mA, Ultralow Noise, High PSRR, Low Dropout Linear Regulator
文件：	总19页 (文件大小：841K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP7185ACPZN1.0-R7 [ADI]

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