ADP8861DBCB-EVALZ [ADI]
Charge Pump, 7-Channel Smart LED Driver with I2C Interface; 电荷泵， 7通道智能LED驱动器，带有I2C接口
| 型号： | ADP8861DBCB-EVALZ |
| 厂家： | 
ADI |
| 描述： | Charge Pump, 7-Channel Smart LED Driver with I2C Interface |
| 文件： | 总40页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Charge Pump, 7-Channel
Smart LED Driver with I2C Interface
ADP8861
TYPICAL OPERATING CIRCUIT
FEATURES
Charge pump with automatic gain selection of 1×, 1.5×, and
2× for maximum efficiency
7 independent, programmable LED drivers
7 drivers capable of 30 mA (typical)
D1
D2
D3
D4
D5
D6
D7
VIN
1 driver also capable of 60 mA (typical)
Programmable maximum current limit (128 levels)
Standby mode for <1 μA current consumption
16 programmable fade in and fade out times
0.1 sec to 5.5 sec
C
IN
1µF
VOUT
OUT
VDDIO
C
1µF
nRST
SDA
SCL
C1+
C1–
C2+
C2–
VDDIO
VDDIO
VDDIO
C1
Choose from linear, square, or cubic rates
Fading override
1µF
ADP8861
I2C-compatible interface for all programming
Dedicated reset pin and built-in power-on reset (POR)
Short-circuit, overvoltage, and overtemperature protection
Internal soft start to limit inrush currents
Input-to-output isolation during faults or shutdown
Operation down to VIN = 2.5 V with undervoltage lockout
(UVLO) at VIN = 2.0 V
C2
1µF
nINT
GND1
GND2
Figure 1.
Small lead frame chip scale package (LFCSP)
APPLICATIONS
Mobile display backlighting
Mobile phone keypad backlighting
Dual RGB backlighting
LED indication
General backlighting of small format displays
GENERAL DESCRIPTION
The ADP8861 provides a powerful charge pump driver with
independent control of up to seven LEDs. These seven LEDs
can be independently driven up to 30 mA (typical). The seventh
LED can also be driven to 60 mA (typical). All LEDs are pro-
grammable for maximum current and fade in/out times via
the I2C interface. These LEDs can also be combined into groups to
reduce the processor instructions during fade in/out.
capable of driving a maximum IOUT of 240 mA from a supply
of 2.5 V to 5.5 V. A full suite of safety features, including short-
circuit, overvoltage, and overtemperature protection, allows
easy implementation of a safe and robust design. Additionally,
input inrush currents are limited via an integrated soft start
combined with controlled input-to-output isolation.
The ADP8861 is available in a compact lead frame chip scale
package (LFCSP).
This entire configuration is driven by a two-capacitor charge
pump with gains of 1×, 1.5×, and 2×. The charge pump is
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADP8861
TABLE OF CONTENTS
Features .............................................................................................. 1
Automated Fade In and Fade Out............................................ 14
Backlight Turn On/Turn Off/Dim........................................... 15
Automatic Dim and Turn Off Timers ..................................... 15
Fade Override ............................................................................. 16
Independent Sink Control ........................................................ 16
Short-Circuit Protection Mode ................................................ 16
Overvoltage Protection.............................................................. 17
Thermal Shutdown/Overtemperature Protection ................. 17
Interrupts..................................................................................... 17
Applications Information.............................................................. 19
Determining the Transition Point of the Charge Pump ....... 19
Layout Guidelines....................................................................... 19
Example Circuits ........................................................................ 20
I2C Programming and Digital Control........................................ 21
Backlight Register Descriptions ............................................... 26
Independent Sink Register Descriptions................................. 31
Outline Dimensions....................................................................... 39
Ordering Guide .......................................................................... 39
Applications....................................................................................... 1
Typical Operating Circuit................................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
I2C Timing Diagram .................................................................... 4
Absolute Maximum Ratings............................................................ 5
Maximum Temperature Ranges ................................................. 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Power Stage.................................................................................. 12
Operating Modes........................................................................ 13
Backlight Operating Levels ....................................................... 14
Backlight Maximum and Dim Settings ................................... 14
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
ADP8861
SPECIFICATIONS
VIN = 3.6 V, SCL = 2.7 V, SDA = 2.7 V, nINT = open, nRST = 2.7 V, VD1:D7 = 0.4 V, Capacitor C1 = 1 μF, Capacitor C2 = 1 μF, COUT = 1 μF,
typical values are at TA = 25°C and are not guaranteed, minimum and maximum limits are guaranteed from TA = −40°C to +85°C, unless
otherwise noted.
Table 1.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max Unit
SUPPLY
Input Voltage
Operating Range
VIN
2.5
5.5
V
Start-Up Level
Low Level
VIN(START) Hysteresis
UVLO Noise Filter
Quiescent Current
Prior to VIN(START)
During Standby
After Startup and Switching
OSCILLATOR
VIN(START)
VIN(STOP)
VIN(HYS)
tUVLO
VIN increasing
VIN decreasing
After startup
2.05
1.97
80
2.30
V
V
mV
μs
1.75
10
IQ
IQ(START)
IQ(STBY)
IQ(ACTIVE)
VIN = VIN(START) − 100 mV
10
0.3
4.5
μA
μA
mA
VIN = 3.6 V, Bit nSTBY = 0, SCL = SDA = 0 V
VIN = 3.6 V, Bit nSTBY = 1, IOUT = 0 mA, gain = 2×
Charge pump gain = 2×
1.0
7.2
Switching Frequency
Duty Cycle
fSW
D
0.8
1
50
1.32 MHz
%
OUTPUT CURRENT CONTROL
Maximum Drive Current
Diode1 to Diode 7
TJ = 25°C
TJ = −40°C to +85°C
Diode 7 Only (60 mA Setting)
TJ = 25°C
TJ = −40°C to +85°C
LED Current Source Matching1
All Current Sinks
ID1:D7(MAX) VD1:D7 = 0.4 V
Bit SCR = 0 in the ISC7 register
26.2
24.4
30
60
34.1 mA
34.1 mA
ID7(60 mA)
VD7 = 0.4 V, Bit SCR = 1 in the ISC7 register
52.5
48.8
67
67
mA
mA
IMATCH
IMATCH7
IMATCH6
VD1:D7 = 0.4 V
VD2:D7 = 0.4 V
2.0
1.5
%
%
Diode 2 to Diode 7 Current
Sinks
Leakage Current on LED Pins
Equivalent Output Resistance
Gain = 1×
Gain = 1.5×
Gain = 2×
Regulated Output Voltage
AUTOMATIC GAIN SELECTION
Minimum Voltage
ID1:D7(LKG)
ROUT
VIN = 5.5 V, VD1:D7 = 2.5 V, Bit nSTBY = 1
0.5
μA
VIN = 3.6 V, IOUT = 100 mA
VIN = 3.1 V, IOUT = 100 mA
VIN = 2.5 V, IOUT = 100 mA
VIN = 3 V, gain = 2×, IOUT = 10 mA
0.5
3.0
3.8
4.9
Ω
Ω
Ω
V
VOUT(REG)
4.3
5.5
Gain Increases
Minimum Current Sink Headroom
Voltage
VHR(UP)
VHR(MIN)
Decrease VD1:D7 until the gain switches up
IDX = IDX(MAX) × 95%
162
200
180
276
mV
mV
Gain Delay
tGAIN
The delay after gain has changed and before
gain is allowed to change again
100
μs
FAULT PROTECTION
Start-Up Charging Current Source
Output Voltage Threshold
Exit Soft Start
ISS
VOUT
VIN = 3.6 V, VOUT = 0.8 × VIN
2.5
3.75
5.5
mA
VOUT(START) VOUT rising
VOUT(SC) VOUT falling
0.92 × VIN
0.55 × VIN
V
V
Short-Circuit Protection
Rev. 0 | Page 3 of 40
ADP8861
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max Unit
Output Overvoltage Protection
Activation Level
OVP Recovery Hysteresis
Thermal Shutdown
Threshold
VOVP
5.8
500
V
mV
TSD
TSD(HYS)
150
20
°C
°C
Hysteresis
Isolation from Input to Output
During Fault
IOUTLKG
VIN = 5.5 V, VOUT = 0 V, Bit nSTBY = 0
1.5
μA
Time to Validate a Fault
I2C INTERFACE
tFAULT
2
μs
Operating VDDIO Voltage
Logic Low Input2
Logic High Input3
VDDIO
VIL
VIH
5.5
0.5
V
V
V
VIN = 2.5 V
VIN = 5.5 V
1.55
I2C TIMING SPECIFICATIONS
Guaranteed by design
Delay from Reset Deassertion to
I2C Access
tRESET
20
μs
SCL Frequency
SCL High Time
SCL Low Time
Setup Time
fSCL
tHIGH
tLOW
400
kHz
μs
μs
0.6
1.3
Data
tSU, DAT
tSU, STA
tSU, STO
100
0.6
0.6
ns
μs
μs
Repeated Start
Stop Condition
Hold Time
Data
tHD, DAT
tHD, STA
tBUF
0
0.6
1.3
0.9
μs
μs
μs
Start/Repeated Start
Bus Free Time (Stop and Start
Conditions)
Rise Time (SCL and SDA)
Fall Time (SCL and SDA)
Pulse Width of Suppressed Spike
Capacitive Load per Bus Line
tR
tF
tSP
CB
20 + 0.1 CB
20 + 0.1 CB
0
300
300
50
ns
ns
ns
pF
400
1 Current source matching is calculated by dividing the difference between the maximum and minimum currents from the sum of the maximum and minimum.
2 VIL is a function of the input voltage. See Figure 15 in the Typical Performance Characteristics section for typical values over operating ranges.
3 VIH is a function of the input voltage. See Figure 15 in the Typical Performance Characteristics section for typical values over operating ranges.
I2C TIMING DIAGRAM
SDA
tBUF
tF
tLOW
tR
tR
tF
tSP
tSU, DAT
tHD, STA
SCL
tHIGH
tSU, STA
tSU, STO
tHD, DAT
S
Sr
P
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Figure 2. I2C Interface Timing Diagram
Rev. 0 | Page 4 of 40
ADP8861
ABSOLUTE MAXIMUM RATINGS
MAXIMUM TEMPERATURE RANGES
Table 2.
The maximum operating junction temperature (TJ(MAX)) takes
precedence over the maximum operating ambient temperature
(TA(MAX)). Therefore, in situations where the ADP8861 is
exposed to poor thermal resistance and high power dissipation
(PD), the maximum ambient temperature may need to be
derated. In these cases, the maximum ambient temperature can
be calculated with the following equation:
Parameter
Rating
VIN, VOUT
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
Indefinite
D1, D2, D3, D4, D5, D6, and D7
nINT, nRST, SCL, and SDA
Output Short-Circuit Duration
Operating Temperature Range
Ambient (TA)
–40°C to +85°C1
–40°C to +125°C
–65°C to +150°C
JEDEC J-STD-020
Junction (TJ)
TA(MAX) = TJ(MAX) − (θJA × PD(MAX))
Storage Temperature Range
Soldering Conditions
ESD (Electrostatic Discharge)
Human Body Model (HBM)
Charged Device Model (CDM)
THERMAL RESISTANCE
θJA (junction to air) is specified for the worst-case conditions,
that is, a device soldered in a circuit board for surface-mount
packages. The θJA and θJC (junction to case) are determined
according to JESD51-9 on a 4-layer printed circuit board (PCB)
with natural convection cooling. For the LFCSP package, the
exposed pad must be soldered to the GND1 and/or GND2
terminal on the board.
3 kV
1.5 kV
1 The maximum operating junction temperature (TJ(MAX)) takes precedence
over the maximum operating ambient temperature (TA(MAX)). See the
Maximum Temperature Ranges section for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
20-Lead LFCSP_WQ
49.5
5.3
°C/W
ESD CAUTION
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all voltages are
referenced to ground.
Rev. 0 | Page 5 of 40
ADP8861
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP8861
TOP VIEW
(Not to Scale)
15
14
D3 1
D2 2
GND1
VIN
3
4
5
D1
SCL
13 VOUT
12
C2+
11 C1+
nRST
NOTES
1. CONNECT THE EXPOSED PADDLE
TO GND1 AND/OR GND2.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
14
3
VIN
D1
Input Voltage, 2.5 V to 5.5 V.
LED Sink 1.
2
D2
LED Sink 2.
1
D3
LED Sink 3.
20
19
17
16
18
13
11
9
12
10
15
8
D4
D5
D6
D7
LED Sink 4.
LED Sink 5.
LED Sink 6.
LED Sink 7.
NA
This pin is not used and must be connected to ground.
Charge Pump Output.
Charge Pump C1+.
Charge Pump C1−.
Charge Pump C2+.
Charge Pump C2−.
Ground. Connect the exposed pad to GND1 and/or GND2.
Ground. Connect the exposed pad to GND1 and/or GND2.
Processor Interrupt (Active Low). Requires an external pull-up resistor. If this pin is not used, it can be left floating.
Hardware Reset (Active Low). This pin resets the device to the default conditions. If not used, this pin must be tied
VOUT
C1+
C1−
C2+
C2−
GND1
GND2
nINT
nRST
6
5
above VIH(MIN)
.
7
4
SDA
SCL
I2C Serial Data. Requires an external pull-up resistor.
I2C Clock. Requires an external pull-up resistor.
21
EPAD
Exposed Paddle. Connect the exposed paddle to GND1 and/or GND2.
Rev. 0 | Page 6 of 40
ADP8861
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6 V, SCL = 2.7 V, SDA = 2.7 V, nRST = 2.7 V, VD1:D7 = 0.4 V, CIN = 1 μF, Capacitor C1 = 1 μF, Capacitor C2 = 1 μF, COUT = 1 μF,
TA= 25°C, unless otherwise noted.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
35
30
25
20
15
10
5
V
= 3.6V
= 30mA
IN
I
= NO LOAD
OUT
I
D1:D7
D1
D2
D3
D4
D5
D6
D7
–40°C
+25°C
+85°C
+105°C
0
1.5
2.0
2.5
3.0
3.5
(V)
4.0
4.5
5.0
5.5
0
0.2
0.4
0.6
0.8
1.0
V (V)
HR
1.2
1.4
1.6
1.8
2.0
V
IN
Figure 4. Typical Quiescent Current, G = 1×
Figure 7. Typical Diode Current vs. Current Sink Headroom Voltage (VHR)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
35
V
= 0.4V
D1:D7
I
= NO LOAD
OUT
34
33
32
31
30
29
28
27
26
25
D1
D2
D3
D4
D5
D6
D7
–40°C
+25°C
+85°C
+105°C
1.5
2.0
2.5
3.0
3.5
(V)
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
IN
Figure 5. Typical Quiescent Current, G = 2×, IQ(ACTIVE)
Figure 8. Typical Diode Current vs. VIN
10
6
5
4
3
2
1
0
SCL = SDA = 0V
V
= 3.6V
= 30mA
–40°C
IN
nRST = 2.7V
I
D1:D7
+25°C
+85°C
+105°C
1
0.1
0.01
0.001
–40°C
+25°C
+85°C
+105°C
0
1
2
3
4
5
6
0.2
0.4
0.6
0.8
1.0
V
1.2
(V)
1.4
1.6
1.8
2.0
V
(V)
IN
HR
Figure 6. Typical Standby IQ vs. VIN
Figure 9. Typical Diode Matching vs. Current Sink Headroom Voltage (VHR)
Rev. 0 | Page 7 of 40
ADP8861
35
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 3.6V
= 30mA
I
= 100mA
OUT
IN
I
D1:D7
30
25
20
15
10
5
–40°C
+25°C
+85°C
+105°C
–40°C
+25°C
+85°C
+105°C
0
0
0.2
0.4
0.6
0.8
1.0
(V)
1.2
1.4
1.6
1.8
2.0
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
HR
Figure 10. Typical Diode Current vs. Current Sink Headroom Voltage (VHR
)
Figure 13. Typical ROUT (G = 1×) vs. VIN
1
10
9
8
7
6
5
4
3
2
1
0
V
V
= 3.6V
= 0.40V
V
= 80% OF V
OUT IN
IN
D1:D7
0
–1
–2
–3
–4
–5
–6
–40°C
+25°C
+85°C
+105°C
–40
–10
20
50
80
110
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
JUNCTION TEMPERATURE (°C)
V
IN
Figure 11. Typical Change In Diode Current vs. Temperature
Figure 14. Typical Output Soft Start Current, ISS
7
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I
= 100mA
OUT
V
V
V
@ +25°C
@ +85°C
@ –40°C
IH
IH
IH
6
5
4
3
2
1
0
G = 2× @ V = 2.5V
IN
V
V
V
@ +25°C
IL
IL
IL
@ +85°C
@ –40°C
G = 1.5× @ V = 3V
IN
G = 1× @ V = 3.6V
IN
–40
–20
0
20
40
60
80
100
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
TEMPERATURE (°C)
V
IN
Figure 15. Typical I2C Thresholds, VIH and VIL
Figure 12. ROUT vs. Temperature
Rev. 0 | Page 8 of 40
ADP8861
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
100
90
80
70
60
50
40
30
20
10
0
450
400
350
300
250
200
150
100
50
V
= 3V
IN
GAIN = 2×
= 10mA
I
OUT
I
I
= 140mA, Vf = 3.85V
= 210mA, Vf = 4.25V
OUT
OUT
0
5.5
–40
–10
20
50
80
110
2.5
3.0
3.5
4.0
(V)
4.5
5.0
JUNCTION TEMPERATURE (°C)
V
IN
Figure 19. Typical Efficiency (High Vf Diode)
Figure 16. Typical Regulated Output Voltage (VOUT(REG)
)
6.0
5.8
5.6
5.4
5.2
T
V
(AC-COUPLED) 50mV/DIV
IN
1
2
3
OVP THRESHOLD
V
(AC-COUPLED) 50mV/DIV
OUT
I
(AC-COUPLED) 10mA/DIV
IN
= 1µF, C1 = 1µF, C2 = 1µF
OUT
C
V
= 1µF, C
= 3.6V
= 120mA
IN
IN
OVP RECOVERY
80
500ns/DIV
I
OUT
–40
–10
20
50
110
JUNCTION TEMPERATURE (°C)
Figure 17. Typical Overvoltage Protection (OVP) Threshold
Figure 20. Typical Operating Waveforms, G = 1×
90
80
70
60
50
40
30
20
10
0
450
T
V
(AC-COUPLED) 50mV/DIV
IN
400
350
300
250
200
150
100
50
1
2
3
V
(AC-COUPLED) 50mV/DIV
OUT
I
(AC-COUPLED) 10mA/DIV
IN
= 1µF, C1 = 1µF, C2 = 1µF
OUT
C
V
= 1µF, C
= 3.0V
= 120mA
IN
I
I
= 140mA, Vf = 3.1V
= 210mA, Vf = 3.2V
OUT
OUT
IN
500ns/DIV
I
OUT
0
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
V
IN
Figure 21. Typical Operating Waveforms, G = 1.5×
Figure 18. Typical Efficiency (Low Vf Diode)
Rev. 0 | Page 9 of 40
ADP8861
V
= 3.7V
T
IN
V
(AC-COUPLED) 50mV/DIV
IN
1
2
3
V
(1V/DIV)
OUT
V
(AC-COUPLED) 50mV/DIV
OUT
2
I
(10mA/DIV)
IN
I
(AC-COUPLED) 10mA/DIV
IN
= 1µF, C1 = 1µF, C2 = 1µF
OUT
C
V
= 1µF, C
= 2.5V
= 120mA
IN
IN
4
500ns/DIV
I (10mA/DIV)
OUT
100µs/DIV
I
OUT
Figure 22. Typical Operating Waveforms, G = 2×
Figure 23. Typical Start-Up Waveform
Rev. 0 | Page 10 of 40
ADP8861
THEORY OF OPERATION
The ADP8861 provides a powerful charge pump driver with
programmable LED control. Up to seven LEDs can be indepen-
dently driven up to 30 mA (typical) each. The seventh LED can
also be driven to 60 mA (typical). All LEDs can be individually
programmed or combined into a group to operate backlight
LEDs. A full suite of safety features, including short-circuit,
overvoltage, and overtemperature protection with input-to-
output isolation, allows for a robust and safe design. The
integrated soft start limits inrush currents at startup, restart
attempts, and gain transitions.
D1
D4
D5
D2
D3
D6
D7
GAIN
SELECT
LOGIC
V
IN
ID1
ID3
ID2
ID4
ID5
ID6
ID7
I
SS
VIN
SOFT
START
CHARGE
PUMP
LOGIC
V
REFS
VBAT
C
VIN
VIN
IN
VOUT
I
UVLO
STNDBY
REFS
C
OUT
VDDIO
EN
CLK
NOISE FILTER
50µs
C1+
C1
1µF
nRST
CHARGE
PUMP
(1×, 1.5×, 2×)
C1–
C2+
STANDBY
RESET
C2
1µF
SCL
SDA
2
C2–
I C
SWITCH CONTROL
LOGIC
CURRENT SINK CONTROL
nINT
GND1
GND2
Figure 24. Detailed Block Diagram
Rev. 0 | Page 11 of 40
ADP8861
in parallel and are discharged to VOUT in parallel. In certain fault
modes, the switches are opened and the output is physically
isolated from the input.
POWER STAGE
Because typical white LEDs require up to 4 V to drive them,
some form of boosting is required over the typical variation in
battery voltage. The ADP8861 accomplishes this with a high
efficiency charge pump capable of producing a maximum IOUT
of 240 mA over the entire input voltage range (2.5 V to 5.5 V).
Charge pumps use the basic principle that a capacitor stores
charge based on the voltage applied to it, as shown in the
following equation:
Automatic Gain Selection
Each LED that is driven requires a current source. The voltage
on this current source must be greater than a minimum head-
room voltage (180 mV typical) to maintain accurate current
regulation. The gain is automatically selected based on the
minimum voltage (VDX) at all of the current sources. At startup,
the device is placed into G = 1× mode and the output charges
to VIN. If any VD1:D7 level is less than the required headroom
(180 mV), the gain is increased to the next step (G = 1.5×).
A 100 μs delay is allowed for the output to stabilize prior to
the next gain switching decision. If there remains insufficient
current sink headroom, then the gain is increased again to 2×.
Conversely, to optimize efficiency, it is not desirable for the
output voltage to be too high. Therefore, the gain reduces when
the headroom voltage is great enough. This point (labeled
Q = C × V
(1)
By charging the capacitors in different configurations, the
charge, and therefore the gain, can be optimized to deliver the
voltage required to power the LEDs. Because a fixed charging
and discharging combination must be used, only certain
multiples of gain are available. The ADP8861 is capable of
automatically optimizing the gain (G) from 1×, 1.5×, and 2×.
These gains are accomplished with two capacitors (labeled C1
and C2 in Figure 24) and an internal switching network.
V
DMAX in Figure 25) is internally calculated to ensure that the
In G = 1× mode, the switches are configured to pass VIN
directly to VOUT. In this mode, several switches are connected
in parallel to minimize the resistive drop from input to output.
In G = 1.5× and 2× modes, the switches alternatively charge
from the battery and discharge into the output. For G = 1.5×,
the capacitors are charged from VIN in series and are discharged to
lower gain still results in ample headroom for all the current
sinks. The entire cycle is illustrated in Figure 25.
Note that the gain selection criteria apply only to active current
sources. If current sources have been deactivated through an
I2C command (for example only five LEDs are used), then the
voltages on the deactivated current sources are ignored.
VOUT in parallel. For G = 2×, the capacitors are charged from VIN
STARTUP:
CHARGE
EXIT STANDBY
STANDBY
V
TO V
IN
OUT
0
1
EXIT
STARTUP
VOUT > V
OUT(START)
0
WAIT
100µs (TYP)
MIN (V
D1:D7
) < V
G = 1
HR(UP)
0
0
WAIT
100µs (TYP)
G = 1.5
MIN (V
D1:D7
) < V
HR(UP)
MIN (V
D1:D7
) > V
DMAX
0
WAIT
100µs (TYP)
MIN (V
D1:D7
) < V
DMAX
G = 2
NOTES
1. V
IS THE CALCULATED GAIN DOWN TRANSITION POINT.
DMAX
Figure 25. State Diagram for Automatic Gain Selection
Rev. 0 | Page 12 of 40
ADP8861
Soft Start Feature
Shutdown Mode
At startup (either from UVLO activation or fault/standby
recovery), the output is first charged by ISS (3.75 mA typical)
until it reaches about 92% of VIN. This soft start feature reduces
the inrush current that is otherwise present when the output
capacitance is initially charged to VIN. When this point is
reached, the controller enters G = 1× mode. If the output
voltage is not sufficient, then the automatic gain selection
determines the optimal point as defined in the Automatic Gain
Selection section.
Shutdown mode disables all circuitry, including the I2C receivers.
Shutdown occurs when VIN is below the undervoltage thresholds.
When VIN rises above VIN(START) (2.05 V typical), all registers are
reset and the part is placed into standby mode.
Reset Mode
In reset mode, all registers are set to their default values and
the part is placed into standby. There are two ways to reset the
part: by power-on reset (POR) or using the nRST pin. POR is
activated any time that the part exits shutdown mode. After
a POR sequence is complete, the part automatically enters
standby mode.
OPERATING MODES
There are four different operating modes: active, standby,
shutdown, and reset.
After startup, the part can be reset by pulling the nRST pin low.
As long as the nRST pin is low, the part is held in a standby state
but no I2C commands are acknowledged (all registers are kept
at their default values). After releasing the nRST pin, all registers
remain at their default values, and the part remains in standby;
however, the part does accept I2C commands.
Active Mode
In active mode, all circuits are powered up and in a fully
operational state. This mode is entered when Bit nSTBY (in
Register MDCR) is set to 1.
Standby Mode
The nRST pin has a 50 μs (typical) noise filter to prevent inad-
vertent activation of the reset function. The nRST pin must be
held low for this entire time to activate reset.
Standby mode disables all circuitry except for the I2C receivers.
Current consumption is reduced to less than 1 μA. This mode is
entered when the nSTBY bit is set to 0 or when the nRST pin is
held low for more than 100 μs (maximum). When standby is
exited, a soft start sequence is performed.
The operating modes function according to the timing diagram
in Figure 26.
SHUTDOWN
V
CROSSES ~2.05V AND TRIGGERS POWER-ON RESET
nRST MUST BE HIGH FOR 20µs (MAX)
BEFORE SENDING I C COMMANDS
IN
V
IN
2
BIT nSTBY IN REGISTER
MDCR GOES LOW
~100µs DELAY BETWEEN POWER-UP AND
WHEN I C COMMANDS CAN BE RECEIVED
STANDBY
nRST
2
nRST IS LOW, WHICH FORCES STANDBY LOW
25µs TO 100µs NOISE FILTER
2
AND RESETS ALL I C REGISTERS
2×
~3.75mA CHARGES
1.5×
V
V
TO V LEVEL
GAIN CHANGES OCCUR ONLY WHEN NECESSARY,
BUT HAVE A MIN TIME BEFORE CHANGING
OUT
V
OUT
IN
IN
1×
SOFT START
SOFT START
10µs 100µs
Figure 26. Typical Timing Diagram
Rev. 0 | Page 13 of 40
ADP8861
30
25
20
15
10
5
BACKLIGHT OPERATING LEVELS
The backlight can be operated at either the maximum level
(Register 0x09) or the dim level (Register 0x0A). The backlight
maximum and dim current settings are determined by a 7-bit
code programmed by the user into these registers. The 7-bit
resolution allows the user to set the backlight to one of 128
different levels between 0 mA and 30 mA.
LINEAR
30mA
SQUARE
BACKLIGHT_MAX
0
0
32
64
CODE
96
128
BACKLIGHT_DIM
Figure 28. Backlight Current vs. Input Code
AUTOMATED FADE IN AND FADE OUT
The LED drivers are easily configured for automated fade in
and fade out. Sixteen fade in and fade out rates can be selected
via the I2C interface. Fade in and fade out rates range from
0.1 sec to 5.5 sec (per full-scale current, either 30 mA or 60 mA).
0
Figure 27. Backlight Operating Levels
The maximum and dim settings can be set between 0 mA and
30 mA; therefore, it is possible to program a dim setting that is
greater than a maximum setting. For normal expected operation,
ensure that the dim setting is programmed to be less than the
maximum setting.
Table 5. Available Fade In and Fade Out Rates
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Fade Rate (in sec per Full-Scale Current)
0.1 (disabled)
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.5
4.0
4.5
5.0
5.5
BACKLIGHT MAXIMUM AND DIM SETTINGS
The ADP8861 can implement two distinct algorithms to
achieve a linear and a nonlinear relationship between input
code and backlight current. The law bits in Register 0x04 are
used to change between these algorithms.
By default, the ADP8861 uses a linear algorithm (law = 00),
where the backlight current increases linearly for a correspond-
ing increase in input code. Backlight current (in milliamperes)
is determined by the following equation:
Backlight Current (mA) = Code × (Full-Scale Current/127) (2)
where:
Code is the input code programmed by the user.
Full-Scale Current is the maximum sink current allowed per
LED (typically 30 mA).
The fade profile is based on the transfer law selected (linear,
square, Cubic 10, or Cubic 11) and the delta between the actual
current and the target current. Smaller changes in current
reduce the fade time. For linear and square law fades, the fade
time is given by
The ADP8861 can also implement a nonlinear (square approxima-
tion) relationship between input code and backlight current
level. In this case (law = 01), the backlight current (in milliam-
peres) is determined by the following equation:
2
⎛
⎞
Fade Time = Fade Rate × (Code/127)
where the Fade Rate is shown in Table 5.
(4)
Full −Scale Current
⎜
⎟
Backlight Current (mA) = Code×
(3)
⎜
⎝
⎟
⎠
127
The Cubic 10 and Cubic 11 laws also use the square law back-
light currents derived from Equation 3; however, the time
between each step is varied to produce a steeper slope at higher
currents and a shallower slope at lower currents (see Figure 29).
Figure 28 shows the backlight current level vs. input code for
both the linear and square law algorithms.
Rev. 0 | Page 14 of 40
ADP8861
30
25
20
15
10
5
AUTOMATIC DIM AND TURN OFF TIMERS
The user can program the backlight to dim automatically by
using the DIMT bits in Register 0x07. The dim timer has
127 settings ranging from 1 sec to 127 sec. Program the dim
timer (DIMT) before turning on the backlight. If BL_EN = 1,
the backlight turns on to its maximum setting and the dim
timer starts counting. When the dim timer expires, the internal
state machine sets DIM_EN = 1, and the backlight enters its
dim setting.
LINEAR
SQUARE
CUBIC 11
BACKLIGHT
CURRENT
DIM TIMER
RUNNING
DIM TIMER
RUNNING
CUBIC 10
0.75
0
0
0.25
0.50
1.00
MAX
UNIT FADE TIME
Figure 29. Comparison of the Dimming Transfers Laws
BACKLIGHT TURN ON/TURN OFF/DIM
With the device in active mode (nSTBY = 1), the backlight can
be turned on using the BL_EN bit in Register 0x01. Before
turning on the backlight, the user should ensure that the
maximum and dim settings are programmed. The backlight
turns on when BL_EN = 1. The backlight turns off when
BL_EN = 0.
DIM
BL_EN = 1 DIM_EN = 1
DIM_EN = 0 DIM_EN = 1 BL_EN = 0
SET BY USER
SET BY INTERNAL STATEMACHINE
BACKLIGHT
CURRENT
Figure 32. Dim Timer
If the user clears the DIM_EN bit, the backlight reverts to its
maximum setting and the dim timer begins counting again.
When the dim timer expires, the internal state machine again
sets DIM_EN = 1, and the backlight enters its dim setting. The
backlight can be turned off at any point during the dim timer
countdown by clearing BL_EN.
MAX
The user can also program the backlight to turn off automati-
cally by using the OFFT bits in Register 0x06. The off timer has
127 settings ranging from 1 sec to 127 sec. Program the off
timer (OFFT) before turning on the backlight. If BL_EN = 1,
the backlight turns on to its maximum setting and the off timer
starts counting. When the off timer expires, the internal state
machine clears the BL_EN bit, and the backlight turns off.
BACKLIGHT
BL_EN = 1
BL_EN = 0
Figure 30. Backlight Turn On/Turn Off
While the backlight is on (BL_EN = 1), the user can change to
the dim setting by programming DIM_EN = 1 in Register 0x01.
If DIM_EN = 0, the backlight reverts to its maximum setting.
BACKLIGHT
CURRENT
OFF TIMER
RUNNING
CURRENT
MAX
MAX
DIM
BL_EN = 1 BL_EN = 0
BL_EN = 1 DIM_EN = 1 DIM_EN = 0 BL_EN = 0
SET BY USER
SET BY INTERNAL STATE MACHINE
Figure 31. Backlight Turn On/Dim/Turn Off
Figure 33. Off Timer
The backlight can be turned off at any point during the off
timer countdown by clearing BL_EN.
Rev. 0 | Page 15 of 40
ADP8861
The dim timer and off timer can be used together for sequential
maximum-to-dim-to-off functionality. With both the dim and
off timers programmed, and BL_EN asserted, the backlight turns
on to its maximum setting, and when the dim timer expires, the
backlight changes to its dim setting. When the off timer expires,
the backlight turns off.
INDEPENDENT SINK CONTROL
Each of the seven LEDs can be configured (in Register 0x05) to
operate as either part of the backlight or to operate as an indepen-
dent sink current (ISC). Each ISC can be enabled independently
and has its own current level. All ISCs share the same fade in
rates, fade out rates, and fade law.
BACKLIGHT
CURRENT
The ISCs have additional timers to facilitate blinking functions.
A shared on timer (SCON) used in conjunction with the off
timers of each ISC (SC1_OFF, SC2_OFF, SC3_OFF, and SC4_OFF
in Register 0x12, and SC5_OFF, SC6_OFF, and SC7_OFF in
Register 0x11) allows the LED current sinks to be configured in
various blinking modes. The on timer can be set to one of four
different settings: 0.2 sec, 0.6 sec, 0.8 sec, or 1.2 sec. The off
timers have four different settings: disabled, 0.6 sec, 1.2 sec, and
1.8 sec. Blink mode is activated by setting the off timers to any
setting other than disabled.
DIM TIMER
RUNNING
MAX
OFF TIMER
RUNNING
DIM
Program all fade, on, and off timers before enabling any of the
LED current sinks. If ISCx is on during a blink cycle and
SCx_EN is cleared, the LED turns off (or fades to off if fade out
is enabled). If ISCx is off during a blink cycle and SCx_EN is
cleared, it stays off.
BL_EN = 1
DIM_EN = 1
BL_EN = 0
SET BY USER
SET BY INTERNAL STATE MACHINE
Figure 34. Dim and Off Timers Used Together
FADE OVERRIDE
ISCx
A fade override feature (FOVR in Register CFGR (0x04)) enables
the host to override the preprogrammed fade in or fade out set-
tings. If FOVR is set and the backlight is enabled in the middle
of a fade out process, the backlight instantly (within approximately
100 ms) returns to its prefade brightness level. Alternatively, if
the backlight is fading in, reasserting BL_EN overrides the pro-
grammed fade in time, and the backlight instantly goes to its final
fade value. This is useful for situations where a key is pressed
during a fade sequence. However, if FOVR is cleared and the
backlight is enabled in the middle of a fade process, the back-
light gradually brightens from where it was interrupted (it does
not go down to 0 and then comes back on).
ON TIME
ON TIME
FADE-IN
FADE-OUT FADE-IN
FADE-OUT
MAX
OFF
TIME
OFF
TIME
ISCx_EN
SET BY USER
BACKLIGHT
CURRENT
Figure 36. Independent Sink Blink Mode with Fading
FADE-IN
FADE-OUT
OVERRIDDEN
OVERRIDDEN
SHORT-CIRCUIT PROTECTION MODE
MAX
The ADP8861 can protect against short circuits on the output
(VOUT). Short-circuit protection (SCP) is activated at the point
when VOUT < 55% of VIN. Note that SCP sensing is disabled
during both startup and restart attempts (fault recovery). SCP
sensing is reenabled 4 ms (typical) after activation. During a
short-circuit fault, the device enters a low current consumption
state and an interrupt flag is set. The device can be restarted at
any time after receiving a short-circuit fault by simply rewriting
nSTBY = 1. It then repeats another complete soft start sequence.
Note that the value of the output capacitance (COUT) should be
small enough to allow VOUT to reach approximately 55% (typical)
of VIN within the 4 ms (typical) time. If COUT is too large, the
device inadvertently enters short-circuit protection.
BL_EN = 1
BL_EN = 1
BL_EN = 0 BL_EN = 1 BL_EN = 0
(REASSERTED)
Figure 35. Fade Override Function (FOVR Is High)
Rev. 0 | Page 16 of 40
ADP8861
pump resumes operation. If the fault or load event recurs, the
process may repeat. An interrupt flag is set at each OVP
instance.
OVERVOLTAGE PROTECTION
Overvoltage protection (OVP) is implemented on the output.
There are two types of overvoltage events: normal (no fault)
and abnormal (from a fault or sudden load change).
THERMAL SHUTDOWN/OVERTEMPERATURE
PROTECTION
Normal Overvoltage
If the die temperature of the ADP8861 rises above a safe limit
(150°C typical), the controllers enter thermal shutdown (TSD)
protection mode. In this mode, most of the internal functions
shut down, the part enters standby, and the TSD_INT interrupt
(Register 0x02) is set. When the die temperature decreases
below ~130°C, the part can be restarted. To restart the part,
simply remove it from standby. No interrupt is generated when
the die temperature falls below 130°C. However, if the software
clears the pending TSD_INT interrupt and the temperature
remains above 130°C, another interrupt is generated.
In a normal (no fault) overvoltage, the output voltage approaches
VOUT(REG) (4.9 V typical) during normal operation. This is not
caused by a fault or load change, but it is simply a consequence
of the input voltage times the gain reaching the same level as the
clamped output voltage (VOUT(REG)). To prevent this type of overvol-
tage, the ADP8861 detects when the output voltage rises to
V
OUT(REG). It then increases the effective ROUT of the gain stage to
reduce the voltage that is delivered. This effectively regulates
OUT to VOUT(REG); however, there is a limit to the effect that this
V
system can have on regulating VOUT. It is designed only for
normal operation and it is not intended to protect against faults
or sudden load changes. When the output voltage is regulated to
The complete state machine for these faults (SCP, OVP, and
TSD) is shown in Figure 37.
V
OUT(REG), no interrupt is set and the operation is transparent to
INTERRUPTS
the LEDs and the overall application.
There are three interrupt sources available on the ADP8861 in
Register 0x02.
Abnormal Overvoltage
Because of the open-loop behavior of the charge pump as well
as how the gain transitions are computed, a sudden load change
or fault can abnormally force VOUT beyond 6 V. This causes an
abnormal overvoltage situation. If the event happens slowly
enough, the system first tries to regulate the output to 4.9 V as
in a normal overvoltage scenario. However, if this is not sufficient,
or if the event happens too quickly, then the ADP8861 enters
OVP mode when VOUT exceeds the OVP threshold (typically
5.8 V). In OVP mode, only the charge pump is disabled to
prevent VOUT from rising too high. The current sources and all
other device functionality remain intact. When the output
voltage falls by about 500 mV (to 5.3 V typical), the charge
•
•
•
Overvoltage protection: The OVP_INT interrupt is
generated when the output voltage exceeds 5.8 V (typical).
Thermal shutdown circuit: An interrupt (TSD_INT) is
generated when entering overtemperature protection.
Short-circuit detection: SHORT_INT is generated when
the device enters short-circuit protection mode.
The interrupt (if any) that appears on the nINT pin is deter-
mined by the bits mapped in Register INTR_EN (0x03). To
clear an interrupt, write a 1 to the interrupt in the MDCR2
register (0x02) or reset the part. Reading the interrupt, or writing a
0, has no effect.
Rev. 0 | Page 17 of 40
ADP8861
STANDBY
0
EXIT STANDBY
1
TSD FAULT
DIE TEMP > TSD
0
EXIT STANDBY
1
STARTUP:
CHARGE
VIN TO VOUT
DIE TEMP <
TSD – TSD
SCP FAULT
(HYS)
0
VOUT > V
OUT(START)
1
0
EXIT
STARTUP
VOUT < V
OUT(SC)
0
1
WAIT
100µs (TYP)
MIN (V
< V
)
VOUT < V
–
D1:D7
OVP
0
G = 1
V
HR(UP)
OVP(HYS)
0
VOUT > V
OVP
1
OVP FAULT
1
0
0
1
MIN (V
)
MIN (V
> V
)
WAIT
100µs (TYP)
D1:D7
D1:D7
DMAX
G = 1.5
< V
HR(UP)
0
VOUT < V
OVP
–
V
(HYS)
OVP
0
VOUT > V
OUT(REG)
OVP FAULT
1
1
TRY TO
REGULATE
VOUT TO
V
OUT(REG)
VOUT > V
OVP
0
1
MIN (V
> V
)
WAIT
100µs (TYP)
D1:D7
VOUT < V
OVP
–
G = 2
0
DMAX
V
OVP (HYS)
0
VOUT > V
OUT(REG)
OVP FAULT
1
1
TRY TO
REGULATE
VOUT TO
NOTES
1. V
IS THE CALCULATED GAIN DOWN TRANSITION POINT.
V
DMAX
OUT(REG)
VOUT > V
OVP
Figure 37. Fault State Machine
Rev. 0 | Page 18 of 40
ADP8861
APPLICATIONS INFORMATION
The ADP8861 allows the charge pump to operate efficiently
with a minimum of external components. Specifically, the user
must select an input capacitor (CIN), output capacitor (COUT),
and two charge pump fly capacitors (C1 and C2). CIN should
be 1 μF or greater. The value must be high enough to produce
a stable input voltage signal at the minimum input voltage and
maximum output load. A 1 μF capacitor for COUT is recommended.
Larger values are permissible, but care must be exercised to
ensure that VOUT charges above 55% (typical) of VIN within
4 ms (typical). See the Short-Circuit Protection Mode section
for more details.
VOUT is also equal to the largest Vf of the LEDs used plus the
voltage drop across the regulating current source. This gives
V
OUT = Vf(MAX) + VDX
(6)
(7)
Combining Equation 5 and Equation 6 gives
VIN = (Vf(MAX) + VDX + IOUT × ROUT(G))/G
Equation 7 is useful for calculating approximate bounds for the
charge pump design.
DETERMINING THE TRANSITION POINT OF THE
CHARGE PUMP
Consider the following design example where:
For best practice, it is recommended that the two charge pump
fly capacitors be 1 μF; larger values are not recommended, and
smaller values may reduce the ability of the charge pump to
deliver maximum current. For optimal efficiency, the charge
pump fly capacitors should have low equivalent series resistance
(ESR). Low ESR X5R or X7R capacitors are recommended for
all four components. The use of fly capacitors sized 0402 and
smaller is allowed, but the GDWN_DIS bit in Register 0x01
must be set. Minimum voltage ratings should adhere to the
guidelines in Table 6.
Vf(MAX) = 3.7 V
I
R
OUT = 140 mA (7 LEDs at 20 mA each)
OUT (G = 1.5×) = 3 Ω (obtained from Figure 12)
At the point of a gain transition, VDX = VHR(UP). Table 1 gives the
typical value of VHR(UP) as 0.2 V. Therefore, the input voltage
level when the gain transitions from 1.5× to 2× is
VIN = (3.7 V + 0.2 V + 140 mA × 3 Ω)/1.5 = 2.88 V
LAYOUT GUIDELINES
Note the following layout guidelines:
Table 6. Capacitor Stress in Each Charge Pump Gain State
Capacitor Gain = 1× Gain = 1.5×
Gain = 2×
For optimal noise immunity, place the CIN and COUT
capacitors as close to their respective pins as possible.
These capacitors should share a short ground trace. If
the LEDs are a significant distance from the VOUT pin,
another capacitor on VOUT, placed closer to the LEDs, is
advisable.
CIN
VIN
VIN
VIN
COUT
C1
VIN
VIN × 1.5 (max of 5.5 V)
VIN × 2.0 (max of 5.5 V)
None
None
VIN/2
VIN/2
VIN
VIN
C2
Any color LED can be used if the Vf (forward voltage) is less
than 4.1 V. However, using lower Vf LEDs reduces the input
power consumption by allowing the charge pump to operate at
lower gain states.
For optimal efficiency, place the charge pump fly capacitors
(C1 and C2) as close to the part as possible.
The ADP8861 does not distinguish between power ground
and analog ground. Therefore, both ground pins can be
connected directly together. It is recommended that these
ground pins be connected at the ground for the input and
output capacitors.
The equivalent circuit model for a charge pump is shown in
Figure 38.
VOUT
R
OUT
I
OUT
Unused diode pins (Pin D1 to Pin D7) can be connected
to ground or to VOUT, or remain floating. However, the
unused diode current sinks must be disabled by setting
them as independent sinks in Register 0x05 and then
disabling them in Register 0x10. If they are not disabled,
the charge pump efficiency may suffer.
If the interrupt pin (nINT) is not used, connect it to
ground or leave it floating. Never connect it to a voltage
supply, except through a ≥1 kꢀ series resistor.
The ADP8861 has an integrated noise filter on the nRST
pin. Under normal conditions, it is not necessary to filter
the reset line. However, if the part is exposed to an unusually
noisy signal, it is beneficial to add a small RC filter or bypass
capacitor on this pin. If the nRST pin is not used, it must
be pulled well above the VIH(MIN) level (see Table 1). Do not
allow the nRST pin to float.
V
DX
G × V
IN
C
OUT
Figure 38. Charge Pump Equivalent Circuit Model
The input voltage is multiplied by the gain (G) and delivered to
the output through an effective resistance (ROUT). The output
current flows through ROUT and produces an IR drop to yield:
V
OUT = G ×VIN − IOUT × ROUT(G)
(5)
The ROUT term is a combination of the RDSON resistance for the
switches used in the charge pump and a small resistance, which
accounts for the effective dynamic charge pump resistance. The
OUT level changes based upon the gain (the configuration of the
switches). Typical ROUT values are given in Table 1, Figure 12,
R
and Figure 13.
Rev. 0 | Page 19 of 40
ADP8861
EXAMPLE CIRCUITS
D1
D2
D3
D4
D5
D6
D7
VIN
1µF
VOUT
1µF
VDDIO
nRST
SDA
SCL
C1+
C1–
C2+
C2–
VDDIO
VDDIO
VDDIO
C1
1µF
ADP8861
C2
1µF
nINT
GND1
GND2
Figure 39. Generic Application Schematic
KEYPAD LIGHT
UP TO 10 LEDs (6mA EACH)
60mA MAX TOTAL CURRENT
DL7
DL8
R6
DL17
R15
R5
ACCESSORY
LIGHTS OR
DISPLAY BACKLIGHT
DL1 DL2 DL3 DL4
SUB-DISPLAY BL
DL5 DL6
D1
VIN
D2
D3
D4
D5 D6
D7
VOUT
GND2
V
IN
C2
C1
GND1
VDDIO
nRST
ADP8861
R1 R2 R3 R4
C1+
C1–
C2+
C2–
nRST
SDA
SCL
C3
C4
2
I C
CONTROL
SIGNALS
nINT
nINT
Figure 40. Application Schematic with Keypad Light Control
Rev. 0 | Page 20 of 40
ADP8861
I2C PROGRAMMING AND DIGITAL CONTROL
The ADP8861 provides full software programmability to facilitate
its adoption in various product architectures. The default I2C
address is 0101010x (x = 0 during write, x = 1 during read). There-
fore, the default write address is 0x54 and the read address is 0x55.
Table 7 through Table 55 provide register and bit descriptions.
The reset value for all bits in the bit map tables is all 0s, except
in Table 9 (see Table 9 for its unique reset value). Wherever the
acronym N/A appears in the tables, it means not applicable.
Note the following general behavior of registers:
•
All registers are set to their default values during reset or
after a UVLO event.
•
•
All registers are read/write unless otherwise specified.
Unused bits are read as zero.
B7
0
B0
B7
B0
B7
0
B0
B7
B0
ST
1
0
1
0
1
0
R/W ACK
REGISTER ADDRESS
ACK RS
1
0
1
0
1
0
R/W ACK
REGISTER VALUE
ACK ST
DEVICE ID
FOR WRITE
OPERATION
SELECT REGISTER TO WRITE
DEVICE ID
FOR READ
OPERATION
8-BIT VALUE TO WRITE IN THE
ADDRESSED REGISTER
SLAVE TO MASTER
MASTER TO SLAVE
Figure 41. I2C Read Command Sequence
B7
B0
B7
B0
B7
B0
ST
0
1
0
1
0
1
0
ACK
REGISTER ADDRESS
ACK
REGISTER VALUE
R/W
ACK ST
DEVICE ID
FOR WRITE
OPERATION
SELECT REGISTER TO WRITE
8-BIT VALUE TO WRITE IN THE
ADDRESSED REGISTER
SLAVE TO MASTER
MASTER TO SLAVE
Figure 42. I2C Write Command Sequence
Rev. 0 | Page 21 of 40
ADP8861
Table 7. Register Set Definitions
Address (Hex) Register Name
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B to 0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
MFDVID
MDCR
MDCR2
INTR_EN
CFGR
BLSEN
BLOFF
BLDIM
BLFR
BLMX
BLDM
Reserved
ISCFR
ISCC
ISCT1
ISCT2
ISCF
ISC7
ISC6
ISC5
ISC4
ISC3
ISC2
Manufacturer and device ID
Device mode and status
Device mode and Status Register 2
Interrupts enable
Configuration register
Sink enable, backlight or independent
Backlight off timeout
Backlight dim timeout
Backlight fade in and fade out rates
Backlight maximum current
Backlight dim current
Independent sink current fade control register
Independent sink current control register
Independent Sink Current Timer Register, LED[7:5]
Independent Sink Current Timer Register, LED[4:1]
Independent sink current fade register
Independent Sink Current, LED7
Independent Sink Current, LED6
Independent Sink Current, LED5
Independent Sink Current, LED4
Independent Sink Current, LED3
Independent Sink Current, LED2
Independent Sink Current, LED1
ISC1
Rev. 0 | Page 22 of 40
ADP8861
Table 8. Register Map
Address Register
(Hex)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
Name
MFDVID
MDCR
MDCR2
INTR_EN
CFGR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Manufacturer ID
Device ID
Reserved INT_CFG
Reserved
Reserved
nSTBY
DIM_EN
GDWN_DIS SIS_EN
Reserved
BL_EN
SHORT_INT
SHORT_IEN
TSD_INT
TSD_IEN
OVP_INT
OVP_IEN
Reserved
Reserved
FOVR
D1EN
Reserved
Law
D2EN
BLSEN
BLOFF
BLDIM
BLFR
Reserved D7EN
D6EN
D5EN
D4EN
OFFT
DIMT
D3EN
Reserved
Reserved
BL_FO
BL_FI
BLMX
BLDM
N/A
Reserved
Reserved
BL_MC
BL_DC
0x0B to
0x0E
Reserved
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
ISCFR
ISCC
ISCT1
ISCT2
ISCF
ISC7
ISC6
ISC5
ISC4
ISC3
ISC2
ISC1
Reserved
SC5_EN
SC7_OFF
SC_LAW
SC1_EN
SC5_OFF
SC1_OFF
Reserved SC7_EN
SCON
SC6_EN
SC4_EN
SC3_EN
SC2_EN
SC6_OFF
SC2_OFF
SC4_OFF
SC3_OFF
SCFO
SCFI
SCR
SCD7
SCD6
SCD5
SCD4
SCD3
SCD2
SCD1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev. 0 | Page 23 of 40
ADP8861
Manufacturer and Device ID (MFDVID)—Register 0x00
Multiple device revisions are tracked by the device ID field. This is a read-only register.
Table 9. MFDVID Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Device ID
Bit 0
Manufacturer ID
0
1
0
0
0
0
0
0
Mode Control Register (MDCR)—Register 0x01
Table 10. MDCR Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
DIM_EN
Bit 3
GDWN_DIS
Bit 2
SIS_EN
Bit 1
Bit 0
Reserved
INT_CFG
nSTBY
Reserved
BL_EN
Table 11. Bit Descriptions for the MDCR Register
Bit Name
Bit No. Description
N/A
7
6
Reserved.
INT_CFG
Interrupt configuration.
1 = processor interrupt deasserts for 50 μs and reasserts with pending events.
0 = processor interrupt remains asserted if the host tries to clear the interrupt while there is a pending event.
nSTBY
5
4
1 = device is in active mode.
0 = device is in standby mode; only the I2C interface is enabled.
DIM_EN
DIM_EN is set by the hardware after a dim timeout. The user can also force the backlight into dim mode by
asserting this bit. Dim mode can only be entered if BL_EN is also enabled.
1 = backlight is operating at the dim current level (BL_EN must also be asserted).
0 = backlight is not in dim mode.
GDWN_DIS
SIS_EN
3
2
1 = the charge pump does not switch down in gain until all LEDs are off. The charge pump switches up in gain as
needed. This feature is useful if the ADP8861 charge pump is used to drive an external load. This feature must be
used when utilizing small fly capacitors (0402 or smaller).
0 = the charge pump automatically switches up and down in gain. This provides optimal efficiency, but is not
suitable for driving loads that are not connected through the ADP8861 diode drivers. Additionally, the charge
pump fly capacitors should be low ESR and sized 0603 or greater.
Synchronous independent sinks enable.
1 = enables all LED current sinks designated as independent sinks. This bit has no effect if any of the SCx_EN bits
in Register 0x10 are set.
0 = disables all LED current sinks designated as independent sinks. This bit has no effect if any of the SCx_EN bits
in Register 0x10 are set.
N/A
1
0
Reserved.
BL_EN
1 = backlight is enabled (nSTBY must also be asserted).
0 = backlight is disabled.
Rev. 0 | Page 24 of 40
ADP8861
Mode Control Register 2 (MDCR2)—Register 0x02
Table 12. MDCR2 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SHORT_INT
TSD_INT
OVP_INT
Reserved
Table 13. Bit Descriptions for the MDCR2 Register
Bit Name
Bit No.
[7:5]
4
Description1
N/A
Reserved
SHORT_INT
Short-circuit error interrupt.
1 = a short-circuit or overload condition on VOUT has been detected.
0 = no short-circuit or overload condition has been detected.
Thermal shutdown interrupt.
1 = the device temperature has exceeded 150°C (typical).
0 = no overtemperature condition has been detected.
Overvoltage interrupt.
TSD_INT
OVP_INT
N/A
3
2
1 = VOUT has exceeded VOVP
.
0 = VOUT has not exceeded VOVP
Reserved.
.
1:0
1 Interrupt bits are cleared by writing a 1 to the flag; writing a 0 or reading the flag has no effect.
Interrupt Enable (INTR_EN)—Register 0x03
Table 14. INTR_EN Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
SHORT_IEN
TSD_IEN
OVP_IEN
Table 15. Bit Descriptions for the INTR_EN Register
Bit Name
Bit No. Description
N/A
[7:5]
4
Reserved.
SHORT_IEN
Short-circuit interrupt is enabled. When the SHORT_INT status bit is set after an error condition, an interrupt is
raised to the host if the SHORT_IEN flag is enabled.
1 = the short-circuit interrupt is enabled.
0 = the short-circuit interrupt is disabled (the SHORT_INT flag continues to assert).
TSD_IEN
OVP_IEN
N/A
3
Thermal shutdown interrupt is enabled. When the TSD_INT status bit is set after an error condition, an interrupt is
raised to the host if the TSD_IEN flag is enabled.
1 = the thermal shutdown interrupt is enabled.
0 = the thermal shutdown interrupt is disabled (the TSD_INT flag continues to assert).
2
Overvoltage interrupt enabled. When the OVP_INT status bit is set after an error condition, an interrupt is raised to
the host if the OVP_IEN flag is enabled.
1 = the overvoltage interrupt is enabled.
0 = the overvoltage interrupt is disabled (the OVP_INT flag continues to assert).
Reserved.
[1:0]
Rev. 0 | Page 25 of 40
ADP8861
BACKLIGHT REGISTER DESCRIPTIONS
Configuration Register (CFGR)—Register 0x04
Table 16. CFGR Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Law
Bit 0
Reserved
FOVR
Table 17. Bit Descriptions for the CFGR Register
Bit Name
Bit No. Description
N/A
[7:3]
[2:1]
Reserved
Law
Backlight transfer law
00 = linear law DAC, linear time steps
01 = square law DAC, linear time steps
10 = square law DAC, nonlinear time steps (Cubic 10)
11 = square law DAC, nonlinear time steps (Cubic 11)
Backlight fade override
FOVR
0
1 = the backlight fade override is enabled
0 = the backlight fade override is disabled
Backlight Sink Enable (BLSEN)—Register 0x05
Table 18. BLSEN Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
D7EN
D6EN
D5EN
D4EN
D3EN
D2EN
D1EN
Table 19. Bit Descriptions for the BLSEN Register
Bit Name
Bit No.
Description
N/A
7
6
Reserved
D7EN
Diode 7 backlight sink enable
1 = selects LED7 as an independent sink
0 = connects LED7 sink to backlight enable (BL_EN)
Diode 6 backlight sink enable
1 = selects LED6 as an independent sink
0 = connects LED6 sink to backlight enable (BL_EN)
Diode 5 backlight sink enable
1 = selects LED5 as an independent sink
0 = connects LED5 sink to backlight enable (BL_EN)
Diode 4 backlight sink enable
1 = selects LED4 as an independent sink
0 = connects LED4 sink to backlight enable (BL_EN)
Diode 3 backlight sink enable
1 = selects LED3 as an independent sink
0 = connects LED3 sink to backlight enable (BL_EN)
Diode 2 backlight sink enable
1 = selects LED2 as an independent sink
0 = connects LED2 sink to backlight enable (BL_EN)
Diode 1 backlight sink enable
D6EN
D5EN
D4EN
D3EN
D2EN
D1EN
5
4
3
2
1
0
1 = selects LED1 as an independent sink
0 = connects LED1 sink to backlight enable (BL_EN)
Rev. 0 | Page 26 of 40
ADP8861
Backlight Off Timeout (BLOFF)—Register 0x06
Table 20. BLOFF Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
OFFT
Bit 2
Bit 1
Bit 0
Reserved
Table 21. Bit Descriptions for the BLOFF Register
Bit Name Bit No. Description
N/A
7
Reserved.
OFFT
[6:0]
Backlight off timeout. After the off timeout (OFFT) period, the backlight turns off. If the dim timeout (DIMT) is
enabled, the off timeout starts after the dim timeout.
0000000 = timeout disabled
0000001 = 1 sec
0000010 = 2 sec
0000011 = 3 sec
…
1111111 = 127 sec
Backlight Dim Timeout (BLDIM)—Register 0x07
Table 22. BLDIM Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DIMT
Bit 2
Bit 1
Bit 0
Reserved
Table 23. Bit Descriptions for the BLDIM Register
Bit Name Bit No. Description
N/A
7
Reserved.
DIMT
[6:0]
Backlight dim timeout. After the dim timeout (DIMT) period, the backlight is set to the dim current value. The dim
timeout starts after backlight reaches the maximum current.
0000000 = timeout disabled
0000001 = 1 sec
0000010 = 2 sec
0000011 = 3 sec
…
1111111 = 127 sec
Rev. 0 | Page 27 of 40
ADP8861
Backlight Fade (BLFR)—Register 0x08
Table 24. BLFR Bit Map
Bit 7
Bit 6
Bit 5
BL_FO
Bit 4
Bit 3
Bit 2
Bit 1
BL_FI
Bit 0
Table 25. Bit Descriptions for the BLFR Register
Bit Name Bit No. Description
BL_FO
[7:4]
Backlight fade out rate. If fade out is disabled (BL_FO = 0000), the backlight changes instantly (within 100 ms). If the
fade out rate is set, the backlight fades from its current value to the dim or the off value. The times listed for BL_FO
are for a full-scale fade out (30 mA to 0 mA). Fades between closer current values reduce the fade time. See the
Automated Fade In and Fade Out section for more information.
0000 = 0.1 sec (fade out disabled)1
0001 = 0.3 sec
0010 = 0.6 sec
0011 = 0.9 sec
0100 = 1.2 sec
0101 = 1.5 sec
0110 = 1.8 sec
0111 = 2.1 sec
1000 = 2.4 sec
1001 = 2.7 sec
1010 = 3.0 sec
1011 = 3.5 sec
1100 = 4.0 sec
1101 = 4.5 sec
1110 = 5.0 sec
1111 = 5.5 sec
BL_FI
[3:0]
Backlight fade in rate. If fade in is disabled (BL_FI = 0000), the backlight changes instantly (within 100 ms). If the fade
in rate is set, the backlight fades from its current value to its maximum value when the backlight is turned on. The
times listed for BL_FI are for a full-scale fade in (0 mA to 30 mA). Fades between closer current values reduce the fade
time. See the Automated Fade In and Fade Out section for more information.
0000 = 0.1 sec (fade in disabled)1
0001 = 0.3 sec
0010 = 0.6 sec
0011 = 0.9 sec
…
1111 = 5.5 sec
1 When fade in and fade out are disabled, the backlight does not instantly fade, but instead, fades rapidly within about 100 ms.
Rev. 0 | Page 28 of 40
ADP8861
Backlight Maximum Current Register (BLMX)—Register 0x09
Table 26. BLMX Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BL_MC
Bit 2
Bit 1
Bit 0
Reserved
Table 27. Bit Descriptions for the BLMX Register
Bit Name Bit No.
Description
N/A
7
Reserved.
BL_MC
[6:0]
Backlight maximum current. The backlight maximum current can be set according to the linear or square law
function (see Table 28 for a complete list of values).
DAC
Linear Law (mA) Square Law (mA)
0000000
0000001
0000010
0000011
…
0
0.000
0.002
0.007
0.017
…
0.236
0.472
0.709
…
1111111
30
30
Table 28. Linear and Square Law Currents Per DAC Code (SCR = 0)
DAC Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
Linear Law (mA)
Square Law (mA)1
0.000
0.002
0.007
0.017
0.030
0.047
0.067
0.091
0.119
0.151
0.186
0.225
0.268
0.314
0.365
0.419
0.476
0.538
0.603
0.671
0.744
0.820
0.900
0.984
1.071
1.163
1.257
1.356
1.458
1.564
1.674
1.787
1.905
2.026
DAC Code
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
Linear Law (mA)
8.031
8.268
8.504
8.740
8.976
9.213
9.449
9.685
Square Law (mA)1
2.150
2.279
2.411
2.546
2.686
2.829
2.976
3.127
3.281
3.439
3.601
3.767
3.936
4.109
4.285
4.466
4.650
4.838
5.029
5.225
5.424
5.627
5.833
6.043
6.257
6.475
6.696
6.921
7.150
7.382
7.619
7.859
8.102
8.350
0
0.236
0.472
0.709
0.945
1.181
1.417
1.654
1.890
2.126
2.362
2.598
2.835
3.071
3.307
3.543
3.780
4.016
4.252
4.488
4.724
4.961
5.197
5.433
5.669
5.906
6.142
6.378
6.614
6.850
7.087
7.323
7.559
7.795
9.921
10.157
10.394
10.630
10.866
11.102
11.339
11.575
11.811
12.047
12.283
12.520
12.756
12.992
13.228
13.465
13.701
13.937
14.173
14.409
14.646
14.882
15.118
15.354
15.591
15.827
Rev. 0 | Page 29 of 40
ADP8861
DAC Code
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
Linear Law (mA)
16.063
16.299
16.535
16.772
17.008
17.244
17.480
17.717
17.953
18.189
18.425
18.661
18.898
19.134
19.370
19.606
19.842
20.079
20.315
20.551
20.787
21.024
21.260
21.496
21.732
21.968
22.205
22.441
22.677
22.913
Square Law (mA)1
8.601
8.855
9.114
9.376
9.642
9.912
DAC Code
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
Linear Law (mA)
23.150
23.386
23.622
23.858
24.094
24.331
24.567
24.803
25.039
25.276
25.512
25.748
25.984
26.220
26.457
26.693
26.929
27.165
27.402
27.638
27.874
28.110
28.346
28.583
28.819
29.055
29.291
29.528
29.764
30.000
Square Law (mA)1
17.863
18.230
18.600
18.974
19.351
19.733
20.118
20.507
20.899
21.295
21.695
22.099
22.506
22.917
23.332
23.750
24.173
24.599
25.028
25.462
25.899
26.340
26.784
27.232
27.684
28.140
28.599
29.063
29.529
30.000
10.185
10.463
10.743
11.028
11.316
11.608
11.904
12.203
12.507
12.814
13.124
13.439
13.757
14.078
14.404
14.733
15.066
15.403
15.743
16.087
16.435
16.787
17.142
17.501
1 Cubic 10 and Cubic 11 laws use the square law DAC setting but vary the time
step per DAC code (see Figure 29).
Rev. 0 | Page 30 of 40
ADP8861
Backlight Dim Current Register (BLDM)—Register 0x0A
Table 29. BLDM Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BL_DC
Bit 2
Bit 1
Bit 0
Reserved
Table 30. Bit Descriptions for the BLDM Register
Bit Name
Bit No.
Description
N/A
7
Reserved.
BL_DC
[6:0]
Backlight dim current. The backlight is set to the dim current value after a dim timeout or if the DIM_EN
flag is set by the user (see Table 28 for a complete list of values).
DAC
Linear Law (mA)
Square Law (mA)
0000000
0000001
0000010
0000011
…
0
0.000
0.002
0.007
0.017
…
0.236
0.472
0.709
…
1111111
30
30
INDEPENDENT SINK REGISTER DESCRIPTIONS
Independent Sink Current Fade Control Register (ISCFR)—Register 0x0F
Table 31. ISCFR Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SC_LAW
Reserved
Table 32. Bit Descriptions for the ISCFR
Bit Name
Bit No.
Description
N/A
[7:2]
Reserved
SC_LAW
[1:0]
Independent sink current fade transfer law
00 = linear law DAC, linear time steps
01 = square law DAC, linear time steps
10 = square law DAC, nonlinear time steps (Cubic 10)
11 = square law DAC, nonlinear time steps (Cubic 11)
Independent Sink Current Control (ISCC)—Register 0x10
Table 33. ISCC Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SC7_EN
SC6_EN
SC5_EN
SC4_EN
SC3_EN
SC2_EN
SC1_EN
Table 34. Bit Descriptions for the ISCC Register
Bit Name
Bit No.
Description
N/A
7
6
Reserved
SC7_EN
This enable acts upon LED7
1 = SC7 is turned on
0 = SC7 is turned off
SC6_EN
SC5_EN
5
4
This enable acts upon LED6
1 = SC6 is turned on
0 = SC6 is turned off
This enable acts upon LED5
1 = SC5 is turned on
0 = SC5 is turned off
Rev. 0 | Page 31 of 40
ADP8861
Bit Name
Bit No.
Description
SC4_EN
3
This enable acts upon LED4
1 = SC4 is turned on
0 = SC4 is turned off
SC3_EN
SC2_EN
SC1_EN
2
1
0
This enable acts upon LED3
1 = SC3 is turned on
0 = SC3 is turned off
This enable acts upon LED2
1 = SC2 is turned on
0 = SC2 is turned off
This enable acts upon LED1
1 = SC1 is turned on
0 = SC1 is turned off
Independent Sink Current Time (ISCT1)—Register 0x11
Table 35. ISCT1 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
SC7_OFF
Bit 3
Bit 2
SC6_OFF
Bit 1
Bit 0
SC5_OFF
SCON
Table 36. Bit Descriptions for the ISCT1 Register
Bit Name
Bit No.
Description1
SCON
[7:6]
SC on time. If the SCx_OFF time is not disabled and the independent current sink is enabled (Register
0x10), the LED(s) remains on for the on time selected (per the following list) and then turns off.
00 = 0.2 sec
01 = 0.6 sec
10 = 0.8 sec
11 = 1.2 sec
SC7_OFF
SC6_OFF
SC5_OFF
[5:4]
[3:2]
[1:0]
SC7 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is
set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns
on according to the SCON setting.
00 = off time disabled
01 = 0.6 sec
10 = 1.2 sec
11 = 1.8 sec
SC6 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is
set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns
on according to the SCON setting.
00 = off time disabled
01 = 0.6 sec
10 = 1.2 sec
11 = 1.8 sec
SC5 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is
set to any other value, then the ISC turns off for the off time (per the following listed times) and then turns
on according to the SCON setting.
00 = off time disabled
01 = 0.6 sec
10 = 1.2 sec
11 = 1.8 sec
1 Each current sink remains on continuously when its enable is set to 1 and its off time is set to 00 (disabled).
Rev. 0 | Page 32 of 40
ADP8861
Independent Sink Current Time (ISCT2)—Register 0x12
Table 37. ISCT2 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
SC3_OFF
Bit 3
Bit 2
SC2_OFF
Bit 1
Bit 0
SC4_OFF
SC1_OFF
Table 38. Bit Descriptions for the ISCT2 Register
Bit Name
Bit No.
Description1
SC4_OFF
[7:6]
SC4 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is
set to any other value, then the ISC turns off for the off time (per the following listed times) and then
turns on according to the SCON setting.
00 = off time disabled
01 = 0.6 sec
10 = 1.2 sec
11 = 1.8 sec
SC3_OFF
SC2_OFF
SC1_OFF
[5:4]
[3:2]
[1:0]
SC3 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is
set to any other value, then the ISC turns off for the off time (per the following listed times) and then
turns on according to the SCON setting.
00 = off time disabled
01 = 0.6 sec
10 = 1.2 sec
11 = 1.8 sec
SC2 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is
set to any other value, then the ISC turns off for the off time (per the following listed times) and then
turns on according to the SCON setting.
00 = off time disabled
01 = 0.6 sec
10 = 1.2 sec
11 = 1.8 sec
SC1 off time. When the SC off time is disabled, the ISC remains on while enabled. When the SC off time is
set to any other value, then the ISC turns off for the off time (per the following listed times) and then
turns on according to the SCON setting.
00 = off time disabled
01 = 0.6 sec
10 = 1.2 sec
11 = 1.8 sec
1 Each current sink remains on continuously when its enable is set to 1 and its off time is set to 00 (disabled).
Rev. 0 | Page 33 of 40
ADP8861
Independent Sink Current Fade (ISCF)—Register 0x13
Table 39. ISCF Bit Map
Bit 7
Bit 6
Bit 5
SCFO
Bit 4
Bit 3
Bit 2
Bit 1
SCFI
Bit 0
Table 40. Bit Descriptions for the ISCF Register
Bit Name
Bit No.
Description
SCFO
[7:4]
Sink current fade out rate. The following times listed are for a full-scale fade out (30 mA to 0 mA). Fades
between closer current values reduce the fade time. See the Automated Fade In and Fade Out section
for more information.
0000 = disabled
0001 = 0.30 sec
0010 = 0.60 sec
0011 = 0.90 sec
0100 = 1.2 sec
0101 = 1.5 sec
0110 = 1.8 sec
0111 = 2.1 sec
1000 = 2.4 sec
1001 = 2.7 sec
1010 = 3.0 sec
1011 = 3.5 sec
1100 = 4.0 sec
1101 = 4.5 sec
1110 = 5.0 sec
1111 = 5.5 sec
SCFI
[3:0]
Sink current fade in rate. The following times listed are for a full-scale fade in (0 mA to 30 mA). Fades
between closer current values reduce the fade time. See the Automated Fade In and Fade Out section
for more information.
0000 = disabled
0001 = 0.30 sec
0010 = 0.60 sec
0011 = 0.90 sec
0100 = 1.2 sec
0101 = 1.5 sec
0110 = 1.8 sec
0111 = 2.1 sec
1000 = 2.4 sec
1001 = 2.7 sec
1010 = 3.0 sec
1011 = 3.5 sec
1100 = 4.0 sec
1101 = 4.5 sec
1110 = 5.0 sec
1111 = 5.5 sec
Rev. 0 | Page 34 of 40
ADP8861
Sink Current Register LED7 (ISC7)—Register 0x14
Table 41. ISC7 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SCD7
Bit 2
Bit 1
Bit 0
SCR
Table 42. Bit Descriptions for the ISC7 Register
Bit Name
Bit No.
Description
SCR
7
1 = Sink Current 1.
0 = Sink Current 0.
SCD7
[6:0]
For Sink Current 0, use the following DAC code schedule (see Table 28 for a complete list of values):
DAC
Linear Law (mA)
Square Law (mA)
0000000
0
0.000
0.002
0.007
0.017
…
0000001 0.236
0000010 0.472
0000011 0.709
…
…
1111111 30
30
For Sink Current 1, use the following DAC code schedule (see Table 43 for a complete list of values):
DAC
Linear Law (mA)
Square Law (mA)
0000000 0.000
0000001 0.472
0000010 0.945
0000011 1.417
0
0.004
0.014
0.034
…
…
…
1111111 60
60
Table 43. Linear and Square Law Currents for LED7 (SCR = 1)
DAC Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
Linear Law (mA)
0.000
0.472
0.945
1.42
1.89
2.36
2.83
3.31
3.78
4.25
4.72
5.20
5.67
6.14
6.61
7.09
7.56
8.03
8.50
8.98
9.45
9.92
10.39
10.87
11.34
Square Law (mA)1
0
DAC Code
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
Linear Law (mA)
11.81
12.28
12.76
13.23
13.70
14.17
14.65
15.12
15.59
16.06
16.54
17.01
17.48
17.95
18.43
18.90
19.37
19.84
20.31
20.79
21.26
21.73
22.20
22.68
23.15
Square Law (mA)1
2.326
2.514
2.712
2.916
3.128
3.348
3.574
3.81
0.004
0.014
0.034
0.06
0.094
0.134
0.182
0.238
0.302
0.372
0.45
0.536
0.628
0.73
0.838
0.952
1.076
1.206
1.342
1.488
1.64
4.052
4.3
4.558
4.822
5.092
5.372
5.658
5.952
6.254
6.562
6.878
7.202
7.534
7.872
8.218
8.57
1.8
1.968
2.142
8.932
Rev. 0 | Page 35 of 40
ADP8861
DAC Code
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
Linear Law (mA)
23.62
24.09
24.57
25.04
25.51
25.98
26.46
26.93
27.40
27.87
28.35
28.82
29.29
29.76
30.24
30.71
31.18
31.65
32.13
32.60
33.07
33.54
34.02
34.49
34.96
35.43
35.91
36.38
36.85
37.32
37.80
38.27
38.74
39.21
39.69
40.16
40.63
41.10
41.57
Square Law (mA)1
9.3
9.676
10.058
10.45
DAC Code
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
Linear Law (mA)
42.05
42.52
42.99
43.46
43.94
44.41
44.88
45.35
45.83
46.30
46.77
47.24
47.72
48.19
48.66
49.13
49.61
50.08
50.55
51.02
51.50
51.97
52.44
52.91
53.39
53.86
54.33
54.80
55.28
55.75
56.22
56.69
57.17
57.64
58.11
58.58
59.06
59.53
60
Square Law (mA)1
29.466
30.132
30.806
31.486
32.174
32.87
33.574
34.284
35.002
35.726
36.46
10.848
11.254
11.666
12.086
12.514
12.95
13.392
13.842
14.3
14.764
15.238
15.718
16.204
16.7
37.2
37.948
38.702
39.466
40.236
41.014
41.798
42.59
17.202
17.71
43.39
18.228
18.752
19.284
19.824
20.37
44.198
45.012
45.834
46.664
47.5
48.346
49.198
50.056
50.924
51.798
52.68
53.568
54.464
55.368
56.28
57.198
58.126
59.058
60
20.926
21.486
22.056
22.632
23.216
23.808
24.406
25.014
25.628
26.248
26.878
27.514
28.156
28.808
1 Cubic 10 and Cubic 11 laws use the square law DAC setting but vary the time
step per DAC code (see Figure 29).
Rev. 0 | Page 36 of 40
ADP8861
Sink Current Register LED6 (ISC6)—Register 0x15
Table 44. ISC6 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SCD6
Bit 2
Bit 1
Bit 0
Reserved
Table 45. Bit Descriptions for the ISC6 Register
Bit Name
Bit No.
Description
N/A
7
Reserved.
SCD6
[6:0]
Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values).
DAC
Linear Law (mA)
Square Law (mA)
0000000
0000001
0000010
0000011
…
0
0.000
0.002
0.007
0.017
…
0.236
0.472
0.709
…
1111111
30
30
Sink Current Register LED5 (ISC5)—Register 0x16
Table 46. ISC5 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SCD5
Table 47. Bit Descriptions for the ISC5 Register
Bit Name
Bit No. Description
N/A
7
Reserved.
Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values):
SCD5
[6:0]
DAC
Linear Law (mA)
Square Law (mA)
0000000
0000001
0000010
0000011
…
0
0.000
0.002
0.007
0.017
…
0.236
0.472
0.709
…
1111111
30
30
Sink Current Register LED4 (ISC4)—Register 0x17
Table 48. ISC4 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SCD4
Table 49. Bit Descriptions for the ISC4 Register
Bit Name
Bit No.
Description
N/A
7
Reserved.
SCD4
[6:0]
Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values):
DAC
Linear Law (mA)
Square Law (mA)
0000000
0000001
0000010
0000011
…
0
0
0.236
0.472
0.709
…
0.002
0.007
0.017
…
1111111
30
30
Rev. 0 | Page 37 of 40
ADP8861
Sink Current Register LED3 (ISC3)—Register 0x18
Table 50. ISC3 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SCD3
Bit 2
Bit 1
Bit 0
Bit 0
Bit 0
Reserved
Table 51. Bit Descriptions for the ISC3 Register
Bit Name
N/A
Bit No.
Description
7
Reserved.
SCD3
[6:0]
Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values):
DAC
Linear Law (mA)
Square Law (mA)
0000000
0000001
0000010
0000011
…
0
0.000
0.002
0.007
0.017
…
0.236
0.472
0.709
…
1111111
30
30
Sink Current Register LED2 (ISC2)—Register 0x19
Table 52. ISC2 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SCD2
Bit 2
Bit 1
Reserved
Table 53. Bit Descriptions for the ISC2 Register
Bit Name
N/A
Bit No.
Description
7
Reserved.
SCD2
[6:0]
Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values):
DAC
Linear Law (mA)
Square Law (mA)
0000000
0000001
0000010
0000011
…
0
0.000
0.002
0.007
0.017
…
0.236
0.472
0.709
…
1111111
30
30
Sink Current Register LED1 (ISC1)—Register 0x1A
Table 54. ISC1 Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SCD1
Bit 2
Bit 1
Reserved
Table 55. Bit Descriptions for the ISC1 Register
Bit Name
Bit No.
Description
N/A
7
Reserved.
SCD1
[6:0]
Sink current. Use the following DAC code schedule (see Table 28 for a complete list of values):
DAC
Linear Law (mA)
Square Law (mA)
0000000
0000001
0000010
0000011
…
0
0.000
0.002
0.007
0.017
…
0.236
0.472
0.709
…
1111111
30
30
Rev. 0 | Page 38 of 40
ADP8861
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.65
2.50 SQ
2.35
5
11
6
10
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 43. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-10)
Dimensions shown in millimeters
Figure 44. Tape and Reel Orientation for LFCSP Units
ORDERING GUIDE
Model1
ADP8861ACPZ-RL
ADP8861DBCB-EVALZ
ADP886XMB1-EVALZ
Temperature Range
−40°C to +85°C
Package Description
Package Option
CP-20-10
20-Lead LFCSP_WQ, 7”Tape and Reel
Daughter Card
USB-to-I2C Adapter Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 39 of 40
ADP8861
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08391-0-4/10(0)
Rev. 0 | Page 40 of 40
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