ADPA1107-EVALZ [ADI]
45.0 dBm (35 W), 4.8 GHz to 6.0 GHz, GaN Power Amplifier;
| 型号： | ADPA1107-EVALZ |
| 厂家： | 
ADI |
| 描述： | 45.0 dBm (35 W), 4.8 GHz to 6.0 GHz, GaN Power Amplifier |
| 文件： | 总20页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
45.0 dBm (35 W), 4.8 GHz to 6.0 GHz,
GaN Power Amplifier
ADPA1107
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
POUT with PIN = 27.0 dBm: 45.0 dBm typical at 5.4 GHz to 6.0 GHz
Small signal gain: 30.5 dB typical at 4.8 GHz to 5.4 GHz
Frequency range: 4.8 GHz to 6.0 GHz
ADPA1107
PAE with PIN = 27.0 dBm: 56.5% typical at 5.4 GHz to 6.0 GHz
VREF
VDD: 28 V at IDQ = 350 mA with a 10% duty cycle
40-lead, 6 mm × 6 mm, LFCSP
GND
RFIN
GND
GND
RFOUT
GND
APPLICATIONS
Weather radars
Marine radars
Military radars
VDET
PACKAGE
BASE
GND
Figure 1.
GENERAL DESCRIPTION
The ADPA1107 is a gallium nitride (GaN), broadband power
amplifier, delivering 45.0 dBm (35 W) with 56.5% typical power
added efficiency (PAE) across a bandwidth of 4.8 GHz to
6.0 GHz. The ADPA1107 provides 0.5 dB gain flatness from
5.4 GHz to 6.0 GHz.
The ADPA1107 is ideal for pulsed applications such as radar,
public mobile radio, and general-purpose amplification.
The ADPA1107 is housed in a 40-lead, 6 mm × 6 mm, lead
frame chip scale package (LFCSP).
Rev. 0
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Technical Support
©2021 Analog Devices, Inc. All rights reserved.
www.analog.com
ADPA1107
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................6
Interface Schematics .....................................................................7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 16
Applications Information.............................................................. 17
Basic Connections...................................................................... 17
Thermal Management ............................................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Electrostatic Discharge (ESD) Ratings ...................................... 5
ESD Caution.................................................................................. 5
REVISION HISTORY
7/2021—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet
ADPA1107
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Base temperature (TBASE) = 25°C, supply voltage (VDD) = 28 V, quiescent current (IDQ) = 350 mA, pulse width = 100 µs, 10% duty cycle,
and frequency range = 4.8 GHz to 5.4 GHz, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Min
4.8
Typ
Max
5.4
Unit
GHz
Test Conditions/Comments
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
28.0
30.5
1.3
dB
dB
16.0
13.5
dB
dB
Output
POWER
Output Power (POUT
)
Input Power (PIN) = 25.0 dBm
PIN = 27.0 dBm
Power Gain
PIN = 25.0 dBm
PIN = 27.0 dBm
45.5
45.5
dBm
dBm
43.5
16.5
20.5
18.5
dB
dB
Power Added Efficiency (PAE)
PIN = 25.0 dBm
PIN = 27.0 dBm
56.5
55.0
350
%
%
QUIESCENT CURRENT (IDQ)
mA
Adjust the gate control voltage (VGG1) between −4 V and −2 V to
achieve an IDQ = 350 mA typical
Rev. 0 | Page 3 of 20
ADPA1107
Data Sheet
TBASE = 25°C, VDD = 28 V, I DQ = 350 mA, pulse width = 100 µs, 10% duty cycle, and frequency range = 5.4 GHz to 6.0 GHz, unless
otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
FREQUENCY RANGE
GAIN
5.4
6.0
GHz
Small Signal Gain
Gain Flatness
27.0
29.5
0.5
dB
dB
RETURN LOSS
Input
Output
7.5
12.0
dB
dB
POWER
POUT
PIN = 25.0 dBm
PIN = 27.0 dBm
Power Gain
PIN = 25.0 dBm
PIN = 27.0 dBm
PAE
45.0
45.0
dBm
dBm
43.0
16.0
20.3
18.0
dB
dB
PIN = 25.0 dBm
PIN = 27.0 dBm
IDQ
56.0
56.5
350
%
%
mA
Adjust the gate control voltage (VGG1) between −4 V and −2 V to achieve an
IDQ = 350 mA typical
Rev. 0 | Page 4 of 20
Data Sheet
ADPA1107
ABSOLUTE MAXIMUM RATINGS
Table 3.
THERMAL RESISTANCE
Overall thermal performance is directly linked to printed circuit
board (PCB) design and operating environment. Careful
attention to PCB thermal design is required.
Parameter
Drain Bias Voltage (VDD1A, VDD1B, VDD2A, and VDD2B
Negative Gate Bias Voltage (VGG1), VDD = 28 V
(Nominal Drain Voltage)
RF Input Power (RFIN)
Drain and Gate Bias
Pulse Width
Rating
35 V dc
−8 V dc to
−1 V dc
31 dBm
)
θJC is the channel to case thermal resistance (channel to exposed
metal on the underside of the device).
1000 µs
40%
Table 4. Thermal Resistance
Package Type1
Duty Cycle
θJC
Unit
Maximum Pulsed Power Dissipation (PDISS
)
CP-40-7
Drain Bias Pulse Width = 100 µs and
TBASE = 85°C
At 10% Duty Cycle, Derate 581 mW/°C
Above 85°C
At 40% Duty Cycle, Derate 538 mW/°C
Above 85°C
Drain Bias Pulse Width = 1000 µs and
TBASE = 85°C
Drain Bias Pulse Width = 100 µs at 10% Duty Cycle
Drain Bias Pulse Width = 100 µs at 40% Duty Cycle
Drain Bias Pulse Width = 1000 µs at 10% Duty Cycle
1.72 °C/W
1.86 °C/W
2.18 °C/W
81.4 W
75.2 W
1 θJC was determined under the following conditions: the heat transfer is due
solely to the thermal conduction from the channel through the ground pad
to the PCB, and the ground pad is held constant at the operating
temperature of 85°C.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
At 10% Duty Cycle, Derate 459 mW/°C
Above 85°C
Temperature
64.2 W
Nominal Pulsed Peak Channel, TBASE = 85°C,
PIN = 27 dBm
Drain Bias Pulse Width = 100 µs
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
ESD Ratings for ADPA1107
Table 5. ADPA1107, 40-Lead LFCSP
PDISS = 27.9 W at 5.4 GHz, and at
10% Duty Cycle
133°C
ESD Model
Withstand Threshold (V)
Class
PDISS = 29.2 W at 5.4 GHz and at
40% Duty Cycle
139.3°C
HBM
500
1B
Drain Bias Pulse Width = 1000 µs
ESD CAUTION
PDISS = 28.3 W at 5.4 GHz and at
10% Duty Cycle
Maximum Channel
146.7°C
225°C
Maximum Peak Reflow for Moisture Sensitivity 260°C
Level (MSL) 31
Storage Range
Operating Range
−60°C to +125°C
−40°C to +85°C
1 See the Ordering Guide section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 5 of 20
ADPA1107
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
40 39 38 37 36 35 34 33 32 31
30
NIC
NIC
1
2
NIC
29 NIC
28
NIC
3
4
NIC
27 VREF
NIC
ADPA1107
TOP VIEW
(Not to Scale)
26
25
5
6
GND
RFOUT
GND
RFIN
GND
NIC
24 GND
23
22
7
8
VDET
NIC
NIC
9
NIC
21 NIC
10
11 12 13 14 15 16 17 18 19 20
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE
NOT CONNECTED INTERNALLY, HOWEVER, ALL DATA
SHOWN WAS MEASURED WITH THESE PINS CONNECTED
TO RF AND DC GROUND EXTERNALLY.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO RF AND DC GROUND
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4, 8 to 12, 14 to 17,
20 to 22, 28 to 31, 34 to 37, 40
NIC
Not Internally Connected. These pins are not connected internally, however, all data
shown was measured with the NIC pins connected to RF and dc ground externally.
5, 7, 24, 26
GND
The GND pins must be connected to RF and dc ground. See Figure 3 for the interface
schematic.
6
RFIN
RF Input. The RFIN pin is ac-coupled and matched to 50 Ω. See Figure 4 for the
interface schematic.
13, 38
VDD1B, VDD1A
VDD2B, VDD2A
VDET
Power Supply Voltage for the Amplifier. First stage drain bias. See Figure 4 for the
interface schematic.
Power Supply Voltage for the Amplifier. Second stage drain bias. See Figure 5 for the
interface schematic.
Detector Diode to Measure RF Output Power. Output power detection via the VDET
pin requires the application of a dc bias voltage through an external series resistor.
Used in combination with the VREF pin, the difference voltage (VREF − VDET) is a
temperature compensated dc voltage that is proportional to the RF output power.
See Figure 5 for the interface schematic.
18, 19, 32, 33
23
25
27
39
RFOUT
VREF
RF Output. The RFOUT pin is ac-coupled and matched to 50 Ω. See Figure 5 for the
interface schematic.
Reference Diode for Temperature Compensation of VDET RF Output Power
Measurements. See Figure 6 for the interface schematic.
Gate Control Voltage Pin. See Figure 4 and Figure 5 for the interface schematic.
Exposed Pad. The exposed pad must be connected to RF and dc ground.
VGG1
EPAD
Rev. 0 | Page 6 of 20
Data Sheet
ADPA1107
INTERFACE SCHEMATICS
VDD2A/VDD2B
RFOUT
GND
VGG1
VDET
Figure 3. GND Interface Schematic
Figure 5. RFOUT, VGG1, VDD2A, VDD2B, and VDET Interface Schematic
VDD1A/VDD1B
RFIN
VGG1
VREF
Figure 6. VREF Interface Schematic
Figure 4. RFIN, VGG1, VDD1A, and VDD1B Interface Schematic
Rev. 0 | Page 7 of 20
ADPA1107
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
40
35
30
25
36
34
32
30
28
26
24
22
20
20
15
INPUT RETURN LOSS
SMALL SIGNAL GAIN
OUTPUT RETURN LOSS
10
5
0
–5
+85°C
+25°C
–40°C
–10
–15
–20
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.0
6.0
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Small Signal Gain vs. Frequency at
Various Temperatures
Figure 7. Small Signal Gain and Return Loss (Response) vs. Frequency
5
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–2
–40°C
–4
–6
–8
–5
–10
–12
–14
–16
–18
–20
–10
–15
–20
4.8
5.0
5.2
5.4
5.6
5.8
4.8
5.0
5.2
5.4
5.6
5.8
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 11. Output Return Loss vs. Frequency at
Various Temperatures
Figure 8. Input Return Loss vs. Frequency at
Various Temperatures
34
32
30
28
26
24
22
20
34
32
30
28
26
24
22
20
450mA
350mA
250mA
24V
28V
32V
4.8
5.0
5.2
5.4
5.6
5.8
4.8
5.0
5.2
5.4
5.6
5.8
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Small Signal Gain vs. Frequency at
Various Quiescent Currents and VDD1x and VDD2x = 28 V
Figure 9. Small Signal Gain vs. Frequency at
Various Supply Voltages and IDQ = 350 mA
Rev. 0 | Page 8 of 20
Data Sheet
ADPA1107
46.0
45.5
45.0
44.5
44.0
43.5
43.0
25
20
15
10
5
23dBm
23dBm
24dBm
25dBm
26dBm
27dBm
28dBm
29dBm
24dBm
25dBm
26dBm
27dBm
28dBm
29dBm
42.5
42.0
41.5
0
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.0
6.0
6.2
6.2
6.2
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.0
6.0
6.2
6.2
6.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. POUT vs. Frequency at
Various PIN Levels
Figure 16. Gain vs. Frequency at
Various PIN Levels
65
60
55
50
45
40
35
47
46
45
44
43
42
41
23dBm
24dBm
25dBm
26dBm
27dBm
28dBm
29dBm
+85°C
+25°C
–40°C
4.6
4.8
5.0
5.2
5.4
5.6
5.8
4.6
4.8
5.0
5.2
5.4
5.6
5.8
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. PAE vs Frequency at
Various PIN Levels
Figure 17. POUT vs. Frequency at
Various Temperatures and PIN = 27 dBm
47
46
45
44
43
42
41
65
60
55
50
45
40
35
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
4.6
4.8
5.0
5.2
5.4
5.6
5.8
4.6
4.8
5.0
5.2
5.4
5.6
5.8
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. POUT vs. Frequency at
Various Temperatures and PIN = 25 dBm
Figure 18. PAE vs. Frequency at
Various Temperatures and PIN = 25 dBm
Rev. 0 | Page 9 of 20
ADPA1107
Data Sheet
65
60
55
50
45
22
21
20
19
18
17
16
15
14
13
12
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
40
35
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.0
6.0
6.2
6.2
6.2
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.2
6.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 19. PAE vs. Frequency at
Figure 22. Gain vs. Frequency at
Various Temperatures and PIN = 27 dBm
Various Temperatures and PIN = 27 dBm
22
21
20
19
18
17
16
15
14
13
12
47
46
45
44
43
42
41
+85°C
+25°C
–40°C
24V
28V
32V
4.6
4.8
5.0
5.2
5.4
5.6
5.8
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. Gain vs. Frequency at
Figure 23. POUT vs. Frequency at
Various Supply Voltages and PIN = 27 dBm, IDQ = 350 mA
Various Temperatures and PIN = 25 dBm
47
46
45
44
43
42
41
65
60
55
50
45
40
35
24V
28V
32V
24V
28V
32V
4.6
4.8
5.0
5.2
5.4
5.6
5.8
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 24. PAE vs. Frequency at
Various Supply Voltages, PIN = 25 dBm, and IDQ = 350 mA
Figure 21. POUT vs. Frequency at
Various Supply Voltages, PIN = 25 dBm, and IDQ = 350 mA
Rev. 0 | Page 10 of 20
Data Sheet
ADPA1107
65
60
55
50
45
22
21
20
19
18
17
16
15
14
13
12
24V
28V
32V
24V
28V
32V
40
35
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.2
6.2
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.2
6.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 25. PAE vs. Frequency at
Various Supply Voltages, PIN = 27 dBm, and IDQ = 350 mA
Figure 28. Gain vs. Frequency at
Various Supply Voltages, PIN = 27 dBm, and IDQ = 350 mA
22
47
21
20
19
18
17
16
15
14
13
12
46
45
44
43
42
41
450mA
350mA
250mA
24V
28V
32V
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. Gain vs. Frequency at
Various Supply Voltages, PIN = 25 dBm, and IDQ = 350 mA
Figure 29. POUT vs. Frequency at
Various Quiescent Currents, PIN = 27 dBm, and VDD = 28 V
47
65
46
45
44
43
42
41
60
55
50
45
40
35
450mA
350mA
250mA
450mA
350mA
250mA
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 30. PAE vs. Frequency at
Various Quiescent Currents, PIN = 25 dBm, and VDD = 28 V
Figure 27. POUT vs. Frequency at
Various Quiescent Currents, PIN = 25 dBm, and VDD = 28 V
Rev. 0 | Page 11 of 20
ADPA1107
Data Sheet
65
60
55
50
45
22
21
20
19
18
17
16
15
14
13
12
450mA
350mA
250mA
450mA
350mA
250mA
40
35
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.2
6.2
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.2
6.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 31. PAE vs. Frequency at
Various Quiescent Currents, PIN = 27 dBm, and VDD = 28 V
Figure 34. Gain vs. Frequency at
PIN = 27 dBm and Various Quiescent Currents
22
47
46
45
44
43
42
41
21
20
19
18
17
16
15
14
13
12
PW = 100µs, DUTY CYCLE = 40%
PW = 100µs, DUTY CYCLE = 20%
PW = 10µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 10%
PW = 300µs, DUTY CYCLE = 10%
PW = 500µs, DUTY CYCLE = 10%
PW = 1000µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 5%
PW = 100µs, DUTY CYCLE = 2%
450mA
350mA
250mA
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 32. Gain vs. Frequency at
Various Quiescent Currents, PIN = 25 dBm, and VDD = 28 V
Figure 35. POUT vs. Frequency at
IN = 27 dBm and Various Pulse Widths (PW) and Duty Cycles
P
47
65
46
45
44
43
42
41
60
55
50
45
40
35
PW = 100µs, DUTY CYCLE = 40%
PW = 100µs, DUTY CYCLE = 20%
PW = 10µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 10%
PW = 300µs, DUTY CYCLE = 10%
PW = 500µs, DUTY CYCLE = 10%
PW = 1000µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 5%
PW = 100µs, DUTY CYCLE = 2%
PW = 100µs, DUTY CYCLE = 40%
PW = 100µs, DUTY CYCLE = 20%
PW = 10µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 10%
PW = 300µs, DUTY CYCLE = 10%
PW = 500µs, DUTY CYCLE = 10%
PW = 1000µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 5%
PW = 100µs, DUTY CYCLE = 2%
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 33. POUT vs. Frequency at
PIN = 25 dBm and Various Pulse Widths (PW) and Duty Cycles
Figure 36. PAE vs. Frequency at
PIN = 25 dBm and Various Pulse Widths (PW) and Duty Cycles
Rev. 0 | Page 12 of 20
Data Sheet
ADPA1107
65
60
55
50
22
21
20
19
18
17
16
15
14
13
12
PW = 100µs, DUTY CYCLE = 40%
PW = 100µs, DUTY CYCLE = 20%
PW = 10µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 10%
PW = 300µs, DUTY CYCLE = 10%
PW = 500µs, DUTY CYCLE = 10%
PW = 1000µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 5%
PW = 100µs, DUTY CYCLE = 2%
PW = 100µs, DUTY CYCLE = 40%
PW = 100µs, DUTY CYCLE = 20%
PW = 10µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 10%
PW = 300µs, DUTY CYCLE = 10%
PW = 500µs, DUTY CYCLE = 10%
PW = 1000µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 5%
PW = 100µs, DUTY CYCLE = 2%
45
40
35
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 37. PAE vs. Frequency at
PIN = 27 dBm and Various Pulse Widths (PW) and Duty Cycles
Figure 40. Gain vs. Frequency at
PIN = 27 dBm and Various Pulse Widths (PW) and Duty Cycles
22
21
20
19
18
17
65
60
55
50
45
40
35
30
25
20
15
10
5
2800
P
OUT
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
GAIN
PAE
I
DD
16
PW = 100µs, DUTY CYCLE = 40%
PW = 100µs, DUTY CYCLE = 20%
PW = 10µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 10%
PW = 300µs, DUTY CYCLE = 10%
PW = 500µs, DUTY CYCLE = 10%
PW = 1000µs, DUTY CYCLE = 10%
PW = 100µs, DUTY CYCLE = 5%
PW = 100µs, DUTY CYCLE = 2%
15
14
13
12
600
400
0
200
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
(dBm)
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
P
FREQUENCY (GHz)
IN
Figure 38. Gain vs. Frequency at
IN = 25 dBm and Various Pulse Widths (PW) and Duty Cycles
Figure 41. POUT, Gain, PAE, and IDD vs. PIN at 5.4 GHz
P
60
55
50
45
40
35
30
25
20
15
10
5
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
60
55
50
45
40
35
30
25
20
15
10
5
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
P
P
OUT
OUT
GAIN
GAIN
PAE
PAE
I
I
DD
DD
600
600
400
400
0
200
0
200
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
(dBm)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
(dBm)
P
P
IN
IN
Figure 39. POUT, Gain, PAE, and IDD vs. PIN at 4.8 GHz
Figure 42. POUT, Gain, PAE, and IDD vs. PIN at 6.0 GHz
Rev. 0 | Page 13 of 20
ADPA1107
Data Sheet
35
35
30
25
20
15
10
5
4.8GHz
4.8GHz
5.0GHz
5.2GHz
5.4GHz
5.6GHz
5.8GHz
6.0GHz
5.0GHz
5.2GHz
5.4GHz
5.6GHz
5.8GHz
6.0GHz
30
25
20
15
10
5
0
–10
0
–10
0
10
20
30
0
10
20
30
P
(dBm)
P
(dBm)
IN
IN
Figure 43. Power Dissipation vs. PIN
Drain Bias Pulse Width = 100 µs, 10% Duty Cycle, and TBASE = 85°C
,
Figure 46. Power Dissipation vs. PIN,
Drain Bias Pulse Width = 100 µs, 20% Duty Cycle, and TBASE = 85°C
35
35
4.8GHz
4.8GHz
5.0GHz
5.0GHz
30
30
5.2GHz
5.2GHz
5.4GHz
5.6GHz
5.4GHz
5.6GHz
25
20
15
10
5
25
20
15
10
5
5.8GHz
6.0GHz
5.8GHz
6.0GHz
0
–10
0
–10
0
10
20
30
0
10
20
30
P
(dBm)
P
(dBm)
IN
IN
Figure 44. Power Dissipation vs. PIN
Drain Bias Pulse Width = 100 µs, 2% Duty Cycle, and TBASE = 85°C
,
Figure 47. Power Dissipation vs. PIN,
Drain Bias Pulse Width = 100 µs, 5% Duty Cycle, and TBASE = 85°C
10
1500
1400
1300
1200
1100
1000
900
+85°C
+25°C
–40°C
1
800
700
600
0.1
500
400
300
200
100
0.01
0
–3.0
26
28
30
32
34
36
38
40
42
44
46
–2.9
–2.8
–2.7
–2.6
–2.5
–2.4
–2.3
–2.2
P
(dBm)
VGG1 (V)
OUT
Figure 48. IDQ vs. VGG1,
VDD1x and VDD2x = 28 V, Representative of a Typical Device
Figure 45. Detector Voltage (VREF − VDET) vs. POUT at
Various Temperatures and 5.4 GHz
Rev. 0 | Page 14 of 20
Data Sheet
ADPA1107
0
+85°C
+25°C
–40°C
–10
–20
–30
–40
–50
–60
4.8
5.0
5.2
5.4
5.6
5.8
6.0
FREQUENCY (GHz)
Figure 49. Reverse Isolation vs. Frequency at
Various Temperatures at VDD1x and VDD2x = 28 V
Rev. 0 | Page 15 of 20
ADPA1107
Data Sheet
THEORY OF OPERATION
The ADPA1107 is a GaN, broadband power amplifier that
delivers 45 dBm (35 W) of pulsed power. The device consists of
two cascaded gain stages. A simplified block diagram is shown
in Figure 50.
must be used). The negative dc voltage applied to the VGG1 pin
biases the gates of the first and the second gain stages,
respectively, to allow control of the drain currents of each stage
A portion of the RF output signal is directionally coupled to a
diode for detection of the RF output power. When the diode is
dc biased, the diode rectifies the RF power and makes the RF
power available for measurement as a dc voltage at the VDET
pin. To allow temperature compensation of VDET, an identical
and symmetrically located circuit, minus the coupled RF power,
is available via VREF. Taking the difference of VREF − VDET
provides a temperature compensated signal that is proportional
to the RF output power (see Figure 51).
The ADPA1107 has single-ended RFIN and RFOUT ports that
are ac-coupled. The impedances of these ports are nominally
50 Ω over the 4.8 GHz to 6.0 GHz frequency range. Consequently,
the ADPA1107 can be directly inserted into a 50 Ω system
without the need for external impedance matching components
or ac coupling capacitors.
The drain bias voltage applied to the VDD1A, VDD1B,
VDD2A, and VDD2B pins biases the drains of the first and the
second gain stages, respectively (a single common supply voltage
VDD1A VDD2A VDD2A
VREF
VGG1
RFIN
RFOUT
DIRECTIONAL
COUPLER
VDET
VDD1B VDD2B VDD2B
Figure 50. Simplified Block Diagram
Rev. 0 | Page 16 of 20
Data Sheet
ADPA1107
APPLICATIONS INFORMATION
In gate pulsed mode, VDDxA and VDDxB are held at a fixed
level (nominally +28 V), while the gate voltage is pulsed between
−4 V (off) and approximately −2.6 V (on). The exact on level
BASIC CONNECTIONS
The basic connections for operating the ADPA1107 are shown
in Figure 51. Apply a power supply voltage of between 28 V and
32 V on all VDDxA and VDDxB pins. Decouple the VDDxA
and VDDxB pins with the capacitor values shown in Figure 51.
The VDD1x pins require a 2.55 Ω resistor in series with the
decoupling capacitor to assist with making the ADPA1107
unconditionally stable. The VGG1 pin is used to set the IDQ of all
stages. The decoupling capacitors on the VDDxA, VDDxB, and
VGG1 lines represent the configuration that was used to
characterize and qualify the ADPA1107.
can be adjusted to achieve the desired IDQ
.
In drain pulsed mode, VDDxA and VDDxB are pulsed on and
off while the gate voltage is held at a fixed negative level
between −2 V and −4 V. Because high currents and voltages are
being switched on and off, a metal-oxide semiconductor field
effect transistor (MOSFET) and a MOSFET switch driver are
required in the circuit. Large capacitors are also required, which
act as local reservoirs of charge and help provide the drain
current required by the ADPA1107 while maintaining a steady
drain voltage during the on time of the pulse.
Pin 1 through Pin 4, Pin 8 through Pin 12, Pin 14 through
Pin 17, Pin 20 through Pin 22, Pin 28 through Pin 31, Pin 34
through Pin 37, and Pin 40 are designated as no internal
connection (NIC) pins. Although the NIC pins are not
internally connected, the NIC pins were all connected to
ground during the characterization of the device.
The ADPA1107-EVALZ includes a plug-in pulser board that
contains the required circuitry to implement drain pulsed
mode. See the ADPA1107A-EVALZ user guide (UG-1962)
for additional information.
To safely turn power on, the VGG1 voltage must be set to −4 V
before the VDDxA and the VDDxB voltages are applied. After
VGG1 is increased to achieve the desired IDQ, the RF input can
be applied.
Apply a voltage between −2 V and −4 V to the VGG1 line to set
the drain current. The device can be operated by pulsing either
the gate voltage or the drain voltage.
To safely turn power off, remove the RF input signal and decrease
VGG1 to −4 V. VDDxA and VDDxB can then be decreased to 0
V before increasing VGG1 to 0 V.
Rev. 0 | Page 17 of 20
ADPA1107
Data Sheet
VDD1A
VDD2A
VGG1
1 µF
2200pF
1000pF
1000pF
2.55Ω
1
2
3
4
NIC
30
29
NIC
NIC
VREF
NIC
NIC
NIC
5V
28
27
NIC
VREF
10kΩ
1pF
GND
RFIN
5
GND
26
25
RFOUT
6
5V
DIRECTIONAL
COUPLER
GND
NIC
NIC
NIC
GND
24
23
22
21
7
8
VDET
GROUND
PAD
10kΩ
1pF
NIC
NIC
9
VDET
10
VDD1B
VDD2B
1000pF
1000pF
2.55Ω
Figure 51. Basic Connections
Rev. 0 | Page 18 of 20
Data Sheet
ADPA1107
Next, consider a pulsed bias condition at a low duty cycle (see
THERMAL MANAGEMENT
Figure 53). When bias is applied, the TCHAN of the device can be
described as a series of exponentially rising and decaying
pulses. The peak channel temperature reached during
consecutive pulses increases during the turn on transient interval,
and eventually, settles to a steady state condition where peak
channel temperatures from pulse to pulse stabilize.
Proper thermal management is critical to achieve the specified
performance and rated operating life. Pulsed biasing limits
the average power dissipated and maintains a safe channel
temperature. The channel (or die) temperature correlates
closely with the mean time to failure (MTTF).
Consider a continuous bias condition (see Figure 52). When
bias is applied, the channel temperature (TCHAN) of the device
rises through a turn on transient interval and eventually settles
to a steady state value. The θJC of the device is the rise in TCHAN
above the starting TBASE divided by the total device PDISS, which is
calculated by
POWER DISSIPATED
DURING THE PULSE
T
CHAN
tRISE = θ × P
JC
DISS
T
BASE
θ
JC = tRISE/PDISS
where:
RISE is the rise in TCHAN of the device above the TBASE (°C).
DISS is the power dissipation (W) of the device.
(1)
TIME
Figure 53. Pulsed Bias Condition at a Low Duty Cycle
t
P
Table 7 shows the thermal resistance values for various pulse
conditions.
Table 7. Pulse Settings and Thermal Resistance Values
T
CHAN
Pulse Settings
tRISE = θ × P
JC
DISS
Pulse Width (µs)
Duty Cycle (%)
θJC (°C/W)
1.72
1.76
T
100
100
500
10
20
10
BASE
TIME
2.10
Figure 52. Channel Temperature Rise for Continuous Bias Condition
Narrower pulse widths and/or lower duty cycles can result in
greater reliability.
Rev. 0 | Page 19 of 20
ADPA1107
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
AREA
PIN 1
IONS
INDICATOR AR EA OP T
(SEE DETAIL A)
31
40
1
30
0.50
BSC
4.70
EXPOSED
PAD
4.60 SQ
4.50
10
21
20
11
0.45
0.40
0.35
0.20 MIN
TOP VIEW
END VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
Figure 54. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature
−40°C to +85°C
−40°C to +85°C
MSL Rating2
MSL3
Description3
Package Option
CP-40-7
CP-40-7
ADPA1107ACPZN
ADPA1107ACPZN-R7
ADPA1107-EVALZ
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
MSL3
1 The ADPA1107ACPZN and ADPA1107ACPZN-R7 models are RoHS compliant parts.
2 See the Absolute Maximum Ratings section for additional information.
3 The lead finish of ADPA1107ACPZN and ADPA1107ACPZN-R7 is nickel palladium gold (NiPdAu).
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D26290-7/21(0)
Rev. 0 | Page 20 of 20
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