ADPA7007AEHZ-R7 [ADI]
20 GHz to 44 GHz, GaAs, pHEMT, 31.5 dBm 1">(>1 W), MMIC Power Amplifier;
| 型号： | ADPA7007AEHZ-R7 |
| 厂家： | 
ADI |
| 描述： | 20 GHz to 44 GHz, GaAs, pHEMT, 31.5 dBm 1">(>1 W), MMIC Power Amplifier |
| 文件： | 总23页 (文件大小：589K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20 GHz to 44 GHz, GaAs, pHEMT,
31.5 dBm (>1 W), MMIC Power Amplifier
Data Sheet
ADPA7007
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADPA7007
Output P1dB: 29 dBm typical at 34 GHz to 44 GHz
PSAT: 31.5 dBm typical at 26 GHz to 34 GHz
Gain: 20.5 dB typical at 34 GHz to 44 GHz
Output IP3: up to 42.5 dBm typical
Supply voltage: 5 V at 1400 mA
50 Ω matched input/output
18-terminal, 7 mm × 7 mm LCC_HS package
Integrated power detector
1
2
3
4
13
12
11
10
V
V
V
V
V
V
V
V
DD1
DD3
DD5
DD2
DD4
DD6
GG2
APPLICATIONS
GG1
Military and space
Test instrumentation
Communications
Figure 1.
GENERAL DESCRIPTION
The ADPA7007 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transfer (pHEMT), monolithic microwave
integrated circuit (MMIC), 31.5 dBm saturated output power
(>1 W) power amplifier, with an integrated temperature
compensated, on-chip power detector that operates between
20 GHz and 44 GHz. The ADPA7007 provides 20.5 dB of small
signal gain and approximately 32 dBm of saturated output power
at 32 GHz from a 5 V supply (see Figure 26). The ADPA7007
has an output IP3 of 42.5 dBm and is ideal for linear
applications such as electronic countermeasure and
instrumentation applications requiring >30 dBm of efficient
saturated output power. The RF input/outputs are internally
matched and dc blocked for ease of integration into higher level
assemblies. The ADPA7007 is packaged in a 7 mm × 7 mm,
18-terminal ceramic leadless chip carrier with heat sink
(LCC_HS) that exhibits low thermal resistance and is
compatible with surface-mount manufacturing techniques.
Rev. 0
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Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADPA7007
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Typical Performance Characteristics .............................................8
Constant IDD Operation............................................................. 15
Theory of Operation ...................................................................... 16
Applications Information ............................................................. 17
Biasing ADPA7007 with the HMC980LP4E.............................. 18
Application Circuit Setup ......................................................... 18
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
20 GHz to 26 GHz Frequency Range ........................................ 3
26 GHz to 34 GHz Frequency Range ........................................ 3
34 GHz to 44 GHz Frequency Range ........................................ 4
Absolute Maximum Ratings ........................................................... 5
Thermal Resistance...................................................................... 5
Electrostatic Discharge (ESD) Ratings...................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions ............................ 6
Interface Schematics .................................................................... 7
Limiting VGATE and VNEG for ADPA7007 VGGx Absolute
Maximum Rating Requirement ............................................... 18
HMC980LP4E Bias Sequence................................................... 21
Constant Drain Current Biasing vs. Constant Gate Voltage
Biasing.......................................................................................... 21
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 23
Data Sheet
ADPA7007
SPECIFICATIONS
20 GHz TO 26 GHz FREQUENCY RANGE
TA = 25°C, drain bias voltage (VDD) = 5 V, and quiescent drain current (IDQ) = 1400 mA for nominal operation, unless otherwise noted.
50 Ω matched input/output.
Table 1.
Parameter
Symbol Min Typ
Max Unit
Test Conditions/Comments
FREQUENCY RANGE
GAIN
20
26
GHz
dB
18
20
Gain Flatness
1
dB
Gain Variation over
Temperature
0.021
dB/°C
NOISE FIGURE
RETURN LOSS
Input
6
dB
12
12
dB
dB
Output
OUTPUT
Output Power for 1 dB
Compression
P1dB
26.5 29
dBm
Saturated Output Power
Output Third-Order
Intercept
PSAT
IP3
30
39
dBm
dBm
Measurement taken at output power (POUT) per tone = 16 dBm
Measured at PSAT
POWER ADDED EFFICIENCY
SUPPLY
PAE
11
%
Adjust VGGx from −1.5 V up to 0 V to achieve the desired IDQ,
VGGx = −0.685 V typical to achieve IDQ = 1400 mA
Quiescent Drain Current
Drain Bias Voltage
IDQ
VDD
1400
5
mA
V
4
26 GHz TO 34 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 1400 mA for nominal operation, unless otherwise noted. 50 Ω matched input/output.
Table 2.
Parameter
Symbol Min Typ
Max Unit
Test Conditions/Comments
FREQUENCY RANGE
GAIN
Gain Flatness
26
34
GHz
dB
dB
19.5 21.5
0.5
Gain Variation over
Temperature
0.021
dB/°C
NOISE FIGURE
RETURN LOSS
Input
5.5
dB
13
13
dB
dB
Output
OUTPUT
Output Power for 1 dB
Compression
P1dB
28
30
dBm
Saturated Output Power
Output Third-Order
Intercept
PSAT
IP3
31.5
42.5
dBm
dBm
Measurement taken at POUT per tone = 16 dBm
Measured at PSAT
POWER ADDED EFFICIENCY
SUPPLY
PAE
14
%
Adjust VGGx from −1.5 V up to 0 V to achieve the desired IDQ,
VGGx = −0.685 V typical to achieve IDQ = 1400 mA
Current
Voltage
IDQ
VDD
1400
5
mA
V
4
Rev. 0 | Page 3 of 23
ADPA7007
Data Sheet
34 GHz TO 44 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 1400 mA for nominal operation, unless otherwise noted. 50 Ω matched input/output.
Table 3.
Parameter
Symbol Min Typ
Max Unit
Test Conditions/Comments
FREQUENCY RANGE
GAIN
34
44
GHz
dB
18.5 20.5
Gain Flatness
1
dB
Gain Variation over
Temperature
0.04
dB/°C
NOISE FIGURE
RETURN LOSS
Input
6
dB
15
18
dB
dB
Output
OUTPUT
Output Power for 1 dB
Compression
P1dB
28.5 29
dBm
Saturated Output Power
Output Third-Order
Intercept
PSAT
IP3
31
41
dBm
dBm
Measurement taken at POUT per tone = 16 dBm
Measured at PSAT
POWER ADDED EFFICIENCY
SUPPLY
PAE
13
%
Adjust VGGx from −1.5 V up to 0 V to achieve the desired IDQ,
VGGx = −0.685 V typical to achieve IDQ = 1400 mA
Current
Voltage
IDQ
VDD
1400
5
mA
V
4
Rev. 0 | Page 4 of 23
Data Sheet
ADPA7007
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Thermal performance is directly linked to system design and
operating environment. Careful attention to the printed circuit
board (PCB) thermal design is required.
Parameter
Rating
Drain Bias Voltage (VDDx
Gate Bias Voltage (VGGx
Radio Frequency Input Power (RFIN)
)
6.0 V
)
−1.6 V to 0 V
27 dBm
12.33 W
θJC is the channel to case thermal resistance, channel to bottom
Continuous Power Dissipation (PDISS),
T = 85°C (Derate 137 mW/°C
Above 85°C)
Storage Temperature Range
Operating Temperature Range
Junction Temperature to Maintain
1,000,000 Hour Mean Time to Failure
(MTTF)
of die using die attach epoxy.
Table 5. Thermal Resistance
Package Type
−55°C to +150°C
−40°C to +85°C
175°C
θJC
Unit
EH-18-11
7.3
°C/W
1 θJC is determined by simulation under the following conditions: the heat
transfer is due solely to thermal conduction from the channel, through the
ground pad, to the PCB. The ground pad is held constant at the operating
temperature of 85°C.
Nominal Junction Temperature
(T = 85°C, VDD = 5 V, IDQ = 1400 mA)
Peak Reflow Temperature1
136.1°C
ELECTROSTATIC DISCHARGE (ESD) RATINGS
260°C
MSL3
The following ESD information is provided for handling of
ESD sensitive devices in an ESD protected area only.
Moisture Sensitivity Level
1 See the Ordering Guide for additional information.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
ESD Ratings for ADPA7007
Table 6. ADPA7007, 18-Terminal LCC_HS
ESD Model
Withstand Threshold (V)
Class
HBM
250
1A
ESD CAUTION
Rev. 0 | Page 5 of 23
ADPA7007
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
13
12
11
10
V
V
V
V
V
V
V
V
DD1
DD3
DD5
DD2
DD4
DD6
GG2
2
3
4
ADPA7007
GG1
NOTES
1. NIC = NO INTERNAL CONNECTION. NOTE
THAT DATA SHOWN HEREIN WAS
MEASURED WITH THESE PINS EXTERNALLY
CONNECTED TO RF AND DC GROUND.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF AND DC GROUND.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
Drain Bias for the Amplifier.
1, 2, 3, 11, 12, 13
V
V
DD1, VDD3, VDD5
DD6, VDD4, VDD2
,
4, 10
5, 9
VGG1, VGG2
NIC
Amplifier Gate Control. ESD protection diodes are included and turn on below −1.5 V.
Not Internally Connected. Note that data shown herein was measured with these pins externally
connected to RF and dc ground.
6, 8, 15, 17
7
14
GND
RFIN
VDET
Ground Pins. Connect the GND pins and the exposed pad to RF and dc ground.
RF Signal Input. This pin is ac-coupled and internally matched to 50 Ω.
Detector Diode Used for Measuring the RF Output Power. Detection via VDET requires the application
of a dc bias voltage through an external series resistor. Used in combination with VREF, the difference
voltage, VREF − VDET, is a temperature compensated dc voltage proportional to the RF output power.
16
18
RFOUT
VREF
RF Signal Output. RFOUT is ac-coupled and internally matched to 50 Ω.
Reference Diode Used for Temperature Compensation of VDET RF Output Power Measurements.
Detection via VERF requires the application of a dc bias voltage through an external series resistor.
Used in combination with VDET, this voltage provides temperature compensation to VDET RF output
power measurements.
EPAD
Exposed Pad. The exposed pad must be connected to RF and dc ground.
Rev. 0 | Page 6 of 23
Data Sheet
ADPA7007
INTERFACE SCHEMATICS
GND
V
,
GG1
V
GG2
Figure 3. GND Interface Schematic
Figure 7. VGG1, VGG2 Interface Schematic
VREF
RFOUT
Figure 8. RFOUT Interface Schematic
Figure 4. VREF Interface Schematic
V
TO V
DD1
DD6
VDET
Figure 5. VDET Interface Schematic
Figure 9. VDD1 to VDD6 Interface Schematic
RFIN
Figure 6. RFIN Interface Schematic
Rev. 0 | Page 7 of 23
ADPA7007
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
30
26
24
22
20
18
16
14
12
10
8
25
20
15
10
INPUT RETURN LOSS
5
0
GAIN
OUTPUT RETURN LOSS
–5
+85°C
+25°C
–40°C
–10
–15
–20
14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Gain and Return Loss vs. Frequency, VDD = 5 V, IDQ = 1400 mA
Figure 13. Gain vs. Frequency for Various Temperatures, VDD = 5 V,
IDQ = 1400 mA
28
26
24
22
20
18
16
26
24
22
20
18
1000mA
16
1200mA
4V
5V
14
1400mA
1500mA
1600mA
1800mA
14
12
12
10
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 11. Gain vs. Frequency for Various VDD, IDQ = 1400 mA
Figure 14. Gain vs. Frequency for Various IDQ, VDD = 5 V
0
0
+85°C
+25°C
–40°C
4V
5V
–5
–10
–15
–20
–25
–5
–10
–15
–20
18 20 22 24 26 28 30 32 34 36 38 40 42 44
–25
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. Input Return Loss vs. Frequency for Various VDD
IDQ = 1400 mA
,
Figure 12. Input Return Loss vs. Frequency for Various Temperatures,
VDD = 5 V, IDQ = 1400 mA
Rev. 0 | Page 8 of 23
Data Sheet
ADPA7007
0
0
–5
+85°C
+25°C
–40°C
–5
–10
–15
–10
–15
–20
–25
1000mA
1200mA
1400mA
1500mA
1600mA
1800mA
–20
–25
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Input Return Loss vs. Frequency for Various IDQ, VDD = 5 V
Figure 19. Output Return Loss vs. Frequency for Various Temperature,
VDD = 5 V, IDQ = 1400 mA
0
0
4V
5V
–5
–10
–15
–20
–5
–10
–15
1000mA
1200mA
1400mA
1500mA
1600mA
1800mA
–20
–25
–25
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 17. Input Return Loss vs Frequency for Various VDD
IDQ = 1400 mA
,
Figure 20. Output Return Loss vs. Frequency for Various IDQ
,
VDD = 5 V
0
10
9
8
7
6
5
4
3
2
1
0
+85°C
+25°C
–40°C
–10
–20
–30
–40
–50
–60
–70
+85°C
+25°C
–40°C
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 18. Reverse Isolation vs. Frequency for Various Temperatures,
VDD = 5 V, IDQ = 1400 mA
Figure 21. Noise Figure vs. Frequency for Various Temperatures,
VDD = 5 V, IDQ = 1400 mA
Rev. 0 | Page 9 of 23
ADPA7007
Data Sheet
36
34
32
30
28
26
24
22
20
18
16
14
12
10
36
34
32
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
4V
5V
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 22. Output P1dB vs. Frequency for Various Temperatures,
VDD = 5 V, IDQ = 1400 mA
Figure 25. Output P1dB vs. Frequency for Various VDD, IDQ = 1400 mA
36
34
32
30
28
26
24
22
20
36
34
32
30
28
26
24
22
20
18
18
16
14
12
10
1000mA
1200mA
1400mA
1500mA
1600mA
1800mA
16
14
12
10
+85°C
+25°C
–40°C
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 23. Output P1dB vs. Frequency for Various IDQ, VDD = 5 V
Figure 26. PSAT vs. Frequency for Various Temperatures, VDD = 5 V,
IDQ = 1400 mA
36
34
32
30
28
26
24
22
20
18
36
34
32
30
28
26
24
22
20
1000mA
18
1200mA
4V
5V
1400mA
1500mA
1600mA
1800mA
16
14
16
14
12
10
12
10
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 24. PSAT vs. Frequency for Various VDD, IDQ = 1400 mA
Figure 27. PSAT vs. Frequency for Various IDQ, VDD = 5 V
Rev. 0 | Page 10 of 23
Data Sheet
ADPA7007
20
18
16
14
12
10
8
20
18
16
14
12
10
8
6
6
+85°C
+25°C
–40°C
4V
5V
4
2
0
4
2
0
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 28. Power Added Efficiency (PAE) vs. Frequency for Various Temperatures,
VDD = 5 V, IDQ = 1400 mA, PAE Measured at PSAT
Figure 31. PAE vs. Frequency for Various VDD, IDQ = 1400 mA,
PAE Measured at PSAT
20
18
16
14
12
10
32
28
24
20
16
12
8
2300
P
GAIN
PAE
OUT
2175
2050
1925
1800
1675
1550
1425
1300
I
DD
8
1000mA
6
1200mA
1400mA
4
2
0
1500mA
1600mA
1800mA
4
0
–15
–10
–5
0
5
10
15
18 20 22 24 26 28 30 32 34 36 38 40 42 44
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 29. PAE vs. Frequency for Various IDQ, VDD = 5 V, IDQ = 1400 mA,
PAE Measured at PSAT
Figure 32. POUT, Gain, PAE, and IDD vs. Input Power, 20 GHz, VDD = 5 V,
IDD = 1400 mA
32
28
24
20
16
12
8
2100
36
32
28
24
20
16
12
8
2110
P
GAIN
PAE
OUT
P
OUT
GAIN
PAE
I
DD
2020
1930
1840
1750
1660
1570
1480
1390
1300
2000
1900
1800
1700
1600
1500
1400
1300
I
DD
4
4
0
–15
0
–15
–10
–5
0
5
10
15
–10
–5
0
5
10
15
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 30. POUT, Gain, PAE, and Drain Current with RF Applied (IDD) vs. Input
Power, 22 GHz, VDD = 5 V, IDD = 1400 mA
Figure 33. POUT, Gain, PAE, and IDD vs. Input Power,
30 GHz, VDD = 5 V, IDD = 1400 mA
Rev. 0 | Page 11 of 23
ADPA7007
Data Sheet
36
2020
1940
1860
1780
1700
1620
1540
1460
1380
1300
32
28
24
20
16
12
8
2020
1930
1840
1750
1660
1570
1480
1390
P
GAIN
PAE
P
OUT
GAIN
PAE
I
DD
OUT
32
28
24
20
16
12
8
I
DD
4
4
0
–15
0
–15
1300
15
–10
–5
0
5
10
15
–10
–5
0
5
10
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 34. POUT, Gain, PAE, and IDD vs. Input Power,
34 GHz, VDD = 5 V, IDD = 1400 mA
Figure 37. POUT, Gain, PAE, and IDD vs. Input Power,
38 GHz, VDD = 5 V, IDD = 1400 mA
32
28
24
20
16
12
8
2260
2140
2020
1900
1780
1660
1540
1420
1300
50
P
GAIN
PAE
OUT
45
40
35
30
25
20
15
I
DD
4V
5V
4
0
–15
–10
–5
0
5
10
15
18 20 22 24 26 28 30 32 34 36 38 40 42 44
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 38. Output IP3 vs. Frequency for Various VDD
POUT per Tone = 16 dBm, IDQ = 1400 mA
,
Figure 35. POUT, Gain, PAE, and IDD vs. Input Power,
44 GHz, VDD = 5 V, IDD = 1400 mA
50
45
40
35
30
25
20
15
50
45
40
35
30
25
20
15
1000mA
1200mA
1400mA
1500mA
1600mA
1800mA
+85°C
+25°C
–40°C
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 36. Output IP3 vs. Frequency for Various Temperatures,
POUT per Tone = 16 dBm, VDD = 5 V, IDQ = 1400 mA
Figure 39. Output IP3 vs Frequency for Various IDQ, POUT per Tone = 16 dBm,
VDD = 5 V
Rev. 0 | Page 12 of 23
Data Sheet
ADPA7007
2100
1800
1500
1200
900
90
80
70
60
50
40
30
20
10
0
20GHz
22GHz
28GHz
30GHz
32GHz
34GHz
38GHz
44GHz
600
300
15
–1.5 –1.4 –1.3 –1.2 –1.1 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5
10
12
14
16
18
20
22
V
(V)
P
OUT
PER TONE (dBm)
GGx
Figure 40. IDQ vs. VGGx
Figure 43. IM3 vs. POUT per Tone, VDD = 5 V, IDQ = 1400 mA
2200
2100
2000
1900
1800
1700
1600
1500
1400
1300
11
10
9
20GHz
22GHz
28GHz
30GHz
32GHz
34GHz
38GHz
44GHz
20GHz
22GHz
28GHz
30GHz
32GHz
34GHz
38GHz
44GHz
8
7
6
5
–10
–15
–10
–5
0
5
10
15
–5
0
5
10
15
RF INPUT POWER (dBm)
RF INPUT POWER (dBm)
Figure 41. IDD vs. RF Input Power at Various Frequencies,
VDD = 5 V, IDD = 1400 mA
Figure 44. Power Dissipation vs. RF Input Power at TA = 85°C, VDD = 5 V,
IDQ = 1400 mA
90
80
70
60
50
40
30
20
10
0
10.00
1.00
0.10
20GHz
22GHz
28GHz
30GHz
32GHz
34GHz
38GHz
44GHz
+85°C
+25°C
–40°C
0.01
4
6
8
10
12
14
16
18
20
4
8
12
16
20
24
28
32
P
PER TONE (dBm)
OUTPUT POWER (dBm)
OUT
Figure 45. VREF − VDET vs. Output Power for Various Temperatures at 30 GHz
Figure 42. Third-Order Intermodulation Distortion (IM3) vs. POUT per Tone,
VDD = 4 V, IDQ = 1400 mA
Rev. 0 | Page 13 of 23
ADPA7007
Data Sheet
10
10
8dBm
20dBm
+85°C
+25°C
–40°C
10dBm
12dBm
22dBm
24dBm
26dBm
28dBm
14dBm
16dBm
18dBm
1
1
0.1
0.1
0.01
0.01
4
8
12
16
20
24
28
32
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
OUTPUT POWER (dBm)
Figure 46. VREF − VDET vs. Output Power for Various Temperatures at 20 GHz
Figure 48. VREF − VDET vs. Frequency for Various POUT Levels
4
10
+85°C
+25°C
–40°C
22GHz
24GHz
26GHz
28GHz
30GHz
32GHz
34GHz
36GHz
38GHz
40GHz
42GHz
44GHz
46GHz
3
2
1
1
0
–1
–2
–3
–4
0.1
0.01
–12
0
2
4
6
8
10 12 14
4
8
12
16
20
24
28
32
RF INPUT POWER (dBm)
OUTPUT POWER (dBm)
Figure 47. VREF − VDET vs. Output Power for Various Temperatures at 40 GHz
Figure 49. Gate Current (IGG) vs. RF Input Power at Various Frequencies,
VDD = 5 V, IDQ = 1400 mA
Rev. 0 | Page 14 of 23
Data Sheet
ADPA7007
CONSTANT IDD OPERATION
Biased with HMC980LP4E active bias controller (see Figure 56), TA = 25°C, VDD = 5 V, and IDD = 1800 mA for nominal operation, unless
otherwise noted. Data measured with constant IDD
.
34
32
30
28
26
24
22
20
34
32
30
28
26
24
22
20
18
16
14
12
10
18
1200mA
1400mA
1600mA
1800mA
2000mA
+85°C
+25°C
–40°C
16
14
12
10
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 50. Output P1dB vs. Frequency for Various Temperatures
Figure 52. Output P1dB vs. Frequency for Various Drain Currents
34
32
30
28
26
24
22
20
34
32
30
28
26
24
22
20
18
18
16
14
12
10
1200mA
1400mA
1600mA
1800mA
2000mA
+85°C
+25°C
–40°C
16
14
12
10
18 20 22 24 26 28 30 32 34 36 38 40 42 44
18 20 22 24 26 28 30 32 34 36 38 40 42 44
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 51. PSAT vs. Frequency for Various Temperatures
Figure 53. PSAT vs. Frequency for Various Drain Currents
Rev. 0 | Page 15 of 23
ADPA7007
Data Sheet
THEORY OF OPERATION
The simplified architecture of the ADPA7007 power amplifier
is shown in Figure 54. The ADPA7007 is a cascaded, three-
stage amplifier with a combined gain of 21.5 dB and a PSAT
value of 31.5 dBm.
A portion of the RF output signal is directionally coupled to a
diode for detection of the RF output power. When the diode is
dc biased, the diode rectifies the RF power and makes the RF
power available for measurement as a dc voltage at VDET. To
allow temperature compensation of VDET, an identical and
symmetrically located circuit (minus the coupled RF power) is
available via VREF. The difference of VREF − VDET provides a
temperature compensated signal that is proportional to the RF
output.
The drain current is controlled by the voltage on the VGG1 and
VGG2 pins. These pins must be connected together and driven
by a negative voltage in the −1.5 V to 0 V range (typical gate
bias voltage for a quiescent drain current bias of 1400 mA is
−0.685 V). Simplified bias pin connections to the dedicated
gain stages are shown in Figure 54.
To obtain optimal performance from the ADPA7007 and avoid
damaging the device, follow the recommended biasing
sequences described in the Applications Information section.
V
V
V
V
V
V
DD5
DD6
DD3 DD4
DD1 DD2
RFIN
RFOUT
V
V
GG1 GG2
Figure 54. Simplified Architecture of ADPA7007
Rev. 0 | Page 16 of 23
Data Sheet
ADPA7007
APPLICATIONS INFORMATION
Figure 55 shows the basic connections for operating the
ADPA7007. All measurements for this device were taken using
the typical application circuit shown in Figure 55.
The following is the recommended bias sequence during
power-down:
1. Turn off the RF signal.
Capacitive bypassing is required for all VGGx and VDDx pins. VGG1
and VGG2 are the gate bias pins, and VDD1 to VDD6 are the drain
bias pins for the cascaded amplifier.
2. Decrease the gate bias voltages, VGG1 and VGG2, to −1.5 V to
achieve an IDQ = 0 mA (approximately).
3. Decrease all drain bias voltages to 0 V.
4. Increase the VGGx gate bias voltage to 0 V.
The power supply and gate voltage decoupling capacitors
shown in Figure 55 represent the configuration that was used to
characterize and qualify the device. There may be scopes to
reduce the number of capacitors, but scopes vary from system
to system. It is recommended to first remove or combine the
largest capacitors that are farthest from the device. The
following is the recommended bias sequence during power-up:
The VDD = 5 V and IDQ = 1400 mA bias conditions are recom-
mended to optimize overall performance when the gate voltage
is being held at a fixed value (note that with the gate voltage held at
a fixed value, the drain current, IDD, increases as the RF input
power level is increased, as shown in Figure 41). Unless otherwise
noted, the data shown was taken using the recommended bias
conditions. Operation of the ADPA7007 at different bias
conditions can result in different performance. Biasing the
ADPA7007 for higher quiescent drain current typically results
in higher gain and output P1dB at the expense of increased
power dissipation (see Table 8).
1. Connect the power supply ground to circuit ground (GND).
2. Set the gate bias voltages, VGG1 and VGG2, to −1.5 V.
3. Set all drain bias voltages (VDDx) to 5 V.
4. Increase the gate bias voltage to achieve the quiescent
supply current and set IDQ = 1400 mA.
5. Apply the RF signal.
Table 8. Power Selection1, 2
IDQ (mA)
Gain (dB)
Output P1dB (dBm)
Output IP3 (dBm)
PDISS (W)
VGGx (V)
−0.73
−0.68
−0.63
1200
1400
1600
15.80
16.20
16.50
31.89
31.93
31.95
42.90
41.30
39.55
6
7
8
1 Data taken at the following nominal bias conditions: VDD = 5 V, TA = 25°C, frequency = 32 GHz.
2 Adjust VGG1 and VGG2 from −1.5 V to 0 V to achieve the desired quiescent drain current, IDQ
.
V
V
,
,
DD1
DD3
V
DD5
C15
4.7µF
C9
1000pF
C3
100pF
C2
100pF
C8
1000pF
C14
4.7µF
+5V
+5V
V
GG1
C1
100pF
C7
1000pF
C13
4.7µF
C31
4.7µF
C26
1000pF
C21
100pF
100kΩ
100kΩ
10kΩ
10kΩ
4
3
2
1
VREF
18
5
6
7
8
9
–
+
17
16
15
14
10kΩ
10kΩ
RFIN
RFOUT
ADPA7007
VOUT = VREF – VDET
VDET
10
11
12
13
SUGGESTED CIRCUIT
–5V
V
GG2
C16
4.7µF
C10
1000pF
C4
100pF
C6
100pF
C12
1000pF
C18
4.7µF
C17
4.7µF
C11
1000pF
C5
100pF
C23
100pF
C19
1000pF
C30
4.7µF
V
,
,
DD2
DD4
V
V
DD6
Figure 55. Typical Application Circuit
Rev. 0 | Page 17 of 23
ADPA7007
Data Sheet
BIASING ADPA7007 WITH THE HMC980LP4E
The HMC980LP4E is an active bias controller that measures
and regulates drain current by automatically adjusting the gate
voltage. The HMC980LP4E can control the biasing of RF
amplifiers with drain voltages up to 16.5 V and currents up to
1.6 A. The controller provides constant drain current biasing
over temperature and device to device variation, and properly
sequences gate and drain voltages to ensure the safe operation
of the amplifier.
Two HMC980LP4E devices are needed to support current
levels at 1800 mA because a single HMC980LP4E device can
support a maximum current of 1600 mA. In the application
circuit shown in Figure 56 and Figure 57, the ADPA7007 drain
voltage and drain current are set by the following equations:
VDRAIN = VDD − IDRAIN × 0.85 Ω
where:
VDRAIN = 5 V, the drain voltage from Pin 17 and Pin 18 of the
(1)
The HMC980LP4E offers self protection in the event of a short
circuit, as well as an internal charge pump that generates the
negative voltage required on the gate of the ADPA7007. The
HMC980LP4E also provides the option to use an external
negative voltage source. The HMC980LP4E is also available in
die form as the HMC980.
HMC980LP4E.
V
DD = 5.765 V, the supply voltage to the HMC980LP4E.
I
DRAIN = 1800 mA, the constant drain current from Pin 17 and
Pin 18 on the HMC980LP4E.
150 Ω
R10 =
(2)
IDRAIN
APPLICATION CIRCUIT SETUP
where:
Figure 56 shows a schematic of an application circuit using the
two HMC980LP4E devices to control the ADPA7007. When
using an external negative supply for VNEG, refer to the
schematic in Figure 57.
I
DRAIN = 900 mA (for each HMC980LP4E, per the dual bias
setup in Figure 56).
R10 = 166.66 Ω.
LIMITING VGATE AND VNEG FOR ADPA7007 VGGX
ABSOLUTE MAXIMUM RATING REQUIREMENT
Although the ADPA7007 is specified with a quiescent drain
current of 1400 mA, the operational drain current, IDRAIN, required
to achieve the maximum output power from the ADPA7007
must be set closer to 1800 mA. The IDRAIN current increases to
approximately 1800 mA when the RF input power is 15 dBm,
the approximate input compression point (see Figure 41). As a
result, a target IDRAIN of 1800 mA is chosen.
When using the HMC980LP4E to control the ADPA7007, set
the minimum voltages for the VNEG and VGATE pins of the
HMC980LP4E to −1.5 V to keep these voltages within the absolute
maximum rating limits for the VGGx pins of the ADPA7007. To
set the minimum voltages, use the R15 and R16 resistors shown
in Figure 56 and Figure 57. Refer to the AN-1363 Application
Note, Meeting Biasing Requirements of Externally Biased
RF/Microwave Amplifiers with Active Bias Controllers, for more
information and calculations for R15 and R16.
Rev. 0 | Page 18 of 23
Data Sheet
ADPA7007
R13
R12
R11
301Ω
R10
165Ω
4.7kΩ 301Ω
R14
10kΩ
VDD
5.765V
24 23 22 21 20 19
VDD
VDRAIN
VDRAIN
VGATE
VNEG
1
2
3
4
5
6
18
17
16
15
C15
C16
C17
C18
C19
C20
C1
4.7µF
C2
VDD
4.7µF
1000pF
100pF
100pF
1000pF
4.7µF
10nF
S0
S1
HMC980LP4E
C21
4.7µF
C22
1000pF
C23
100pF
EN
EN
C24
100pF
C25
1000pF
C26
4.7µF
14 VG2
13
ALM
VG2_CONT
R16
475kΩ
7
8
9
10 11 12
4
3
2
1
18
17
16
15
14
5
6
7
8
9
VDRAIN = 5V
= 1.8A
I
DRAIN
RFIN
RFOUT
C3
ADPA7007
R15
100pF
VDIG
3.3V TO 5.0V
732kΩ
C6
D1 DUAL
1µF SCHOTTKY
C4
4.7µF
C5
10nF
10
11
12
13
C7
10µF
C27
4.7µF
C28
1000pF
C29
100pF
C30
100pF
C31
1000pF
C32
4.7µF
R19
R18
R17
301Ω
4.7kΩ 301Ω
C33
4.7µF
C34
1000pF
C35
100pF
C36
100pF
C37
1000pF
C38
4.7µF
R20
10kΩ
VDD
5.765V
24 23 22 21 20 19
VDD
VDRAIN
VDRAIN
1
2
3
4
5
6
18
17
C8
4.7µF
C9
VDD
10nF
S0
S1
16 VGATE
HMC980LP4E
VNEG
15
EN
EN
14 VG2
13
ALM
VG2_CONT
7
8
9
10 11 12
C10
100pF
VDIG
3.3V TO 5.0V
C11
4.7µF
C12
10nF
Figure 56. Application Circuit Using Dual HMC980LP4E with ADPA7007
Rev. 0 | Page 19 of 23
ADPA7007
Data Sheet
R13
R12
R11
301Ω
R10
165Ω
4.7kΩ 301Ω
R14
10kΩ
VDD
5.765V
24 23 22 21 20 19
VDD
VDRAIN
VDRAIN
VGATE
VNEG
1
2
3
4
5
6
18
17
16
15
C15
C16
C17
C18
C19
C20
C1
4.7µF
C2
VDD
4.7µF
1000pF
100pF
100pF
1000pF
4.7µF
10nF
S0
S1
HMC980LP4E
C21
4.7µF
C22
1000pF
C23
100pF
EN
EN
C24
100pF
C25
1000pF
C26
4.7µF
14 VG2
13
ALM
VG2_CONT
R16
475kΩ
7
8
9
10 11 12
4
3
2
1
18
17
16
15
14
5
6
7
8
9
VDRAIN = 5V
= 1.8A
I
DRAIN
RFIN
RFOUT
C3
ADPA7007
100pF
VDIG
3.3V TO 5.0V
C4
4.7µF
C5
10nF
10
11
12
13
C27
4.7µF
C28
1000pF
C29
100pF
C30
100pF
C31
1000pF
C32
4.7µF
R19
R18
R17
301Ω
4.7kΩ 301Ω
C33
4.7µF
C34
1000pF
C35
100pF
C36
100pF
C37
1000pF
C38
4.7µF
R20
10kΩ
VDD
5.765V
24 23 22 21 20 19
VDD
VDRAIN
VDRAIN
1
2
3
4
5
6
18
17
16
15
C8
4.7µF
C9
VDD
10nF
S0
S1
VNEG
–1.5V
VGATE
VNEG
HMC980LP4E
EN
EN
14 VG2
13
ALM
VG2_CONT
7
8
9
10 11 12
C10
100pF
VDIG
3.3V TO 5.0V
C11
4.7µF
C12
10nF
Figure 57. Application Circuit Using Dual HMC980LP4E with ADPA7007 and External Negative Voltage Source
Rev. 0 | Page 20 of 23
Data Sheet
ADPA7007
HMC980LP4E BIAS SEQUENCE
T
V
DD
The dc supply sequencing in the Power-Up Sequence section
and the Power-Down Sequence section is required to prevent
damage to the HMC980LP4E when using it to control the
ADPA7007.
VDRAIN
EN
1
Power-Up Sequence
3
VGATE
The power-up sequence is as follows:
1. Set VDIG (Pin 9) of both HMC980LP4E devices to 3.3 V.
2. Set the VDD pins of both HMC980LP4E devices to
5.765 V.
3. Set VNEG (Pin 15) of both HMC980LP4E devices to
−1.5 V. This step is not needed if using an internally
generated voltage.
4. Set EN (Pin 5) of both HMC980LP4E devices to 3.3 V
(transitioning from 0 V to 3.3 V turns on VGATE and
VDRAIN).
CH1 2V CH2 1V
CH3 2V CH4 2V
M20.0ms
A
CH1
1.12V
50.00%
Figure 59. Turn Off HMC980LP4E Outputs to ADPA7007
CONSTANT DRAIN CURRENT BIASING vs.
CONSTANT GATE VOLTAGE BIASING
Power-Down Sequence
The HMC980LP4E uses a feedback loop to continuously adjust
VGATE to maintain a constant drain current over dc supply
variation, temperature, RF input/output level, and device to
device variation. Constant drain current bias is the preferred
method for reducing time in calibration procedures and for
maintaining consistent performance over time.
The power-down sequence is as follows:
1. Set EN (Pin 5 of both HMC980LP4E devices) to 0 V
(transitioning from 3.3 V to 0 V turns off VDRAIN and
VGATE).
2. Set VNEG (Pin 15 of both HMC980LP4E devices) to 0 V.
This step is not needed if using an internally generated
voltage.
In comparison to a constant gate voltage bias, where the current
increases when RF power is applied, a constant drain current has
a slightly lower output P1dB. This output P1db is shown in
Figure 63, where the RF performance is slightly lower than
constant gate bias voltage operation due to a lower drain current at
high input power (see Figure 60) as the HMC980LP4E reaches
1 dB compression.
3. Set the VDD pins of both HMC980LP4E devices to 0 V.
4. Set VDIG (Pin 9 of both HMC980LP4E devices) to 0 V.
When the HMC980LP4E bias control circuit is set up, toggle
the bias to the ADPA7007 on or off by applying 3.3 V or 0 V,
respectively, to the EN pin of the HMC980LP4E. At EN = 3.3 V,
the VGATE pin of the HMC980LP4E drops to −1.5 V and the
VDRAIN pin of the HMC980LP4E turns on at 5 V. VGATE
then rises until IDRAIN = 1800 mA, and the closed control loop
regulates IDRAIN at 1800 mA. When EN = 0 V, VGATE is set to
−1.5 V, and VDRAIN is set to 0 V (see Figure 58 and Figure 59).
The output P1dB performance for constant drain current bias
can be increased toward constant gate voltage bias performance
by increasing the set current toward the IDD value it reaches
under RF drive in the constant gate voltage bias condition (see
Figure 63).
The limit of increasing drain current under the constant
current operation is set by the thermal limitations found in
Table 4 with the maximum power dissipation specification. As
the IDD increase continues, the actual output P1dB does not
continue to increase indefinitely but the power dissipation
increases linearly. Therefore, take the trade-off between the
power dissipation and output P1dB performance into
consideration when using constant drain current biasing.
T
V
DD
VDRAIN
EN
1
3
VGATE
CH1 2V CH2 1V
CH3 2V CH4 2V
M20.0ms
CH1 1.12V
A
50.00%
Figure 58. Turn On HMC980LP4E Outputs to ADPA7007
Rev. 0 | Page 21 of 23
ADPA7007
Data Sheet
2200
2000
1800
1600
1400
1200
18
16
14
12
10
8
CONSTANT GATE VOLTAGE
CONSTANT DRAIN CURRENT
6
4
CONSTANT GATE VOLTAGE
CONSTANT DRAIN CURRENT
2
1000
–15
0
–15
–10
–5
0
5
10
15
–10
–5
0
5
10
15
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 60. Drain Current vs. Input Power, VDD = 5 V, Frequency = 32 GHz,
Constant Drain Current Bias (IDRAIN Setpoint = 1800 mA) and Constant Gate
Voltage Bias (VGGx ≈ −0.68 V)
Figure 62. PAE vs. Input Power, VDD = 5 V, Frequency = 32 GHz,
Constant Drain Current Bias (IDRAIN Setpoint = 1800 mA) and Constant Gate
Voltage Bias (VGGx ≈ −0.68 V)
34
30
26
22
18
14
34
32
30
28
26
24
22
20
18
CONSTANT GATE VOLTAGE
CONSTANT DRAIN CURRENT
10
16
14
12
10
CONSTANT GATE VOLTAGE
CONSTANT DRAIN CURRENT
6
2
–15
–10
–5
0
5
10
15
18 20 22 24 26 28 30 32 34 36 38 40 42 44
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 61. Output Power vs. Input Power, VDD = 5 V, Frequency = 32 GHz,
Constant Drain Current Bias (IDRAIN Setpoint = 1800 mA) and Constant Gate
Voltage Bias (VGGx ≈ −0.68 V)
Figure 63. Output P1dB vs. Frequency, VDD = 5 V, Constant Drain Current Bias
(IDRAIN Setpoint = 1800 mA) and Constant Gate Voltage Bias
(VGGx ≈ −0.68 V))
Rev. 0 | Page 22 of 23
Data Sheet
ADPA7007
OUTLINE DIMENSIONS
3.55
3.45
3.35
1.75
1.65
1.55
7.20
7.00 SQ
6.80
0.31
0.25
0.19
0.35 REF
0.89
1.05
PIN 1
INDICATOR
14
18
13
10
1
0.60
0.50
0.40
3.10
3.00
2.90
4.50
4.40
4.30
4.55 BSC
SQ
4
1.00 BSC
9
5
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1.21
1.15
1.09
0.80 REF
0.63
0.57
0.51
1.444
1.317
1.190
5.40 SQ
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 64. 18-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HS]
(EH-18-1)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
MSL
Package
Option
Model1
Rating2
Package Description
ADPA7007AEHZ
ADPA7007AEHZ-R7 −40°C to +85°C MSL3
ADPA7007-EVALZ
−40°C to +85°C MSL3
18-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HS] EH-18-1
18-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HS] EH-18-1
1 Z = RoHS Compliant Part.
2 See the Absolute Maximum Ratings section for additional information.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21544-7/20(0)
Rev. 0 | Page 23 of 23
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