ADPA9002ACGZN-R7 [ADI]
GaAs, pHEMT, MMIC, Single Positive Supply, DC to 10 GHz Power Amplifier;
| 型号： | ADPA9002ACGZN-R7 |
| 厂家： | 
ADI |
| 描述： | GaAs, pHEMT, MMIC, Single Positive Supply, DC to 10 GHz Power Amplifier 射频 微波 |
| 文件： | 总19页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GaAs, pHEMT, MMIC, Single Positive Supply,
DC to 10 GHz Power Amplifier
ADPA9002
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADPA9002
OP1dB: 29 dBm typical
Gain: up to 15 dB typical
OIP3: up to 43 dBm typical
Self biased at VDD = 12 V at 385 mA typical with an optional
bias control on VGG1 for IDQ adjustment
50 Ω matched input/output
GND
NIC
NIC
1
2
3
4
5
6
7
8
24 GND
23 NIC
22
GND
32-lead, 5 mm × 5 mm LFCSP
21 RFOUT/V
GND
RFIN
GND
NIC
DD
20
19
GND
NIC
APPLICATIONS
18 NIC
17 GND
GND
Military and space
Test instrumentation
PACKAGE
BASE
GND
Figure 1.
GENERAL DESCRIPTION
The ADPA9002 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transistor (pHEMT), monolithic
microwave integrated circuit (MMIC), power amplifier that
operates between dc and 10 GHz. The amplifier provides 15 dB
of gain, 42 dBm of OIP3, and 31.5 dBm of saturated output
power (PSAT) while requiring 385 mA from a 12 V supply. The
ADPA9002 is self biased in normal operation and has an
test equipment applications. The ADPA9002 also features inputs
and outputs that are internally matched to 50 Ω, housed in a
RoHS compliant, 5 mm × 5 mm LFCSP premolded cavity
package, making it compatible with high volume surface-mount
technology (SMT) assembly equipment.
Note that throughout this data sheet, multifunction pins, such
as RFOUT/VDD, are referred to either by the entire pin name or
by a single function of the pin, for example, VDD, when only that
function is relevant.
optional bias control for supply quiescent current (IDQ
)
adjustment. The amplifier is ideal for military and space and
Rev. 0
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2019 Analog Devices, Inc. All rights reserved.
www.analog.com
ADPA9002
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Interface Schematics .....................................................................7
Typical Performance Characteristics ..............................................8
Constant IDD Operation ............................................................. 16
Theory of Operation ...................................................................... 17
Applications Information .............................................................. 18
Typical Application Circuit....................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC to 2 GHz ................................................................................. 3
2 GHz to 5 GHz ............................................................................ 3
5 GHz to 10 GHz .......................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
REVISION HISTORY
10/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 19
Data Sheet
ADPA9002
SPECIFICATIONS
DC TO 2 GHz
TA = 25°C, VDD = 12 V, IDQ = 385 mA, VGG1= GND for nominal self biased operation, and frequency range = dc to 2 GHz, with a 50 Ω
matched input and output, unless otherwise noted.
Table 1.
Parameter
Symbol
Min Typ
DC
Max
Unit
GHz
dB
Test Conditions/Comments
FREQUENCY RANGE
GAIN
2
12.5 14.5
Gain Variation Over Temperature
NOISE FIGURE
RETURN LOSS
Input
0.01
dB/°C
dB
5
18
14
dB
dB
Output
OUTPUT
Output Power for 1 dB Compression OP1dB
27
10
29
31
43
dBm
dBm
dBm
Saturated Output Power
PSAT
Output Third-Order Intercept
OIP3
Measurement taken at output power (POUT) per tone =
14 dBm
SUPPLY
Quiescent Current
IDQ
385
12
mA
V
For external bias control, adjust VGG1 between −2 V and
+0.5 V to achieve the desired IDQ
Drain Voltage
VDD
15
2 GHz TO 5 GHz
TA = 25°C, VDD = 12 V, IDQ = 385 mA, VGG1 = GND for nominal self biased operation, and frequency range = 2 GHz to 5 GHz, unless
otherwise noted. 50 Ω matched input/output.
Table 2.
Parameter
Symbol
Min Typ
Max Unit
Test Conditions/Comments
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
NOISE FIGURE
RETURN LOSS
Input
2
5
GHz
dB
dB/°C
dB
13
15
0.008
3
14
15
dB
dB
Output
OUTPUT
Output Power for 1 dB Compression OP1dB
27
10
29
31.5
42
dBm
dBm
dBm
Saturated Output Power
PSAT
Output Third-Order Intercept
OIP3
Measurement taken at POUT per tone = 14 dBm
SUPPLY
Quiescent Current
IDQ
385
12
mA
V
For external bias control, adjust VGG1 between −2 V and
+0.5 V to achieve the desired IDQ
Drain Voltage
VDD
15
Rev. 0 | Page 3 of 19
ADPA9002
Data Sheet
5 GHz TO 10 GHz
TA = 25°C, VDD = 12 V, IDQ = 385 mA, VGG1 = GND for nominal self biased operation, and frequency range = 5 GHz to 10 GHz, with a
50 Ω matched input and output, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
5
Typ
Max Unit
Test Conditions/Comments
FREQUENCY RANGE
GAIN
10
GHz
dB
13.5
15.5
Gain Variation Over Temperature
NOISE FIGURE
0.016
dB/°C
dB
4
RETURN LOSS
Input
Output
19
13
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY
OP1dB
PSAT
OIP3
25
10
28
31
40.5
dBm
dBm
dBm
Measurement taken at POUT/tone = 14 dBm
Quiescent Current
IDQ
385
12
mA
V
For external bias control, adjust VGG1 between
−2 V and +0.5 V to achieve the desired IDQ
Drain Voltage
VDD
15
Rev. 0 | Page 4 of 19
Data Sheet
ADPA9002
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
VDD
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required. θJC is the junction to case
thermal resistance.
Rating
16 V
VGG1
RFIN
−2.5 V to +1 V
25 dBm
10.2 W
Continuous Power Dissipation (PDISS), T = 85°C
(Derate 113.64 mW/°C Above 85°C)
Table 5. Thermal Resistance
Package
θJC
Unit
Output Load Voltage Standing Wave Ratio
(VSWR)
7:1
CG-32-2
8.8
°C/W
Temperature
Storage Range
Operating Range
Peak Reflow (Moisture Sensitivity Level
(MSL) 3)
−65°C to +150°C
−40°C to +85°C
260°C
ESD CAUTION
Junction to Maintain 1 Million Hour Mean
Time to Failure (MTTF)
175°C
Nominal Junction (T = 85°C, VDD = 12 V)
125.7°C
ESD Sensitivity
Human Body Model (HBM)
Class 1B, passed
500 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 5 of 19
ADPA9002
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
NIC
NIC
1
2
3
4
5
6
7
8
24 GND
23 NIC
22
GND
ADPA9002
21 RFOUT/V
GND
RFIN
GND
NIC
DD
TOP VIEW
20
19
GND
NIC
(Not to Scale)
18 NIC
17 GND
GND
PACKAGE
BASE
GND
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS
MUST BE CONNECTED TO RF AND DC GROUND.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF AND DC GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 4, 6, 8, 9, 16, 17, 20,
22, 24, 25, 32
GND
Ground. These pins must be connected to RF and dc ground.
2, 3, 7, 10, 11, 12, 14, 18, NIC
19, 23, 26, 27, 28, 31
Not Internally Connected. These pins must be connected to RF and dc ground.
5
13
RFIN
VGG1
RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 6 for the interface schematic.
Gate Voltage. This pin is used for external bias operation of the device. If grounded, the amplifier
runs in self biased mode at the standard current of 385 mA. Adjusting the voltage above or
below the ground potential controls the drain current. External bypass capacitors are required
(see Figure 62). See Figure 7 for the interface schematic.
15, 29, 30
21
ACG3, ACG2, ACG1
RFOUT/VDD
AC Ground Pins. These pins are used for low frequency termination. External bypass
capacitor required (see Figure 62). See Figure 4 and Figure 5 for the interface schematics.
RF Output for the Amplifier (RFOUT).
Drain Voltage (VDD). Connect the VDD network to provide the drain current (IDD) (see Figure 62).
See Figure 5 for the interface schematic.
EPAD
Exposed Pad. The exposed pad must be connected to RF and dc ground.
Rev. 0 | Page 6 of 19
Data Sheet
ADPA9002
INTERFACE SCHEMATICS
GND
RFIN
Figure 3. GND Interface Schematic
Figure 6. RFIN Interface Schematic
RFIN
ACG3
V
GG1
Figure 7. VGG1 Interface Schematic
Figure 4. ACG3 Interface Schematic
ACG1
ACG2
RFOUT/V
DD
Figure 5. RFOUT/VDD, ACG1, ACG2 Interface Schematic
Rev. 0 | Page 7 of 19
ADPA9002
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
20
15
10
15
10
5
5
S22 (dB)
S21 (dB)
S11 (dB)
S22 (dB)
S21 (dB)
S11 (dB)
0
–5
0
–5
–10
–15
–20
–10
–15
–20
0
100
200
300
400
500
0
2
4
6
8
10
12
14
16
FREQUENCY (MHz)
FREQUENCY (GHz)
Figure 8. S22, S21, and S11 vs. Frequency, 10 MHz to 500 MHz,
Self Biased Mode, VDD = 12 V, VGG1 = GND
Figure 11. S22, S21, and S11 vs. Frequency, 500 MHz to 16 GHz,
Self Biased Mode, VDD = 12 V, VGG1 = GND
18
18
16
14
12
10
16
14
12
10
8
8
T
T
T
= +85°C
= +25°C
= –40°C
15V, 410mA
12V, 385mA
10V, 375mA
A
A
A
6
6
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Gain vs. Frequency for Various Temperatures, Self Biased Mode,
DD = 12 V, VGG1 = GND
Figure 12. Gain vs. Frequency for Various VDD and Quiescent Currents,
Self Biased Mode, VGG1 = GND
V
18
0
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
16
14
12
10
8
–4
–8
–12
–16
–20
500mA
400mA
300mA
385mA, SELF BIASED
6
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 10. Gain vs. Frequency for Various IDQ, Externally Biased Mode,
DD = 12 V, Controlled VGG1
Figure 13. Input Return Loss vs. Frequency for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG1 = GND
V
Rev. 0 | Page 8 of 19
Data Sheet
ADPA9002
0
0
–4
–8
15V, 410mA
12V, 385mA
10V, 375mA
500mA
400mA
300mA
–4
385mA, SELF BIASED
–8
–12
–16
–12
–16
–20
–20
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 17. Input Return Loss vs. Frequency for Various IDQ, Externally Biased
Mode, VDD = 12 V, Controlled VGG1
Figure 14. Input Return Loss vs. Frequency for Various VDD and Quiescent
Currents, Self Biased Mode, VGG1 = GND
0
0
15V, 410mA
12V, 385mA
10V, 375mA
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–4
–8
–4
–8
–12
–16
–20
–12
–16
–20
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. Output Return Loss vs. Frequency for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG1 = GND
Figure 18. Output Return Loss vs. Frequency for Various VDD and Quiescent
Currents, Self Biased Mode, VGG1 = GND
0
0
T
T
T
= +85°C
= +25°C
= –40°C
500mA
400mA
300mA
A
A
A
–10
385mA, SELF BIASED
–4
–8
–20
–30
–40
–12
–16
–20
–50
–60
–70
–80
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 16. Output Return Loss vs. Frequency for Various IDQ, External Biased
Condition, VDD = 12 V, Controlled VGG1
Figure 19. Reverse Isolation vs. Frequency for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG1 = GND
Rev. 0 | Page 9 of 19
ADPA9002
Data Sheet
16
16
14
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
14
12
10
8
12
10
8
6
4
2
0
6
4
2
0
10
20
30
40
50
60
70
80
90
100
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (GHz)
Figure 20. Noise Figure vs. Frequency, 10 MHz to 100 MHz, for Various
Temperatures, Self Biased Mode, VDD = 12 V, VGG1 = GND
Figure 23. Noise Figure vs. Frequency, 100 MHz to 12 GHz, for Various
Temperatures, Self Biased Mode, VDD = 12 V, VGG1 = GND
32
32
30
28
26
24
22
30
28
26
24
22
T
T
T
= +85°C
= +25°C
= –40°C
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
20
20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 21. OP1dB vs. Frequency,10 MHz to 1 GHz for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG1 = GND
Figure 24. OP1dB vs. Frequency, 1 GHz to 12 GHz for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG1 = GND
32
32
30
28
26
24
30
28
26
24
500mA
400mA
300mA
385mA, SELF BIASED
22
20
22
15V, 410mA
12V, 385mA
10V, 375mA
20
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 22. OP1dB vs. Frequency for Various VDD and Quiescent Currents, Self
Biased Mode, VGG1 = GND
Figure 25. OP1dB vs. Frequency for Various IDQ
Externally Biased Mode, VDD = 12 V, Controlled VGG1
,
Rev. 0 | Page 10 of 19
Data Sheet
ADPA9002
36
36
34
32
30
34
32
30
28
28
26
24
22
20
26
24
22
20
T
T
T
= +85°C
= +25°C
= –40°C
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. PSAT vs. Low Frequency,10 MHz to 1 GHz for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG1 = GND
Figure 29. PSAT vs. Frequency, 1 GHz to 12 GHz for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG1 = GND
36
36
34
32
30
34
32
30
28
26
28
26
24
24
500mA
400mA
300mA
15V, 410mA
12V, 385mA
10V, 375mA
22
22
385mA, SELF BIASED
20
20
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 27. PSAT vs. Frequency for Various VDD and Quiescent Currents,
Self Biased Mode, VGG1 = GND
Figure 30. PSAT vs. Frequency for Various IDQ, Externally Biased Mode,
VDD = 12 V, Controlled VGG1
30
27
24
21
18
15
12
9
30
27
24
21
18
15
12
9
6
6
15V, 410mA
12V, 385mA
10V, 375mA
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
3
0
3
0
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 28. Power Added Efficiency (PAE) vs. Frequency for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG1 = GND, PAE Measured at PSAT
Figure 31. PAE vs. Frequency for Various VDD and Quiescent Currents,
Self Biased Mode, VGG1 = GND, PAE Measured at PSAT
Rev. 0 | Page 11 of 19
ADPA9002
Data Sheet
30
27
24
21
18
15
12
9
35
30
25
480
PAE
GAIN
470
460
450
440
430
420
P
OUT
I
DD
20
15
10
5
410
400
6
500mA
400mA
300mA
385mA, SELF BIASED
3
0
0
–5
390
20
0
1
2
3
4
5
6
7
8
9
10 11 12
0
5
10
15
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 32. PAE vs. Frequency for Various IDQ, Externally Biased Mode,
Figure 35. POUT, Gain, PAE, IDD vs. Input Power, 1 GHz,
Self Biased Mode, VDD = 12 V, VGG1 = GND
VDD = 12 V, Controlled VGG1, PAE Measured at PSAT
35
30
25
530
510
490
35
30
25
480
PAE
GAIN
PAE
GAIN
470
460
450
440
430
420
P
OUT
P
OUT
I
DD
I
DD
20
15
470
450
20
15
10
5
430
410
390
10
5
410
400
390
0
–5
0
–5
0
5
10
15
20
0
5
10
15
20
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 33. POUT, Gain, PAE, Supply Current (IDD) vs. Input Power, 3 GHz,
Self Biased Mode, VDD = 12 V, VGG1 = GND
Figure 36. POUT, Gain, PAE, IDD vs. Input Power, 6 GHz,
Self Biased Mode, VDD = 12 V, VGG1 = GND
35
30
25
540
520
500
35
520
PAE
GAIN
PAE
GAIN
30
25
500
480
P
P
OUT
OUT
I
I
DD
DD
480
460
20
15
20
15
460
440
440
420
400
380
10
5
10
5
420
400
380
0
–5
0
–5
0
5
10
15
20
0
5
10
15
20
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 34. POUT, Gain, PAE, IDD vs. Input Power, 8 GHz,
Self Biased Mode, VDD = 12 V, VGG1 = GND
Figure 37. POUT, Gain, PAE, IDD vs. Input Power, 10 GHz,
Self Biased Mode, VDD = 12 V, VGG1 = GND
Rev. 0 | Page 12 of 19
Data Sheet
ADPA9002
50
6
5
4
3
45
40
35
30
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
8GHz
9GHz
10GHz
2
1
0
25
20
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
0
1
2
3
4
5
6
7
8
9
10 11 12
–5
0
5
10
15
20
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 41. OIP3 vs. Frequency for Various Temperatures,
OUT per Tone = 14 dBm, Self Biased Mode, VDD = 12 V, VGG1 = GND
Figure 38. Power Dissipation vs. Input Power for Various Frequencies at TA
85°C, Self Biased Mode, VDD = 12 V, VGG1 = GND
=
P
50
50
45
40
35
45
40
35
30
30
500mA
400mA
300mA
SELF BIASED
25
25
20
15V, 410mA
12V, 385mA
10V, 375mA
20
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 42. OIP3 vs. Frequency for Various IDQ, Externally Biased Mode,
Figure 39. OIP3 vs. Frequency for Various VDD and Quiescent Currents,
Self Biased Mode, VGG1 = GND, POUT per Tone = 14 dBm
VDD = 12 V, Controlled VGG1, POUT per Tone = 14 dBm
100
90
80
70
60
50
45
40
35
50
40
30
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
8GHz
9GHz
10GHz
30
10dBm
12dBm
14dBm
16dBm
18dBm
20
10
0
25
20dBm
20
0
2
4
6
8
10
PER TONE (dBm)
OUT
12
14
16
18
20
0
1
2
3
4
5
6
7
8
9
10 11 12
P
FREQUENCY (GHz)
Figure 43. Third-Order Intermodulation Distortion Relative to Carrier (IM3) vs.
OUT per Tone for Various Frequencies, Self Biased Mode, VDD = 10 V,
GG1 = GND
Figure 40. OIP3 vs. Frequency for Various POUT per Tone, Self Biased Mode,
DD = 12 V, VGG1 = GND
P
V
V
Rev. 0 | Page 13 of 19
ADPA9002
Data Sheet
100
90
80
70
60
50
100
90
80
70
60
50
40
30
1GHz
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
8GHz
9GHz
10GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
8GHz
9GHz
10GHz
40
30
20
10
0
20
10
0
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
P
PER TONE (dBm)
P
OUT
PER TONE (dBm)
OUT
Figure 44. IM3 vs. POUT per Tone for Various Frequencies, Self Biased Mode,
DD = 12 V, VGG1 = GND
Figure 47. IM3 vs. POUT per Tone for Various Frequencies, Self Biased Mode,
DD = 15 V, VGG1 = GND
V
V
60
60
55
50
45
55
50
45
40
35
30
40
35
30
15V, 410mA
12V, 385mA
10V, 375mA
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
25
20
25
20
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 45. OIP2 vs. Frequency for Various Temperatures,
OUT per Tone = 14 dBm, Self Biased, VDD = 12 V, VGG1 = GND
Figure 48. OIP2 vs. Frequency for Various VDD and Quiescent Currents, Self
Biased Mode, VGG1 = GND, POUT per Tone = 14 dBm
P
60
60
55
50
45
55
50
45
40
40
35
30
35
10dBm
30
25
20
12dBm
14dBm
16dBm
18dBm
20dBm
500mA
400mA
300mA
SELF BIASED
25
20
0
1
2
3
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 46. OIP2 vs. Frequency for Various IDQ, Externally Biased Mode,
DD = 12 V, Controlled VGG1, POUT per Tone = 14 dBm
Figure 49. OIP2 vs. Frequency for Various POUT per Tone, Self Biased Mode,
DD = 12 V, VGG1 = GND
V
V
Rev. 0 | Page 14 of 19
Data Sheet
ADPA9002
570
570
545
520
495
470
1GHz
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
8GHz
9GHz
10GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
8GHz
9GHz
10GHz
545
520
495
470
445
420
395
370
445
420
395
370
–5
0
5
10
15
20
–5
0
5
10
15
20
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 50. IDD vs. Input Power for Various Frequencies,
Self Biased Mode, VDD = 12 V, VGG1 = GND
Figure 53. IDD vs. Input Power for Various Frequencies,
DD = 12 V, IDQ = 400 mA, Controlled VGG1
V
0.5
0.4
0.3
500
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
8GHz
9GHz
10GHz
450
400
0.2
0.1
350
300
250
0
–0.1
–0.2
–5
0
5
10
15
20
2
4
6
8
10
(V)
12
14
16
INPUT POWER (dBm)
V
DD
Figure 54. IDQ vs. VDD, VGG1 = GND, Self Biased Mode
Figure 51. Gate 1 Current (IGG1) vs. Input Power for Various Frequencies,
DD = 12 V, IDQ = 400 mA, Controlled VGG1
V
1000
900
800
700
600
500
400
300
200
100
0
–2.0
–1.5
–1.0
–0.5
(V)
0
0.5
1.0
V
GG1
Figure 52. IDQ vs. VGG1, VDD = 12 V, Externally Biased Mode
Rev. 0 | Page 15 of 19
ADPA9002
Data Sheet
CONSTANT IDD OPERATION
Biased with the HMC980LP4E active bias controller for constant IDD operation. TA = 25°C, VDD = 12 V, and IDQ = 400 mA for nominal
operation, unless otherwise noted.
32
32
30
28
26
24
22
20
30
28
26
24
22
20
T
T
T
= +85°C
= +25°C
= –40°C
15V
12V
10V
A
A
A
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 55. OP1dB vs. Frequency for Various Temperatures, VDD = 12 V,
Constant IDD = 400 mA
Figure 58. OP1dB vs. Frequency for Various Supply Voltages,
Constant IDD = 400 mA
32
34
32
30
28
26
24
30
28
26
24
22
20
500mA
400mA
300mA
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
22
20
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 56. OP1dB vs. Frequency for Various Constant IDD, VDD = 12 V
Figure 59. PSAT vs. Frequency for Various Temperatures, VDD = 12 V,
Constant IDD = 400 mA
34
34
32
30
28
26
24
32
30
28
26
24
500mA
400mA
300mA
15V
12V
10V
22
22
20
20
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 57. PSAT vs. Frequency for Various Supply Voltages,
Constant IDD = 400 mA
Figure 60. PSAT vs. Frequency for Various Constant IDD, VDD = 12 V
Rev. 0 | Page 16 of 19
Data Sheet
ADPA9002
THEORY OF OPERATION
The ADPA9002 is a GaAs, MMIC, pHEMT, cascode distributed
power amplifier. The cascode distributed architecture of the
ADPA9002 uses a fundamental cell consisting of a stack of two
field effect transistors (FETs) with the source of the upper FET
connected to the drain of the lower FET. The fundamental cell
is then duplicated several times with an RFIN transmission line
interconnecting the gates of the lower FETs and an RFOUT
transmission line interconnecting the drains of the upper FETs.
ACG1 ACG2
allowing adjustment of the quiescent drain current above and
below the 385 mA nominal. As an example, Figure 52 shows that,
by adjusting VGG1 from approximately −0.3 V to +0.3 V, quiescent
drain currents from 250 mA to 450 mA can be obtained.
The ADPA9002 has single-ended input and output ports whose
impedances are nominally equal to 50 Ω over the dc to 10 GHz
frequency range. Consequently, the ADPA9002 can be directly
inserted into a 50 Ω system with no required impedance
matching circuitry. Similarly, the input and output impedances
are sufficiently stable across variations in temperature and
supply voltage so that no impedance matching compensation is
required. The RF output port additionally functions as the VDD
bias, requiring an RF choke through which dc bias is applied.
Though the device operates down to dc, blocking capacitors are
recommended at the RF input and output ports to prevent
damages on the RF stages when loading the dc bias supplies. The
RF choke and blocking capacitor at the RF output together
constitute a bias tee. In practice, the external RF choke and dc
blocking capacitor selections limit the lowest frequency of
operation.
RFOUT/
RFIN
V
DD
V
ACG3
GG1
Figure 61. Simplified Schematic of the Cascode Distributed Amplifier
Additional circuit design techniques are used around each cell
to optimize the overall bandwidth, output power, and noise
figure. The major benefit of this architecture is that a high
output level is maintained across a bandwidth far greater than a
single instance of the fundamental cell provides. A simplified
schematic of this architecture is shown in Figure 61.
ACG1 through ACG3 are nodes at which ac terminations
(capacitors) to ground can be provided. The use of such
terminations serves to roll off the gain at frequencies below
200 MHz, allowing the flattest possible gain response to be
obtained over various frequencies.
It is critical to supply low inductance ground connections to the
GND pins and to the package base exposed pad to ensure stable
operation. To achieve optimal performance from the ADPA9002
and to prevent damage to the device, do not exceed the absolute
maximum ratings.
For simplified biasing without the need for a negative voltage
rail, VGG1 can be connected directly to GND. With VDD = 12 V
and VGG1 grounded, a quiescent drain current of 385 mA (typical)
results. An externally generated VGG1 can optionally be applied,
Rev. 0 | Page 17 of 19
ADPA9002
Data Sheet
APPLICATIONS INFORMATION
Capacitive bypassing is required for VDD and VGG1, as shown in
Figure 62. Both the RFIN and RFOUT/VDD pins are dc-coupled.
Use of an external dc blocking capacitor at RFIN is recommended.
Use of an external RF choke plus a dc blocking capacitor (for
example, a bias tee) at the RFOUT/VDD pin is required. For
wideband applications, ensure that the frequency responses of
the external biasing and blocking components are adequate for
use across the entire frequency range of the application.
4. Increase the VGG1 pin to achieve the IDQ
5. Apply the RF signal to the RFIN pin.
.
The recommended bias sequence during power-down for
externally biased operation is as follows:
1. Turn off the RFIN signal.
2. Decrease the VGG1 pin to −2 V to achieve a typical IDQ of 0 mA.
3. Set VDD to 0 V.
4. Set the VGG1 pin to 0 V.
The ADPA9002 operates in either self biased or externally
biased mode. Ground the VGG1 pin to operate the device in self
biased mode. For the externally biased configuration, adjust the
Take care to ensure adherence to the values shown in the
Absolute Maximum Ratings section.
V
GG1 pin within −2 V to +0.5 V to set the target drain.
Unless otherwise noted, all measurements and data shown were
taken using the typical application circuit (see Figure 62) and
biased per the conditions in this section. The bias conditions
described in this section are the operating points recommended
to optimize the overall device performance. Operation using
other bias conditions may result in performance that differs
from what is shown in the Typical Performance Characteristics
section. To obtain optimal performance while not damaging the
device, follow the recommended biasing sequences described in
this section.
The recommended bias sequence during power-up for self biased
operation is as follows:
1. Connect the VGG1 pin to ground and ground all GND pins.
2. Set VDD to 12 V.
3. Apply the RF signal to the RFIN pin.
The recommended bias sequence during power-down for self
biased operation is as follows:
1. Turn off the RFIN signal.
2. Set VDD to 0 V.
TYPICAL APPLICATION CIRCUIT
The recommended bias sequence during power-up for externally
biased operation is as follows:
In Figure 62, the drain voltage (VDD) must be applied through an
external broadband bias tee connected at the RFOUT/VDD pin and
connect an external dc block to the RFIN pin. Use optional
capacitors if the device is operated below 200 MHz.
1. Connect all GND pins to ground.
2. Set the VGG1 pin to −2 V.
3. Set VDD to 12 V.
NOTE 2
C1
1000pF
C5
0.01µF
C9
4.7µF
V
DD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
RFOUT
RFIN
NOTE 1
NOTE 2
NOTE 1
C3
1000pF
C8
0.01µF
C10
4.7µF
C4
1000pF
C7
0.01µF
C11
4.7µF
V
GG1
NOTES
1. DRAIN VOLTAGE (V ) MUST BE APPLIED THROUGH AN ETERNAL BIAS TEE CONNECTED
DD
AT THE RFOUT/V PIN AND AN EXTERNAL DC BLOCK MUST BE CONNECTED AT THE RFIN PIN.
DD
2. USE OPTIONAL CAPACITORS IF THE DEVICE IS OPERATED BELOW 200MHz.
Figure 62. Typical Application Circuit
Rev. 0 | Page 18 of 19
Data Sheet
ADPA9002
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
25
24
32
1
0.50
BSC
3.20
3.10 SQ
3.00
EXPOSED
PAD
17
16
8
9
0.45
0.40
0.35
TOP VIEW
SIDE VIEW
BOTTOM VIEW
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.35
1.25
1.15
0.60 REF
0.40
0.050 MAX
0.035 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
SEATING
PLANE
0.08
0.203 REF
Figure 63. 32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
5 mm × 5 mm Body and 1.25 mm Package Height
(CG-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model1
Temperature
MSL Rating2 Description3
ADPA9002ACGZN
ADPA9002ACGZN-R7
ADPA9002-EVALZ
−40°C to +85°C
−40°C to +85°C
3
3
32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
Evaluation Board
CG-32-2
CG-32-2
1 Z = RoHS Compliant Part.
2 See the Absolute Maximum Ratings section for additional information.
3 The lead finish of the ADPA9002ACGZN and the ADPA9002ACGZN-R7 is nickel palladium gold (NiPdAu).
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21196-0-10/19(0)
Rev. 0 | Page 19 of 19
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