ADRF5045BCCZN-R7 [ADI]
9 kHz to 30 GHz, Silicon, SP4T Switch;
| 型号： | ADRF5045BCCZN-R7 |
| 厂家： | 
ADI |
| 描述： | 9 kHz to 30 GHz, Silicon, SP4T Switch |
| 文件： | 总14页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
9 kHz to 30 GHz,
Silicon, SP4T Switch
Data Sheet
ADRF5045
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Ultrawideband frequency range: 9 kHz to 30 GHz
Nonreflective 50 Ω design
Low insertion loss: 2.4 dB at 20 GHz to 30 GHz
High isolation: 45 dB at 20 GHz to 30 GHz
High input linearity
P1dB: 28 dBm typical
IP3: 50 dBm typical
High power handling
24 dBm through path
24
23
22
21
20
19
ADRF5045
GND
GND
RFC
GND
GND
GND
1
2
3
4
5
6
18
17
16
15
14
13
GND
VDD
50Ω
50Ω
V1
V2
24 dBm terminated path
ESD rating: 1500 V HBM
No low frequency spurious
VSS
50Ω 50Ω
GND
0.1 dB settling time (50% VCTL to 0.1 dB final RF output): 6 µs
24-terminal LGA package
7
8
9
10
11
12
APPLICATIONS
Figure 1.
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Broadband telecommunications systems
GENERAL DESCRIPTION
The ADRF5045 is a general-purpose, single-pole, four-throw
(SP4T) switch manufactured using a silicon process. It comes
in a 24-terminal land grid array (LGA) package and provides
high isolation and low insertion loss from 9 kHz to 30 GHz.
This broadband switch requires dual supply voltages, +3.3 V and
−3.3 V, and provides complementary metal-oxide semiconductor
(CMOS)/low voltage transistor-transistor logic (LVTTL) logic-
compatible control.
Rev. A
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ADRF5045
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Typical Performance Characteristics .............................................7
Insertion Loss, Return Loss, and Isolation ................................7
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Absolute Maximum Ratings ........................................................... 5
Thermal Resistance...................................................................... 5
Power Derating Curves ............................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions ............................ 6
Interface Schematics .................................................................... 6
Input 0.1 dB, 1 dB Power Compression, and Third-Order
Intercept .........................................................................................9
Theory of Operation ...................................................................... 10
Applications Information ............................................................. 11
Evaluation Board........................................................................ 11
Probe Matrix Board ................................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
3/2020—Rev. 0 to Rev. A
Changes to Digital Control Inputs Parameter, Table 2 .............. 5
Added Endnote 1, Table 2; Renumbered Sequentially ............... 5
Changes to Theory of Operation Section.................................... 10
12/2017—Revision 0: Initial Version
Rev. A | Page 2 of 14
Data Sheet
ADRF5045
SPECIFICATIONS
VDD = 3.3 V, VSS = −3.3 V, V1 = 0 V or 3.3 V, V2 = 0 V or 3.3 V, and TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Symbol Test Conditions/Comments
Min
Typ Max
Unit
FREQUENCY RANGE
0.009
30,000 MHz
INSERTION LOSS
Between RFC and RF1 to RF4 (On) (Worst Case)
9 kHz to 10 GHz
10 GHz to 20 GHz
20 GHz to 30 GHz
1.5
1.7
2.4
dB
dB
dB
ISOLATION
Between RFC and RF1 to RF4 (Off) (Worst Case)
9 kHz to 10 GHz
10 GHz to 20 GHz
20 GHz to 30 GHz
58
53
45
dB
dB
dB
RETURN LOSS
RFC and RF1 to RF4 (On)
9 kHz to 10 GHz
10 GHz to 20 GHz
20 GHz to 30 GHz
9 kHz to 10 GHz
10 GHz to 20 GHz
20 GHz to 30 GHz
16
25
17
21
17
11
dB
dB
dB
dB
dB
dB
RF1 to RF4 (Off)
SWITCHING TIME
Rise and Fall
On and Off
Settling
tRISE, tFALL 10% to 90% of radio frequency (RF) output
2
4
µs
µs
tON, tOFF
50% VCTL to 90% of RF output
0.1 dB
0.05 dB
50% VCTL to 0.1 dB of final RF output
50% VCTL to 0.05 dB of final RF output
6
7
µs
µs
INPUT LINEARITY
Power Compression
0.1 dB
P0.1dB
P1dB
IP3
26
28
50
dBm
dBm
dBm
1 dB
Third-Order Intercept
Two-tone input power = 14 dBm each
tone, Δf = 1 MHz
SUPPLY CURRENT
Positive
VDD, VSS pins
Typical at VCTL = 0 V or 3.3 V,
maximum at VCTL = 0.8 V or 1.4 V
Typical at VCTL = 0 V or 3.3 V,
IDD
ISS
3
20
µA
µA
Negative
110 130
maximum at VCTL = 0.8 V or 1.4 V
DIGITAL CONTROL INPUTS
V1, V2 pins
Voltage
Low
High
VINL
VINH
0
1.2
0.8
3.3
V
V
Current
Low and High
IINL, IINH
<1
µA
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive
Negative
Digital Control Voltage
VDD
VSS
VCTL
3.15
−3.45
0
3.45
−3.15
VDD
V
V
V
Rev. A | Page 3 of 14
ADRF5045
Data Sheet
Parameter
Symbol Test Conditions/Comments
Min
Typ Max
Unit
RFx Input Power
Through Path
PIN
TCASE = 85°C
RF signal is applied to RFC or through
connected RF1/RF2
RF signal is applied to terminated
RF1/RF2
RF signal is present at RFC while
switching between RF1 and RF2
24
dBm
dBm
dBm
°C
Terminated Path
Hot Switching
24
21
Case Temperature
TCASE
−40
+85
Rev. A | Page 4 of 14
Data Sheet
ADRF5045
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
POWER DERATING CURVES
4
Table 2.
2
0
Parameter
Rating
Supply Voltage
Positive
Negative
Digital Control Inputs1
−0.3 V to +3.6 V
−3.6 V to +0.3 V
−0.3 V to VDD + 0.3 V
or 3.3 mA, whichever
occurs first
–2
–4
–6
–8
RFx Input Power2 (f = 500 kHz to 30 GHz,
TCASE = 85°C)
–10
–12
–14
Through Path
Terminated Path
Hot Switching
Temperature
25 dBm
25 dBm
22 dBm
10k
100k
1M
10M
100M
1G
10G
100G
FREQUENCY (Hz)
Junction, TJ
Storage Range
Reflow (Moisture Sensitivity Level 3
(MSL3) Rating)
135°C
−65°C to +150°C
260°C
Figure 2. Power Derating for Through Path and Hot Switching vs. Frequency,
TCASE = 85°C
4
2
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
RFC, RF1 to RF4 Pins
0
–2
1500 V
2000 V
Other Pins
–4
1 Overvoltages at digital control inputs are clamped by internal diodes.
Current must be limited to the maximum rating given.
–6
2 For power derating less than 500 kHz, see Figure 2 and Figure 3.
–8
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
–10
–12
–14
10k
100k
1M
10M
100M
1G
10G
100G
FREQUENCY (Hz)
Figure 3. Power Derating for Terminated Path vs. Frequency, TCASE = 85°C
ESD CAUTION
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type
θJC
Unit
CC-24-4
Through Path
Terminated Path
400
160
°C/W
°C/W
Rev. A | Page 5 of 14
ADRF5045
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 23 22 21 20 19
GND
GND
RFC
GND
GND
GND
18 GND
VDD
1
2
3
4
5
6
17
ADRF5045
16 V1
15 V2
TOP VIEW
(Not to Scale)
VSS
14
13 GND
7
8
9
10 11 12
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF/DC GROUND
OF THE PCB.
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No. Mnemonic
Description
1, 2, 4 to 7, 9, 10, 12, GND
13, 18, 19, 21, 22, 24
Ground. These pins must be connected to the RF/dc ground of the PCB.
3
RFC
RF4
RF3
RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
8
11
14
15
16
17
20
VSS
V2
V1
VDD
RF2
Negative Supply Voltage.
Control Input 2. See Table 5 for the control voltage truth table.
Control Input 1. See Table 5 for the control voltage truth table.
Positive Supply Voltage.
RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
23
RF1
RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc. See Figure 5 for the interface schematic.
EPAD
Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2,
RF3,
RF4
V1, V2
Figure 5. RFx Pins (RFC and RF1 to RF4) Interface Schematic
Figure 6. Digital Pins (V1 and V2) Interface Schematic
Rev. A | Page 6 of 14
Data Sheet
ADRF5045
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
Insertion loss and return loss measured on the probe matrix board using ground signal ground (GSG) probes close to the RFx pins;
isolation measured on the evaluation board because signal coupling between the probes limits the isolation performance of the
ADRF5045 on the probe matrix board.
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
RF1
RF2
RF3
RF4
+85°C
+25°C
–40°C
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. Insertion Loss vs. Frequency for RF1, RF2, RF3, and RF4
Figure 10. Insertion Loss vs. Frequency over Various Temperatures
Between RFC and RF1
0
–5
0
ON
OFF
–5
–10
–15
–20
–25
–30
–35
–40
–10
–15
–20
–25
–30
–35
–40
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Return Loss vs. Frequency for RFC
Figure 11. Return Loss vs. Frequency for RF1, RF2, RF3, and RF4
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
RFC TO RF2
RFC TO RF3
RFC TO RF4
RFC TO RF1
RFC TO RF3
RFC TO RF4
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Isolation vs. Frequency, RFC to RF1 On
Figure 12. Isolation vs. Frequency, RFC to RF2 On
Rev. A | Page 7 of 14
ADRF5045
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
RFC TO RF1
RFC TO RF2
RFC TO RF4
RFC TO RF1
RFC TO RF2
RFC TO RF3
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. Isolation vs. Frequency, RFC to RF3 On
Figure 15. Isolation vs. Frequency, RFC to RF4 On
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
0
5
10
15
20
25
30
35
40
FREQUENCY (GHz)
Figure 14. Channel to Channel Isolation vs. Frequency, RFC to RF1 On
Rev. A | Page 8 of 14
Data Sheet
ADRF5045
INPUT 0.1 dB, 1 dB POWER COMPRESSION, AND THIRD-ORDER INTERCEPT
All large signal performance parameters were measured on the evaluation board.
32
30
28
26
24
22
20
18
16
14
12
10
32
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0
5
10
15
20
10k
100k
1M
10M
100M
1G
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 16. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Various Temperatures
Figure 19. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Various Temperatures (Low Frequency Detail)
32
30
28
26
24
22
20
18
16
32
30
28
26
24
22
20
18
16
14
14
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
12
10
12
10
0
5
10
15
20
10k
100k
1M
10M
100M
1G
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 17. Input 1 dB Power Compression (P1dB) vs. Frequency over Various
Temperatures
Figure 20. Input 1 dB Power Compression (P1dB) vs. Frequency over Various
Temperatures (Low Frequency Detail)
60
55
50
45
40
35
30
60
55
50
45
40
35
30
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
25
20
25
20
0
5
10
15
20
25
30
10k
100k
1M
10M
100M
1G
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 18. Input IP3 vs. Frequency over Various Temperatures
Figure 21. Input IP3 vs. Frequency over Various Temperatures
(Low Frequency Detail)
Rev. A | Page 9 of 14
ADRF5045
Data Sheet
THEORY OF OPERATION
The ADRF5045 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
minimize RF coupling.
The ideal power-up sequence for the ADRF5045 is as follows:
1. Connect GND.
2. Power up VDD and VSS. Powering up VSS after VDD
avoids current transients on VDD during ramp-up.
3. Apply the digital control inputs, V1 and V2. Applying
the digital control inputs before the VDD supply may
inadvertently forward bias and damage the internal ESD
protection structures. In such a case, use a series 1 kΩ
resistor to limit the current flowing in to the control pin.
If the control pins are not driven to a valid logic state (for
example, if the controller output is in a high impedance
state) after VDD is powered up, it is recommended to use
pull-up and pull-down resistors.
4. Apply an RF input signal. The design is bidirectional. The
RF input signal can be applied to the RFC port, while the
RF throw ports are outputs, or vice versa. The RF ports are
dc-coupled to 0 V, and no dc blocking is required at the RF
ports when the RF line potential is equal to 0 V.
The ADRF5045 incorporates a driver to perform logic functions
internally and to provide the user with the advantage of a
simplified control interface. The driver features two digital
control input pins (V1 and V2) that control the state of the RF
paths. Depending on the logic level applied to the V1 and V2
pins, one RF path is in an insertion loss state, while the other
three paths are in an isolation state (see Table 5). The insertion
loss path conducts the RF signal equally well in both directions
between the RF throw port and the RF common port, and the
isolation paths provides high loss between the RF throw ports
terminated to internal 50 Ω resistors and the insertion loss
path.
The ideal power-down sequence is the reverse order of the
power-up sequence.
Table 5. Control Voltage Truth Table
Digital Control Input
RF Paths
V1
V2
RF1 to RFC
RF2 to RFC
RF3 to RFC
RF4 to RFC
Low
High
Low
High
Low
Low
High
High
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Rev. A | Page 10 of 14
Data Sheet
ADRF5045
APPLICATIONS INFORMATION
through vias as possible are arranged around transmission lines
and under the exposed pad of the package.
EVALUATION BOARD
Figure 22 shows the top view of the ADRF5045-EVALZ, and
Figure 23 shows the cross sectional view of the ADRF5045-
EVALZ.
Figure 24 shows the actual ADRF5045-EVALZ with
component placement. Two power supply ports are connected
to the VDD and VSS test points (TP1 and TP4), control voltages
are connected to the V1 and V2 test points (TP2 and TP3), and
the ground reference is connected to the GND test point (TP5).
Figure 22. Evaluation Board Layout, Top View
W = 14mil G = 5mil
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
T = 0.7mil
H = 8mil
RO4003
0.5oz Cu (0.7mil)
Figure 24. Evaluation Board Component Placement
On the control traces (V1 and V2), a 0 Ω resistor connects the
test points to the pins on the ADRF5045. On the supply traces
(VDD and VSS), a 100 pF bypass capacitor filters high frequency
noise. Additionally, unpopulated components positions are
available for applying extra bypass capacitors.
0.5oz Cu (0.7mil)
0.5 oz Cu (0.7mil)
The RF input and output ports (RFC, RF1, RF2, RF3, and RF4)
are connected through 50 Ω transmission lines to the 2.4 mm
RF launchers (J1 to J5). These high frequency RF launchers are
by contact and not soldered onto the board. A thru calibration
line connects the unpopulated J6 and J7 launchers; this
transmission line is used to estimate the loss of the PCB
over the environmental conditions being evaluated.
Figure 23. Evaluation Board (Cross Sectional View)
The ADRF5045-EVALZ is a 4-layer evaluation board. Each
copper layer is 0.7 mil (0.5 oz) and separated by dielectric
materials. All RF and dc traces are routed on the top copper
layer, and the inner and bottom layers are grounded planes that
provide a solid ground for the RF transmission lines. The top
dielectric material is 8 mil Rogers RO4003, offering optimal
high frequency performance. The middle and bottom dielectric
materials provide mechanical strength. The overall board
thickness is 62 mil, which allows 2.4 mm RF launchers to be
connected at the board edges.
The schematic of the ADRF5045-EVALZ is shown in Figure 25.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with a trace width of 14 mil and a
ground clearance of 5 mil, to have a characteristic impedance of
50 Ω. For optimal RF and thermal grounding, as many plated
Rev. A | Page 11 of 14
ADRF5045
Data Sheet
RF2
RF1
1
J1
2 3 4 5
AGND
1
J2
2 3 4 5
AGND
VDD
TP1
C1
C4
C5
100pF
0.1µF
DNI
10µF
DNI
TP5
1
2
3
4
5
6
18
17
16
15
14
13
AGND
AGND
AGND
R1
GND
GND
RFC
GND
GND
GND
GND
VDD
AGND
1
RFC
U1
ADRF5045
V1
V2
J3
V1
V2
TP2
TP3
0Ω
R2
2 3 4 5
AGND
VSS
0Ω
C7
C8
GND
0.1µF
DNI
0.1µF
DNI
AGND
AGND
VSS
AGND
TP4
C2
C3
C6
100pF
0.1µF
DNI
10µF
DNI
AGND
AGND
AGND
1
RF4
RF3
J4
2 3 4 5
AGND
1
J5
2 3 4 5
AGND
1
1
THRU_CAL
J6
J7
2 3 4 5 DNI
AGND
DNI
5 4 3 2
AGND
Figure 25. ADRF5045-EVALZ Evaluation Board Schematic
Table 6. Evaluation Board Components
Component
Default Value
Description
C1, C2
100 pF
Capacitors, C0402 package
C5, C6
10 µF
0.1 µF
Not applicable
0 Ω
Capacitors, C3216 package, do not install (DNI)
Capacitors, C0402 package, DNI
2.4 mm end launch connector (Southwest Microwave: 1492-04A-5)
Resistors, 0402 package
C3, C4, C7, C8
J1 to J7
R1, R2
TP1 to TP5
U1
PCB
Not applicable
ADRF5045
08-042615-01
Through-hole mount test point
ADRF5045 digital attenuator, Analog Devices, Inc.
Evaluation PCB, Analog Devices
Rev. A | Page 12 of 14
Data Sheet
ADRF5045
PROBE MATRIX BOARD
The probe matrix board is a 4-layer board that uses a 12 mil
Rogers RO4003 as the top dielectric material. The external
copper layer is 0.7 mil and the internal copper layers are
1.4 mil. The RF transmission lines were designed using
a CPWG model, with a 16 mil width and a ground spacing of
6 mil, to have a characteristic impedance of 50 Ω.
Figure 26 shows the cross sectional view of the probe matrix
board and Figure 27 shows the top view of the probe matrix
board. Measurements were made using 535 µm GSG probes at
close proximity to the RFx pins. Unlike the ADRF5045-EVALZ,
probing reduces reflections caused by mismatch arising from
connectors, cables, and board layout, resulting in a more
accurate measurement of the performance of the ADRF5045.
W = 16mil G = 6mil
Figure 27. Probe Board Layout (Top View)
RF traces for a through reflect line (TRL) calibration are
designed on the board itself. A nonzero line length compensates
for board loss at calibration. The actual board duplicates the
same layout in matrix form to assemble multiple devices at
once. Insertion loss and input and output return losses were
measured on this probe matrix board. Isolation performance
measured on the probe matrix board is limited due to signal
coupling between the RF probes that are in close proximity.
Therefore, RF port to port isolation was measured on the
ADRF5045-EVALZ.
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
T = 0.7mil
H = 12mil
RO4003
1oz Cu (1.4mil)
FR4
1oz Cu (1.4mil)
FR4
0.5 oz Cu (0.7mil)
Figure 26. Probe Matrix Board (Cross Sectional View)
Rev. A | Page 13 of 14
ADRF5045
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00
3.90
0.30
0.25
0.20
0.35
0.30
0.25
PIN A1
PIN 1
CORNER AREA
INDICATOR
0.30 × 0.45°
24
19
1
18
2.40 BSC
SQ
2.50 REF
SQ
13
6
0.50
BSC
12
7
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.125
BSC
0.53 REF
0.96
MAX
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.37
0.33
0.28
SECTION OF THIS DATA SHEET.
Figure 28. 24-Terminal Land Grid Array [LGA]
(CC-24-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF5045BCCZN
ADRF5045BCCZN-R7
ADRF5045-EVALZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
24-Terminal Land Grid Array [LGA]
24-Terminal Land Grid Array [LGA]
Evaluation Board
CC-24-4
CC-24-4
1 Z = RoHS Compliant Part.
©2017–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16314-3/20(A)
Rev. A | Page 14 of 14
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