ADRF5047 [ADI]
Silicon SP4T Switch, Reflective, 9 kHz to 44 GHz;
| 型号： | ADRF5047 |
| 厂家： | 
ADI |
| 描述： | Silicon SP4T Switch, Reflective, 9 kHz to 44 GHz |
| 文件： | 总15页 (文件大小：552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Silicon SP4T Switch,
Reflective, 9 kHz to 44 GHz
ADRF5047
Data Sheet
FEATURES
Ultrawideband frequency range: 9 kHz to 44 GHz
Reflective design
FUNCTIONAL BLOCK DIAGRAM
ADRF5047
Low insertion loss
20
19
18
17
16
1.5 dB to 18 GHz
2.4 dB to 40 GHz
2.7 dB to 44 GHz
High isolation
47 dB to 18 GHz
33 dB to 40 GHz
1
2
3
4
5
15
14
13
12
11
RF2
GND
GND
GND
RF3
V1
GND
RFC
GND
VSS
DRIVER
31 dB to 44 GHz
6
7
8
9
10
High input linearity
P0.1dB: 26.5 dBm typical
IP3: 50 dBm typical
Figure 1.
High RF input power handling
Through path: 26 dBm
Hot switching: 26 dBm
No low frequency spurious
0.1 dB RF settling time: 5.2 µs
20-terminal, 3 mm × 3 mm, RoHS-compliant, LGA package
Pin compatible with ADRF5046, fast switching version
APPLICATIONS
Industrial scanner
Test instrumentation
Cellular infrastructure—mmWave 5G
Military radios, radars, and electronic counter measures (ECMs)
Microwave radios and very small aperture terminals (VSATs)
GENERAL DESCRIPTION
The ADRF5047 is a reflective, single-pole, four-throw (SP4T)
switch manufactured in the silicon process.
The ADRF5047 is pin-compatible with the ADRF5046 fast
switching version, which operates from 100 MHz to 44 GHz.
The ADRF5047 operates from 9 kHz to 44 GHz with an insertion
loss of lower than 2.7 dB and an isolation of higher than 31 dB.
The device has a radio frequency (RF) input power handling
capability of 26.5 dBm for both through path and hot switching.
The ADRF5047 comes in a 20-terminal, 3 mm × 3 mm, RoHS-
compliant, land grid array (LGA) package and operates from
−40°C to +105°C.
The ADRF5047 draws a low current of 3 µA on the positive
supply of +3.3 V, and −110 µA on the negative supply of −3.3 V.
The device provides complementary metal-oxide semiconductor
(CMOS)-/low voltage transistor-transistor logic (LVTTL)-
compatible controls.
Rev. 0
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Technical Support
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www.analog.com
ADRF5047
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Typical Performance Characteristics..............................................7
Insertion Loss, Return Loss, and Isolation ................................7
Input 0.1 dB Power Compression and Third-Order Intercept.....9
Theory of Operation ...................................................................... 10
Applications Information...............................................................11
Evaluation Board.........................................................................11
Probe Matrix Board ................................................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Power Derating Curves................................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
REVISION HISTORY
11/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 15
Data Sheet
ADRF5047
SPECIFICATIONS
Positive supply voltage (VDD) = +3.3 V, negative supply voltage (VSS) = −3.3 V, digital control input voltage (VCTL) = 0 V or +3.3 V, and case
temperature (TCASE) = 25°C on a 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGE
INSERTION LOSS
f
0.009
44,000 MHz
Between RFC and RF1 to RF4 (On)
9 kHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
1.5
1.6
2.2
2.4
2.7
dB
dB
dB
dB
dB
ISOLATION
Between RFC and RF1 to RF4 (Off)
9 kHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
47
41
35
33
31
dB
dB
dB
dB
dB
RETURN LOSS
RFC and RF1 to RF4 (On)
9 kHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
40 GHz to 44 GHz
15
16
15
15
14
dB
dB
dB
dB
dB
SWITCHING CHARACTERISTICS
Rise Time and Fall Time
On Time and Off Time
RF Settling Time
tRISE, tFALL
tON, tOFF
10% to 90% of RF output
50% VCTL to 90% of RF output
1.4
3.4
µs
µs
0.1 dB
0.05 dB
50% VCTL to 0.1 dB of final RF output
50% VCTL to 0.05 dB of final RF output
5.2
7.2
µs
µs
INPUT LINEARITY1
0.1 dB Power Compression
Third-Order Intercept
P0.1dB
IP3
f = 200 kHz to 40 GHz
Two-tone input power = 14 dBm each tone,
f = 200 kHz to 40 GHz, Δf = 1 MHz
26.5
50
dBm
dBm
Second-Order Intercept
IP2
Two-tone input power = 14 dBm each tone,
f = 10 GHz, Δf = 1 MHz
100
2
dBm
VIDEO FEEDTHROUGH2
mV p-p
SUPPLY CURRENT
Positive
Negative
VDD, VSS pins
V1, V2 pins
IDD
ISS
3
µA
µA
−110
DIGITAL CONTROL INPUTS
Voltage
Low
High
VINL
VINH
0
1.2
0.8
3.3
V
V
Current
Low
High
IINL
IINH
<1
35
µA
µA
Rev. 0 | Page 3 of 15
ADRF5047
Data Sheet
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive
Negative
Digital Control Inputs Voltage
RFx Input Power3
Through Path
VDD
VSS
VCTL
3.15
−3.45
0
3.45
−3.15
VDD
V
V
V
PIN
f = 200 kHz to 40 GHz, TCASE = 85°C4
RF signal is applied to RFC or through
connected RF throw port
RF signal is present at RFC while switching
between RF throw port
26
dBm
dBm
°C
Hot Switching
26
Case Temperature
TCASE
−40
+105
1 For input linearity performance over frequency, see Figure 19 to Figure 22.
2 Video feedthrough is the spurious dc transient measured at the RF ports in a 50 Ω test setup, without an RF signal present while switching the control voltage.
3 For power derating over frequency, see Figure 2 and Figure 3.
4 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
Rev. 0 | Page 4 of 15
Data Sheet
ADRF5047
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
POWER DERATING CURVES
2
Table 2.
Parameter
Supply Voltage
Positive
Negative
0
–2
Rating
−0.3 V to +3.6 V
−3.6 V to +0.3 V
−0.3 V to VDD + 0.3 V
–4
–6
Digital Control Inputs Voltage
RFx Input Power (f1 = 5 MHz to 40 GHz,
–8
TCASE = 85°C2)
–10
–12
–14
Through Path
Hot Switching
Temperature
26.5 dBm
26.5 dBm
10k
100k
1M
10M
100M
1G
10G
100G
Junction, TJ
Storage
135°C
−65°C to +150°C
FREQUENCY (Hz)
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
RFx Pins
2
2000 V
2000 V
0
–2
Supply and Digital Control Pins
1 For power derating over frequency, see Figure 2 and Figure 3.
2 For 105°C operation, the power handling degrades from the TCASE = 85°C
specification by 3 dB.
–4
–6
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
–8
–10
–12
–14
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FREQUENCY (GHz)
Only one absolute maximum rating can be applied at any one time.
Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85°C
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
ESD CAUTION
θ
JC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type
θJC
Unit
CC-20-6, Through Path
240
°C/W
Rev. 0 | Page 5 of 15
ADRF5047
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
20
19
18
17
16
1
2
3
4
5
15
14
13
12
11
RF2
GND
GND
GND
RF3
V1
GND
RFC
GND
ADRF5047
TOP VIEW
(Not to Scale)
VSS
6
7
8
9
10
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO RF AND DC GROUND OF THE PCB.
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
V1
Control Input 1. See Table 5 for the control voltage truth table, and see Figure 6 for the interface
schematic.
2, 4, 7, 9, 10, 12 to 14, 16, 17, 19
3
GND
RFC
Ground. These pins must be connected to the RF and dc ground of the PCB.
RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking
capacitor is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface
schematic.
5
6
8
VSS
VDD
RF4
Negative Supply Voltage.
Positive Supply Voltage.
RF Throw Port 4. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor
is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
11
15
18
20
RF3
RF2
RF1
V2
RF Throw Port 3. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor
is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
RF Throw Port 2. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor
is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
RF Throw Port 1. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor
is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.
Control Input 2. See Table 5 for the control voltage truth table, and see Figure 6 for the interface
schematic.
EPAD
Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2,
RF3,
RF4
V1, V2
Figure 6. Control Pins (V1 and V2) Interface Schematic
Figure 5. RF Pins (RFC and RF1 to RF4) Interface Schematic
Rev. 0 | Page 6 of 15
Data Sheet
ADRF5047
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
VDD = 3.3 V, VSS = −3.3 V, VCTL = 0 V or 3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. Measured on the probe matrix board.
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
RF1
RF2
RF3
RF4
CASE
CASE
CASE
CASE
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. Insertion Loss vs. Frequency for RF1, RF2, RF3, and RF4
Figure 10. Insertion Loss vs. Frequency over Temperature,
RFC and RF1 On
0
–5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–10
–15
–20
–25
–30
–35
–40
–45
–50
RF1
RF2
RF3
RF4
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. RFC Return Loss vs. Frequency, RFC to RF1 On
Figure 11. Return Loss vs. Frequency, RF1, RF2, RF3, RF4 On
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
RF2
RF1
RF3
RF4
RF3
RF4
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 9. Isolation vs. Frequency, RFC to RF1 On
Figure 12. Isolation vs. Frequency, RFC to RF2 On
Rev. 0 | Page 7 of 15
ADRF5047
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
RF1
RF2
RF3
RF1
RF2
RF4
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 13. Isolation vs. Frequency, RFC to RF3 On
Figure 16. Isolation vs. Frequency, RFC to RF4 On
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
RF1 TO RF2
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. Channel to Channel Isolation vs. Frequency, RFC to RF1 On
Figure 17. Channel to Channel Isolation vs. Frequency, RFC to RF2 On
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
–70
–70
RF1 TO RF2
RF1 TO RF3
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
RF1 TO RF4
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
–80
–90
–80
–90
–100
–100
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 15. Channel to Channel Isolation vs. Frequency, RFC to RF3 On
Figure 18. Channel to Channel Isolation vs. Frequency, RFC to RF4 On
Rev. 0 | Page 8 of 15
Data Sheet
ADRF5047
INPUT 0.1 dB POWER COMPRESSION AND THIRD-ORDER INTERCEPT
VDD = 3.3 V, VSS = −3.3 V, VCTL = 0 V or 3.3 V, and TCASE = 25°C on a 50 Ω system, unless otherwise noted. Measured on the evaluation
board.
30
28
26
24
22
20
18
16
14
12
10
30
28
26
24
22
20
18
16
14
12
10
P0.1dB
P1dB
P0.1dB
P1dB
10k
100k
1M
10M
100M
1G
0
5
10
15
20
25
30
35
40
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 19. Input Power Compression vs. Frequency
Figure 21. Input Power Compression vs. Frequency
(Low Frequency Detail)
60
60
55
50
45
40
35
30
25
20
55
50
45
40
35
30
25
20
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
T
T
T
T
= +105°C
= +85°C
= +25°C
= –40°C
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
0
5
10
15
20
25
30
35
40
10k
1G
100k
1M
10M
100M
FREQUENCY (GHz)
FREQUENCY (Hz)
Figure 20. Input IP3 vs. Frequency over Various Temperatures
Figure 22. Input IP3 vs. Frequency over Various Temperatures
(Low Frequency Detail)
Rev. 0 | Page 9 of 15
ADRF5047
Data Sheet
THEORY OF OPERATION
The ADRF5047 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
minimize RF coupling.
The ideal power-up sequence is as follows:
1. Connect GND.
2. Power up VDD and VSS. Power up VSS after VDD to avoid
current transients on VDD during ramp up.
All of the RF ports (RFC, RF1 to RF4) are dc-coupled to 0 V,
and no dc blocking is required at the RF ports when the RF line
potential is equal to 0 V. The RF ports are internally matched to
50 Ω. Therefore, external matching networks are not required.
3. Apply digital control inputs, V1 and V2. Applying these
digital control inputs before applying the VDD supply
inadvertently forwards bias and damages the internal ESD
protection structures. To avoid this damage, use a series
1 kΩ resistor to limit the current flowing into the control
pin. Use pull-up or pull-down resistors if the controller
output is in a high impedance state after VDD is powered
up and the control pins are not driven to a valid logic state.
4. Apply an RF input signal to either the RFC port or the RF
throw port.
The ADRF5047 integrates a driver to perform logic functions
internally and to provide the user with the advantage of a
simplified CMOS/LVTTL-compatible control interface. The
driver features two digital control input pins (V1 and V2) that
control the state of the RF paths. The logic level applied to the
V1 and V2 pins determines which RF port is in the insertion
loss state, while the other three paths are in the isolation state
(see Table 5).
The ideal power-down sequence is the reverse order of the
power-up sequence.
The insertion loss path conducts the RF signal between the
selected RF throw port and the RF common port. The switch
design is bidirectional with equal power handling capabilities.
The RF input signal can be applied to the RFC port or the
selected RF throw port. The isolation paths provide high loss
between the insertion loss path and the unselected RF throw
ports that are reflective.
Table 5. Control Voltage Truth Table
Digital Control Inputs
RF Paths
V1
V2
RF1 to RFC
RF2 to RFC
RF3 to RFC
RF4 to RFC
Low
High
Low
High
Low
Low
High
High
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Isolation (off)
Isolation (off)
Isolation (off)
Insertion loss (on)
Rev. 0 | Page 10 of 15
Data Sheet
ADRF5047
APPLICATIONS INFORMATION
EVALUATION BOARD
The ADRF5047-EVALZ is a 4-layer evaluation board. The outer
copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil)
and are separated by dielectric materials. Figure 23 shows the
evaluation board cross sectional view.
G = 7mil
W = 14mil
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
T = 2.2mil
H = 8mil
RO4003
Figure 25. RF Transmission Lines
0.5oz Cu (0.7mil)
Two power supply ports are connected to the VDD and VSS
test points, control voltages are connected to the V1 and V2
test points, and the ground reference is connected to the GND
test point.
On the supply traces, a 100 pF bypass capacitor is used to filter
the high frequency noise. Additionally, unpopulated components
positions are available for applying extra bypass capacitors.
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
On the control traces, there are provisions for the resistor capacitor
(RC) filter to eliminate dc-coupled noise, if needed, by the
application. The resistor can also improve the isolation between
the RF and the control signal.
Figure 23. Evaluation Board Cross Sectional View
All RF and dc traces are routed on the top copper layer, whereas
the inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. The top dielectric
material is 8 mil Rogers RO4003, offering optimal high frequency
performance. The middle and bottom dielectric materials provide
mechanical strength. The overall board thickness is 62 mil, which
allows 2.4 mm RF launchers to be connected at the board edges.
Figure 24 shows the top view of the evaluation board.
The RF input and output ports (RFC, RF1 to RF4) are connected
through 50 ꢀ transmission lines to the 2.4 mm RF launchers.
These high frequency RF launchers are by contact and not
soldered onto the board.
A thru calibration line (THRU CAL) connects the unpopulated
RF launchers. This transmission line is used to calibrate out the
board loss effects from the ADRF5047-EVALZ evaluation board
measurements to determine the device performance at the pins
of the IC. Figure 26 shows the typical board loss at room
temperature, the embedded insertion loss, and the de-embedded
insertion loss for the ADRF5047.
0
–1
–2
–3
–4
–5
Figure 24. Evaluation Board Layout, Top View
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with a trace width of 14 mil and
ground clearance of 7 mil to have a characteristic impedance of
50 Ω. The RF transmission lines are extended by 8 mil from
package edge to the tapered line used for RF pin transition as
shown in Figure 25. For optimal RF and thermal grounding, as
many plated through vias as possible are arranged around
transmission lines and under the exposed pad of the package.
–6
THRU LOSS
–7
EMBEDDED INSERTION LOSS
DEEMBEDDED INSERTION LOSS
–8
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (GHz)
Figure 26. Insertion Loss vs. Frequency
Figure 27 and Figure 28 shows the ADRF5047-EVALZ assembly
drawing with component placement and the schematic,
respectively.
Rev. 0 | Page 11 of 15
ADRF5047
Data Sheet
Figure 27. Evaluation Board Assembly Drawing
Rev. 0 | Page 12 of 15
Data Sheet
ADRF5047
V
V
SS
C1
C3
DNI
10nF
AGND
AGND
DD
C2
10nF
C4
DNI
AGND
AGND
R1
V1
0Ω
C7
DNI
C8
DNI
AGND
AGND
R2
V2
0Ω
C5
DNI
C6
DNI
AGND
AGND
AGND
GND
1
RF2
1
RF1
2 3 4 5
AGND
2 3 4 5
AGND
U1
V1
RF2
1
1
THRU1_CAL
GND
GND
GND
RF3
GND
RFC
GND
THRU1
THRU2
1
RFC
ADRF5047
2 3 4 5
AGND
5 4 3 2
AGND
2 3 4 5
AGND
VSS
AGND
1
RF4
RF3
2 3 4 5
AGND
1
2 3 4 5
AGND
Figure 28. Evaluation Board Schematic
Table 6. Evaluation Board Components
Component
Default Value
Description
C1, C2
10 nF
Capacitors, C0402 package
C3, C4, C5, C7
C6, C8
RFC, RF1 to RF4
THRU1, THRU2
R1, R2
Not applicable
Not applicable
Not applicable
Not applicable
0 Ω
Capacitors, C0402 package, do not install (DNI)
Capacitors, C0402 package, DNI
2.4 mm end launch connectors (Southwest Microwave 1492-04A-5)
2.4 mm end launch connectors, DNI
Resistors, 0402 package
VDD, VSS, V1, V2, GND
U1
Not applicable
ADRF5047
Through-hole mount test points
SP4T switch, Analog Devices, Inc.
PCB
08-044567D
Evaluation PCB, Analog Devices
Rev. 0 | Page 13 of 15
ADRF5047
Data Sheet
PROBE MATRIX BOARD
The probe matrix board uses same stackup as the evaluation
board but a different layout designed to take measurements
using ground, signal, ground (GSG) probes at close proximity
to the RFx pins. Probing eliminates the mismatch reflections
caused by connectors, cables, and board layout. Therefore, the
probe matrix board provides more accurate measurement of the
device performance than the evaluation board. Figure 29 shows
the top view of the probe matrix board layout.
The probe matrix board includes a through reflect line (TRL)
calibration kit allowing board loss de-embedding. The actual
board duplicates the same layout in matrix form to assemble
multiple devices at one time. All s parameters were measured on
this board.
Figure 29. Probe Matrix Board Layout (Top View)
Rev. 0 | Page 14 of 15
Data Sheet
ADRF5047
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.250
0.200
0.150
CHAMFERED
0.325
0.275
0.225
PIN 1 (0.25 × 45°)
PIN 1
CORNER AREA
0.125
16
20
REF
1
15
1.60
1.50 SQ
1.40
1.60 REF
SQ
EXPOSED
PAD
11
5
0.40
BSC
6
10
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.530 REF
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.960 MAX
0.333
0.330
0.300
SECTION OF THIS DATA SHEET
Figure 30. 20-Terminal Land Grid Array [LGA]
(CC-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF5047BCCZN
ADRF5047BCCZN-R7
ADRF5047-EVALZ
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CC-20-6
CC-20-6
Marking Code
047
047
20-Terminal Land Grid Array [LGA]
20-Terminal Land Grid Array [LGA]
Evaluation Board
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16765-0-11/19(0)
Rev. 0 | Page 15 of 15
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