ADRF5132-EVALZ [ADI]
High Power, 20 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 5.0 GHz;
| 型号： | ADRF5132-EVALZ |
| 厂家： | 
ADI |
| 描述： | High Power, 20 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 5.0 GHz 光电二极管 |
| 文件： | 总12页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Power, 20 W Peak, Silicon SPDT,
Reflective Switch, 0.7 GHz to 5.0 GHz
ADRF5132
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADRF5132
Reflective, 50 Ω design
Low insertion loss: 0.6 dB typical at 2.7 GHz
High power handling at TCASE = 105°C
Long-term (>10 years operation)
Peak power: 43 dBm
GND
RF1
NIC
1
2
3
4
12 GND
11 RF2
CW power: 38 dBm
10
9
NIC
LTE power average (8 dB PAR): 35 dBm
Single event (<10 sec operation)
LTE power average (8 dB PAR): 41 dBm
High linearity
GND
GND
P0.1dB: 42.5 dBm typical
Figure 1.
IP3: 65 dBm typical at 2.0 GHz to 4.0 GHz
ESD ratings
HBM: 2 kV, Class 2
CDM: 1.25 kV
Single positive supply: 5 V
Positive control, CMOS/TTL compatible
16-lead, 3 mm × 3 mm LFCSP package
APPLICATIONS
Cellular/4G infrastructure
Wireless infrastructure
Military and high reliability applications
Test equipment
Pin diode replacement
GENERAL DESCRIPTION
The ADRF5132 is a high power, reflective, 0.7 GHz to 5.0 GHz,
silicon, single-pole, double-throw (SPDT) reflective switch in a
leadless, surface-mount package. The switch is ideal for high
power and cellular infrastructure applications, like long-term
evolution (LTE) base stations. The ADRF5132 has high power
handling of 35 dBm LTE (average typical at 105°C), a low insertion
loss of 0.6 dB at 2.7 GHz, input third-order intercept of 65 dBm
(typical), and 0.1 dB compression (P0.1dB) of 42.5 dBm.
The on-chip circuitry operates at a single, positive supply
voltage of 5 V and a typical supply current of 1.1 mA typical,
making the ADRF5132 an ideal alternative to pin diode-based
switches.
The device is in a RoHS compliant, compact, 16-lead, 3 mm ×
3 mm LFCSP package.
Rev. B
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Tel: 781.329.4700 ©2017–2019 Analog Devices, Inc. All rights reserved.
Technical Support
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ADRF5132
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................5
Typical Performance Characteristics ..............................................6
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Insertion Loss, Isolation, Return Loss, Third-Order Intercept,
and Power Compression...............................................................6
Theory of Operation .........................................................................8
Applications Information.................................................................9
Evaluation Board...........................................................................9
Application Circuit..................................................................... 10
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
8/2019—Rev. A to Rev. B
Changes to Figure 11 and Figure 12............................................... 7
Updated Outline Dimensions ....................................................... 12
4/2018—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Figure 2 and Table 2..................................................... 5
Changes to Figure 17...................................................................... 11
12/2017—Revision 0: Initial Version
Rev. B | Page 2 of 12
Data Sheet
ADRF5132
SPECIFICATIONS
VDD = 5 V, V CTL = 0 V or VDD, TA = 25°C, and 50 Ω system, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max
Unit
FREQUENCY RANGE
INSERTION LOSS
0.7
5.0
GHz
dB
dB
dB
dB
0.9 GHz
2.7 GHz
3.8 GHz
5.0 GHz
0.5
0.6
0.65
0.9
ISOLATION
RFC to RF1/RF2 (Worst Case)
0.7 GHz to 2.0 GHz
2.0 GHz to 5.0 GHz
0.7 GHz to 2.0 GHz
2.0 GHz to 5.0 GHz
50
45
50
35
dB
dB
dB
dB
RF1 to RF2 (Worst Case)
RETURN LOSS
RFC
0.7 GHz to 4.0 GHz
4.0 GHz to 5.0 GHz
0.7 GHz to 4.0 GHz
4.0 GHz to 5.0 GHz
25
15
25
15
dB
dB
dB
dB
RFC to RF1/RF2
SWITCHING SPEED
Rise and Fall Time (tRISE, tFALL
)
90% to 10% of radio frequency (RF) output
50% VCTL to 10% to 90% of RF output
140
550
ns
ns
On and Off Time (tON, tOFF
INPUT POWER
)
0.1 dB Compression (P0.1dB)
42.5
dB
INPUT THIRD-ORDER INTERCEPT (IP3)
Two-tone input power = 30 dBm per tone at 10 MHz tone spacing
0.7 GHz to 2.0 GHz
2.0 GHz to 4.0 GHz
4.0 GHz to 5.0 GHz
0.7 GHz to 4.0 GHz
68
65
62
dBm
dBm
dBm
RECOMMENDED OPERATING CONDITIONS
Bias Voltage Range (VDD)
4.5
0
5.4
VDD
V
V
Control Voltage Range (VCTL
Maximum RF Input Power
TCASE = 105°C1
)
Continuous wave (CW)
8 dB peak average ratio (PAR), long-term (>10 years operation),
average
38
35
dBm
dBm
8 dB PAR LTE, single event (<10 sec), average
CW
8 dB PAR LTE, long-term (>10 years operation), average
8 dB PAR LTE, single event (<10 sec), average
CW
41
40
35
41
43
35
41
dBm
dBm
dBm
dBm
dBm
dBm
dBm
TCASE = 85°C
TCASE = 25°C
8 dB PAR LTE, long-term (>10 years operation), average
8 dB PAR LTE, single event (<10 sec), average
Case Temperature Range (TCASE
)
−40
+105 °C
DIGITAL INPUT CONTROL VOLTAGE
Low (VIL)
High (VIH)
VDD = 4.5 V to 5.4 V, TCASE = −40°C to +105°C, at <1 µA typical
0
1.3
0.8
5.0
V
V
SUPPLY CURRENT (IDD)
VDD = 5 V
1.1
mA
1 Peak power is 43 dBm, corresponding to PAR of 8 dB at LTE long-term.
Rev. B | Page 3 of 12
ADRF5132
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Bias Voltage Range (VDD)
Control Voltage Range (VCTL
RF Input Power1
−0.3 V to +5.5 V
−0.3 V to VDD
43 dBm
)
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Channel Temperature
135°C
Storage Temperature Range
Operating Temperature Range
Peak Reflow Temperature (MSL3)
ESD Sensitivity
−65°C to +150°C
−40°C to +105°C
260°C
Table 3. Thermal Resistance
Package Type
θJC
Unit
CP-16-35
17
°C/W
Human Body Model (HBM)
Charged Device Model (CDM)
2 kV (Class 2)
1.25 kV
ESD CAUTION
1 For recommended operating conditions, see Table 1.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 4 of 12
Data Sheet
ADRF5132
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
RF1
NIC
1
2
3
4
12 GND
11 RF2
ADRF5132
TOP VIEW
10
9
NIC
(Not to Scale)
GND
GND
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT
CONNECTED INTERNALLY; HOWEVER, ALL DATA SHOWN
HEREIN WAS MEASURED WITH THESE PINS CONNECTED
TO RF/DC GROUND EXTERNALLY.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO RF/DC GROUND.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 4, 5, 6, 8, 9, 12, 13, 15
2
3, 10
GND
RF1
NIC
Ground. See Figure 3 for the GND interface schematic.
RF Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
Not Internally Connected. These pins are not connected internally; however, all data shown herein
was measured with these pins connected to RF/dc ground externally.
7
RFC
RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required
on this pin.
11
14
RF2
VCTL
RF Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
Control Input. See Figure 4 for the VCTL interface schematic. Refer to Table 5 and the recommended
digital input control voltage range in Table 1.
16
VDD
Supply Voltage.
EPAD
Exposed Pad. The exposed pad must be connected to RF/dc ground.
Table 5. Truth Table
Signal Path State
Control Input, VCTL State
RFC to RF1
RFC to RF2
High
Low
Off
On
On
Off
INTERFACE SCHEMATICS
V
DD
GND
V
CTL
Figure 3. Ground Interface
Figure 4. Control Interface
Rev. B | Page 5 of 12
ADRF5132
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, ISOLATION, RETURN LOSS, THIRD-ORDER INTERCEPT, AND POWER COMPRESSION
VDD = 5 V, V CTL = 0 V or VDD, TA = 25°C, and 50 Ω system, unless otherwise noted.
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
RF1
RF2
+105°C
+85°C
+25°C
–40°C
–1.6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 5. Insertion Loss of RF1 and RF2 vs. Frequency at VDD = 5 V
Figure 8. Insertion Loss vs. Frequency over Temperature, VDD = 5 V
–20
–20
RF1
RF2
RF1 ON
RF2 ON
–30
–40
–50
–60
–70
–80
–30
–40
–50
–60
–70
–80
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 6. Isolation Between RFC and RF1/RF2 vs. Frequency at VDD = 5 V
Figure 9. Isolation Between RF1 and RF2 vs. Frequency at VDD = 5 V,
Switch Mode On
0
80
+105°C
+85°C
+25°C
RFC
RF1
RF2
–5
75
70
65
60
55
50
–40°C
–10
–15
–20
–25
–30
–35
–40
0
1
2
3
4
5
6
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. Return Loss vs. Frequency at VDD = 5 V
Figure 10. Input IP3 vs. Frequency over Temperature, VDD = 5 V
Rev. B | Page 6 of 12
Data Sheet
ADRF5132
55
50
45
40
35
30
55
50
45
40
35
30
RF1
RF2
+105°C
+85°C
+25°C
–40°C
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 11. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Temperature, VDD = 5 V
Figure 12. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency, VDD = 5 V
Rev. B | Page 7 of 12
ADRF5132
Data Sheet
THEORY OF OPERATION
The ADRF5132 requires a single-supply voltage applied to the
The ideal power-up sequence is as follows:
1. Connect the device to ground.
V
DD pin. Bypass capacitors are recommended on the supply line
to minimize RF coupling.
2. Power up VDD
.
The ADRF5132 is controlled via a digital control voltage
applied to the VCTL pin. A small bypassing capacitor is
recommended on the VCTL signal line to improve the RF signal
isolation.
3. Power up the digital control input. Powering the digital
control input before the VDD supply can inadvertently
forward bias and damage ESD protection structures.
4. Power up the RF input. Depending on the logic level
applied to the VCTL pin, one RF output port (for example,
RF1) is set to on mode, by which an insertion loss path is
provided from RFC to the output, while the other RF
output port (for example, RF2) is set to off mode, by which
the output is isolated from RFC.
The ADRF5132 is internally matched to 50 Ω at the RF input
port (RFC) and the RF output ports (RF1 and RF2); therefore,
no external matching components are required. The RFx (RFC,
RF1, and RF2) pins are dc-coupled, and dc blocking capacitors
are required on the RFx lines. The design is bidirectional; the
input and outputs are interchangeable.
Table 6. Switch Operation Mode
Switch Mode
RFC to RF2
Digital Control Input,
VCTL
RFC to RF1
1
Off mode: the RF1 port is isolated from RFC and is
reflective.
On mode: a low insertion loss path from RFC to the RF2
port.
0
On mode: a low insertion loss path from RFC to the RF1 Off mode: the RF2 port is isolated from RFC and is
port. reflective.
Rev. B | Page 8 of 12
Data Sheet
ADRF5132
APPLICATIONS INFORMATION
To ensure maximum heat dissipation and reduce thermal rise
on the evaluation board, some application considerations are
essential. Attach the ADRF5132-EVALZ to a copper support
plate at the bottom of the evaluation board. The ADRF5132-
EVALZ comes with this support plate attachment. Attach the
ADRF5132-EVALZ with its support plate to a big heat sink
using thermal grease during all high power operations. Figure 14
shows the evaluation board temperature vs. RF power input
tested with the preceding conditions and precautions
(evaluation board and support plate attached to a big heat sink).
The temperature rise is less than 5°C up to 43 dBm RF power
input, which provides the required thermal dissipation when
operated at high power levels.
EVALUATION BOARD
The ADRF5132-EVALZ can handle high power levels and
temperatures at which the device operates.
The ADRF5132-EVALZ evaluation board is constructed with
eight metal layers and dielectrics between each layer as shown
in Figure 13. Each metal layer has 1 oz (1.3 mil) copper
thickness, whereas the external layers are 1.5 oz copper.
The top dielectric material is 10 mil Rogers RO4350, which
exhibits a very low thermal coefficient, offering control over the
thermal rise of the board. The dielectrics between the other
metal layers are FR4. The total board thickness achieved is
60 mil.
81
G = 13mil
W = 18mil
1.5oz Cu (2.1mil)
1.5oz Cu (2.1mil)
1.5oz Cu (2.1mil)
T = 2.1 mil
H = 10mil
80
79
78
77
76
RO4350 = 10mil
1oz Cu (1.3mil)
FR4
1oz Cu (1.3mil)
75
38.0 38.5 39.0 39.5 40.0 40.5 41.0 41.5 42.0 42.5 43.0
FR4
RF POWER INPUT (dBm)
Figure 14. ADRF5132-EVALZ Evaluation Board Temperature Rise
(Oven Temperature Set to 75°C)
1oz Cu (1.3mil)
FR4
1oz Cu (1.3mil)
FR4
1oz Cu (1.3mil)
FR4
1oz Cu (1.3mil)
FR4
1.5oz Cu (2.1mil)
Figure 13. ADRF5132-EVALZ Evaluation Board Cross Sectional View
The top copper layer has all RF and dc traces, whereas the other
seven layers provide sufficient ground and help to handle the
thermal rise on the ADRF5132-EVALZ. In addition, via holes
are provided around transmission lines and under the exposed
pad of package, as shown in Figure 15, for proper thermal
grounding. RF transmission lines on the evaluation board are
coplanar wave guide design with a width of 18 mil and ground
spacing of 13 mil.
Figure 15. ADRF5132-EVALZ Evaluation Board Layout
Rev. B | Page 9 of 12
ADRF5132
Data Sheet
impedance, and the package ground leads and backside ground
slug must connect directly to the ground plane. The evaluation
board shown in Figure 16 is available from Analog Devices,
Inc., upon request.
APPLICATION CIRCUIT
Generate the evaluation printed circuit board (PCB) used in the
application circuit shown in Figure 17 with proper RF circuit
design techniques. Signal lines at the RF port must have a 50 Ω
Figure 16. ADRF5132-EVALZ Evaluation Board Component Placement
Table 7. Bill of Materials for ADRF5132-EVALZ Evaluation Board
Reference Designator
Description
J1 to J3
C1 to C5
C6
PCB mount SMA connector
100 pF, 250 V capacitor, 0402 package
1000 pF capacitor, 0402 package
1 μF capacitor, 0402 package
Do not insert
C7
C8, C9, C12
R1
0 Ω resistor, 0402 package
U1
PCB1
ADRF5132 SPDT switch
ADRF5132-EVALZ2 evaluation PCB
1 Circuit board material: Roger 4350 or Arlon 25FR.
2 Reference this evaluation board number when ordering the complete evaluation board.
Rev. B | Page 10 of 12
Data Sheet
ADRF5132
V
1
C0402_A
V
R1
DD
CTL
TP2
TP1
1
C7
1µF
C6
1000pF
C5
100pF
C4
100pF
0Ω
GND
GND
GND
GND
GND
RF1
NIC
1
2
3
4
12 GND
11 RF2
C1
100pF
C3
100pF
1
RF1
RF2
1
J1
J3
ADRF5132
C8
C12
1pF
DNI
10
9
NIC
1pF
DNI
GND
2 3 4 5
GND
5 4 3 2
GND
GND
GND
GND
GND
C2
100pF
1
RFC
J2
C9
1pF
DNI
GND
2 3 4 5
GND
Figure 17. Application Circuit
Rev. B | Page 11 of 12
ADRF5132
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.32
0.25
0.20
PIN 1
INDICATOR
AREA
PIN 1
16
13
IONS
INDICATOR AR EA OP T
(SEE DETAIL A)
0.50
BSC
1
12
1.80
1.70 SQ
1.60
EXPOSED
PAD
4
9
8
5
0.50
0.40
0.25
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-2
Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-35)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF5132BCPZN
ADRF5132BCPZN-R7
ADRF5132-EVALZ
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CP-16-35
CP-16-35
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16424-0-8/19(B)
Rev. B | Page 12 of 12
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