ADRF5473BCZ [ADI]
Die on Carrier, Silicon Digital Attenuator, 0.5 dB LSB, 6-Bit, 100 MHz to 40 GHz;
| 型号： | ADRF5473BCZ |
| 厂家： | 
ADI |
| 描述： | Die on Carrier, Silicon Digital Attenuator, 0.5 dB LSB, 6-Bit, 100 MHz to 40 GHz |
| 文件： | 总17页 (文件大小：1415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
ADRF5473
Die on Carrier, Silicon Digital Attenuator, 0.5 dB LSB, 6-Bit, 100 MHz to 40 GHz
FEATURES
FUNCTIONAL BLOCK DIAGRAM
► Ultrawideband frequency range: 100 MHz to 40 GHz
► Attenuation range: 31.5 dB with 0.5 dB steps
► Bond pads for wire bond and ribbon bond
► Low insertion loss
► 1.7 dB typical up to 18 GHz
► 2.2 dB typical up to 26 GHz
► 3.2 dB typical up to 40 GHz
► Attenuation accuracy
► ±(0.10 + 2.0% of attenuation state) typical up to 26 GHz
► ±(0.13 + 1.5% of attenuation state) typical up to 35 GHz
► ±(0.30 + 1.5% of attenuation state) typical up to 40 GHz
► Typical step error
► ±0.12 dB typical up to 26 GHz
► ±0.30 dB typical up to 35 GHz
► ±0.60 dB typical up to 40 GHz
► High input linearity
Figure 1.
► P0.1dB insertion loss state: 31 dBm typical
► P0.1dB other attenuation states: 28 dBm typical
► IP3: 50 dBm typical
GENERAL DESCRIPTION
The ADRF5473 is a 6-bit digital attenuator with a 31.5 dB attenua-
tion range in 0.5 dB steps manufactured in a silicon process attach-
ed on a gallium arsenide (GaAs) carrier substrate. The substrate
incorporates the bond pads for chip and wire assembly, and the
bottom of the device is metalized and connected to ground.
► High RF power handling
► 26 dBm steady state average
► 31 dBm steady state peak
► Tight distribution in relative phase
► No low frequency spurious signals
► SPI and parallel mode control, CMOS/LVTTL compatible
► RF amplitude settling time (0.1 dB of final RF output): 250 ns
► 18-pad, 3.171 mm × 1.616 mm, die on carrier [CHIP]
This device operates from 100 MHz to 40 GHz with better than
3.2 dB of insertion loss and excellent attenuation accuracy. The
ADRF5473 has an RF input power handling capability of 26 dBm
average and 31 dBm peak for all states.
The ADRF5473 requires a dual-supply voltage of +3.3 V and
−3.3 V. The device features serial peripheral interface (SPI), paral-
lel mode control, and complementary metal-oxide semiconductor
(CMOS)-/low voltage transistor to transistor logic (LVTTL)-compati-
ble controls.
APPLICATIONS
► Test and instrumentation
► Cellular infrastructure: 5G millimeter wave
► Military radios, radars, and electronic counter measures (ECMs)
► Microwave radios and very small aperture terminals (VSATs)
The ADRF5473 is designed to match a characteristic impedance of
50 Ω.
Note that when referring to a single function of a multifunction pad
in this data sheet, only the portion of the pad name that is relevant
is mentioned. For full pad names of the multifunction pads, refer to
the section.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Data Sheet
ADRF5473
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Specifications........................................................ 3
Electrical Specifications......................................3
Timing Specifications......................................... 5
Absolute Maximum Ratings...................................6
Thermal Resistance........................................... 6
Power Derating Curves...................................... 6
Electrostatic Discharge (ESD) Ratings...............7
ESD Caution.......................................................7
Pin Configuration and Function Descriptions........ 8
Interface Schematics..........................................9
Typical Performance Characteristics...................10
Insertion Loss, Return Loss, State Error,
Step Error, and Relative Phase......................10
Input Power Compression and Third-Order
Intercept......................................................... 12
Theory of Operation.............................................13
Power Supply................................................... 13
RF Input and Output.........................................13
Serial or Parallel Mode Selection..................... 14
Serial Mode Interface....................................... 14
Parallel Mode Interface.................................... 15
Applications Information...................................... 16
Die Assembly................................................... 16
Handling, Mounting, and Epoxy Die Attach......16
Outline Dimensions............................................. 17
Ordering Guide.................................................17
REVISION HISTORY
12/2021—Revision 0: Initial Version
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Rev. 0 | 2 of 17
Data Sheet
ADRF5473
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = +3.3 V, VSS = −3.3 V, control voltages = 0 V or VDD, TDIE = 25°C, and 50 Ω system, unless otherwise noted.
S-parameters are measured with microstrip launchers and 3 mil width ribbon bonds using ground-signal-ground (GSG) probes. The launchers
are deembedded. See Applications Information section for assembly details.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY RANGE
INSERTION LOSS
100
40,000
MHz
dB
100 MHz to 10 GHz
10 GHz to 18 GHz
1.3
1.7
2.2
2.8
3.2
dB
18 GHz to 26 GHz
dB
26 GHz to 35 GHz
dB
35 GHz to 40 GHz
dB
RETURN LOSS
ATTIN and ATTOUT, all attenuation states
100 MHz to 10 GHz
10 GHz to 18 GHz
17
18
17
15
15
dB
dB
dB
dB
dB
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
ATTENUATION
Range
Between minimum and maximum attenuation states
Between any successive attenuation states
Referenced to insertion loss
100 MHz to 10 GHz
31.5
0.5
dB
dB
Step Size
Accuracy
±(0.05 + 1.5% of state)
±(0.07 + 2.0% of state)
±(0.10 + 2.0% of state)
±(0.13 + 1.5% of state)
±(0.30 + 1.5% of state)
dB
dB
dB
dB
dB
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
Step Error
Between any successive state
100 MHz to 10 GHz
±0.11
±0.12
±0.12
±0.30
±0.60
dB
dB
dB
dB
dB
10 GHz to 18 GHz
18 GHz to 26 GHz
26 GHz to 35 GHz
35 GHz to 40 GHz
RELATIVE PHASE
Referenced to insertion loss
10 GHz
18
33
50
75
80
Degrees
Degrees
Degrees
Degrees
Degrees
18 GHz
26 GHz
35 GHz
40 GHz
SWITCHING CHARACTERISTICS
Rise and Fall Time (tRISE and tFALL
All attenuation states at input power (PIN) = 10 dBm
10% to 90% of RF output
50% triggered control to 90% of RF output
)
35
ns
ns
On and Off Time (tON and tOFF
RF Amplitude Settling Time
0.1 dB
)
125
50% triggered control to 0.1 dB of final RF output
50% triggered control to 0.05 dB of final RF output
250
350
1
ns
ns
dB
dB
0.05 dB
Overshoot
Undershoot
−2.5
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Data Sheet
ADRF5473
SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF Phase Settling Time
5°
Frequency = 5 GHz
50% triggered control to 5° of final RF output
50% triggered control to 1° of final RF output
Frequency = 100 MHz to 30 GHz
160
180
ns
ns
1°
INPUT LINEARITY1
0.1 dB Power Compression (P0.1dB)
Insertion Loss State
Other Attenuation States
Third-Order Intercept (IP3)
31
28
50
dBm
dBm
dBm
Two-tone PIN = 14 dBm per tone, Δf = 1 MHz, all
attenuation states
DIGITAL CONTROL INPUTS
Voltage
LE, PS, D0, D1, D2, D3/SEROUT2, D4/SERIN, and
D5/CLK
Low (VINL
High (VINH
Current
Low (IINL
High (IINH
)
0
0.8
3.3
V
V
)
1.2
)
<1
33
<1
µA
µA
µA
)
D0, D1, D2
LE, PS, D3/SEROUT2, D4/SERIN, and D5/CLK
D3/SEROUT2
DIGITAL CONTROL OUTPUT
Voltage
Low (VOUTL
)
0 ± 0.3
V
High (VOUTH
)
VDD ± 0.3
V
Low and High Current (IOUTL and IOUTH
)
0.5
mA
SUPPLY CURRENT
VDD and VSS
Positive Supply Current
117
µA
µA
Negative Supply Current
−117
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Positive (VDD
)
3.15
−3.45
0
3.45
−3.15
VDD
V
V
V
Negative (VSS
)
Digital Control Voltage
RF Power Handling3
5
Frequency = 100 MHz to 30 GHz, TDIE4 = 85°C , all
attenuation states
Input at ATTIN
26
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
°C
Steady state average
Steady state peak
Hot switching average
Hot switching peak
Steady state average
Steady state peak
Hot switching average
Hot switching peak
31
23
27
Input at ATTOUT
17
21
14
18
4
Die Temperature (TDIE
)
−40
+105
1
2
3
4
5
Input linearity performance degrades over frequency, see Figure 20 to Figure 23.
D3/SEROUT is an input in parallel control mode and an output in serial control mode. See Table 6 for the pad function descriptions.
For power derating over frequency, see Figure 2 and Figure 3. Applicable for all ATTIN and ATTOUT power specifications.
TDIE refers to the bottom of the die on carrier.
For 105°C operation, the power handling degrades from the TDIE = 85°C specifications by 3 dB.
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Data Sheet
ADRF5473
SPECIFICATIONS
TIMING SPECIFICATIONS
See Figure 25, Figure 26, and Figure 27 for the timing diagrams.
Table 2.
Parameter
Description
Min
Typ
Max
Unit
tSCK
tCS
Minimum serial period, see Figure 25
Control setup time, see Figure 25
70
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCH
Control hold time, see Figure 25
3
5
tLN
LE setup time, see Figure 25
15
tLEW
tLES
tCKN
tPH
Minimum LE pulse width, see Figure 25 and Figure 27
Minimum LE pulse spacing, see Figure 25
Serial clock hold time from LE, see Figure 25
Hold time, see Figure 27
10
630
0
10
2
tPS
Setup time, see Figure 27
tCO
Clock to output (SEROUT) time, see Figure 26
15
20
25
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Data Sheet
ADRF5473
ABSOLUTE MAXIMUM RATINGS
Table 3.
THERMAL RESISTANCE
Parameter
Rating
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
Positive Supply Voltage
Negative Supply Voltage
Digital Control Inputs
Voltage
−0.3 V to +3.6 V
−3.6 V to +0.3 V
θJC is the junction to case bottom (channel to carrier bottom)
thermal resistance.
−0.3 V to VDD + 0.3 V
3 mA
Current
RF Input Power1 (f = 100 MHz to 30 GHz, TDIE
=
Table 4. Thermal Resistance
85°C2)
Package Type
θJC
Unit
ATTIN
C-18-1
125
°C/W
Steady State Average
Steady State Peak
Hot Switching Average
Hot Switching Peak
ATTOUT
27 dBm
32 dBm
24 dBm
28 dBm
POWER DERATING CURVES
Steady State Average
Steady State Peak
Hot Switching Average
Hot Switching Peak
18 dBm
22 dBm
15 dBm
19 dBm
RF Power Under Unbiased Condition (VDD and
VSS = 0 V)
Input at ATTIN
Input at ATTOUT
Temperature
Junction (TJ)
Storage
21 dBm
15 dBm
135°C
−55°C to +150°C
170°C
Processing
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TDIE = 85°C
Continuous Power Dissipation (PDISS
)
0.4 W
1
For power derating over frequency, see Figure 2 and Figure 3. Applicable for
all ATTIN and ATTOUT power specifications.
2
For 105°C operation, the power handling degrades from the TDIE = 85°C
specifications by 3 dB.
Stresses at or above those listed under absolute maximum ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
Figure 3. Power Derating vs. Frequency, High Frequency Detail, TDIE = 85°C
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Data Sheet
ADRF5473
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC DISCHARGE (ESD) RATINGS
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
The following ESD information is provided for handling of ESD-sen-
sitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
ESD Ratings for ADRF5473
Table 5. ADRF5473, 18-Pad Die on Carrier [CHIP]
ESD Model
Withstand Threshold (V)
Human Body Model (HBM)
ATTIN and ATTOUT Pads
Supply and Control Pads
±500
±2000
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Data Sheet
ADRF5473
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pad Configuration
Table 6. Pad Function Descriptions
Pad No.
Mnemonic
Description
1, 3, 4, 6, 7, 18
2
GND
Ground. Bonding of these GND pads are optional. See the Applications Information section.
ATTIN
Attenuator Input. No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 7 for the interface
schematic.
5
ATTOUT
Attenuator Output. No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 7 for the interface
schematic.
8
VSS
VDD
D0
Negative Supply Input. See Figure 9 for the interface schematic.
Positive Supply Input. See Figure 8 for the interface schematic.
9
10
Parallel Control Input for 0.5 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for the
interface schematic.
11
12
13
14
15
D1
Parallel Control Input for 1 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for the
interface schematic.
D2
Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for the
interface schematic.
D3/SEROUT
D4/SERIN
D5/CLK
Parallel Control Input for 4 dB Attenuator Bit (D3). Serial Data Output (SEROUT). See the Theory of Operation section for more
information. See Figure 5 for the interface schematic.
Parallel Control Input for 8 dB Attenuator Bit (D4). Serial Data Input (SERIN). See the Theory of Operation section for more
information. See Figure 5 for the interface schematic.
Parallel Control Input for 16 dB Attenuator Bit (D5). Serial Clock Input (CLK). See the Theory of Operation section for more
information. See Figure 5 for the interface schematic.
16
17
LE
PS
Latch Enable Input. See the Theory of Operation section for more information. See Figure 5 for the interface schematic.
Parallel or Serial Control Interface Selection Input. See the Theory of Operation section for more information. See Figure 5 for the
interface schematic.
Carrier Bottom
The carrier bottom is gold metalized and must be directly attached to the ground plane using conductive epoxy.
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Data Sheet
ADRF5473
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INTERFACE SCHEMATICS
Figure 8. VDD Interface Schematic
Figure 5. Digital Input Interface Schematic (LE, PS, D3/SEROUT, D4/SERIN,
and D5/CLK)
Figure 9. VSS Interface Schematic
Figure 6. Digital Input Interface Schematic (D0, D1, and D2)
Figure 7. ATTIN and ATTOUT Interface Schematic
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Data Sheet
ADRF5473
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
VDD = +3.3 V, VSS = −3.3 V, control voltages = 0 V or VDD, TDIE = 25°C, and a 50 Ω system, unless otherwise noted.
S-parameters are measured with microstrip launchers and 3 mil width ribbon bonds using ground-signal-ground (GSG) probes. The launchers
are deembedded. See Applications Information section for assembly details.
Figure 10. Insertion Loss vs. Frequency over Temperature
Figure 12. Normalized Attenuation vs. Frequency for All States
Figure 11. Input Return Loss vs. Frequency
Figure 13. Output Return Loss vs. Frequency
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Data Sheet
ADRF5473
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 17. Step Error vs. Attenuation State over Frequency
Figure 14. Step Error vs. Frequency
Figure 18. State Error vs. Attenuation State over Frequency
Figure 15. State Error vs. Frequency
Figure 19. Relative Phase vs. Attenuation State over Frequency
Figure 16. Relative Phase vs. Frequency
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Data Sheet
ADRF5473
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
VDD = +3.3 V, VSS = −3.3 V, control voltages = 0 V or VDD, TDIE = 25°C, and a 50 Ω system, unless otherwise noted.
Figure 20. Input P0.1dB vs. Frequency
Figure 22. Input P0.1dB vs. Frequency, Low Frequency Detail
Figure 21. Input IP3 vs. Frequency
Figure 23. Input IP3 vs. Frequency, Low Frequency Detail
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Data Sheet
ADRF5473
THEORY OF OPERATION
The ADRF5473 incorporates a 6-bit fixed attenuator array that
offers an attenuation range of 31.5 dB in 0.5 dB steps. An integrat-
ed driver provides both serial and parallel mode control of the
attenuator array (see Figure 24).
flowing into the control pad. Use pull-up or pull-down resistors if
the controller output is in a high impedance state after the VDD
voltage is powered up and the control pads are not driven to a
valid logic state.
4. Apply an RF input signal to ATTIN or ATTOUT.
Note that when referring to a single function of a multifunction pad
in this data sheet, only the portion of the pad name that is relevant
is mentioned. For full pad names of the multifunction pads, refer to
the Pin Configuration and Function Descriptions section.
The power-down sequence is the reverse order of the power-up
sequence.
Power-Up State
POWER SUPPLY
The ADRF5473 has internal power-on-reset circuity. This circuitry
sets the attenuator to the maximum attenuation state (31.5 dB)
when VDD and VSS voltages are applied, and LE is set to low.
The ADRF5473 requires a positive supply voltage applied to the
VDD pad and a negative supply voltage applied to the VSS pad.
Bypassing capacitors are recommended on the supply lines to filter
high frequency noise.
RF INPUT AND OUTPUT
The power-up sequence is as follows:
Both RF ports (ATTIN and ATTOUT) are dc-coupled to 0 V. No dc
blocking is required at the RF ports when the RF line potential is
equal to 0 V.
1. Connect GND.
2. Power up the VDD and VSS voltages. Power up VSS after VDD to
avoid current transients on VDD during ramp up.
The ADRF5473 supports bidirectional operation at a lower power
level. The power handling of the ATTIN and ATTOUT ports are
different. Therefore, the bidirectional power handling is defined by
the ATTOUT port. Refer to the RF input power specifications in
Table 1.
3. Power up the digital control inputs. The order of the digital
control inputs is not important. However, powering the digital
control inputs before the VDD voltage supply can inadvertently
forward bias and damage the internal ESD structures. To avoid
this damage, use a series 1 kΩ resistor to limit the current
Table 7. Truth Table
Digital Control Input1
D5
D4
D3
D2
D1
D0
Attenuation State (dB)
Low
Low
Low
Low
Low
Low
High
High
Low
Low
Low
Low
Low
High
Low
High
Low
Low
Low
Low
High
Low
Low
High
Low
Low
Low
High
Low
Low
Low
High
Low
Low
High
Low
Low
Low
Low
High
Low
High
Low
Low
Low
Low
Low
High
0 (reference)
0.5
1.0
2.0
4.0
8.0
16.0
31.5
1
Any combination of the control voltage input states shown in this table provides an attenuation equal to the sum of the bits selected.
Figure 24. Simplified Circuit Diagram
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Data Sheet
ADRF5473
THEORY OF OPERATION
In serial mode, the SERIN data is clocked MSB first on the rising
CLK edges into the shift register. Then, LE must be toggled high
to latch the new attenuation state into the device. LE must be set
to low to clock new SERIN data into the shift register as CLK is
masked to prevent the attenuator value from changing if LE is kept
high. See Figure 25, Table 2, and Table 7 for additional information.
SERIAL OR PARALLEL MODE SELECTION
The ADRF5473 can be controlled in either serial or parallel mode
by setting the PS pad to high or low, respectively (see Table 8).
Table 8. Mode Selection
PS
Control Mode
Low
Parallel
Serial
Using SEROUT
High
The ADRF5473 also features a serial data output (SEROUT).
SEROUT outputs the serial input data at the 8th clock cycle and can
control a cascaded attenuator using a single SPI bus.
Figure 26 shows the serial out timing diagram.
SERIAL MODE INTERFACE
The ADRF5473 supports a 4-wire SPI: serial data input (SERIN),
clock (CLK), serial data output (SEROUT), and latch enable (LE).
The serial control interface is activated when PS is set to high.
When using the attenuator in a daisy-chain operation, 8-bit SERIN
data must be used due to the eight clock cycle delay between
SERIN and SEROUT. The SEROUT pad does not support high
impedance mode. A tristate buffer can be used to interface a
shared bus.
The ADRF5473 attenuation states can be controlled using 6-bit or
8-bit SERIN data. If an 8-bit word is used to control the state of
the attenuator, the first two bits, D7 and D6, are don’t care bits. It
does not matter if these two bits are held low or high, or if they are
omitted altogether. Only Bits[D0:D5] set the state of the attenuator.
Figure 25. Serial Control Timing Diagram
Figure 26. Serial Output Timing Diagram
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Data Sheet
ADRF5473
THEORY OF OPERATION
state. When the desired state is set, toggle LE high to transfer
the 6-bit data to the bypass switches of the attenuator array, and
then toggle LE low to latch the change into the device until the
next desired attenuation change (see Figure 27 and Table 2 for
additional information).
PARALLEL MODE INTERFACE
The ADRF5473 has six digital control inputs, D0 (LSB) to D5
(MSB), to select the desired attenuation state in parallel mode, as
shown in Table 7. The parallel control interface is activated when
PS is set to low.
There are two modes of parallel operation: direct parallel and
latched parallel.
Direct Parallel Mode
To enable direct parallel mode, the LE pad must be kept high. The
attenuation state is changed by the control voltage inputs (D0 to
D5) directly. This mode is ideal for manual control of the attenuator.
Figure 27. Latched Parallel Mode Timing Diagram
Latched Parallel Mode
To enable latched parallel mode, keep the LE pad low when
changing the control voltage inputs (D0 to D5) to set the attenuation
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Data Sheet
ADRF5473
APPLICATIONS INFORMATION
DIE ASSEMBLY
An assembly diagram of the ADRF5473 is shown in Figure 28.
Figure 28. Die Assembly Diagram
Figure 29. Bonding Diagram Top View
The ADRF5473 is designed to have the optimum RF input and
output impedance match with 3 mil × 0.5 mil gold ribbon wire and
3 mil loop height typical. The bonding diagrams are shown in
Figure 29 and Figure 30. Alternatively, using multiple wire bonds
with equivalent inductance yields similar performance. For RF rout-
ing from the device, coplanar wave guide or microstrip transmission
lines can be used. No impedance matching is required on the
transmission line pad because the device is designed to match
internally to the recommended ribbon bond. A spacing of 3 mils
from the RF transmission line to the device edge is recommended
for optimum performance.
Figure 30. Bonding Diagram Side View
HANDLING, MOUNTING, AND EPOXY DIE
ATTACH
DC pads can be connected using standard 1 mil diameter wire by
keeping the wire lengths as short as possible to minimize the para-
sitic inductance. The dc pads are large enough to accommodate
ribbon bonds, if preferred.
Keep devices in ESD protective sealed bags for shipment, and
store all bare die in a dry nitrogen environment.
For manual picking, it is a common practice to use a pair of
tweezers for GaAs devices. However, for die on carrier devices, the
use of a vacuum tool is recommended to avoid any damage on the
device substrate. Handle these devices in a clean environment.
All bonds must be thermosonically bonded at a nominal stage
temperature of 150°C, and a minimum amount of ultrasonic energy
must be applied to achieve reliable bonds.
The device is metalized on the backside, and the ground connec-
tion can be done by attaching the device directly to the RF ground
plane using a conductive epoxy. In this case, connecting the ground
pads is optional but still recommended to ensure a solid ground
connection.
To attach the die with epoxy, apply an amount of epoxy to the
mounting surface so that a thin epoxy fillet is observed around
the perimeter of the chip after it is placed into position. Set epoxy
cure temperatures per the recommendations of the manufacturer
and the maximum ratings of the device to minimize accumulated
mechanical stress after assembly.
Because both dies are attached with solder joints, users must follow
best practices for the thermomechanical design of their module
assemblies. The temperature expansion coefficient of the substrate
material must match the thermal expansion coefficient of the GaAs
and silicon (Si) die. Do not allow warpage or other mechanical
deformation on the substrate. Set the die attach process and the
epoxy cure temperatures to lower the accumulated stress after
assembly.
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Data Sheet
ADRF5473
OUTLINE DIMENSIONS
Figure 31. 18-Pad Die on Carrier [CHIP],
(C-18-1),
Dimensions Shown in Millimeters
ORDERING GUIDE
Package
Option
Model1
Temperature Range
Package Description
Packing Information
ADRF5473BCZ
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
18-Pad Die on Carrier [CHIP]
18-Pad Die on Carrier [CHIP]
18-Pad Die on Carrier [CHIP]
Waffle Pack, 50
Gel Pack, 50
C-18-1
C-18-1
C-18-1
ADRF5473BCZ-GP
ADRF5473BCZ-SX
Waffle Pack, 2
1
Z = RoHS Compliant Part.
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One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. 0 | 17 of 17
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