ADRV9002_技术文档

Data Sheet

ADRV9002

Dual Narrow-Band and Wideband RF Transceiver

The transceiver consists of direct conversion signal paths with

state-of-the-art noise figure and linearity. Each complete receiver

and transmitter subsystem includes dc offset correction, quadrature

error correction (QEC), and programmable digital filters, which

eliminate the need for these functions in the digital baseband. In ad-

dition, several auxiliary functions, such as auxiliary analog-to-digital

converters (ADCs), auxiliary digital-to-analog converters (DACs),

and general-purpose inputs/outputs (GPIOs), are integrated to pro-

vide additional monitoring and control capability.

FEATURES

► 2 × 2 highly integrated transceiver

► Frequency range of 30 MHz to 6000 MHz

► Transmitter and receiver bandwidth from 12 kHz to 40 MHz

► Two fully integrated, fractional-N, RF synthesizers

► LVDS and CMOS synchronous serial data interface options

► Low power monitor and sleep modes

► Multichip synchronization capabilities

► Fast frequency hopping

► Dynamic profile switching for dynamic data rates and sample

rates

► Fully integrated DPD for narrow-band and wideband waveforms

► Fully programmable via a 4-wire SPI

The fully integrated phase-locked loops (PLLs) provide high per-

formance, low power, fractional-N frequency synthesis for the trans-

mitter, receiver, and clock sections. Careful design and layout tech-

niques provide the isolation required in high performance personal

radio applications.

All voltage controlled oscillator (VCO) and loop filter components

are integrated to minimize the external component count. The local

oscillators (LOs) have flexible configuration options and include fast

lock modes.

► 12 mm × 12 mm, 196-ball CSP_BGA

APPLICATIONS

► Mission critical communications

► Very high frequency (VHF), ultrahigh frequency (UHF), and cellu-

lar to 6 GHz

► Time division duplexing (TDD) and frequency division duplexing

(FDD) applications

The transceiver includes low power sleep and monitor modes to

save power and extend the battery life of portable devices while

monitoring communications.

The fully integrated, low power digital predistortion (DPD) is opti-

mized for both narrow-band and wideband signals and enables

linearization of high efficiency power amplifiers.

GENERAL DESCRIPTION

The ADRV9002 core can be powered directly from 1.0 V, 1.3 V,

and 1.8 V regulators and is controlled via a standard 4-wire serial

port. Other voltage supplies are used to provide proper digital inter-

face levels and to optimize the receiver, transmitter, and auxiliary

converter performance.

The ADRV9002 is a highly integrated RF transceiver that has

dual-channel transmitters, dual-channel receivers, integrated syn-

thesizers, and digital signal processing functions.

The ADRV9002 is a high performance, highly linear, high dynamic

range transceiver designed for performance vs. power consumption

system optimization. The device is configurable and ideally suited

to demanding, low power, portable and battery powered equipment.

The ADRV9002 operates from 30 MHz to 6000 MHz and covers the

UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellu-

lar frequency bands in narrow-band (kHz) and wideband operation

up to 40 MHz. The ADRV9002 is capable of both TDD and FDD

operation.

High data rate and low data rate interfaces are supported using

configurable CMOS or low voltage differential signaling (LVDS)

serial synchronous interface (SSI) choice.

The ADRV9002 is packaged in a 12 mm × 12 mm, 196-ball chip

scale package ball grid array (CSP_BGA).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to

change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

DOCUMENT FEEDBACK

TECHNICAL SUPPORT

Data Sheet

ADRV9002

TABLE OF CONTENTS

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Functional Block Diagram......................................3

Specifications........................................................ 4

Transmitter Specifications..................................4

Receiver Specifications......................................6

Internal LO, External LO, and Device Clock.....12

Digital Interfaces and Auxiliary Converters...... 13

Power Supply Specifications............................15

Current Consumption Estimates (Typical

Values)........................................................... 15

Timing Specifications....................................... 17

Absolute Maximum Ratings.................................20

Reflow Profile................................................... 20

Thermal Resistance......................................... 20

Electrostatic Discharge (ESD) Ratings.............20

ESD Caution.....................................................20

Pin Configuration and Function Descriptions...... 21

Typical Performance Characteristics...................26

Wideband......................................................... 26

Narrow-Band.................................................... 58

Phase Noise.....................................................82

Theory of Operation.............................................84

Transmitter....................................................... 84

Receiver........................................................... 85

DPD..................................................................86

Clock Input....................................................... 86

Synthesizers.....................................................86

SPI....................................................................87

GPIO Pins........................................................ 87

Auxiliary Converters......................................... 87

JTAG Boundary Scan.......................................88

Applications Information...................................... 89

Power Supply Sequence..................................89

Digital Data Interface........................................89

Outline Dimensions............................................. 92

Ordering Guide.................................................92

REVISION HISTORY

4/2021—Revision 0: Initial Version

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Rev. 0 | 2 of 92

Data Sheet

ADRV9002

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

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Rev. 0 | 3 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Electrical characteristics are at the operating ambient temperature range, VDDA_1P0 = 1.0 V, VDDA_1P3 = 1.3 V, VDDA_1P8 = 1.8 V,

VDD_1P0 = 1.0 V, and VDD_1P8 = 1.8 V.

TRANSMITTER SPECIFICATIONS

Table 1. Transmitters (Tx1 and Tx2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

CENTER FREQUENCY

30

6000

40

MHz

TRANSMITTER SYNTHESIS

BANDWIDTH

0.012

Zero-IF mode, see the DPD section for more information

BANDWIDTH FLATNESS

DEVIATION FROM LINEAR PHASE

POWER CONTROL RANGE

In-Phase (I) and Quadrature (Q) Mode

Direct Modulation Mode

0.1

1

dB

10 MHz bandwidth span, including digital compensation

40 MHz bandwidth

Degrees

42

12

dB

POWER CONTROL RESOLUTION

I and Q Mode

0.05

0.5

dB

Direct Modulation Mode

dB

IN BAND NOISE FLOOR

−154

dBFS¹/Hz

0 dB attenuation, in band noise falls 1 dB for each dB of attenuation for

attenuation settings between 0 dB and 20 dB

OUT OF BAND NOISE FLOOR

Tx1 TO Tx2 ISOLATION

30 MHz

−156

dBFS/Hz

0 dB attenuation with 3 × bandwidth/2 offset

98

97

93

79

70

dB

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

IMAGE REJECTION WITH

INITIALIZATION CALIBRATION ONLY

Wideband

Up to 20 dB transmitter attenuation, 40 MHz bandwidth, 0 dB observation

receiver attenuation, 18 MHz continuous wave²signal input, QEC³tracking

calibration is disabled

50 MHz

470 MHz

55

63

59

60

57

55

dBc

900 MHz

2400 MHz

3500 MHz

5800 MHz

Narrow-Band

Up to 20 dB transmitter attenuation, 25 kHz bandwidth, 0 dB observation

receiver attenuation, 2.1 kHz continuous wave²signal input, QEC tracking

calibration is disabled

30 MHz

61

68

65

60

50

dBc

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

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Rev. 0 | 4 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 1. Transmitters (Tx1 and Tx2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

IMAGE REJECTION WITH

INITIALIZATION CALIBRATION AND

TRACKING CALIBRATION

Wideband

0 dB transmitter attenuation, 40 MHz bandwidth, −0.2 dBFS, 18 MHz

continuous wave²signal input, 50 Ω load, 0 dB observation receiver

attenuation, QEC is active

50 MHz

57

66

63

60

61

57

dBc

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

CONTINUOUS WAVE FULL-SCALE

OUTPUT POWER

−0.2 dBFS, 18 MHz continuous wave²signal input, 50 Ω load, 0 dB

transmitter attenuation

30 MHz

7.3

7.6

7.4

7.8

7.2

50

dBm

Ω

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

OUTPUT IMPEDANCE

Z_OUT

Differential, see the ADRV9001 system development user guide for more

information

MAXIMUM OUTPUT LOAD VOLTAGE

STANDING WAVE RATIO (VSWR)

3

Use the maximum value to ensure adequate calibration

OUTPUT RETURN LOSS

30 MHz

Single-ended return loss measured with balun in place on board

17

18

17

23

13

10

dB

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

OUTPUT THIRD-ORDER INTERCEPT

POINT

0 dB transmitter attenuation, 40 MHz bandwidth, 17 MHz and 18 MHz

continuous wave²signal input, digital backoff = 11 dBFS/tone, calibrated at

the device output

Wideband

50 MHz

OIP3_WB

31

30

28

29

27

dBm

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

Narrow-Band

OIP3_NB

0 dB transmitter attenuation, 25 kHz bandwidth, 2.1 kHz and 3.1 kHz

continuous wave²signal input, digital backoff = 5 dBFS/tone, calibrated at

the device output

30 MHz

30

31

30

28

27

25

dBm

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

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Rev. 0 | 5 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 1. Transmitters (Tx1 and Tx2)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

CARRIER LEAKAGE WITH

INITIALIZATION CALIBRATION ONLY

LO leakage tracking calibration disabled, 0 dB transmitter attenuation,

scales dB for dB with attenuation, input tone backoff = 6 dBFS

Wideband

50 MHz

−68

−65

−67

−68

−62

−56

dBm

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

Narrow-Band

30 MHz

−70

−72

−74

−71

−58

dBm

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

1

dBFS represents the ratio of the actual output signal to the maximum possible output level for a continuous wave output signal at the given RF attenuation setting.

A continuous wave is a single frequency signal.

2

3

Quadrature error correction (QEC) is the system for minimizing quadrature images of a desired signal.

RECEIVER SPECIFICATIONS

Table 2. Receivers (Rx1A, Rx1B, Rx2A, and Rx2B)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

CENTER FREQUENCY

MAXIMUM GAIN

Wideband

30

6000

MHz

High performance receiver ADCs, 0 dB attenuation, 5.6 MHz baseband

frequency

50 MHz

470 MHz

21

22

21

dB

900 MHz

2400 MHz

3500 MHz

5800 MHz

Narrow-Band

High performance receiver ADCs, 0 dB attenuation, 2.1 kHz baseband

frequency

30 MHz

21

22

21

34

dB

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

ATTENUATION RANGE FROM MAXIMUM

GAIN

Attenuation Accuracy

Gain Step

0.5

1.0

dB

Attenuator steps from 0 dB to 30 dB

Attenuator steps from 30 dB to 34 dB

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Rev. 0 | 6 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 2. Receivers (Rx1A, Rx1B, Rx2A, and Rx2B)

Parameter

Gain Step Error

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

0.1

0.2

0.1

dB

Attenuation step from 0 dB to 30 dB, LO from 30 MHz to 3 GHz

Attenuation step from 0 dB to 30 dB, LO from 3 GHz to 6 GHz

Attenuation step from 30 dB to 34 dB

FREQUENCY RESPONSE

Peak-to-Peak Gain Deviation

RECEIVER BANDWIDTH

1

dB

40 MHz bandwidth including digital compensation

Any 10 MHz span including digital compensation

0.2

dB

0.012

80

40

MHz

Zero-IF mode, the analog low-pass filter (LPF) bandwidth is 5 MHz

minimum, the programmable finite impulse response (FIR) filter bandwidth

is configurable over the entire range

RECEIVER ALIAS BAND REJECTION

dB

This performance is achieved because of the digital filters

CONTINUOUS WAVE FULL-SCALE

INPUT POWER¹

FSIP

−11.4

100

dBm

This continuous wave signal level corresponds to the input power at

maximum gain that produces 0 dBFS at the ADC output, this level increases

dB for dB with attenuation, backoff by at least −2 dBFS is required

INPUT IMPEDANCE

Ω

Differential, see the ADRV9001 system development user guide for more

information

INPUT PORT RETURN LOSS

30 MHz

Single-ended return loss measured with balun in place on board

20

21

20

22

9

dB

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

NOISE FIGURE

Wideband

50 MHz

10

NF_WB

11.6

10.6

10.5

11.4

12.5

12.6

dB

470 MHz

900 MHz

High performance receiver ADCs, 0 dB attenuation at the device under test

(DUT) receive port, integrated bandwidth from 8 MHz to 9 MHz

2400 MHz

3500 MHz

5800 MHz

NOISE FIGURE

Wideband

50 MHz

13.1

11.9

12.0

12.6

13.6

13.9

dB

470 MHz

900 MHz

Low power receiver ADCs, 0 dB attenuation at the DUT receive port,

integrated bandwidth from 8 MHz to 9 MHz

2400 MHz

3500 MHz

5800 MHz

NOISE FIGURE

Narrow-Band

30 MHz

NF_NB

13.8

11.8

12.3

14.2

15.1

dB

High performance receiver ADCs, 0 dB attenuation at the device under

test (DUT) receive port, integrated bandwidth from 4 kHz to 8 kHz, 18 dB

interface gain, intermediate frequency (IF) = 490 kHz

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

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Rev. 0 | 7 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 2. Receivers (Rx1A, Rx1B, Rx2A, and Rx2B)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

NOISE FIGURE

Narrow-Band

30 MHz

16.7

14.8

15.1

15.6

17.0

17.5

dB

Low power receiver ADCs, 0 dB attenuation at the DUT receive port,

integrated bandwidth from 4 kHz to 8 kHz, 18 dB interface gain, IF = 490

kHz

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

SECOND-ORDER INPUT

INTERMODULATION INTERCEPT POINT

Wideband

IIP2_WB

High performance receiver ADCs, 0 dB receiver attenuation, 1 dB cutoff

frequency (f_1dB) of the transimpedance amplifier (TIA) = 20 MHz, two

continuous wave tones at 17 MHz and 18 MHz, for LO = 50 MHz, tone

output power is −11.6 dBFS/tone, for all other LOs, tone output power is

−8.1 dBFS/tone

50 MHz

79

81

85

73

60

dBm

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

SECOND-ORDER INPUT

INTERMODULATION INTERCEPT POINT

Wideband

IIP2_WB

Low power receiver ADCs, 0 dB receiver attenuation, f_1dBof the TIA = 20

MHz, two continuous wave tones at 17 MHz and 18 MHz, for LO = 50 MHz,

tone output power is −11.6 dBFS/tone, for all other LOs, tone output power

is −8.1 dBFS/tone

50 MHz

70

74

72

65

59

60

dBm

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

THIRD-ORDER INPUT

INTERMODULATION INTERCEPT POINT,

DIFFERENCE PRODUCT

Wideband

IIP3_WB

High performance receiver ADCs, 0 dB receiver attenuation, f_1dBof the TIA

= 20 MHz, two continuous wave tones at 17 MHz and 18 MHz, for LO = 50

MHz, tone output power is −11.6 dBFS/tone, for all other LOs, tone output

power is −8.1 dBFS/tone

50 MHz

22

26

27

28

26

25

dBm

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

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Rev. 0 | 8 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 2. Receivers (Rx1A, Rx1B, Rx2A, and Rx2B)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

THIRD-ORDER INPUT

INTERMODULATION INTERCEPT POINT,

DIFFERENCE PRODUCT

Wideband

IIP3_WB

Low power receiver ADCs, 0 dB receiver attenuation, f_1dBof the TIA = 20

MHz, two continuous wave tones at 17 MHz and 18 MHz, for LO = 50 MHz,

tone output power is −11.6 dBFS/tone, for all other LOs, tone output power

is −8.1 dBFS/tone

50 MHz

21

22

21

23

20

dBm

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

THIRD-ORDER HARMONIC DISTORTION

Wideband

HD3_WB

High performance receiver ADCs, −20 dBm input power continuous wave

tone at 5.6 MHz at maximum gain at Rx input port, f_1dBof the TIA = 20 MHz,

HD3 product at 16.8 MHz

50 MHz

470 MHz

−84

−74

−82

−92

−93

−89

dBc

900 MHz

2400 MHz

3500 MHz

5800 MHz

Narrow-Band

HD3_NB

High performance receiver ADCs, −20 dBm input power continuous wave

tone at 2.1 kHz at maximum gain at Rx input port, f_1dBof the TIA = 2 MHz,

HD3 product at 6.3 kHz

30 MHz

−102

−97

−89

−79

−80

−72

dBc

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

THIRD-ORDER HARMONIC DISTORTION

Wideband

HD3_WB

Low power receiver ADCs, −20 dBm input power continuous wave tone at

5.6 MHz at maximum gain at Rx input port, f_1dBof the TIA = 20 MHz, HD3

product at 16.8 MHz

50 MHz

470 MHz

−90

−71

−79

−81

−82

−84

dBc

900 MHz

2400 MHz

3500 MHz

5800 MHz

Narrow-Band

HD3_NB

Low power receiver ADCs, −20 dBm input power continuous wave tone at

2.1 kHz at maximum gain at Rx input port, f_1dBof the TIA = 2 MHz, HD3

product at 6.3 kHz

30 MHz

−108

−95

−89

−81

−80

−71

dBc

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

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Rev. 0 | 9 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 2. Receivers (Rx1A, Rx1B, Rx2A, and Rx2B)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SECOND-ORDER HARMONIC

DISTORTION

Wideband

HD2_WB

High performance receiver ADCs, −20 dBm input power continuous wave

tone at 5.6 MHz at maximum gain at Rx input port, f_1dBof the TIA = 20 MHz,

HD2 product at 11.2 MHz

50 MHz

470 MHz

−91

−93

−89

−83

−82

dBc

900 MHz

2400 MHz

3500 MHz

5800 MHz

Narrow-Band

HD2_NB

High performance receiver ADCs, −20 dBm input power continuous wave

tone at 2.1 kHz at maximum gain at Rx input port, f_1dBof the TIA = 2 MHz,

HD2 product at 4.2 kHz

30 MHz

−102

−96

−90

−79

−80

−71

dBc

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

SECOND-ORDER HARMONIC

DISTORTION

Wideband

HD2_WB

Low power receiver ADCs, −20 dBm input power continuous wave tone at

5.6 MHz at maximum gain at Rx input port, f_1dBof the TIA = 20 MHz, HD2

product at 11.2 MHz

50 MHz

470 MHz

−92

−91

−89

−84

−79

dBc

900 MHz

2400 MHz

3500 MHz

5800 MHz

Narrow-Band

HD2_NB

Low power receiver ADCs, −20 dBm input power continuous wave tone at

2.1 kHz at maximum gain at Rx input port, f_1dBof the TIA = 2 MHz, HD2

product at 4.2 kHz

30 MHz

−109

−94

−90

−81

−80

−70

dBc

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

IMAGE REJECTION WITH

INITIALIZATION CALIBRATION AND

HARDWARE TRACKING ONLY

Wideband

High performance receiver ADCs, software QEC disabled, 40 MHz receiver

bandwidth, maximum receiver gain index, −20 dBm input power continuous

wave tone at 5.6 MHz

50 MHz

84

83

82

81

82

dBc

470 MHz

900 MHz

1900 MHz

3500 MHz

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Rev. 0 | 10 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 2. Receivers (Rx1A, Rx1B, Rx2A, and Rx2B)

Parameter

5800 MHz

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

78

dBc

IMAGE REJECTION WITH

INITIALIZATION CALIBRATION AND

HARDWARE TRACKING ONLY

Wideband

Low power receiver ADCs, software QEC disabled, 40 MHz receiver

bandwidth, maximum receiver gain index, −20 dBm input power continuous

wave tone at 5.6 MHz

50 MHz

87

90

86

84

82

75

dBc

470 MHz

900 MHz

1900 MHz

3500 MHz

5800 MHz

RECEIVER INPUT LO LEAKAGE AT

MAXIMUM GAIN

Leakage decreased dB for dB with attenuation for the first 12 dB

50 MHz

470 MHz

−66

−62

−60

dBm

900 MHz

2400 MHz

3500 MHz

5800 MHz

SIGNAL ISOLATION

Tx1 to Rx1A or Rx1B Signal Isolation

and Tx2 to Rx2A or Rx2B Signal

Isolation

Isolation between Tx and Rx port, isolation changes dB for dB with Rx gain

30 MHz

100

85

78

77

62

64

dB

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

Tx1 to Rx2A or Rx2B Isolation and Tx2

to Rx1A or Rx2B Signal Isolation

Isolation between Tx and Rx port, isolation changes dB for dB with Rx gain

30 MHz

120

110

100

90

dB

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

74

81

Rx1A or Rx1B to Rx2A or Rx2B Signal

Isolation

30 MHz

106

103

98

dB

470 MHz

900 MHz

2400 MHz

3500 MHz

5800 MHz

92

83

71

Rx1A to Rx1B and Rx2A to Rx2B Signal

Isolation

30 MHz

99

dB

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Rev. 0 | 11 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 2. Receivers (Rx1A, Rx1B, Rx2A, and Rx2B)

Parameter

470 MHz

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

97

90

86

84

70

dB

900 MHz

2400 MHz

3500 MHz

5800 MHz

1

Note that the input signal power limit does not correspond to 0 dBFS at the digital output because of the nature of the continuous time Σ-Δ ADCs. Unlike the hard clipping

characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level.

INTERNAL LO, EXTERNAL LO, AND DEVICE CLOCK

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

LO

Frequency Step

4.5

Hz

For 38.4 MHz DEV_CLK, use the

equation DEV_CLK/2²³− 15 to

calculate

Reference Spurs

LO WITH HIGH PERFORMANCE MODE

Integrated Phase Noise

30 MHz LO

−80

dBc

LO < 1 GHz, PLL bandwidth = 300 kHz

Integrated from 100 Hz to 50 MHz

PLL bandwidth = 300 kHz

0.008

0.04

0.08

0.22

0.27

0.6

°rms

470 MHz LO

900 MHz LO

2400 MHz LO

3500 MHz LO

5800 MHz LO

Phase Noise

DEV_CLK = 38.4 MHz, typical

performance

30 MHz LO

See Figure 292

See Figure 293

See Figure 294

See Figure 295

See Figure 296

See Figure 297

PLL bandwidth = 300 kHz

470 MHz LO

900 MHz LO

2400 MHz LO

3500 MHz LO

5800 MHz LO

LO PHASE SYNCHRONIZATION

Initial Phase Synchronization Accuracy

EXTERNAL LO INPUT

Input Frequency

3

Degrees

Input frequency must be 2× or higher

than the desired frequency for the

LO frequency (f_LO), a 1× multiplier is

available for an LO range from 500

MHz to 1 GHz

f_EXTLO

60

−6

12000

+6

MHz

Input Signal Power

0

dBm

50 Ω matching at the source

Input Signal Differential Phase Balance

20

Degrees

Do not exceed 20 degrees to ensure

adequate quadrature error correction

Input Signal Differential Amplitude Balance

Input Signal Duty Cycle

1

dB

%

Ω

2.5

100

Input Impedance

Differential, see the ADRV9001 system

development user guide for more

information

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Rev. 0 | 12 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE CLOCK (DEV_CLK_IN SIGNAL)

Differential mode

Frequency Range

10

1000

1

MHz

Signal Level

0.2

V p-p

AC-coupled, for optimal spurious

performance and to meet the specified

PLL performance parameters, use a 1

V p-p (2 V p-p differential) input clock.

Single-Ended Mode

Frequency Range

Signal Level

10

80

1

MHz

0.2

V p-p

AC-coupled, for optimal spurious

performance and to meet the specified

PLL performance parameters, use a 1

V p-p input clock.

REFERENCE CLOCK (XTAL)

Frequency Range

20

10

80

MHz

CLOCK OUTPUT (DEV_CLK_OUT SIGNAL)

Frequency Range

DIGITAL INTERFACES AND AUXILIARY CONVERTERS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

AUXILIARY ADC CONVERTERS

Resolution

10

Bits

Input Voltage

Minimum

0.05

0.95

V

Maximum

AUXILIARY DAC CONVERTERS

Resolution

12

Bits

Output Voltage

Minimum

0.05

VDDA_1P8¹

V

Maximum

−

0.05

Drive Capability

10

mA

DIGITAL SPECIFICATIONS (CMOS SSI

SIGNALS)

Logic Inputs

Input Voltage

High Level

VDIGIO_1P8 ×

0.65

VDIGIO_1P8 +

0.18

V

Low Level

−0.30

VDIGIO_1P8 ×

0.35

Logic Outputs

Output Voltage

High Level

VDIGIO_1P8 −

0.45

V

Low Level

0.45

V

Drive Capability

10

mA

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Rev. 0 | 13 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL SPECIFICATIONS (DIGITAL

GPIO SIGNALS)

Logic Inputs

Input Voltage

High Level

VDIGIO_1P8 ×

0.65

VDIGIO_1P8 +

0.18

V

Low Level

−0.30

VDIGIO_1P8 ×

0.35

Logic Outputs

Output Voltage

High Level

VDIGIO_1P8 −

0.45

V

Low Level

0.45

V

Drive Capability

10

mA

DATAPORT SPECIFICATIONS (LVDS

SSI, MCS+ and MCS−)

Logic Inputs

Input Voltage Range

825

1675

+100

mV

Each differential input in the pair

Internal termination enabled

Input Differential Voltage

Threshold

−100

Receiver Differential Input

Impedance

100

Ω

Logic Outputs

Output Voltage

High Level

Low Level

Differential

Offset

1390

17

mV

mA

1000

300

1200

Drivers are shorted to ground, there is no internal termination

available, an off-chip 100 Ω termination is required

Output Current

4.1

55

mA

%

Drivers are shorted together

500 MHz

Clock Signal Duty Cycle

Output Rise and Fall Time

45

50

0.371

ns

300 mV p-p swing

DIGITAL SPECIFICATIONS (ANALOG

GPIO SIGNALS)

Logic Inputs

Input Voltage

High Level

VDDA_1P8 × 0.65

−0.30

VDDA_1P8 + 0.18

VDDA_1P8 × 0.35

V

Low Level

Logic Outputs

Output Voltage

High Level

VDDA_1P8 − 0.45

V

Low Level

0.45

V

Drive Capability

10

mA

1

VDDA_1P8 refers to all analog 1.8 V supplies including VCONV_1P8, VAGPIO_1P8, VANA2_1P8, and VANA1_1P8.

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Rev. 0 | 14 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter

Min

Typ

Max

Unit

SUPPLY CHARACTERISTICS

VDDA_1P0¹Analog Supplies

VDD_1P0²Digital Supply

VDDA_1P3³Analog Supplies

VDDA_1P8 Analog Supplies

VDD_1P8⁴Digital Supply

0.975

0.95

1.0

1.3

1.8

1.025

1.05

1.33

1.89

V

1.267

1.71

1

VDDA_1P0 refers to all analog 1.0 V supplies that operate with the internal low dropout (LDO) regulator bypassed. The power domain that allows the internal LDO regulator

bypass includes VRFLO2_1P0, VRFLO1_1P0, VRX2LO_1P3, VRX1LO_1P3, VTX2LO_1P3, VCONV_1P3, and VTX1LO_1P3.

2

3

VDD_1P0 refers to all digital 1.0 V supplies including VDIG_1P0.

VDDA_1P3 refers to all analog 1.3 V supplies including VRFVCO2_1P3, VRFVCO1_1P3, VANA2_1P3, VANA1_1P3, VRX2LO_1P3, VCLKSYN_1P3, VRFSYN2_1P3,

VRFSYN1_1P3, VAUXSYN_1P3, VRX1LO_1P3, VTX2LO_1P3, VCLKVCO_1P3, VAUXVCO_1P3, VTX1LO_1P3, and VCONV_1P3.

4

VDD_1P8 refers to all digital 1.8 V supplies including VDIGIO_1P8.

CURRENT CONSUMPTION ESTIMATES (TYPICAL VALUES)

No external VDDA_1P0 1.0 V power domain is used in Table 6 to Table 11. In all following modes described, the ADRV9002 operates with

internal LDO regulators used to produce an on-chip, 1.0 V analog power domain.

Sleep Mode

Table 6. Digital Mobile Radio (DMR) CMOS SSI

Supply (mA)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Total Average

Power (W)

ADRV9002 Mode Conditions

Receiver, Transmitter, Clock PLL, and LDO Regulator Powered

Down, Internal Microprocessor Active, CMOS SSI Interface Off,

DEV_CLK_OUT Off, and Auxiliary DACs Off

Not used

18.9

8.2

9.7

1.3

0.049

Receiver, Transmitter, Clock PLL, LDO Regulator, and Internal

Microprocessor Powered Down, CMOS SSI Interface Off,

DEV_CLK_OUT Off, and Auxiliary DACs Off

Not used

2.3

6.9

9.7

1.3

0.031

Table 7. Long-Term Evolution (LTE) Dual Transmitter and Dual Receiver LVDS SSI

Supply (mA)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Total Average

Power (W)

ADRV9002 Mode Conditions

Receiver, Transmitter, Clock PLL, and LDO Regulator Powered Down,

Internal Microprocessor Active, LVDS SSI Interface Off, DEV_CLK_OUT

Off, and Auxiliary DACs Off

Not used

24.6

12.4

11.3

1.3

0.066

Receiver, Transmitter, Clock PLL, LDO Regulator, and Internal

Microprocessor Powered Down, LVDS SSI Interface Off, DEV_CLK_OUT

Off, and Auxiliary DACs Off

Not used

2.3

10.3

10.6

1.3

0.037

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Rev. 0 | 15 of 92

Data Sheet

SPECIFICATIONS

TDD Operation

ADRV9002

Table 8. DMR, 4× External LO, LO = 470 MHz, Low Power Mode Clock PLL, Processor Clock Divisor = 4, CMOS SSI

Supply (mA)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Total Average

Power (W)

ADRV9002 Mode Conditions

1 × Receiver Low Power ADC, Low IF, 12.5 kHz Receiver Bandwidth,

24 kSPS Data Rate, Receiver QEC Enabled, QEC Engine Active, and

Transmitter Powered Down

Not used

92

171

26

3

0.367

1 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 12.5

kHz Transmitter Bandwidth, 96 kSPS Data Rate, Direct Modulation (DM)

Mode, Transmitter QEC Disabled, QEC Engine Inactive, and Receiver

Powered Down

Not used

62

257

100

3

0.582

1 × Transmitter RF Attenuation = 6 dB, Full-Scale Continuous Wave

12.5 kHz Transmitter Bandwidth, 96 kSPS Data Rate, DM Mode,

Transmitter QEC Disabled, QEC Engine Inactive, and Receiver Powered

Down

Not used

62

257

58

3

0.506

Table 9. LTE40 Two Transmitters and Two Receivers (2T2R), LO = 2.5 GHz, High Performance Clock PLL, LVDS SSI

Supply (mA)

VDDA_1P3

VDDA_1P0

Analog

VDD_1P0

Digital

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Total

Average

Power (W)

Analog

ADRV9002 Mode Conditions

Supplies

Supply

Supplies

2 × Receiver Low Power ADC Low Rate, 40 MHz Receiver Bandwidth,

61.44 MSPS Data Rate, Receiver QEC Enabled, QEC Engine Active, and

Transmitter in Primed State

Not used

446

225

397

546

701

1136

64

53

52

1.366

1.727

1.446

2.500

2 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Disabled,

QEC Engine Inactive, and Receiver in Primed State

Not used

276

120

296

2 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave 40 MHz Not used

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Disabled,

QEC Engine Inactive, and Receiver in Primed State

2 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Disabled,

QEC Engine Active, Receiver in Primed State, Transmitter QEC Tracking

Always On, Observation Receiver Continuously On, and Transmitter Tracking

Duty Cycled (Practical Scenario)

Not used

2 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave 40 MHz Not used

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Enabled,

QEC Engine Active, Receiver in Primed State, Transmitter QEC Tracking

Always On, Observation Receiver Continuously On, and Transmitter Tracking

Duty Cycled (Practical Scenario)

395

1126

144

52

2.212

Table 10. LTE40 One Transmitter and One Receiver (1T1R), LO = 2.5 GHz, High Performance Clock PLL, LVDS SSI

Supply (mA)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Total

Average

Power (W)

ADRV9002 Mode Conditions

1 × Receiver Low Power ADC Low Rate, 40 MHz Receiver Bandwidth,

61.44 MSPS Data Rate, Receiver QEC Enabled, QEC Engine Active, and

Transmitter in Primed State

Not used

258

406

39

28

0.906

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Rev. 0 | 16 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 10. LTE40 One Transmitter and One Receiver (1T1R), LO = 2.5 GHz, High Performance Clock PLL, LVDS SSI

Supply (mA)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Total

Average

Power (W)

ADRV9002 Mode Conditions

1 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz Not used

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Disabled,

QEC Engine Inactive, and Receiver in Primed State

140

141

232

486

754

143

28

1.080

0.942

1.543

1 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave

40 MHz Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC

Disabled, QEC Engine Inactive, and Receiver in Primed State

Not used

66

1 × Transmitter RF Attenuation = 0 dB, Full-Scale Continuous Wave 40 MHz Not used

Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC Enabled,

QEC Engine Active, Receiver in Primed State, Transmitter QEC Tracking

Always On, Observation Receiver Continuously On, and Transmitter Tracking

is Duty Cycled (Practical Scenario)

156

1 × Transmitter RF Attenuation = 10 dB, Full-Scale Continuous Wave

40 MHz Transmitter Bandwidth, 61.44 MSPS Data Rate, Transmitter QEC

Enabled, QEC Engine Active, Receiver in Primed State, Transmitter QEC

Tracking Always On, Observation Receiver Continuously On, and Transmitter

Tracking is Duty Cycled (Practical Scenario)

Not used

231

755

79

28

1.405

FDD Operation

Transmit channel enabled, 40 MHz transmitter bandwidth, 61.44 MSPS data rate, transmitter internal LO = 2.4 GHz, transmit QEC disabled,

QEC engine inactive, LVDS SSI. Receive channel enabled, 40 MHz receiver bandwidth, 61.44 MSPS data rate, receiver internal LO = 2.5 GHz,

high performance clock PLL, high performance receiver ADC low rate, receive QEC enabled, and QEC engine active. Using a low power ADC

decreases power consumption by approximately 110 mW per receiver channel. No auxiliary DACs or auxiliary ADCs are enabled.

Table 11. FDD Modes

Supply (mA)

VDDA_1P0 Analog

Supplies

VDD_1P0 Digital

Supply

VDDA_1P3 Analog

Supplies

VDDA_1P8 Analog

Supplies

VDD_1P8 Digital

Supply

Total Average

Power (W)

ADRV9002 Mode Conditions

1 × Receiver, 1 × Transmitter RF

Attenuation = 0 dB, Full-Scale Continuous

Wave

Not used

298

507

835

179

103

344

190

28

53

1.756

1.619

2.826

2.549

1 × Receiver, 1 × Transmitter

RF Attenuation = 10 dB, Full-Scale

Continuous Wave

835

2 × Receiver, 2 × Transmitter RF

Attenuation = 0 dB, Full-Scale Continuous

Wave

1234

2 × Receiver, 2 × Transmitter

RF Attenuation = 10 dB, Full-Scale

Continuous Wave

TIMING SPECIFICATIONS

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SERIAL PERIPHERAL INTERFACE (SPI) TIMING

t_CP

28

22

10

3

ns

SPI_CLK period, 3-wire mode

SPI_CLK period, 4-wire mode

SPI_CLK pulse width

t_MP

t_SC

SPI_EN setup to first SPI_CLK rising edge

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Rev. 0 | 17 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

t_HC

t_S

0

2

0

3

t_H

ns

Last SPI_CLK falling edge to SPI_EN hold

SPI_DIO data input setup to SPI_CLK

SPI_DIO data input hold to SPI_CLK

t_H

t_CO

15

10

t_CO

SPI_CLK falling edge to output data delay (3-wire mode)

SPI_CLK falling edge to output data delay (4-wire mode)

Bus turnaround time after the baseband processor drives the

last address bit

t_HZM

0

t_CO

ns

Bus turnaround time after the ADRV9002 drives the last

address bit, not shown in Figure 2

t_HZS

DIGITAL TIMING¹

TX1_ENABLE or TX2_ENABLE Pulse Width

RX1_ENABLE or RX2_ENABLE Pulse Width

TX1_ENABLE or TX2_ENABLE Valid Data

RX1_ENABLE or RX2_ENABLE Valid Data

DIGITAL DATA TIMING (LVDS SSI)

10

µs

2

Zero on-chip lane skew and an adjustable delay of ±300 ps

available per lane

TXx_DCLK_IN±, RXx_DCLK_OUT± and

TXx_DCLK_OUT± Clock Period

2

1

ns

500 MHz

TXx_DCLK_IN±, RXx_DCLK_OUT± and

TXx_DCLK_OUT± Pulse Width

Transmitter Data

TXx_IDATA_IN± or TXx_QDATA_IN or

TXx_STROBE_IN± Setup to TXx_DCLK_IN±

0.25

0.55

ns

TXx_IDATA_IN± or TXx_QDATA_IN± or

TXx_STROBE_IN± Hold to TXx_DCLK_IN±

Receiver Data

RXx_DCLK_OUT± to RXx_IDATA_OUT± or

RXx_QDATA_OUT± or RXx_STROBE_OUT± Delay

0.2

ns

DC-coupled

80 MHz

DIGITAL DATA TIMING (CMOS-SSI)

TXx_DCLK_IN±, RXx_DCLK_OUT± and

TXx_DCLK_OUT± Clock Period

12.5

6.25

ns

TXx_DCLK_IN±, RXx_DCLK_OUT± and

TXx_DCLK_OUT± Pulse Width

Transmitter Data

TXx_DATA_IN± or TXx_STROBE_IN± Setup to

TXx_DCLK_IN±

2

ns

TXx_DATA_IN± or TXx_STROBE_IN± Hold to

TXx_DCLK_IN±

Receiver Data

RXx_DCLK_OUT± to RXx_DATA_OUT± or

RXx_STROBE_OUT± Delay

4.5

ns

DC-coupled

MULTICHIP SYNCHRONIZATION (MCS) TIMING

LVDS Setup

LVDS Hold

0.62

ns

0

1

3

CMOS Setup

CMOS Hold

1

TX1_ENABLE, TX2_ENABLE, RX1_ENABLE, and RX2_ENABLE are the channel enabling and disabling signals.

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Rev. 0 | 18 of 92

Data Sheet

ADRV9002

SPECIFICATIONS

Figure 2. 3-Wire SPI Timing with Parameter Labels, SPI Read

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Data Sheet

ADRV9002

ABSOLUTE MAXIMUM RATINGS

Table 13.

THERMAL RESISTANCE

Parameter

Rating

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to PCB

thermal design is required.

VDDA_1P0 to VSSA

−0.2 V to +1.2 V

−0.2 V to +1.5 V

−0.3 V to +2.2 V

−0.2 V to +1.2 V

−0.3 V to +2.2 V

±10 mA

VDDA_1P3 to VSSA

VDDA_1P8 to VSSA

The thermal resistance values specified in Table 15 are calculated

based on JEDEC specifications (unless specified otherwise) and

must be used in compliance with JESD51-12. Note that using

enhanced heat removal techniques (PCB, heat sink, airflow, and so

on) improves thermal resistance.

VDD_1P0 to VSSD

VDD_1P8 to VSSD

Input Current to Any Pin Except Supplies

Maximum Input Power into RF Ports

See Table 14 for limits vs.

survival time

Junction Temperature Range

Storage Temperature Range

−40°C to +110°C

−65°C to +150°C

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

θ_{JC_TOP}is the thermal resistance from the junction to the top of the

package case.

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress

rating only; functional operation of the product at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum operat-

ing conditions for extended periods may affect product reliability.

Table 15. Thermal Resistance Values^{1, 2}

θ_{JC_TOP}

Package Type θ_JA(°C/W) (°C/W)

θ_JB(°C/W) Ψ_JC(°C/W) Ψ_JB(°C/W)

3.96 0.02 3.63

BC-196-13 18.21 0.04

Table 14. Maximum Input Power into RF Ports vs. Lifetime

¹For test, 100 μm thermal interface material (TIM) is used. TIM is

assumed to have 3.6 W/mK.

Lifetime

30 dB of

²Using enhanced heat removal (PCB, heat sink, airflow, and so on)

techniques improve thermal resistance values.

RF Port Input Power,

Continuous Wave Signal (dBm)

Attenuation from

Maximum Gain

0 dB of Attenuation

from Maximum Gain

7

>10 years

>7 years

>10 years

20000 hours

14 hours

ELECTROSTATIC DISCHARGE (ESD) RATINGS

10

20

23

25

The following ESD information is provided for handling of ESD-sen-

sitive devices in an ESD protected area only.

110 minutes

60 minutes

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.

REFLOW PROFILE

The ADRV9002 reflow profile is in accordance with the JEDEC

JESD20 criteria for Pb-free devices. The maximum reflow tempera-

ture is 260°C.

ESD Ratings for ADRV9002

Table 16. ADRV9002, 196-Ball CSP_BGA

ESD Model

Withstand Threshold (V)

Class

HBM

CDM

2000

350

2

C1

C2A

CDM (Excluding

AUXADC_2)

500

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Charged devi-

ces and circuit boards can discharge without detection. Although

this product features patented or proprietary protection circuitry,

damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

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Data Sheet

ADRV9002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 17. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

A1, A2, A13, A14, B2 to B5,

B10 to B13, C2, C5, C10, C13,

D1 to D6, D9 to D14, E6, E9,

F1 to F3, F6 to F9, F12 to F14,

G2, G13, J1 to J14

Input

VSSA

Analog Ground (V_SSA).

A3, A4

Input

EXT_LO2+, EXT_LO2−

VRFVCO2_1P3

Differential External LO Input 1 (LO1). If EXT_LO2+ and EXT_LO2− are used for the external LO1, the

input frequency must be 2× or higher than the desired carrier frequency. For an LO range from 500 MHz

to 1 GHz, a 1× multiplier is available. If unused, connect EXT_LO2+ and EXT_LO2− to VSSA.

A5

A6

1.3 V Internal LDO Regulator Input Supply for RF External LO Input 2 (LO2) VCO and LO Generation

Circuitry. VRFVCO2_1P3 is sensitive to supply noise.

Input and VRFLO2_1P0

Output

1.0 V Internal Supply Node for RF LO2 LO Generation Circuitry. Connect VRFLO2_1P0 together with

VRFVCO2_1P0 and bypass with a 4.7 µF capacitor when the internal LDO regulator operated from the

VRFVCO2_1P3 input is in use. Provide a 1.0 V supply to VRFLO2_1P0 when the internal LDO regulator

that is operated from VRFVCO2_1P3 is not in use.

A7

Input

MODEA

Use MODEA to configure the boot up option for the DEV_CLK_IN± inputs and the DEV_CLK_OUT

output. Connect MODEA to VSSA to enable the differential clock receiver at the DEV_CLK_IN± pins.

Connect MODEA to a voltage level higher than any VSSA to enable either the single-ended clock at

DEV_CLK_IN+ or the crystal oscillator resonator at both of the DEV_CLK_IN± pins.

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Rev. 0 | 21 of 92

Data Sheet

ADRV9002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 17. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

A8

Input

RBIAS

Bias Resistor Connection. RBIAS generates an internal current based on an external 1% resistor.

Connect a 4.99 kΩ resistor between RBIAS and VSSA (analog ground) .

A9

Input and VRFLO1_1P0

Outputt

1.0 V Internal Supply Node for RF LO1 LO Generation Circuitry. Connect VRFLO1_1P0 together with

VRFVCO1_1P0 and bypass with a 4.7 µF capacitor when the internal LDO regulator operated from the

VRFVCO1_1P3 input is in use. Provide a 1.0 V supply to VRFLO1_1P0 when the internal LDO regulator

operated from VRFVCO1_1P3 is not in use.

A10

Input

VRFVCO1_1P3

1.3 V Internal LDO Input Supply for RF LO1 VCO and LO Generation Circuitry. VRFVCO1_1P3 is

sensitive to supply noise.

A11, A12

EXT_LO1−, EXT_LO1+

Differential External LO Input 2. If EXT_LO1+ and EXT_LO1− are used for the external LO2, the input

frequency must be 2× or higher than the desired carrier frequency. For an LO range from 500 MHz to 1

GHz, a 1× multiplier is available. If unused, connect EXT_LO1+ and EXT_LO1− to VSSA.

B1, C1

B6

Input

RX2A−, RX2A+

VRFVCO2_1P0

Differential Input A for Rx2. If unused, connect RX2A− and RX2A+ to VSSA.

Output

1.0 V Internal Supply Node for RF LO2 VCO Circuitry. Connect this VRFVCO2_1P0 together with

VRFLO2_1P0 and bypass with a 4.7 µF capacitor when the internal LDO regulator operated from the

VRFVCO2_1P3 input is in use.

B7

B8

B9

Input

AUXADC_2

Input 2 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_2.

Input 1 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_1.

Input

AUXADC_1

Output

VRFVCO1_1P0

1.0 V Internal Supply node for RF LO1 VCO Circuitry. Connect VRFVCO1_1P0 together with

VRFLO1_1P0 and bypass with a 4.7 µF capacitor when the internal LDO regulator operated from

the VRFVCO1_1P3 input is in use.

B14, C14

C3, C4

C6

Input

RX1A−, RX1A+

RX2B+, RX2B−

Differential Input A for Rx1. If unused, connect RX1A− and RX1A+ to VSSA.

Differential Input B for Rx2. If unused, connect RX2B+ and RX2B− to VSSA.

Input and VANA2_1P0

Output

1.0 V Internal Supply Node for Tx2 and Rx2 Baseband Circuits, TIA, Transmitter Transconductance (GM)

Baseband Filters, and Auxiliary DACs and ADCs. For normal operation, leave VANA2_1P0 unconnected.

C7

C8

C9

Input

VANA2_1P3

1.3 V Internal LDO Input Supply for Tx2 and Rx2 Baseband Circuits, TIA, Transmitter GM, Baseband

Filters, and Auxiliary DACs and ADCs. VANA2_1P3 is sensitive to supply noise.

Input

VANA1_1P3

1.3 V Internal LDO Input Supply for Tx1 and Rx1 Baseband Circuits, TIA, Transmitter GM and Baseband

Filters. VANA1_1P3 is sensitive to supply noise.

Input and VANA1_1P0

Output

1.0 V Internal Supply Node for Tx1 and Rx1 Baseband Circuits, TIA, Transmitter GM and Baseband

Filters. For normal operation, leave VANA1_1P0 unconnected.

C11, C12

D7, D8

E1

Input

RX1B−, RX1B+

MCS+, MCS−

VRX2LO_1P0

Differential Input B for Rx1. If unused, connect RX1B− and RX1B+ to VSSA.

Input

Multichip Synchronization Reference Inputs. If unused, connect MCS+ and MCS− to VSSA.

Output

1.0 V Internal Supply Node for Rx2 LO Buffers and Mixers. VRX2LO_1P0 is sensitive to supply noise.

Bypass VRX2LO_1P0 with a 4.7 µF capacitor.

E2

Input

VRX2LO_1P3

1.3 V Internal LDO Input Supply for Rx2 LO Buffers and Mixers. Provide a 1.0 V supply to VRX2LO_1P3

when the internal LDO regulator is not used. VRX2LO_1P3 is sensitive to supply noise.

E3, E12, F4, F5, F10, F11, G4, Input and AGPIO_xx

GPIOs Signals Referenced to VAGPIO_1P8 1.8 V Supply. See Table 18 to match the ball location to the

AGPIO_xx signal name. Some AGPIO_xx pins can also function as auxiliary DAC outputs. See Table 18

for mapping between AGPIO_xx and the auxiliary DAC signals. If unused, do not connect AGPIO_xx.

G6, G9, G11, H6, H9

Output

E4

Input

VRFSYN2_1P3

VCLKSYN_1P3

1.3 V Supply for RF LO2 Synthesizer. VRFSYN2_1P3 is sensitive to supply noise.

1.3 V Supply for Clock Synthesizer. VCLKSYN_1P3 is sensitive to supply noise.

E5

E7, E8

DEV_CLK_IN+,

DEV_CLK_IN−

Device Clock Input. DEV_CLK_IN± can operate as differential, single-ended, or be connected to the

external crystal oscillator. In single-ended mode, apply the clock signal to the DEV_CLK_IN+ pin and

leave the DEV_CLK_IN− pin unconnected.

E10

E11

E13

Input

VAUXSYN_1P3

VRFSYN1_1P3

VRX1LO_1P3

1.3 V Supply for Auxiliary Synthesizer. VAUXSYN_1P3 is sensitive to supply noise.

1.3 V Supply for RF LO1 Synthesizer. VRFSYN1_1P3 is sensitive to supply noise.

1.3 V Internal LDO Input Supply for Rx1 LO Buffers and Mixers. Provide a 1.0 V supply to VRX1LO_1P3

when the internal LDO regulator is not used. VRX1LO_1P3 is sensitive to supply noise.

E14

Output

VRX1LO_1P0

TX2+, TX2−

1.0 V Internal Supply Node for Rx1 LO Buffers and Mixers. VRX1LO_1P0 is sensitive to supply noise.

Bypass VRX1LO_1P0 with a 4.7 µF capacitor.

G1, H1

Differential Output for Transmitter Channel 2. If unused, do not connect TX2+ and TX2−.

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Data Sheet

ADRV9002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 17. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

G3

Input

VTX2LO_1P3

1.3 V Supply for Tx2 LO Buffers, Upconverter, and LO Delay. Provide a 1.0 V supply to VTX2LO_1P3

when the internal LDO is not used. VTX2LO_1P3 is sensitive to supply noise.

G5

Input

VCLKVCO_1P3

1.3 V Internal LDO Input Supply for Clock LO VCO and LO Generation Circuitry. VCLKVCO_1P3 is

sensitive to supply noise.

G7

Input

VCONV_1P8

VAGPIO_1P8

VAUXVCO_1P3

1.8 V Supply for Tx1 and Tx2 DAC and Rx1 and Rx2 ADC.

G8

1.8 V Supply for Auxiliary DACs, Auxiliary ADCs, and AGPIO Signals.

G10

1.3 V Internal LDO Input Supply for Auxiliary LO VCO and LO Generation Circuitry. VAUXVCO_1P3 is

sensitive to supply noise.

G12

Input

VTX1LO_1P3

1.3 V Internal LDO Input Supply for Tx1 LO Buffers, Upconverter, and LO Delay. Provide a 1.0 V supply

to VTX1LO_1P3 when the internal LDO regulator is not used. VTX1LO_1P3 is sensitive to supply noise.

G14, H14

H2

Output

Input

TX1+, TX1−

VANA2_1P8

VTX2LO_1P0

Differential Output for Transmitter Channel 1. If unused, do not connect TX1+ and TX1−.

1.8 V Supply for Rx2 Mixer, Rx2 TIA, Tx2 LPF, and Internal References.

H3

Output

1.0 V Internal Supply Node for Tx2 LO Buffers, Upconverter, and LO Delay. For normal operation, leave

VTX2LO_1P0 unconnected.

H4

H5

Input

AUXADC_3

Input 3 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_3.

Output

VCLKVCO_1P0

1.0 V Internal Supply Node for Clock LO VCO and LO Generation Circuitry. Bypass VCLKVCO_1P0 with

a 4.7 µF capacitor.

H7

Output

Input

VCONV_1P0

VCONV_1P3

VAUXVCO_1P0

1.0 V Internal Supply Node for Receiver ADCs and Transmitter DACs. Bypass VCONV_1P0 with a 4.7

µF capacitor.

H8

1.3 V Internal LDO Input Supply for Receiver ADCs and Transmitter DACs. Provide a 1.0 V supply to

VCONV_1P3 when the internal LDO regulator is not used. VCONV_1P3 is sensitive to supply noise.

H10

Output

1.0 V Internal Supply Node for Auxiliary LO VCO and LO Generation Circuitry. Bypass VAUXVCO_1P0

with a 4.7 µF Capacitor.

H11

H12

Input

AUXADC_0

Input 0 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_0.

Output

VTX1LO_1P0

1.0 V Internal Supply Node for Tx1 LO Buffers, Upconverter, and LO Delay. For normal operation, leave

VTX1LO_1P0 unconnected.

H13

Input

VANA1_1P8

SPI_CLK

1.8 V Supply for Rx1 Mixer, Rx1 TIA, Tx1 LPF, Crystal Oscillator, DEV_CLK Circuitry, and Internal

References.

K1

K2

Serial Data Bus Clock Input.

Input and SPI_DIO

Output

Serial Data Input in 4-Wire Mode or Input and Output in 3-Wire Mode.

K3

K4

K5

Input

RX2_EN

Enable Input for Rx2. If unused, do not connect RX2_EN.

Connect VSSA/TESTCK+ to VSSA for normal operation.

Connect VSSA/TESTCK− to VSSA for normal operation.

VSSA/TESTCK+

VSSA/TESTCK−

K6 to K11, L4 to L6, L9 to L11 Input and DGPIO_xx

Output

Digital GPIO. VDIGIO_1P8 supplies 1.8 V to DGPIO_xx. See Table 18 to match the pin location to the

DGPIO_xx signal name. If unused, do not connect DGPIO_xx.

K12

K13

K14

L1

Input

Output

Input

Output

Input

RX1_EN

RESETB

GP_INT

SPI_EN

SPI_DO

TX2_EN

VDIG_1P0

Enable Input for Rx1. If unused, do not connect RX1_EN.

Active Low Chip Reset.

General-Purpose Digital Interrupt Output Signal. If unused, do not connect GP_INT.

Active Low Serial Data Bus Chip Select.

L2

Serial Data Output. If unused in SPI 3-wire mode, do not connect SPI_DO.

Enable Input for Transmitter Channel 2. If unused, do not connect TX2_EN.

L3

L7, L8

1.0 V Digital Core. Connect Pin L7 and Pin L8 together. Use a wide trace to connect the VDIG_1P0 pins

to a separate power supply domain. Provide reservoir capacitance close to the chip.

L12

L13

Input

TX1_EN

MODE

Enable Input for Transmitter Channel 1. If unused, do not connect TX1_EN.

Joint Test Action Group (JTAG) Boundary Scan Pin. See Table 19 for more information. If unused,

connect MODE to VSSA.

L14

Output

DEV_CLK_OUT

Single-Ended Device Clock Output. DEV_CLK_OUT provides a DEV_CLK signal or the divided version

to the baseband IC. If unused, do not connect DEV_CLK_OUT.

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Data Sheet

ADRV9002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 17. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

M1

Output

RX2_IDATA_OUT−

In LVDS SSI mode, RX2_IDATA_OUT− is the Rx2 I sample data output on the negative side or the Rx2 I

and Q sample data output on the negative side. In CMOS SSI mode, RX2_IDATA_OUT− is the Rx2 Data

Output 0 or the Rx2 I and Q sample data output. If unused, do not connect RX2_IDATA_OUT−.

M2

Output

RX2_IDATA_OUT+

In LVDS SSI mode, RX2_IDATA_OUT+ is the Rx2 I sample data output positive side of the differential

pair or the Rx2 I and Q sample data output positive side of the differential pair. In CMOS SSI mode,

RX2_IDATA_OUT+ is the Rx2 Data Output 1. If unused, do not connect RX2_IDATA_OUT+.

M3

M4

M5

Output

RX2_DCLK_OUT−

RX2_DCLK_OUT+

In LVDS SSI mode, RX2_DCLK_OUT− is the Rx2 data clock output negative side. In CMOS SSI mode,

RX2_DCLK_OUT− is not used. If unused, do not connect RX2_DCLK_OUT−.

In LVDS SSI mode, RX2_DCLK_OUT+ is the Rx2 data clock output positive side. In CMOS SSI mode,

RX2_DCLK_OUT+ is the Rx2 data clock output. If unused, do not connect RX2_DCLK_OUT+.

Input and DGPIO_15/TX2_

Output DCLK_OUT+

Digital GPIO 15. VDIGIO_1P8 supplies 1.8 V to DGPIO_15/TX2_DCLK_OUT+. Alternative function of

DGPIO_15/TX2_DCLK_OUT+ is to provide the positive side of the reference clock output for the Tx2

data port in LVDS SSI mode. If unused, do not connect DGPIO_15/TX2_DCLK_OUT+.

M6

M7

Input and DGPIO_14/TX2_

Digital GPIO 14. VDIGIO_1P8 supplies 1.8 V to DGPIO_14/TX2_DCLK_OUT−. The alternative function

of DGPIO_14/TX2_DCLK_OUT− is to provide the negative side of the reference clock output for the Tx2

data port in LVDS SSI mode. If unused, do not connect DGPIO_14/TX2_DCLK_OUT−.

Output

DCLK_OUT−

VDIGIO_1P8

VDIG_0P9

Input

1.8 V Supply Input for Data Port Interface (CMOS-SSI and LVDS SSI Mode), SPI Signals, Control Input

and Output Signals, and DGPIO Interface.

M8

M9

Output

1.0 V Internal Supply Node for Digital Circuitry. Bypass VDIG_0P9 with a 4.7 µF capacitor.

Input and DGPIO_12/TX1_

Output DCLK_OUT−

Digital GPIO 12. VDIGIO_1P8 supplies 1.8 V to DGPIO_12/TX1_DCLK_OUT−. The alternative function

of DGPIO_12/TX1_DCLK_OUT− is to provide the negative side of the reference clock output for the Tx1

data port in LVDS SSI mode. If unused, do not connect DGPIO_12/TX1_DCLK_OUT−.

M10

Input and DGPIO_13/TX1_

Digital GPIO 13. VDIGIO_1P8 supplies 1.8 V to DGPIO_13/TX1_DCLK_OUT+. The alternative function

of DGPIO_13/TX1_DCLK_OUT+ is to provide the positive side of the reference clock output for the Tx1

data port in LVDS SSI mode. If unused, do not connect DGPIO_13/TX1_DCLK_OUT+.

Output

DCLK_OUT+

M11

M12

M13

M14

RX1_DCLK_OUT+

RX1_DCLK_OUT−

RX1_IDATA_OUT+

RX1_IDATA_OUT−

In LVDS SSI mode, RX1_DCLK_OUT+ is the Rx1 data clock output positive side. In CMOS SSI mode,

RX1_DCLK_OUT+ is the Rx1 data clock output. If unused, do not connect RX1_DCLK_OUT+.

In LVDS SSI mode, RX1_DCLK_OUT− is the Rx1 data clock output negative side. In CMOS SSI mode,

RX1_DCLK_OUT− is not used. If unused, do not connect RX1_DCLK_OUT−.

In LVDS SSI mode, RX1_IDATA_OUT+ is the Rx1 I sample data output positive side or the Rx1 I and Q

sample data output positive side. In CMOS SSI mode, RX1_IDATA_OUT+ is the Rx1 Data Output 1.

In LVDS SSI mode, RX1_IDATA_OUT− is the Rx1 I sample data output negative side or the Rx1 I and Q

sample data output negative side. In CMOS SSI mode, RX1_IDATA_OUT− is the Rx1 Data Output 0 or

the Rx1 I and Q sample data output.

N1

N2

N3

N4

N5

N6

Output

Input

RX2_STROBE_OUT−

RX2_STROBE_OUT+

RX2_QDATA_OUT−

RX2_QDATA_OUT+

TX2_DCLK_IN+

In LVDS SSI mode, RX2_STROBE_OUT− is the Rx2 strobe output negative side. In CMOS SSI mode,

RX2_STROBE_OUT− is not used. If unused, do not connect RX2_STROBE_OUT−.

In LVDS SSI mode, RX2_STROBE_OUT+ is the Rx2 strobe output positive side. In CMOS SSI mode,

RX2_STROBE_OUT+ is the Rx2 strobe output. If unused, do not connect RX2_STROBE_OUT+.

In LVDS SSI mode, RX2_QDATA_OUT− is the Rx2 Q sample data output positive side. In CMOS SSI

mode, RX2_QDATA_OUT− is the Rx2 Data Output 2. If unused, do not connect RX2_QDATA_OUT−.

In LVDS SSI mode, RX2_QDATA_OUT+ is the Rx2 Q sample data output positive side. In CMOS SSI

mode, RX2_QDATA_OUT+ is the Rx2 Data Output 3. If unused, do not connect RX2_QDATA_OUT+.

In LVDS SSI mode, TX2_DCLK_IN+ is the Tx2 data clock input positive side. In CMOS SSI mode,

TX2_DCLK_IN+ is the Tx2 data clock input. If unused, do not connect TX2_DCLK_IN+.

Input

TX2_DCLK_IN−

In LVDS SSI mode, TX2_DCLK_IN− is the Tx2 data clock input negative side. In CMOS SSI mode,

TX2_DCLK_IN− is not used. If unused, do not connect TX2_DCLK_IN−.

N7, N8, P1, P14

N9

Input

VSSD

Digital Supply Voltage (V_SSD).

TX1_DCLK_IN−

In LVDS SSI mode, TX1_DCLK_IN− is the Tx1 data clock input negative side. In CMOS SSI mode,

TX1_DCLK_IN− is not used. If unused, do not connect TX1_DCLK_IN−.

N10

N11

Input

TX1_DCLK_IN+

In LVDS SSI mode, TX1_DCLK_IN+ is the Tx1 data clock input positive side. In CMOS SSI mode,

TX1_DCLK_IN+ is the Tx1data clock input. If unused, do not connect TX1_DCLK_IN+.

Output

RX1_QDATA_OUT+

In LVDS SSI mode, RX1_QDATA_OUT+ is the Rx1 Q sample data output positive side. In CMOS SSI

mode, RX1_QDATA_OUT+ is the Rx1 Data Output 3. If unused, do not connect RX1_QDATA_OUT+.

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Data Sheet

ADRV9002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 17. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

N12

Output

RX1_QDATA_OUT−

In LVDS SSI mode, RX1_QDATA_OUT− is the Rx1 Q sample data output positive side. In CMOS SSI

mode, RX1_QDATA_OUT− is the Rx1 Data Output 2. If unused, do not connect RX1_QDATA_OUT−.

N13

N14

P2

Output

Input

RX1_STROBE_OUT+

RX1_STROBE_OUT−

TX2_STROBE_IN+

In LVDS SSI mode, RX1_STROBE_OUT+ is the Rx1 strobe output positive side. In CMOS SSI mode,

RX1_STROBE_OUT+ is the Rx1 strobe output. If unused, do not connect RX1_STROBE_OUT+.

In LVDS SSI mode, RX1_STROBE_OUT− is the Rx1 strobe output negative side. In CMOS SSI mode,

RX1_STROBE_OUT− is not used. If unused, do not connect RX1_STROBE_OUT−.

In LVDS SSI mode, TX2_STROBE_IN+ is the Tx2 strobe input positive side. In CMOS SSI mode,

TX2_STROBE_IN+ is the Tx2 strobe input. If unused, do not connect TX2_STROBE_IN+.

P3

Input and TX2_STROBE_IN−

Output

In LVDS SSI mode, TX2_STROBE_IN− is the Tx2 strobe input negative side. In CMOS SSI

mode, TX2_STROBE_IN− is the Tx2 reference data clock output. If unused, do not connect

TX2_STROBE_IN−.

P4

P5

P6

Input

TX2_QDATA_IN−

TX2_QDATA_IN+

TX2_IDATA_IN+

In LVDS SSI mode, TX2_QDATA_IN− is the Tx2 Q sample data input negative side. In CMOS SSI mode,

TX2_QDATA_IN− is the Tx2 Data Input 2. If unused, do not connect TX2_QDATA_IN−.

In LVDS SSI mode, TX2_QDATA_IN+ is the Tx2 Q sample data input positive side. In CMOS SSI mode,

TX2_QDATA_IN+ is the Tx2 Data Input 3. If unused, do not connect TX2_QDATA_IN+.

In LVDS SSI mode, TX2_IDATA_IN+ is the Tx2 I sample data input positive side or the Tx2 I and Q

sample data input positive side. In CMOS SSI mode, TX2_IDATA_IN+ is the Tx2 Data Input 1. If unused,

do not connect TX2_IDATA_IN+.

P7

P8

P9

Input

TX2_IDATA_IN−

TX1_IDATA_IN−

TX1_IDATA_IN+

In LVDS SSI mode, TX2_IDATA_IN− is the Tx2 I sample data input negative side or the Tx2 I and Q

sample data input negative side. In CMOS SSI mode, TX2_IDATA_IN− is the Tx2 Data Input 0 or the Tx2

I and Q sample data input. If unused, do not connect TX2_IDATA_IN−.

In LVDS SSI mode, TX1_IDATA_IN− is the Tx1 I sample data input negative side or the Tx1 I and Q

sample data input negative side. In CMOS SSI mode, TX1_IDATA_IN− is the Tx1 Data Input 0 or the Tx1

I and Q sample data input. If unused, do not connect TX1_IDATA_IN−.

In LVDS SSI mode, TX1_IDATA_IN+ is the Tx1 I sample data input positive side or the Tx1 I and Q

sample data input positive side. In CMOS SSI mode, TX1_IDATA_IN+ is the Tx1 Data Input 1. If unused,

do not connect TX1_IDATA_IN+.

P10

P11

P12

Input

TX1_QDATA_IN+

TX1_QDATA_IN−

In LVDS SSI mode, TX1_QDATA_IN+ is the Tx1 Q sample data input positive side. In CMOS SSI mode,

TX1_QDATA_IN+ is the Tx1 Data Input 3. If unused, do not connect TX1_QDATA_IN+.

In LVDS SSI mode, TX1_QDATA_IN− is the Tx1 Q sample data input negative side. In CMOS SSI mode,

TX1_QDATA_IN− is the Tx1 Data Input 2. If unused, do not connect TX1_QDATA_IN−.

Input and TX1_STROBE_IN−

Output

In LVDS SSI mode, TX1_STROBE_IN− is the Tx1 strobe input negative side. In CMOS SSI

mode, TX1_STROBE_IN− is the Tx1 reference data clock output. If unused, do not connect

TX1_STROBE_IN−.

P13

Input

TX1_STROBE_IN+

In LVDS SSI mode, TX1_STROBE_IN+ is the Tx1 strobe input positive side. In CMOS SSI mode,

TX1_STROBE_IN+ is the Tx1 strobe input. If unused, do not connect TX1_STROBE_IN+.

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

The ADRV9002 supports a signal bandwidth from 12 kHz to 40 MHz. The bandwidth of 1 MHz is the boundary to distinguish between

narrow-band and wideband profiles. If the signal bandwidth is less than 1 MHz, it is considered a narrow-band profile. Otherwise, it is

considered a wideband profile. The performance of the ADRV9002 is measured for both wideband and narrow-band profiles.

WIDEBAND

Device configuration profile: receiver = 40 MHz bandwidth, I/Q rate = 61.44 MHz, transmitter = 40 MHz bandwidth, I/Q rate = 61.44 MHz, device

clock = 38.4 MHz, and an internal LO is used for all measurements. Measurements are at nominal power supply voltages. All RF specifications

are based on measurements that include PCB and matching circuit losses, unless otherwise noted. Specifications are applicable over the

lifetime of the device.

50 MHz LO

The temperature settings refer to the die temperature. All LO frequencies are set to 50 MHz, unless otherwise noted.

Figure 4. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 5.6 MHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 6. Receiver Noise Figure vs. Gain Index, Baseband Frequency =

5.6 MHz, ADC = High Performance

Figure 5. Receiver Absolute Gain (Complex) vs. LO Frequency, Baseband

Frequency = 5.6 MHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 7. Receiver Noise Figure vs. LO Frequency, Baseband Frequency =

5.6 MHz, ADC = High Performance

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. Receiver Noise Figure vs. Gain Index, Baseband Frequency =

5.6 MHz, ADC = Low Power

Figure 11. Receiver Image Rejection vs. LO Frequency, Baseband Frequency

= 5.6 MHz, ADC = Low Power, Initialization Calibration and Hardware

Tracking Calibration Only

Figure 9. Receiver Noise Figure vs. LO Frequency, Baseband Frequency =

5.6 MHz, ADC = Low Power

Figure 12. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 10. Receiver Image Rejection vs. LO Frequency, Baseband Frequency

= 5.6 MHz, ADC = High Performance, Initialization Calibration and Hardware

Tracking Calibration Only

Figure 13. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 14. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 17. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 15. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 18. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 16. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 19. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 20. Receiver DC Offset vs. Gain Index, Baseband Frequency = 5.6

MHz, ADC = High Performance

Figure 23. Receiver Input IP2 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

Figure 21. Receiver Input IP3 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

Figure 24. Receiver Input IP2 vs. Baseband Frequency, ADC = Low Power, F1

= Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index = 255

Figure 22. Receiver Input IP3 vs. Baseband Frequency, ADC = Low Power, F1

= Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index = 255

Figure 25. Receiver and Transmitter Return Loss vs. Frequency (For LO = 30

MHz to 3 GHz)

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 26. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 29. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code =

20

Figure 27. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 30. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

Figure 28. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code = 0

Figure 31. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 32. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 35. Transmitter Third-Order Intermodulation Distortion (IMD3) vs.

Baseband Frequency, Transmitter Attenuation Code = 0, F1 = Baseband

Frequency, F2 = Baseband Frequency + 1 MHz

Figure 33. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 6 dBFS, Initialization Calibration

Only

Figure 36. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 5.6 MHz, Transmitter Channel = Ch1

Figure 34. Transmitter Second-Order Intermodulation Distortion (IMD2) vs.

Baseband Frequency, Transmitter Attenuation Code = 0, F1 = Baseband

Frequency, F2 = Baseband Frequency + 1 MHz

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

470 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 470 MHz, unless otherwise noted.

Figure 40. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 37. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 5.6 MHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 41. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 38. Receiver Noise Figure vs. Gain Index, Baseband Frequency =

5.6 MHz, ADC = High Performance

Figure 42. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 39. Receiver Noise Figure vs. Gain Index, Baseband Frequency =

5.6 MHz, ADC = Low Power

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 43. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 46. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 44. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 47. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 48. Receiver DC Offset vs. Gain Index, Baseband Frequency = 5.6

MHz, ADC = High Performance

Figure 45. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 49. Receiver Input IP3 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

Figure 52. Receiver Input IP2 vs. Baseband Frequency, ADC = Low Power, F1

= Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index = 255

Figure 53. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 50. Receiver Input IP3 vs. Baseband Frequency, ADC = Low Power, F1

= Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index = 255

Figure 54. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 51. Receiver Input IP2 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 55. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code = 0

Figure 58. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 56. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code =

20

Figure 59. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 60. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 6 dBFS, Initialization Calibration

Only

Figure 57. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 61. Transmitter IMD2 vs. Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

Figure 63. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 5.6 MHz, Transmitter Channel = Ch1

Figure 62. Transmitter IMD3 vs. Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

900 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 900 MHz, unless otherwise noted.

Figure 67. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 64. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 5.6 MHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 68. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 65. Receiver Noise Figure vs. Gain Index, Baseband Frequency =

5.6 MHz, ADC = High Performance

Figure 69. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 66. Receiver Noise Figure vs. Gain Index, Baseband Frequency =

5.6 MHz, ADC = Low Power

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 73. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 70. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 71. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 74. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 75. Receiver DC Offset vs. Gain Index, Baseband Frequency = 5.6

MHz, ADC = High Performance

Figure 72. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 76. Receiver Input IP3 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

Figure 79. Receiver Input IP2 vs. Baseband Frequency, ADC = Low Power, F1

= Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index = 255

Figure 80. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 77. Receiver Input IP3 vs. Baseband Frequency, ADC = Low Power, F1

= Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index = 255

Figure 81. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 78. Receiver Input IP2 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 82. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code = 0

Figure 85. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 83. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code =

20

Figure 86. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 87. Transmitter LO Leakage Power vs. Attenuation Code, Baseband

Frequency = 18 MHz, Backoff = 6 dBFS, Initialization Calibration Only

Figure 84. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 88. Transmitter IMD2 vs. Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

Figure 90. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 5.6 MHz, Transmitter Channel = Ch1

Figure 89. Transmitter IMD3 vs. Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

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TYPICAL PERFORMANCE CHARACTERISTICS

2400 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 2400 MHz, unless otherwise noted.

Figure 91. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 5.6 MHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 94. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 92. Receiver Noise Figure vs. Gain Index, Baseband Frequency =

5.6 MHz, ADC = High Performance

Figure 95. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 93. Receiver Noise Figure vs. Gain Index, Baseband Frequency =

5.6 MHz, ADC = Low Power

Figure 96. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

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Figure 97. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 100. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 98. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 101. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 99. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 102. Receiver DC Offset vs. Gain Index, Baseband Frequency =

5.6 MHz, ADC = High Performance

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Figure 103. Receiver Input IP3 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

Figure 106. Receiver Input IP2 vs. Baseband Frequency, ADC = Low Power,

F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index =

255

Figure 104. Receiver Input IP3 vs. Baseband Frequency, ADC = Low Power,

F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index =

255

Figure 107. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 108. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 105. Receiver Input IP2 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

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Figure 109. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code = 0

Figure 112. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 110. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code =

20

Figure 113. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 114. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 6 dBFS, Initialization Calibration

Only

Figure 111. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

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Figure 115. Transmitter IMD2 vs. Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

Figure 117. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 5.6 MHz, Transmitter Channel = Ch1

Figure 116. Transmitter IMD3 vs Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

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TYPICAL PERFORMANCE CHARACTERISTICS

3500 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 3500 MHz, unless otherwise noted.

Figure 118. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 5.6 MHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 121. Receiver Noise Figure vs. LO Frequency, Baseband Frequency =

5.6 MHz, ADC = High Performance

Figure 119. Receiver Absolute Gain (Complex) vs. LO Frequency, Baseband

Frequency = 5.6 MHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 122. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 5.6

MHz, ADC = Low Power

Figure 120. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 5.6

MHz, ADC = High Performance

Figure 123. Receiver Noise Figure vs. LO Frequency, Baseband Frequency =

5.6 MHz, ADC = Low Power

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 124. Receiver Image Rejection vs. LO Frequency, Baseband

Frequency = 5.6 MHz, ADC = High Performance, Initialization Calibration

and Hardware Tracking Calibration Only

Figure 127. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 128. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 125. Receiver Image Rejection vs. LO Frequency, Baseband

Frequency = 5.6 MHz, ADC = Low Power, Initialization Calibration and

Hardware Tracking Calibration Only

Figure 129. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 126. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

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Figure 130. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 133. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain index = 255, ADC = Low Power

Figure 131. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 134. Receiver DC Offset vs. Gain Index, Baseband Frequency = 5.6

MHz, ADC = High Performance

Figure 132. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 135. Receiver Input IP3 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

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Figure 136. Receiver Input IP3 vs. Baseband Frequency, ADC = Low Power,

F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index =

255

Figure 139. Receiver and Transmitter Return Loss vs. Frequency (For LO = 3

GHz to 6 GHz)

Figure 140. Transmitter Absolute Power vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 137. Receiver Input IP2 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

Figure 141. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 138. Receiver Input IP2 vs. Baseband Frequency, ADC = Low Power,

F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index =

255

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Figure 142. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code = 0

Figure 145. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 143. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code =

20

Figure 146. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 147. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 6 dBFS, Initialization Calibration

Only

Figure 144. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 148. Transmitter IMD2 vs. Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

Figure 150. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 5.6 MHz, Transmitter Channel = Ch1

Figure 149. Transmitter IMD3 vs. Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

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TYPICAL PERFORMANCE CHARACTERISTICS

5800 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 5800 MHz, unless otherwise noted.

Figure 151. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 5.6 MHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 154. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 152. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 5.6

MHz, ADC = High Performance

Figure 155. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 153. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 5.6

MHz, ADC = Low Power

Figure 156. Receiver Second-Order Harmonic Distortion vs. Gain

Index, Baseband Frequency = 5.6 MHz, ADC = Low Power

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 157. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 160. Receiver Third-Order Harmonic Distortion vs. Gain

Index, Baseband Frequency = 5.6 MHz, ADC = Low Power

Figure 158. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 5.6 MHz, ADC = High Performance

Figure 161. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain index = 255, ADC = Low Power

Figure 159. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 162. Receiver DC Offset vs. Gain Index, Baseband Frequency = 5.6

MHz, ADC = High Performance

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Figure 163. Receiver Input IP3 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

Figure 166. Receiver Input IP2 vs. Baseband Frequency, ADC = Low Power,

F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index =

255

Figure 164. Receiver Input IP3 vs. Baseband Frequency, ADC = Low Power,

F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz, Gain Index =

255

Figure 167. Transmitter Absolute Power vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 168. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 165. Receiver Input IP2 vs. Baseband Frequency, ADC = High

Performance, F1 = Baseband Frequency, F2 = Baseband Frequency + 1 MHz,

Gain Index = 255

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 169. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code = 0

Figure 172. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 170. Transmitter Image Rejection vs. Baseband Frequency, Tracking

Calibration On vs. Tracking Calibration Off, Transmitter Attenuation Code =

20

Figure 173. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS

Figure 174. Transmitter LO Leakage Power vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 6 dBFS, Initialization

Calibration Only

Figure 171. Transmitter Image Rejection vs. Transmitter Attenuation

Code, Baseband Frequency = 18 MHz, Backoff = 0.2 dBFS, Initialization

Calibration Only

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Figure 175. Transmitter IMD2 vs. Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

Figure 177. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 5.6 MHz, Transmitter Channel = Ch1

Figure 176. Transmitter IMD3 vs. Baseband Frequency, Transmitter

Attenuation Code = 0, F1 = Baseband Frequency, F2 = Baseband Frequency

+ 1 MHz

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ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

NARROW-BAND

Device configuration profile: receiver = 25 kHz bandwidth, receiver IF = 490 kHz, I/Q rate = 144 kHz, transmitter = 25 kHz bandwidth, I/Q rate

= 144 kHz, device clock = 38.4 MHz, and an internal LO is used for all measurements. Measurements are at nominal power supply voltages.

All RF specifications are based on measurements that include PCB and matching circuit losses, unless otherwise noted. Specifications are

applicable over the lifetime of the device.

30 MHz LO

The temperature settings refer to the die temperature. All LO frequencies are set to 30 MHz, unless otherwise noted.

Figure 178. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 2.1 kHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 180. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = Low Power

Figure 179. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

Figure 181. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

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Figure 182. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 185. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 183. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

Figure 186. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 184. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 187. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

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Figure 188. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 191. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 189. Receiver DC Offset vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

Figure 192. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 190. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 193. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS,

Initialization Calibration Only

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Figure 194. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 196. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 2.1 kHz, Transmitter Channel = Ch1

Figure 195. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 6 dBFS, Initialization Calibration

Only

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TYPICAL PERFORMANCE CHARACTERISTICS

470 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 470 MHz, unless otherwise noted.

Figure 197. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 2.1 kHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 200. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 198. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

Figure 201. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 199. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = Low Power

Figure 202. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power>

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Figure 203. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 206. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

Figure 204. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 207. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 205. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 208. Receiver DC Offset vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

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Figure 209. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 211. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

Figure 210. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 212. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

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Figure 213. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 215. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 2.1 kHz, Transmitter Channel = Ch1

Figure 214. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 6 dBFS, Initialization Calibration

Only

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TYPICAL PERFORMANCE CHARACTERISTICS

900 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 900 MHz, unless otherwise noted.

Figure 216. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 2.1 kHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 219. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 217. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

Figure 220. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 218. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = Low Power

Figure 221. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

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ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 222. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 225. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

Figure 223. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 226. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 224. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 227. Receiver DC Offset vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 228. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 230. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

Figure 229. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 231. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 232. Transmitter HD2 vs. Transmitter Attenuation Code, Baseband

Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 234. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 2.1 kHz, Transmitter Channel = Ch1

Figure 233. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 6 dBFS, Initialization Calibration

Only

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

2400 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 2400 MHz, unless otherwise noted.

Figure 235. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 2.1 kHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 238. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 236. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

Figure 239. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 237. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = Low Power

Figure 240. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 241. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 244. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

Figure 242. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 245. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 243. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 246. Receiver DC Offset vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 247. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 249. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

Figure 248. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 250. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 251. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 253. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 2.1 kHz, Transmitter Channel = Ch1

Figure 252. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 6 dBFS, Initialization Calibration

Only

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

3500 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 3500 MHz, unless otherwise noted.

Figure 254. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 2.1 kHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 257. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 255. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

Figure 258. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 256. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = Low Power

Figure 259. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 260. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 263. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

Figure 261. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 264. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 262. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 265. Receiver DC Offset vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 266. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 268. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

Figure 267. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 269. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 270. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 272. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 2.1 kHz, Transmitter Channel = Ch1

Figure 271. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 6 dBFS, Initialization Calibration

Only

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

5800 MHz LO

The temperature settings refer to the die temperature. All LO frequencies set to 5800 MHz, unless otherwise noted.

Figure 273. Receiver Absolute Gain (Complex) vs. Gain Index, Baseband

Frequency = 2.1 kHz, ADC = High Performance, P_OUT= −9.6 dBFS

Figure 276. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 274. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

Figure 277. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 275. Receiver Noise Figure vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = Low Power

Figure 278. Receiver Second-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 279. Receiver Second-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 282. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = Low Power

Figure 280. Receiver Third-Order Harmonic Distortion vs. Gain Index,

Baseband Frequency = 2.1 kHz, ADC = High Performance

Figure 283. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = Low Power

Figure 281. Receiver Third-Order Harmonic Distortion vs. Baseband

Frequency, Gain Index = 255, ADC = High Performance

Figure 284. Receiver DC Offset vs. Gain Index, Baseband Frequency = 2.1

kHz, ADC = High Performance

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 285. Transmitter Absolute Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 287. Transmitter Image Rejection vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS, Initialization Calibration

Only

Figure 286. Transmitter Attenuation Delta (Error) vs. Transmitter Attenuation

Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 288. Transmitter Third-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 289. Transmitter Second-Order Harmonic Distortion vs. Transmitter

Attenuation Code, Baseband Frequency = 2.1 kHz, Backoff = 0.2 dBFS

Figure 291. Transmitter NSD vs. Frequency Offset from LO, Baseband

Frequency = 2.1 kHz, Transmitter Channel = Ch1

Figure 290. Transmitter LO Leakage Power vs. Transmitter Attenuation Code,

Baseband Frequency = 2.1 kHz, Backoff = 6 dBFS, Initialization Calibration

Only

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

PHASE NOISE

PLL bandwidth = 300 kHz. DEV_CLK = 38.4 MHz. Narrow-band or wideband profile with IQ mode. A high performance, low noise, Wenzel type

oscillator is used as a reference clock.

Figure 292. Internal Local Oscillator Phase Noise at 30 MHz LO

Figure 293. Internal Local Oscillator Phase Noise at 470 MHz LO

Figure 294. Internal Local Oscillator Phase Noise at 900 MHz LO

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Data Sheet

ADRV9002

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 295. Internal Local Oscillator Phase Noise at 2400 MHz LO

Figure 296. Internal Local Oscillator Phase Noise at 3500 MHz LO

Figure 297. Internal Local Oscillator Phase Noise at 5800 MHz LO

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Data Sheet

ADRV9002

THEORY OF OPERATION

The ADRV9002 is a highly integrated RF transceiver that can be

configured for a wide range of applications. The device integrates

all RF, mixed-signal, and digital blocks necessary to provide trans-

mit and receive functions in a single device. Programmability allows

the two receiver channels and two transmitter channels to be used

in TDD and FDD systems for mobile radio and cellular standards.

that provide all digital processing, mixed signals, PLLs, and RF

blocks necessary to implement a direct conversion system. Refer to

Figure 298 for the transmitter data path overview.

The ADRV9002 has an optional, fully programmable, 128-tap FIR.

The FIR output is sent to a series of interpolation filters that provide

additional filtering and data rate interpolation prior to reaching the

DAC. Each DAC has an adjustable sample rate and is linear up to

full scale.

The ADRV9002 contains serial interface links that consist of LVDS

and a CMOS synchronous serial interface (CSSI). Both receiver

and transmitter channels provide a low pin count and reliable

data interface to a field-programmable gate array (FPGA) or other

integrated baseband solutions.

The DAC output produces baseband analog signals. The I and

Q signals are first filtered to remove sampling artifacts and then

fed to the upconversion mixers. At the mixer stage, the I and Q

signals are recombined and modulated onto the carrier frequency

for transmission to the output stage. Each transmit chain provides

a wide attenuation adjustment range with fine granularity to help

designers optimize the signal-to-noise ratio (SNR).

The ADRV9002 provides self calibration for dc offset, LO leakage,

and QEC using an integrated microcontroller core to maintain a

high performance level under varying temperatures and input signal

conditions. Firmware is supplied with the device to schedule all

calibrations with no user interaction.

TRANSMITTER

The ADRV9002 uses a direct conversion transmitter architecture

that consists of two identical and independently controlled channels

Figure 298. Transmitter Architecture

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Data Sheet

THEORY OF OPERATION

RECEIVER

ADRV9002

The receiver includes two ADC pairs. One pair consists of high per-

formance Σ-Δ ADCs to provide maximum interferer tolerance, and

the second pair consists of ADCs for significant power reduction.

The extra pair of ADCs allow a smart trade-off between power and

performance.

Figure 299 shows a simplified block diagram of the ADRV9002

receiver. It is a fully integrated, direct conversion, low IF receiver

signal chain. The receiver subsystem consists of a resistive input

network for gain control followed by a current mode passive mixer.

The output current of the mixer is converted to a voltage by a

transimpedance amplifier and then digitized. There are two sets of

ADCs, a high performance Σ-Δ ADC and a low power ADC. The

digital baseband that provides the required filtering and decimation

follows these ADCs.

The ADC output can be conditioned further by a series of deci-

mation filters and a fully programmable, 128-tap FIR filter with

additional decimation settings. The sample rate of each digital filter

block automatically adjusts with each change of the decimation

factors to produce the desired output data rate.

For standards that demand low phase noise performance, the

ADRV9002 can operate in low IF mode. The ADRV9002 can re-

ceive signals offset from the carrier, as with an IF downconversion

scheme. A digital NCO and mixer that follow the analog receive

path can downconvert the IF signal to baseband. Downconverting

the signal to baseband allows a lower sample rate on the data bus.

The ADRV9002 makes no assumptions about high-side or low-side

injection.

There are two RF inputs for each receiver to match different

bands in one reference design. The mixer architecture is linear and

inherently wideband, which facilitates impedance matching. The

differential input impedance of the receiver inputs is 100 Ω.

To achieve gain control, a programmed gain index map is imple-

mented. This gain map distributes attenuation among the various

receiver blocks for optimal performance at each power level. The

gain range is 34 dB. Additional support is available for both auto-

matic and manual gain control modes.

Monitor Mode

The receive LPFs can be reconfigured to help provide antialias

filtering and improve out of band blockers. The ADRV9002 is a

wideband architecture transceiver that relies on the ADC high

dynamic range to receive signals and interference at the same

time. Filtering provided by the receive LPF attenuates ADC alias

images. The receive LPF characteristic is flat and not intended to

provide rejection of close in blockers. The baseband filter supports

a baseband bandwidth from 5 MHz to 50 MHz.

The ADRV9002 receiver signal chain can be configured to monitor

the radio channel signal level in duty cycle detection and sleep

fashion. Monitor mode allows the digital baseband processor to

power down until the ADRV9002 detects a signal. Monitor mode

provides overall system power saving. The timing of detection and

sleep mode is fully programmable. Alternatively, the ADRV9002

can be under full control of the baseband processor during monitor

mode.

Figure 299. Receiver Architecture

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Data Sheet

THEORY OF OPERATION

DPD

ADRV9002

For optimal performance, drive the reference clock differentially via

an external source or from an external crystal. If a differential input

clock is provided, the clock signal must be ac-coupled with the input

range limited from 10 MHz to 1 GHz. The ADRV9002 can also

accept an external crystal (XTAL) as a clock source. The frequency

range of the supported crystal is between 20 MHz to 80 MHz. The

external crystal connection must be dc-coupled.

The ADRV9002 provides a fully integrated DPD function that alters

the digital waveform to compensate for nonlinearities in the power

amplifier response, which linearizes the output of the power amplifi-

er of the transmit system. The internal DPD block is optimized for

both narrow-band and wideband signals. The DPD actuator and

coefficient calculation engine are both integrated. This functionality

uses the receive channel to monitor the output of the power am-

plifier and calculates the appropriate predistortion to linearize the

output. The integrated DPD capability allows the system to drive

the power amplifier closer to saturation, enabling a higher efficiency

power amplifier while maintaining linearity.

If a differential clock is not available, a single-ended, ac-cou-

pled, 1 V p-p (maximum) CMOS signal can be applied to the

DEV_CLK_IN+ pin with the DEV_CLK_IN− pin unconnected. The

maximum clock frequency in this mode is limited to 80 MHz.

SYNTHESIZERS

Receiver as an Observation Receiver

The ADRV9002 offers two distinct PLL paths, an RF PLL for the

high frequency RF path and a baseband PLL for the digital and

sampling clocks of the data converters.

In FDD type applications where only one receiver is used or in

the TDD type applications during transmitter time slots, unused

receiver inputs can be used to perform transmitter observation.

The observation receiver operates in a similar manner to the main

receivers.

RF PLL

The PLL structure in the ADRV9002 is unique in the sense that

instead of having one dedicated PLL for the receive data path and

a dedicated PLL for the transmit data path, two RF PLLs are in the

device and both PLLs can source the receiver, the transmitter, both

paths, or neither. This flexibility enables the ADRV9002 to meet

various applications that require versatility.

Use the observation receiver channel to perform the following:

► Monitor the transmitter channels and implement transmitter local

oscillator leakage (LOL) correction and transmitter QEC.

► Monitor signal levels after the power amplifier output. This data

can be used by a fully integrated low power DPD block. The

integrated DPD is optimized for both narrow-band and wideband

signals and enables linearization of high efficiency power amplifi-

ers.

The RF PLL supports the use of both internal and external LO

signals. The internal LO is generated by an on-chip VCO, which is

tunable over a frequency range of 6.5 GHz to 13 GHz. The output

of the VCO is phase-locked to an external reference clock through

a fractional-N PLL that is programmable through the API command.

The VCO outputs are steered through a combination of frequency

dividers to produce in-phase and quadrature phase LO signals in

the 30 MHz to 6 GHz frequency range.

► Monitor signal levels after the power amplifier output for further

data processing in the external baseband processor.

In cases where the observation receiver path is used for DPD oper-

ation, there is a limit to the maximum bandwidth of the transmitter

signal the DPD can support. For example, if the DPD observation

factor is 5×, the transmitter signal bandwidth is limited to 1/5 of the

DPD observation bandwidth. When using the ADRV9002 internal

DPD block, the largest transmitter bandwidth that the internal DPD

can support is 20 MHz because of the largest internal DPD obser-

vation bandwidth of 100 MHz. When external DPD is used, the

largest DPD observation bandwidth is limited by the transmitter and

observation receiver RF bandwidth. 40 MHz is the largest RF band-

width that can be received and sent over the digital data port to

the baseband processor, which implies that 8 MHz represents the

largest transmitter bandwidth that the DPD implemented externally

to the ADRV9002 can support.

Alternatively, an external LO signal can be applied to the external

LO inputs of the ADRV9002 to generate the LO signals in quadra-

ture for the RF path. If the external LO path is chosen, the input

frequency range is between 60 MHz and 12 GHz.

PLL synthesizers are fractional-N designs that incorporate com-

pletely integrated VCOs and loop filters. In TDD mode, LO distri-

bution paths and receive and transmit data paths turn on and

off as appropriate for the receive and transmit frames. In FDD

mode, the transmit PLL and the receive PLL can be activated

simultaneously. These PLLs require no external components. The

RF LO generation circuits offer a trade-off between performance

and power consumption.

CLOCK INPUT

The reference clock inputs provide a low frequency clock from

which all internal ADRV9002 clocks are derived. The ADRV9002

offers multiple reference input clocking options. The reference input

clock pins on the device are labeled DEV_CLK_IN±.

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Data Sheet

ADRV9002

THEORY OF OPERATION

GPIO PINS

Digital General-Purpose Inputs/Outputs

(DGPIOs)

The ADRV9002 GPIO signals referenced to the VDIGIO_1P8

supply are intended to interface with digital circuitry and can be

configured for numerous functions. Some of these pins, when

configured as outputs, are used by the baseband processor as

real-time signals to provide a number of internal settings and

measurements. This configuration allows the baseband processor

to monitor receiver performance in different situations. Signals used

for manual gain mode, calibration flags, state machine states, and

various receiver parameters are among the outputs that can be

monitored on these pins. In addition, certain pins can be configured

as inputs and used in various functions, such as setting the receiver

gain or transmitter attenuation in real time.

Figure 300. RF LO

The ADRV9002 supports various forms of fast frequency hopping

(FFH) with the frequency dwell time and transition time as the main

distinguishing factors between these forms. The RF PLL phase

noise and the QEC and LOL algorithm performance degrade as

a function of decreasing frequency transition times. FFH mode sup-

ports hop frequencies that are preloaded at power-up or streamed

by the user onto the ADRV9002. Hopping between the frequencies

in FFH mode can be triggered by toggling a GPIO pin or executing

an API command.

Analog General-Purpose Inputs/Outputs

(AGPIOs)

The AGPIO pins are intended to interface with system blocks

that perform analog functions. The AGPIO pins referenced to

the VAGPIO_1P8 supply provide control signals to the external

components, such as the low noise amplifier (LNA) or digital step

attenuator (DSA). The selected AGPIO pins provide an alternate

auxiliary DAC functionality. See Table 18 for more details on pin

mapping.

Baseband PLL

The ADRV9002 contains a baseband PLL synthesizer that gen-

erates all baseband and data port related clocks. Two options

are provided for a high performance baseband PLL and a low

power baseband PLL. A high performance baseband PLL offers

greater flexibility in generating clocks to support a wider range

of sample rates. A low power baseband PLL has a limitation in

supporting certain sample rates but consumes less power. Both

high performance and low power baseband PLLs are automatically

programmed based on the data rate and sample rate requirements

of the system.

AUXILIARY CONVERTERS

Auxiliary ADC Inputs (AUXADC_x)

The ADRV9002 contains four auxiliary ADCs with the correspond-

ing inputs connected to four dedicated input pins (AUXADC_x).

This block can monitor system voltages without additional compo-

nents. The auxiliary ADC is 10 bits with an input voltage range of

0.05 V to 0.95 V. When enabled, the auxiliary ADC is free running.

An API function allows the user to read back the last value latched

by the ADC.

SPI

The ADRV9002 uses an SPI to communicate with the baseband

processor. This interface can be configured either as a 4-wire

interface with dedicated receive and transmit ports, or as a 3-wire

interface with a bidirectional data communications port. This bus

allows the baseband processor to set all device control parameters

using a simple address data serial bus protocol.

Auxiliary DACs Outputs (AUXDAC_x)

The ADRV9002 contains four identical auxiliary DACs (AUXDAC_x)

that can supply bias voltages, analog control voltages, or other sys-

tem functionality. The auxiliary DACs (AUXDAC_0 to AUXDAC_3)

are multiplexed with the AGPIO_xx pins, as shown in Table 18. The

auxiliary DACs are 12 bits and have an output voltage range of

approximately 0.05 V to VDDA_1P8 − 0.05 V and have a current

drive of 10 mA. The auxiliary DACs generate ramp up and ramp

down patterns that can be loaded into the ADRV9002 and then

triggered based on state of dedicated DGPIO pin.

Write commands follow a 24-bit format. The first bit sets the bus

direction of the bus transfer. The next 15 bits set the address where

the data is written. The final eight bits contain the data transferred

to the specific register address. Read commands follow a similar

format with the exception that the first 16 bits are transferred on the

SPI_DIO pin and the final eight bits are read from the ADRV9002

either on the SPI_DO pin in 4-wire mode or on the SPI_DIO pin in

3-wire mode.

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Data Sheet

ADRV9002

THEORY OF OPERATION

test access port. To enable the JTAG functionality, set the DGPIO_8

JTAG BOUNDARY SCAN

pin through DGPIO_11 pin and the MODE pin, as shown in Table

19.

The ADRV9002 provides support for a JTAG boundary scan. There

are five dual function pins associated with the JTAG interface.

These pins, as shown in Table 19, are used to access the on-chip

Table 18. Pin Number to AGPIO_xx Mapping and AUXDAC_x

Pin Number

Primary Function

Alternate Function

E12

F10

E3

AGPIO_0

AGPIO_1

AGPIO_2

AGPIO_3

AGPIO_4

AGPIO_5

AGPIO_6

AGPIO_7

AGPIO_8

AGPIO_9

AGPIO_10

AGPIO_11

AUXDAC_0

AUXDAC_1

AUXDAC_2

F5

AUXDAC_3

F4

Not applicable

G4

G6

H6

G9

H9

F11

G11

Table 19. Pin Number to DGPIO_xx Mapping and JTAG Function

Pin Number

Primary Function

JTAG Function, Boundary Scan CMOS Mode

JTAG Function, Boundary Scan LVDS Mode

K6

DGPIO_0

Not applicable

TDO

Not applicable

TDO

K7

DGPIO_1

K8

DGPIO_2

K9

DGPIO_3

K10

K11

L4

DGPIO_4

TRST

DGPIO_5

TDI

DGPIO_6

TMS

L5

DGPIO_7

TCLK

L6

DGPIO_8

User sets to 0

Not applicable

User sets to 1

User sets to 0

Not applicable

User sets to 1

L9

DGPIO_9

L10

L11

M9

M10

M6

M5

L13

DGPIO_10

DGPIO_11

DGPIO_12/TX1_DCLK_OUT−

DGPIO_13/TX1_DCLK_OUT+

DGPIO_14/TX2_DCLK_OUT−

DGPIO_15/TX2_DCLK_OUT+

MODE Pin

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Data Sheet

ADRV9002

APPLICATIONS INFORMATION

lane requirement as described for the CSSI in 1-lane mode and the

CSSI in 4-lane mode, which allows a total of three signal lanes for

the CSSI in 1-lane data mode and six total signal lanes for the CSSI

in 4-lane data mode.

POWER SUPPLY SEQUENCE

The ADRV9002 requires a specific power-up sequence to avoid

undesired power-up currents. The optimal power-on sequence re-

quires VDD_1P0 to power up first. The VDDA_1P3 and VDDA_1P8

supplies must then power up after the VDD_1P0 supply. If

VDDA_1P0 is used, VDDA_1P0 must be powered up after

VDDA_1P3 and VDDA_1P8 are enabled.

RXx_DCLK_OUT is an output clock signal that synchronizes the

data and strobe output signals. RXx_STROBE_OUT is a strobe

output signal that indicates the first bit of the serial data stream.

The RXx_STROBE_OUT signal can be configured to indicate

the start of the I and Q samples. For a 16-bit data sample, the

RXx_STROBE_OUT signal is high for one clock cycle and low for

31 clock cycles. Alternatively, the RXx_STROBE_OUT signal can

be configured to be high for I data duration and low for Q data dura-

tion. In this case, for a 16-bit data sample, the RXx_STROBE_OUT

signal is high for 16 clock cycles (I data) and low for 16 clock cycles

(Q data).

The user must toggle the RESET signal after power has stabilized

prior to configuration.

DIGITAL DATA INTERFACE

The ADRV9002 data interface supports both CMOS and LVDS

electrical interfaces. The CSSI is intended for narrow RF signal

bandwidths, and the LVDS synchronous serial interface (LSSI) can

support the full RF bandwidth of the ADRV9002. Table 20 provides

a high level overview. For more details, refer to the ADRV9001

system development user guide.

CSSI Transmit

For the transmit CMOS configuration, three additional signal lanes

are required for the strobe, clock input, and clock output in addition

to the data lane requirement as described for the CSSI in 1-lane

data mode and the CSSI in 4-lane data mode, which allows a total

of four signal lanes for the CSSI in 1-lane data mode and seven

total signal lanes for the CSSI in 4-lane data mode.

All signal lanes support both electrical interfaces, but concurrent

operation of both interfaces is not supported. Additionally, each

receive and transmit channel has a dedicated set of lanes for

transferring information. The receive and transmit channels cannot

be reconfigured to an alternative ball configuration that is different

from how it has been assigned by design.

TXx_DCLK_IN is an input clock to the ADRV9002 that syn-

chronizes to the data inputs (TXx_DATA_IN) and strobe inputs

(TXx_STROBE_IN). TXx_STROBE_IN is an input signal that in-

dicates the first bit of the serial data sample. Similar to the

receive path, the transmit strobe has two configuration options.

The TXx_DCLK_OUT is an output clock from the ADRV9002

to the external baseband device to generate the TXx_DCLK_IN,

TXx_STROBE_IN, and TXx_DATA_IN signals.

CSSI

The CSSI supports two modes of operation, 1-lane serialized data

or 4-lane data. In either case, the maximum clock frequency sup-

ported by the CMOS configuration is 80 MHz.

For the CSSI in 1-lane data mode, 16 bits of I data and 16 bits of Q

data (a total of 32 data bits) are serialized on a single lane. Figure

301 shows a graphical overview of the CSSI in 1-lane data mode.

LSSI

For the CSSI in 4-lane data mode, the I and Q digital data is spread

across four data lanes. The 16 bits of I data and 16 bits of Q

data are split into 8 bits and sent over one of four data lanes. For

example, Lane 0 would have 8 LSB bits of I data, Lane 1 would

have 8 MSB bits of I data, Lane 2 would have 8 LSB bits of Q data,

and Lane 3 would have 8 MSB bits of Q data.

The LSSI supports the higher RF channel bandwidths and requires

differential signal pairs. In LSSI mode, there are two data transfer

formats, 1-lane data mode, where both the I and Q data are

serialized on a single differential pair, or 2-lane data mode, where

the I and Q data occupy separate differential pairs. The selection

of either 1-lane data mode or 2-lane data mode depends on the

RF channel bandwidth. To capture the maximum 40 MHz RF

bandwidth of the ADRV9002, select the LSSI in 2-lane data mode.

In either case, the maximum clock frequency supported by the LSSI

configuration is 491.52 MHz and the clock type is DDR. Refer to

Figure 303 for more details.

The CSSI in 4-lane data mode supports both a full rate clock and a

double data rate (DDR) clock. The DDR clock mode allows data to

be latched on both the rising and falling edges, which enables twice

the available RF bandwidth, as shown in Figure 302.

CSSI Receive

In the receive CMOS configuration, two additional signal lanes are

required for the strobe and clock signals in addition to the data

analog.com

Rev. 0 | 89 of 92

Data Sheet

ADRV9002

APPLICATIONS INFORMATION

Table 20. ADRV9002 Data Port Interface Modes

Maximum Data

Lane Rate

(MHz)

Maximum

Clock Rate

(MHz)

Data Lanes per

Channel

Serialization Factor

per Data Lane

Maximum RF

Bandwidth (MHz)

Sample Rate for I

and Q Data (MHz)

Data

Figure

Reference

Interface Mode

Type¹

CSSI in 1-Lane

Data

1

4

1

2

32

80

1.25

2.5

5

2.5

Normal

Figure 301

CSSI in 1-Lane

Data

32

8

160

80

5

DDR

CSSI in 4-Lane

Data

80

10

Normal

DDR

CSSI in 4-Lane

Data

8

160

80

10

20

40

20

Figure 302

Figure 303

LSSI in 1-Lane

Data

32

16

12

983.04

737.28

491.52

368.64

30.72

61.44

DDR

LSSI in 2-Lane

Data

DDR

LSSI in 2-Lane

Data

DDR

1

Normal data type refers to data on the rising edges, and DDR is double data rate, where data is available on the rising and falling edges of the input clock.

Figure 301. CSSI in 1-Lane Data Mode

analog.com

Rev. 0 | 90 of 92

Data Sheet

ADRV9002

APPLICATIONS INFORMATION

Figure 302. CSSI in 4-Lane Data Mode, DDR

Figure 303. LSSI in 2-Lane Data Mode, DDR

analog.com

Rev. 0 | 91 of 92

Data Sheet

ADRV9002

OUTLINE DIMENSIONS

Figure 304. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-196-16)

Dimensions shown in millimeters

ORDERING GUIDE

Package

Option

Model¹

Temperature Range

Package Description

Packing Quantity

ADRV9002BBCZ

−40°C to +85°C

196-Ball CSP-BGA (12 mm × 12 mm × 1.09 mm)

Tray, 189

BC-196-14

ADRV9002BBCZ-RL

Reel, 1500

1

Z = RoHS Compliant Part

registered trademarks are the property of their respective owners.

Rev. 0 | 92 of 92

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.


型号：	ADRV9002
厂家：	ADI
描述：	Dual Narrow-Band and Wideband RF Transceiver
文件：	总92页 (文件大小：11962K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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