ADRV9009-W/PCBZ_技术文档

Integrated Dual RF Transmitter, Receiver,

and Observation Receiver

ADRV9009

Data Sheet

In addition to automatic gain control (AGC), the ADRV9009

also features flexible external gain control modes, allowing

significant flexibility in setting system level gain dynamically.

FEATURES

Dual transmitters

Dual receivers

Dual input shared observation receiver

Maximum receiver bandwidth: 200 MHz

Maximum tunable transmitter synthesis bandwidth:

450 MHz

Maximum observation receiver bandwidth: 450 MHz

Fully integrated fractional-N RF synthesizers

Fully integrated clock synthesizer

The received signals are digitized with a set of four high dynamic

range, continuous time Σ-Δ ADCs that provide inherent

antialiasing. The combination of the direct conversion

architecture, which does not suffer from out of band image

mixing, and the lack of aliasing, relaxes the requirements of the

RF filters when compared to traditional intermediate frequency

(IF) receivers.

Multichip phase synchronization for RF LO and baseband

clocks

JESD204B datapath interface

The transmitters use an innovative direct conversion

modulator that achieves high modulation accuracy with

exceptionally low noise.

Tuning range (center frequency): 75 MHz to 6000 MHz

The observation receiver path consists of a wide bandwidth,

direct conversion receiver with state-of-the-art dynamic range.

APPLICATIONS

3G, 4G, and 5G TDD macrocell base stations

TDD active antenna systems

Massive multiple input, multiple output (MIMO)

Phased array radar

Electronic warfare

Military communications

The fully integrated phase-locked loop (PLL) provides high

performance, low power, fractional-N RF frequency synthesis

for the transmitter (Tx) and receiver (Rx) signal paths. An

additional synthesizer generates the clocks needed for the

converters, digital circuits, and the serial interface. A multichip

synchronization mechanism synchronizes the phase of the RF

local oscillator (LO) and baseband clocks between multiple

ADRV9009 chips. Precautions are taken to provide the isolation

required in high performance base station applications. All

voltage controlled oscillators (VCOs) and loop filter

components are integrated.

Portable test equipment

GENERAL DESCRIPTION

The ADRV9009 is a highly integrated, radio frequency (RF), agile

transceiver offering dual transmitters and receivers, integrated

synthesizers, and digital signal processing functions. The IC

delivers a versatile combination of high performance and low

power consumption demanded by 3G, 4G, and 5G macro cell

time division duplex (TDD) base station applications.

The high speed JESD204B interface supports up to 12.288 Gbps

lane rates, resulting in two lanes per transmitter and a single

lane per receiver in the widest bandwidth mode. The interface

also supports interleaved mode for lower bandwidths, thus

reducing the total number of high speed data interface lanes to

one. Both fixed and floating point data formats are supported.

The floating point format allows internal AGC to be invisible to

the demodulator device.

The receive path consists of two independent, wide bandwidth,

direct conversion receivers with state-of-the-art dynamic range.

The device also supports a wide bandwidth, time shared

observation path receiver (ORx) for use in TDD applications.

The complete receive subsystem includes automatic and

manual attenuation control, dc offset correction, quadrature error

correction (QEC), and digital filtering, thus eliminating the need

for these functions in the digital baseband. Several auxiliary

functions, such as analog-to-digital converters (ADCs), digital-to-

analog converters (DACs), and general-purpose inputs/outputs

(GPIOs) for the power amplifier (PA), and RF front-end

control are also integrated.

The core of the ADRV9009 can be powered directly from 1.3 V

regulators and 1.8 V regulators, and is controlled via a standard

4-wire serial port. Comprehensive power-down modes are

included to minimize power consumption in normal use. The

ADRV9009 is packaged in a 12 mm × 12 mm, 196-ball chip

scale ball grid array (CSP_BGA).

Rev. B

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rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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ADRV9009

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 98

Transmitter.................................................................................. 98

Receiver........................................................................................ 98

Observation Receiver................................................................. 98

Clock Input.................................................................................. 98

Synthesizers................................................................................. 98

SPI................................................................................................. 99

JTAG Boundary Scan................................................................. 99

Power Supply Sequence............................................................. 99

GPIO_x Pins ............................................................................... 99

Auxiliary Converters.................................................................. 99

JESD204B Data Interface .......................................................... 99

Applications Information............................................................ 101

PCB Layout and Power Supply Recommendations............. 101

PCB Material and Stackup Selection ..................................... 101

Fanout and Trace Space Guidelines....................................... 103

Component Placement and Routing Guidelines ................. 104

RF and JESD204B Transmission Line Layout ...................... 110

Isolation Techniques Used on the ADRV9009-W/PCBZ... 114

RF Port Interface Information................................................ 116

Outline Dimensions..................................................................... 127

Ordering Guide ........................................................................ 127

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Current and Power Consumption Specifications................... 14

Timing Diagrams........................................................................ 15

Absolute Maximum Ratings.......................................................... 16

Reflow Profile.............................................................................. 16

Thermal Management ............................................................... 16

Thermal Resistance .................................................................... 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 23

75 MHz to 525 MHz Band ........................................................ 23

650 MHz to 3000 MHz Band.................................................... 44

3400 MHz to 4800 MHz Band.................................................. 63

5100 MHz to 5900 MHz Band.................................................. 80

Transmitter Output Impedance................................................ 95

Observation Receiver Input Impedance.................................. 95

Receiver Input Impedance......................................................... 96

Terminology .................................................................................... 97

REVISION HISTORY

5/2019—Rev. A to Rev B.

Replaced ADRV9009 Customer Card to

Changes to Terminology Section ................................................. 97

Deleted Figure 432 ......................................................................... 98

Changes to Theory of Operation Section and Clock

Input Section................................................................................... 98

Changed Serial Peripheral Interface Section to SPI Section and

AUX DAC_x Section to Auxiliary DAC x Section......................... 99

Changes to Power Supply Sequence Section, GPIO_x Pins

Section, Auxiliary DAC x Section, and JESD204B Data

Interface Section............................................................................. 99

Changes to Table 7 Title, Figure 430, and Figure 431................... 100

Changes to Overview Section, PCB Material and Stackup

Selection Section, and Figure 432 Caption ............................... 101

Changes to Table 9 and Table 10 ................................................ 102

Changes to Fanout and Trace Space Guidelines Section......... 103

Changes to Signals with Highest Routing Priority Section and

Figure 434...................................................................................... 104

Change to Figure 435 Caption.................................................... 105

Changes to Signals with Second Routing Priority Section and

Figure 436...................................................................................... 106

Changes to Figure 437 ................................................................. 107

Changes to Figure 438 ................................................................. 108

ADRV9009-WPCBZ..................................................... Throughout

Changes to Features Section............................................................ 1

Changes to Figure 1.......................................................................... 4

Changes to Specifications Section and Table 1............................. 5

Change to Figure 2 ......................................................................... 15

Changes to Table 3 and Thermal Resistance Section................. 16

Changes to 75 MHz to 525 MHz Band Section, Figures and

Captions........................................................................................... 23

Deleted Figure 83 to Figure 85; Renumbered Sequentially ...... 34

Added Figure 78, Figure 79, and Figure 80; Renumbered

Sequentially ..................................................................................... 35

Added Figure 90.............................................................................. 37

Added Figure 125 to Figure 127 ................................................... 43

Changes to 650 MHz to 3000 MHz Band Section, Figures and

Captions........................................................................................... 44

Changes to 3400 MHz to 4800 MHz Band Section, Figures and

Captions........................................................................................... 63

Changes to 5100 MHz to 5900 MHz Band Section, Figures and

Captions........................................................................................... 80

Rev. B | Page 2 of 127

Data Sheet

ADRV9009

Changes to Signals with Lowest Routing Priority Section and

Figure 439.......................................................................................109

Changes to RF Routing Guidelines Section and

Figure 440 Caption........................................................................110

Change to Figure 441 Caption.....................................................111

Changes to Transmitter Balun DC Feed

Supplies Section.............................................................................112

Changes to Stripline Transmission Lines vs. Microstrip

Transmission Lines Section .........................................................113

Moved Figure 444 to Isolation Techniques Used on the

ADRV9009-W/PCBZ Section .....................................................114

Moved Figure 446..........................................................................115

Changes to Isolation Between JESD204B Lines Section..........115

Changes to RF Port Interface Information Section ..................116

Deleted RF Port Interface Overview Section ............................117

Changes to Figure 448 Caption...................................................117

Moved Table 11..............................................................................120

Changes to Figure 456 Caption to Figure 459 Caption ................121

Changes to General Receiver Path Interface Section ...............122

Changes to Figure 463 ..................................................................124

Changes to Figure 464 and Figure 465.......................................125

Deleted Endnote 1, Table 12 to Endnote 1, Table 15;

Renumbered Sequentially, and Endnote 2, Table 16 and

Endnote 2, Table 17.......................................................................126

Changes to Table 15 ......................................................................126

6/2018—Revision A: Initial Version

Rev. B | Page 3 of 127

ADRV9009

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

Rx1

ADRV9009

RX1_IN +

RX1_IN –

Rx2

RX2_IN +

RX2_IN –

ADC

LPF

ORx1

ORx2

SYNCINx±

ORX1_IN +

ORX1_IN –

SERDOUTx±

SERDINx±

ORX2_IN +

ORX2_IN –

SYNCOUTx±

SYSREF_IN±

GP_INTERRUPT

RXx_ENABLE

TXx_ENABLE

RESET

DIGITAL

PROCESSING

RF_EXT_LO_I/O+

RF_EXT_LO_I/O–

LO

DECIMATION

pFIR

SYNTH

ARM

AGC

M3

DC-OFFSET

QEC

LOL

JESD204B

CIF/RIF

Tx1

TX1_OUT +

TX1_OUT –

TEST

Tx2

DAC

SCLK

CS

TX2_OUT +

TX2_OUT –

LPF

SDO

SDIO

DAC

LPF

GPIOS, AUXADCs, AND AUXDACs

REF_CLK_IN +

REF_CLK_IN –

CLOCK

GENERATION

GPIO_3P3_x

GPIO_x AUXADC_0 THROUGH AUXADC_3

Figure 1.

Rev. B | Page 4 of 127

Data Sheet

ADRV9009

SPECIFICATIONS

Electrical characteristics at VDDA1P3¹= 1.3 V, VDDD1P3_DIG = 1.3 V, VDDA1P8_TX = 1.8 V, junction temperature (T_J) = full

operating temperature range. LO frequency (f_LO) = 1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer

to the Typical Performance Characteristics section for input and output circuit path loss. The device configuration profile for the 75 MHz to

525 MHz frequency range is as follows: receiver = 50 MHz bandwidth (inphase quadrature (IQ) rate = 61.44 MHz), transmitter = 50 MHz

transmitter large signal bandwidth and 100 MHz transmitter synthesis bandwidth (IQ rate = 122.88 MHz), observation receiver = 100 MHz

bandwidth (IQ rate = 122.88 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Unless otherwise specified, the device

configuration for all other frequency ranges is as follows: receiver = 200 MHz bandwidth (IQ rate = 245.76 MHz), transmitter = 200 MHz

transmitter large signal bandwidth and 450 MHz transmitter synthesis bandwidth (IQ rate = 491.52 MHz), observation receiver = 450 MHz

bandwidth (IQ rate = 491.52 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

TRANSMITTERS

Center Frequency

Transmitter Synthesis

Bandwidth

75

6000

450

MHz

Transmitter Large Signal

Bandwidth

Peak-to-Peak Gain

Deviation

200

MHz

dB

1.0

0.1

1

450 MHz bandwidth, compensated by

programmable finite impulse response

(FIR) filter

Any 20 MHz bandwidth span,

compensated by programmable FIR

filter

450 MHz bandwidth

Signal-to-noise ratio (SNR) maintained

for attenuation between 0 dB and 20 dB

Gain Slope

dB

Deviation from Linear Phase

Transmitter Attenuation

Power Control Range

Degrees

dB

0

32

Transmitter Attenuation

Power Control Resolution

Transmitter Attenuation

Integral Nonlinearity

Transmitter Attenuation

Differential Nonlinearity

0.05

0.1

dB

INL

For any 4 dB step

Monotonic

DNL

0.04

Transmitter Attenuation

Serial Peripheral

See Figure 4

Interface 2 (SPI 2) Timing

Time from CS Going High

to Change in Transmitter

Attenuation

Time Between Consecutive

Microattenuation Steps

t_SCH

t_ACH

t_DCH

19.5

6.5

24

ns

dB

8.1

A large change in attenuation can be

broken up into a series of smaller

attenuation changes

Time required to complete the change

in attenuation from start attenuation

to final attenuation value

Time Required to Reach

Final Attenuation Value

800

+0.5

0.5

Maximum Attenuation

Overshoot During

Transition

Change in Attenuation per

Microstep

Maximum Attenuation

Change when CS Goes

High

−1.0

dB

32

Rev. B | Page 5 of 127

ADRV9009

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Adjacent Channel Leakage

Ratio (ACLR) Long Term

Evolution (LTE)

20 MHz LTE at −12 dBFS

−67

−64

−60

dB

75 MHz < f ≤ 2800 MHz

2800 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

In Band Noise Floor

0 dB attenuation, in band noise falls

1 dB for each dB of attenuation for

attenuation between 0 dB and 20 dB

−147

−148

−149

−150.5

dBm/Hz

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

0 dB attenuation, 3 × bandwidth/2 offset

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Out of Band Noise Floor

Interpolation Images

−147

−153

−154

−155.5

−80

dBm/Hz

dBc

Transmitter to Transmitter

Isolation

85

dB

75 MHz < f ≤ 600 MHz

75

70

65

56

dB

600 MHz < f ≤ 2800 MHz

2800 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 5700 MHz

5700 MHz < f ≤ 6000 MHz

Image Rejection

Within Large Signal

Bandwidth

QEC active

70

65

62

60

40

dB

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 4000 MHz

4000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Assumes that distortion power density is

25 dB below desired power density

Beyond Large Signal

Bandwidth

Maximum Output Power

0 dBFS, continuous wave (CW) tone into

50 Ω load, 0 dB transmitter attenuation

9

7

6

4.5

dBm

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

0 dB transmitter attenuation

Third-Order Output

Intermodulation

Intercept Point

OIP3

29

27

23

dBm

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 4000 MHz

4000 MHz < f ≤ 6000 MHz

Carrier Leakage

With LO leakage correction active, 0 dB

attenuation, scales decibel for decibel

with attenuation, measured in 1 MHz

bandwidth, resolution bandwidth and

video bandwidth = 100 kHz, rms

detector, 100 trace average

Carrier Offset from LO

Carrier on LO

−84

−82

−80

−71

dBFS

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Rev. B | Page 6 of 127

Data Sheet

ADRV9009

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Error Vector Magnitude

(Third Generation

EVM

Partnership Project

(3GPP) Test Signals)

75 MHz LO

0.5

%

300 kHz RF PLL loop bandwidth, test

equipment phase noise performance

limited

1900 MHz LO

3800 MHz LO

5900 MHz LO

0.7

1.1

50

%

Ω

50 kHz RF PLL loop bandwidth

300 kHz RF PLL loop bandwidth

Differential (see Figure 427)

Output Impedance

OBSERVATION RECEIVER

Center Frequency

Gain Range

Z_OUT

ORx

75

6000

MHz

dB

30

Third-order input intermodulation

intercept point (IIP3) improves decibel

for decibel for the first 18 dB of gain

attenuation, QEC performance optimi-

zed for 0 dB to 6 dB of attenuation only

Analog Gain Step

Peak-to-Peak Gain

Deviation

0.5

1

dB

For attenuator steps from 0 dB to 6 dB

450 MHz bandwidth, compensated by

programmable FIR filter

Gain Slope

0.1

1

dB

Any 20 MHz bandwidth span, compens-

ated by programmable FIR filter

Degree 450 MHz RF bandwidth

s

Deviation from Linear Phase

Observation Receiver

Bandwidth

450

MHz

Observation Receiver Alias

Band Rejection

60

dB

Due to digital filters

Maximum Useable Input

Level

P_HIGH

0 dB attenuation, increases decibel for

decibel with attenuation, CW

corresponds to −1 dBFS at ADC

−11

−9.5

−8

−58.5

−57.5

62

dBm

dBFS

dBm

75 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

450 MHz integration bandwidth

491.52 MHz integration bandwidth

Maximum observation receiver gain,

(P_HIGH− 14 dB) per tone (see the

Terminology section), 75 MHz < f ≤

600 MHz

Integrated Noise

Second-Order Input

Intermodulation

Intercept Point

IIP2

IIP3

62

dBm

Maximum observation receiver gain,

(P_HIGH− 8 dB) per tone (see the

Terminology section), 600 MHz < f ≤

3000 MHz

Third-Order Input

Intermodulation

Intercept Point

Narrow Band

4

dBm

75 MHz < f ≤ 300 MHz, test condition:

(P_HIGH− 14) dB per tone

300 MHz < f ≤ 600 MHz, (P_HIGH− 14) dB

per tone

11

Third-order intermodulation product

(IM3) product < 130 MHz at baseband,

(P_HIGH− 8) dB per tone

12

11

dBm

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Rev. B | Page 7 of 127

ADRV9009

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Wide Band

7

6

dBm

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Third-Order Intermodulation IM3

Product

IM3 product < 130 MHz at baseband,

two tones, each at (P_HIGH− 12) dB

−70

−67

−62

−80

dBc

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

IM5 product < 50 MHz at baseband,

two tones, each at (P_HIGH− 12) dB,

600 MHz < f ≤ 6000 MHz

Fifth-Order Intermodulation

Product (1800 MHz)

IM5

Seventh-Order

Intermodulation Product

(1800 MHz)

Spurious-Free Dynamic

Range

IM7

−80

70

dBc

dB

IM7 product < 50 MHz at baseband,

two tones, each at (P_HIGH− 12) dB,

600 MHz < f ≤ 6000 MHz

Non IMx related spurs, does not

include HDx, (P_HIGH− 9) dB input signal,

600 MHz < f ≤ 6000 MHz

SFDR

Harmonic Distortion

(P_HIGH− 11) dB input signal

Second-Order Harmonic

Distortion Product

HD2

HD3

−80

dBc

(P_HIGH– 11) dB input signal 75 MHz < f ≤

600 MHz, (P_HIGH– 9) dB input signal

600 MHz < f ≤ 6000 MHz, in band harmo-

nic distortion falls within 100 MHz

Out of band harmonic distortion falls

within 225 MHz

In band harmonic distortion falls

within 100 MHz

Out of band harmonic distortion falls

within 225 MHz

−80

−70

−60

dBc

Third-Order Harmonic

Distortion Product

Image Rejection

QEC active

Within Large Signal

Bandwidth

Outside Large Signal

Bandwidth

Input Impedance

Isolation

65

dB

Ω

55

100

Differential (see Figure 428)

75 MHz < f ≤ 600 MHz

Transmitter 1 (Tx1) to

Observation Receiver 1

(ORx1) and

100

dB

Transmitter 2 (Tx2) to

Observation Receiver 2

(ORx2)

65

55

105

dB

600 MHz < f ≤ 5300 MHz

5300 MHz < f ≤ 6000 MHz

75 MHz < f ≤ 600 MHz

Tx1 to ORx2 and Tx2 to

ORx1

65

55

dB

600 MHz < f ≤ 5300 MHz

5300 MHz < f ≤ 6000 MHz

RECEIVERS

Center Frequency

Gain Range

Analog Gain Step

75

6000

MHz

dB

30

0.5

1

Attenuator steps from 0 dB to 6 dB

Attenuator steps from 6 dB to 30 dB

dB

Bandwidth Ripple

0.5

dB

200 MHz bandwidth, compensated by

programmable FIR filter

0.2

dB

Any 20 MHz bandwidth span, compens-

ated by programmable FIR filter

Rev. B | Page 8 of 127

Data Sheet

ADRV9009

Parameter

Symbol

Min

Typ

Max

Unit

MHz

dB

Test Conditions/Comments

Receiver Bandwidth

Receiver Alias Band

Rejection

200

80

Due to digital filters

Maximum Useable Input

Level

P_HIGH

0 dB attenuation, increases decibel for

decibel with attenuation, CW =

1800 MHz, corresponds to −1 dBFS at

ADC

−11

−10.2

−9.5

dBm

75 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

0 dB attenuation, at receiver port

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Noise Figure

Ripple

NF

11.5

12

13

15.2

1.8

dB

At band edge maximum bandwidth

mode

Third-Order Input

Intermodulation

Intercept Point

IIP3

Difference Product

IIP3D

12

dBm

75 MHz < f ≤ 600 MHz, (P_HIGH− 12) dB

per tone, 600 MHz < f ≤ 6000 MHz,

(P_HIGH− 10) dB per tone, two tones near

band edge

75 MHz < f ≤ 600 MHz, (P_HIGH− 12) dB

per tone, 600 MHz < f ≤ 6000 MHz,

(P_HIGH− 10) dB per tone, two tones at

bandwidth/6 offset from the LO

75 MHz < f ≤ 600 MHz, (P_HIGH− 6) dB,

600 MHz < f ≤ 6000 MHz, (P_HIGH− 4) dB,

CW tone at bandwidth/6 offset from

the LO

Sum Product

IIP3S

HD3

Third-Order Harmonic

Distortion Product

−65

−66

−62

62

dBc

dBm

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

75 MHz < f ≤ 600 MHz, (P_HIGH− 12) dB

per tone, 600 MHz < f ≤ 6000 MHz,

(P_HIGH− 10) dB per tone, 0 dB

attenuation, complex

Second-Order Input

Intermodulation

Intercept Point

IIP2

Image Rejection

Input Impedance

Receiver to Receiver

Isolation

75

dB

QEC active, within 200 MHz receiver

bandwidth

Differential (see Figure 429)

75 MHz < f ≤ 600 MHz

100

77

Ω

dB

65

61

dB

600 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Receiver Band Spurs

Referenced to RF Input

at Maximum Gain

−95

dBm

No more than one spur at this level per

10 MHz of receiver bandwidth

Receiver LO Leakage at

Receiver Input at

Maximum Gain

Leakage decreases decibel for decibel

with attenuation for first 12 dB

−70

−65

dBm

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 6000 MHz

Rev. B | Page 9 of 127

ADRV9009

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

LO SYNTHESIZER

LO Frequency Step

2.3

Hz

1.5 GHz to 2.8 GHz, 76.8 MHz phase

frequency detector (PFD) frequency

LO Spur

Integrated Phase Noise

75 MHz LO

1900 MHz LO

3800 MHz LO

−85

dBc

Excludes integer boundary spurs

2 kHz to 18 MHz

Narrow PLL loop bandwidth (50 kHz)

Wide PLL loop bandwidth (300 kHz)

0.014

0.2

0.36

0.54

°rms

5900 MHz LO

Spot Phase Noise

75 MHz LO

Narrow PLL loop bandwidth

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

1900 MHz LO

−126.5

−132.8

−150.1

−150.7

dBc/Hz

Narrow PLL loop bandwidth

100 kHz Offset

200 kHz Offset

400 kHz Offset

600 kHz Offset

800 kHz Offset

1.2 MHz Offset

1.8 MHz Offset

6 MHz Offset

−100

−115

−120

−129

−132

−135

−140

−150

−153

dBc/Hz

10 MHz Offset

3800 MHz LO

Wide PLL loop bandwidth

100 kHz Offset

1.2 MHz Offset

10 MHz Offset

5900 MHz LO

−104

−125

−145

dBc/Hz

100 kHz Offset

1.2 MHz Offset

10 MHz Offset

LO PHASE SYNCHRONIZATION

Phase Deviation

−99

−119.7

−135.4

dBc/Hz

1.6

ps/°C

Change in LO delay per temperature

change

EXTERNAL LO INPUT

Input Frequency

f_EXTLO

150

0

8000

12

MHz

Input frequency must be 2 × the

desired LO frequency

50 Ω matching at the source

f_EXTLO≤ 2 GHz, add 0.5 dBm/GHz above

2 GHz

Input Signal Power

dBm

3

6

dBm

f_EXTLO= 8 GHz

External LO Input Signal

Differential

To ensure adequate QEC

Phase Error

Amplitude Error

Duty Cycle Error

3.6

1

2

ps

dB

%

Even Order Harmonics

CLOCK SYNTHESIZER

Integrated Phase Noise

1966.08 MHz LO

−50

dBc

1 kHz to 100 MHz

PLL optimized for close in phase noise

0.4

°rms

Rev. B | Page 10 of 127

Data Sheet

ADRV9009

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Spot Phase Noise

1966.08 MHz

100 kHz Offset

1 MHz Offset

10 MHz Offset

−109

−129

−149

dBc/Hz

REFERENCE CLOCK

(REF_CLK_IN )

Frequency Range

Signal Level

10

0.3

1000

2.0

MHz

V p-p

AC-coupled, common-mode voltage

(VCM) = 618 mV, for best spurious

performance use <1 V p-p input clock

AUXILIARY CONVERTERS

ADC

Resolution

12

Bits

Input Voltage

Minimum

Maximum

0.05

V

VDDA_

3P3 −

0.05

DAC

Resolution

Output Voltage

Minimum

Maximum

10

Bits

Includes four offset levels

0.7

VDDA_

V

1 V voltage reference (VREF)

2.5 V VREF

3P3 − 0.3

Output Drive Capability

10

mA

DIGITAL SPECIFICATIONS

(COMPLEMENTARY METAL-

OXIDE SEMICONDUCTOR

(CMOS)) FOR SPI, GPIO_x,

TXx_ENABLE, ORXx_ENABLE

Logic Inputs

Input Voltage

High Level

VDD_

INTERFACE

× 0.8

VDD_

INTERFACE

V

Low Level

0

VDD_

INTERFACE

× 0.2

Input Current

High Level

Low Level

−10

+10

μA

Logic Outputs

Output Voltage

High Level

VDD_

INTERFACE

× 0.8

V

Low Level

VDD_

V

INTERFACE

× 0.2

Drive Capability

3

mA

Rev. B | Page 11 of 127

ADRV9009

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL SPECIFICATIONS

(CMOS) FOR GPIO_3P3_x

Logic Inputs

Input Voltage

High Level

VDDA_

3P3 × 0.8

0

VDDA_3P3

V

Low Level

VDDA_

3P3 × 0.2

Input Current

High Level

Low Level

−10

+10

μA

Logic Outputs

Output Voltage

High Level

VDDA_

3P3 × 0.8

V

Low Level

VDDA_

V

3P3 × 0.2

Drive Capability

4

mA

DIGITAL SPECIFICATIONS

(LOW VOLTAGE

DIFFERENTIAL SIGNALING

(LVDS))

Logic Inputs (SYSREF_IN ,

SYNCINx )

Input Voltage Range

Input Differential

Voltage Threshold

Receiver Differential

Input Impedance

825

−100

1675

+100

mV

Each differential input in the pair

Internal termination enabled

100

Ω

Logic Outputs (SYNCOUTx )

Output Voltage

High

Low

Output Differential

Voltage

1375

mV

1025

225

Programmable in 75 mV steps

Output Offset Voltage

SPI TIMING

1200

mV

SCLK Period

SCLK Pulse Width

CS Setup to First SCLK Rising t_SC

Edge

t_CP

t_MP

20

10

3

ns

Last SCLK Falling Edge to CS

Hold

SDIO Data Input Setup to

SCLK

SDIO Data Input Hold to

SCLK

SCLK Rising Edge to Output

Data Delay (3-Wire or

4-Wire Mode)

t_HC

0

2

0

3

ns

t_S

t_H

t_CO

8

Bus Turnaround Time,

Read After Baseband

Processor (BBP) Drives

Last Address Bit

Bus Turnaround Time,

Read After ADRV9009

Drives Last Data Bit

t_HZM

t_H

0

t_CO

ns

t_HZS

t_CO

Rev. B | Page 12 of 127

Data Sheet

ADRV9009

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

JESD204B DATA OUTPUT

TIMING

AC-coupled

Unit Interval

Data Rate per Channel,

Nonreturn to Zero (NRZ)

UI

81.38

3125

320

12,288

ps

Mbps

Rise Time

Fall Time

Output Common-Mode

Voltage

t_R

t_F

V_CM

24

0

39.5

39.4

ps

V

20% to 80% in 100 Ω load

AC-coupled

1.8

Differential Output Voltage

Short-Circuit Current

Differential Termination

Impedance

V_DIFF

I_DSHORT

360

−100

80

600

770

+100

120

mV

mA

Ω

94.2

Total Jitter

Uncorrelated Bounded High UBHPJ

Probability Jitter

15.13

0.56

ps

Bit error rate (BER) = 10⁻¹⁵

Duty Cycle Distortion

SYSREF_IN Setup Time to

REF_CLK_IN

SYSREF_IN Hold Time to

REF_CLK_IN

Latency

DCD

0.369

116.5

ps

ns

2.5

See Figure 2

−1.5

ns

See Figure 2

t_{LAT_FRM}

REF_CLK_IN = 245.76 MHz

Clock

Observation receiver bandwidth =

450 MHz, IQ rate = 491.52 MHz, lane

rate = 9830.4 MHz, number of

cycles

converters (M) = 4, number of lanes (L)

= 2, converter resolution (N) = 16,

number of samples per converter (S) = 1

237.02

89.4

ns

Clock

cycles

Receiver bandwidth = 200 MHz, IQ rate

= 245.76 MHz, lane rate = 9830.4 MHz,

M = 2, L = 2, N = 16, S = 1

364.18

ns

JESD204B DATA INPUT TIMING

Unit Interval

Data Rate per Channel (NRZ)

Differential Voltage

Termination Voltage (VTT)

Source Impedance

AC-coupled

UI

81.38

3125

125

320

12288

750

30

ps

Mbps

mV

Ω

V_DIFF

Z_TT

8.9

Differential Impedance

Termination Voltage

AC-Coupled

Z_RDIFF

V_TT

80

105.1

120

Ω

V

1.267

1.33

Latency

t_{LAT_DEFRM}

74.45

Clock

cycles

Device clock = 245.76 MHz, transmitter

bandwidth = 200 MHz, IQ rate =

491.52 MHz, lane rate = 9830.4 MHz,

M = 2, L = 2, N = 16, S = 1

153.5

ns

¹VDDA1P3 refers to all analog 1.3 V supplies, including: VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_RF_VCO_LDO,

VDDA1P3_RF_LO, VDDA1P3_DES, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.

Rev. B | Page 13 of 127

ADRV9009

Data Sheet

CURRENT AND POWER CONSUMPTION SPECIFICATIONS

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY CHARACTERISTICS

VDDA1P3¹Analog Supply

VDDD1P3_DIG Supply

VDDA1P8_TX Supply

VDDA1P8_BB Supply

VDD_INTERFACE Supply

VDDA_3P3 Supply

1.267 1.3

1.33

1.89

2.625

3.465

V

1.71

1.8

CMOS and LVDS supply, 1.8 V to 2.5 V nominal range

3.135 3.3

POSITIVE SUPPLY CURRENT

LO at 2600 MHz

450 MHz Transmitter Bandwidth,

Observation Receiver Disabled

Two transmitters enabled

VDDA1P3¹Analog Supply

VDDD1P3_DIG Supply

VDDA1P8_TX Supply

1520

mA

619

455

135

30

8

Transmitter QEC active

Transmitter RF attenuation = 0 dB, full-scale CW

Transmitter RF attenuation = 15 dB, full-scale CW

VDDA1P8_BB Supply

VDD_INTERFACE Supply

VDDA_3P3 Supply

VDD_INTERFACE = 2.5 V

No Auxiliary DAC x or AUXADC_x enabled, if enabled,

3

AUXADC_x adds 2.7 mA and each Auxiliary DAC x adds 1.5 mA

Total Power Dissipation

3.68

3.11

W

Typical supply voltages, 0 dB transmitter attenuation,

transmitter QEC active

Typical supply voltages, 15 dB transmitter attenuation,

transmitter QEC active

450 MHz Transmitter Bandwidth,

Observation Receiver Enabled

Two transmitters enabled, one ORx enabled

VDDA1P3¹Analog Supply

VDDD1P3_DIG Supply

2073

1541

mA

Transmitter QEC tracking active, observation receiver QEC

enabled, transmitter LTE20 centered on LO, observation

receiver LTE20 at −16 dBm centered on LO

2100

mA

Transmitter two tone = −99 MHz and 100 MHz at −7 dBFS each,

observation receiver one tone = 100 MHz at −16 dBm

VDDA1P8_TX Supply

455

135

63

8

mA

Transmitter RF attenuation = 0 dB, full scale CW

Transmitter RF attenuation = 15 dB, full scale CW

VDDA1P8_BB Supply

VDD_INTERFACE Supply

VDDA_3P3 Power Supply

VDD_INTERFACE = 2.5 V

No Auxiliary DAC x or AUXADC_x enabled, if enabled,

3

AUXADC_x adds 2.7 mA and each Auxiliary DAC x adds 1.5 mA

Total Power Dissipation

5.66

5.08

W

Typical supply voltages, 0 dB transmitter attenuation,

transmitter QEC active

Typical supply voltages, 15 dB transmitter attenuation,

transmitter QEC active

200 MHz Receiver Bandwidth,

Observation Receiver Disabled

Two receivers enabled

Receiver QEC active

VDDA1P3¹Analog Supply

VDDD1P3_DIG Supply

VDDA1P8_TX Supply

VDDA1P8_BB Supply

VDD_INTERFACE Supply

VDDA_3P3 Supply

1645

984

0.4

68

8

3

mA

No Auxiliary DAC x or AUXADC_x enabled, if enabled,

AUXADC_x adds 2.7 mA and each Auxiliary DAC x adds 1.5 mA

Total Power Dissipation

3.57

W

Typical supply voltages, receiver QEC active

¹VDDA1P3 refers to all analog 1.3 V supplies, including: VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_RF_VCO_LDO,

VDDA1P3_RF_LO, VDDA1P3_DES, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.

Rev. B | Page 14 of 127

Data Sheet

ADRV9009

TIMING DIAGRAMS

AT DEVICE PINS

REF_CLK_IN± DELAY

IN REFERENCE TO SYSREF_IN±

AT DEVICE CORE

t’_H

t_H

t_S

t’_S

REF_CLK_IN±

t_H= –1.5ns

t_S= +2.5ns

CLK DELAY = 2ns

t’_H= +0.5ns

t’_S= +0.5ns

NOTES

1. t_HAND t_SARE THE HOLD AND SETUP TIMES FOR THE REF_CLK_IN± PINS. t’_HAND t’_SREFER TO THE

DELAYED HOLD AND SETUP TIMES AT THE DEVICE CORE IN REFERENCE TO THE SYSREF_N± SIGNALS

DUE TO AN INTERNAL BUFFER THAT THE SIGNAL PASSES THROUGH.

Figure 2. SYSREF_IN Setup and Hold Timing

t_H

t_S

REF_CLK_IN±

SYSREF_IN±

t_H= –1.5ns

t_S= +2.5ns

VALID SYSREF

INVALID SYSREF

Figure 3. SYSREF_IN Setup and Hold Timing Examples, Relative to Device Clock

SCLK

SDIO

CS

t_DCH

Tx

ATTENUATION

t_SCHt_ACH

Figure 4. Transmitter Attenuation Update via SPI 2 Port

Rev. B | Page 15 of 127

ADRV9009

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL MANAGEMENT

Table 3.

The ADRV9009 is a high power device that can dissipate over

3 W depending on the user application and configuration.

Because of the power dissipation, the ADRV9009 uses an

exposed die package to provide the customer with the most

effective method of controlling the die temperature. The exposed

die allows cooling of the die directly. Figure 5 shows the profile

view of the device mounted to a user printed circuit board (PCB)

and a heat sink (typically the aluminum case) to keep the junction

(exposed die) below the maximum T_Jdetailed in Table 3. The

device is designed for a lifetime of 10 years when operating at

the maximum T_J.

Parameter

Rating

VDDA1P3¹to VSSA

VDDD1P3_DIG to VSSD

VDD_INTERFACE to VSSA

VDDA_3P3 to VSSA

VDDA1P8_TX to VSSA

−0.3 V to +1.4 V

−0.3 V to +3.0 V

−0.3 V to +3.9 V

−0.3 V to +2.0 V

−0.3 V to VDD_

INTERFACE + 0.3 V

−0.3 V to

VDDA1P3_SER

VDD_INTERFACE Logic Inputs and

Outputs to VSSD

JESD204B Logic Outputs to VSSA

JESD204B Logic Inputs to VSSA

−0.3 V to

VDDA1P3_DES +0.3 V

THERMAL RESISTANCE

Input Current to any Pin Except

Supplies

Maximum Input Power into RF Port 23 dBm (peak)

Maximum Transmitter Voltage

Standing Wave Ratio (VSWR)

10 mA

Thermal performance is directly linked to PCB design and

operating environment. Careful attention to PCB thermal

design is required.

3:1

θ_JAis the natural convection junction to ambient thermal

resistance measured in a circuit board for surface-mount

packages.

Maximum T_J

Storage Temperature Range

110°C

−65°C to +150°C

¹VDDA1P3 refers to all analog 1.3 V supplies.

θ

_{JC_TOP}is the conduction thermal resistance from junction to case

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

where the case temperature is measured at the top of the package.

Thermal resistance data for the ADRV9009 mounted on both a

JEDEC 2S2P test board and a 10-layer Analog Devices, Inc.,

evaluation board is listed in Table 4. Do not exceed the absolute

maximum T_Jrating in Table 3. Ten-layer PCB entries refer to the

10-layer Analog Devices evaluation board, which more

accurately reflects the PCB used in customer applications.

REFLOW PROFILE

Table 4. Thermal Resistance^{1, 2}

The ADRV9009 reflow profile is in accordance with the JEDEC

JESD204B criteria for Pb-free devices. The maximum reflow

temperature is 260°C.

Package Type

θ_JA

θ_{JC_TOP}θ_JBΨ_JTΨ_JBUnit

BC-196-13

21.1 0.04

4.9 0.3 4.9

°C/W

¹For the θ_JCtest, 100 µm thermal interface material (TIM) is used. TIM is

assumed to have 3.6 thermal conductivity watts/(meter × Kelvin).

²Using enhanced heat removal techniques such as PCB, heat sink, and airflow

improves the thermal resistance values.

ESD CAUTION

CUSTOMER CASE (HEAT SINK)

CUSTOMER THERMAL FILLER

SILICON (DIE)

PACKAGE SUBSTRATE

CUSTOMER PCB

Figure 5. Typical Thermal Management Solution

Rev. B | Page 16 of 127

Data Sheet

ADRV9009

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

C

D

E

F

VSSA

ORX2_IN+

ORX2_IN–

VSSA

RX2_IN+

RX2_IN–

VSSA

RX1_IN+

RX1_IN–

VSSA

ORX1_IN+

ORX1_IN–

VSSA

VDDA1P3_

RX_RF

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VSSA

VDDA_3P3

VSSA

VDDA1P3_

AUX_VCO_

LDO

VDDA1P3_

RX_TX

VDDA1P3_

RF_VCO_LDO RF_VCO_LDO

VDDA1P3_

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

GPIO_3P3_0 GPIO_3P3_3

GPIO_3P3_1 GPIO_3P3_4

GPIO_3P3_9

RBIAS

VDDA1P1_

AUX_VCO

VSSA

GPIO_3P3_8 GPIO_3P3_10

AUX_SYNTH_

OUT

GPIO_3P3_2 GPIO_3P3_5 GPIO_3P3_6 VDDA1P8_BB VDDA1P3_BB

REF_CLK_IN+ REF_CLK_IN–

AUXADC_3

AUXADC_2

VSSA

VDDA1P8_TX GPIO_3P3_7 GPIO_3P3_11

VSSA

AUXADC_0

VSSA

AUXADC_1

VSSA

VDDA1P3_

CLOCK_ SYNTH

VDDA1P3_

RF_SYNTH

VDDA1P3_

AUX_SYNTH

RF_SYNTH_

VTUNE

G

H

J

VSSA

TX2_OUT–

TX2_OUT+

VSSA

GPIO_2

GPIO_3

VSSD

VSSA

SDIO

SCLK

VSSA

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

SERDIN1+

SERDIN3–

GPIO_11

GPIO_10

GPIO_9

GPIO_8

TX1_OUT+

TX1_OUT–

VSSA

GP_

INTERRUPT

GPIO_18

RESET

TEST

GPIO_1

GPIO_0

SDO

K

L

SYSREF_IN+ SYSREF_IN–

GPIO_5

GPIO_6

GPIO_4

GPIO_7

CS

VDDD1P3_

DIG

VDDD1P3_

DIG

VSSA

SYNCIN1–

SYNCIN0–

SYNCIN1+

SYNCIN0+

VSSD

SYNCOUT1– SYNCOUT1+

SYNCOUT0– SYNCOUT0+

VDDA1P1_

CLOCK_VCO

VDD_

INTERFACE

M

N

P

RX1_ENABLE TX1_ENABLE RX2_ENABLE TX2_ENABLE

VSSA

GPIO_17

SERDIN1–

VSSA

VDDA1P3_

CLOCK_

VCO_LDO

VDDA1P3_

SER

VDDA1P3_

DES

SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+

VSSA

SERDIN0–

SERDIN3+

SERDIN0+

SERDIN2–

VSSA

AUX_SYNTH_

VTUNE

VDDA1P3_

SER

VDDA1P3_

DES

VSSA

SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+

SERDIN2+

ADRV9009

Figure 6. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Type

Mnemonic

Description

A1, A4, A7, A8, A11, A14, B2 to Input

B6, B9 to B14, C4, C9, C11,

D3 to D9, D11, D12, E6, E9,

F1, F2, F5 to F10, F12 to

F14, G1 to G4, G6, G10 to

G14, H2 to H10, H13, J2,

J13, K1, K2, K13, K14, L1, L2,

M2, M9, N2, N7, N14, P2,

P3, P10

VSSA

Analog Supply Voltage (V_SS).

A2, A3

Input

ORX2_IN+, ORX2_IN−

Differential Input for Observation Receiver 2. When unused, connect

these pins to ground.

Rev. B | Page 17 of 127

ADRV9009

Data Sheet

Pin No.

Type

Mnemonic

Description

A5, A6

Input

RX2_IN+, RX2_IN−

Differential Input for Main Receiver 2. When unused, connect these pins

to ground.

A9, A10

Input

RX1_IN+, RX1_IN−

ORX1_IN+, ORX1_IN−

VDDA1P3_RX_RF

Differential Input for Main Receiver 1. When unused, connect these

pins to ground.

Differential Input for Observation Receiver 1. When unused, connect

these pins to ground.

A12, A13

B1

B7, B8

Input

Observation Receiver Supply.

RF_EXT_LO_I/O−,

RF_EXT_LO_I/O+,

Differential External LO Input/Output. If these pins are used for the

external LO, the input frequency must be 2× the desired carrier

frequency. When unused, do not connect these pins.

C1

Input/

output

GPIO_3P3_0

GPIO_3P3_3

GPIO_3P3_9

GPIO_3P3_1

GPIO_3P3_4

GPIO_3P3_8

GPIO_3P3_10

GPIO_3P3_2

GPIO_3P3_5

GPIO_3P3_6

GPIO Pin Referenced to 3.3 V Supply. The alternate function is AUXDAC_4.

Because this pin contains an input stage, the voltage on the pin must

be controlled. When unused, this pin can be tied to ground through a

resistor (to safeguard against misconfiguration), or this pin can be left

floating, programmed as outputs, and driven low.

GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input

stage, the voltage on the pin must be controlled. When unused, this pin

can be tied to ground through a resistor (to safeguard against

misconfiguration), or these pins can be left floating, programmed as

outputs, and driven low.

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_9. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_5. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_6. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_1. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_0. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input

stage, the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor (to safeguard against

misconfiguration), or these pins can be left floating, programmed as

outputs, and driven low.

C2

Input/

output

C13

D1

D2

D13

D14

E1

Input/

output

Input/

output

Input/

output

Input/

output

Input/

output

Input/

output

E2

Input/

output

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_7. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_8. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

E3

Input/

output

Rev. B | Page 18 of 127

Data Sheet

ADRV9009

Pin No.

Type

Mnemonic

Description

E13

Input/

output

GPIO_3P3_7

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_2. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

E14

Input/

output

GPIO_3P3_11

GPIO Pin Referenced to 3.3 V Supply. The alternative function is

AUXDAC_3. Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied to

ground through a resistor (to safeguard against misconfiguration), or

these pins can be left floating, programmed as outputs, and driven low.

C3

Input

VDDA1P3_RX_TX

1.3 V Supply for Transmitter/Receiver Baseband Circuits, Transimpedance

Amplifier (TIA), Transmitter Transconductance (GM), Baseband Filters,

and Auxiliary DACs.

RF VCO LDO Supply Inputs. Connect Pin C5 to Pin C6. Use a separate

trace on the PCB back to a common supply point.

C5, C6

VDDA1P3_RF_VCO_LDO

C7

C8

Input

VDDA1P1_RF_VCO

VDDA1P3_RF_LO

1.1 V VCO Supply. Decouple this pin with 1 μF.

1.3 V LO Generator for the RF Synthesizer. This pin is sensitive to

supply noise.

C10

C12

Input

VDDA1P3_AUX_VCO_LDO 1.3 V Supply.

VDDA_3P3

General-Purpose Output Pull-Up Voltage and Auxiliary DAC Supply

Voltage.

C14

Input/

output

RBIAS

Bias Resistor. Tie this pin to ground using a 14.3 kΩ resistor. This pin

generates an internal current based on an external 1% resistor.

D10

E4

E5

Input

VDDA1P1_AUX_VCO

VDDA1P8_BB

VDDA1P3_BB

REF_CLK_IN+,

REF_CLK_IN−

1.1 V VCO Supply. Decouple this pin with 1 μF.

1.8 V Supply for the ADC and DAC.

1.3 V Supply for the ADC, DAC, and AUXADC.

Device Clock Differential Input.

E7, E8

E10

E12

Output AUX_SYNTH_OUT

Auxiliary PLL Output. When unused, do not connect this pin.

1.8 V Supply for Transmitter.

Input

VDDA1P8_TX

F3, F4, F11, E11

AUXADC_0 to AUXADC_3 Auxiliary ADC Input. When unused, connect these pins to ground with a

pull-down resistor, or connect directly to ground.

G5

Input

VDDA1P3_CLOCK_SYNTH

1.3 V Supply Input for Clock Synthesizer. Use a separate trace on the

PCB back to a common supply point.

G7

G8

Input

VDDA1P3_RF_SYNTH

VDDA1P3_AUX_SYNTH

1.3 V RF Synthesizer Supply Input. This pin is sensitive to supply noise.

1.3 V Auxiliary Synthesizer Supply Input.

G9

Output RF_SYNTH_VTUNE

RF Synthesizer VTUNE Output.

H11

Input/

output

GPIO_12

GPIO_11

GPIO_13

GPIO_10

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin can be

tied to ground through a resistor (to safeguard against misconfiguration),

or it can be left floating, programmed as output, and driven low.