ADSP-21060CW-133_技术文档

®

ADSP-21060 Industrial SHARC

a

DSP Microcomputer Family

ADSP-21060C/ADSP-21060LC

SUMMARY

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

High Performance Signal Processor for Communica-

tions, Graphics, and Imaging Applications

Super Harvard Architecture

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation

Four Independent Buses for Dual Data Fetch,

Instruction Fetch, and Nonintrusive I/O

32-Bit IEEE Floating-Point Computation Units—

Multiplier, ALU, and Shifter

240-Lead Thermally Enhanced CQFP Package

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats or 32-Bit Fixed-

Point Data Format

Dual-Ported On-Chip SRAM and Integrated I/O

Peripherals—A Complete System-On-A-Chip

Integrated Multiprocessing Features

Industrial Temperature Grade Hermetic Ceramic QFP

Package

Parallel Computations

Single-Cycle Multiply and ALU Operations in Parallel

with Dual Memory Read/Writes and Instruction Fetch

Multiply with Add and Subtract for Accelerated FFT

Butterfly Computation

KEY FEATURES

40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction

Execution

120 MFLOPS Peak, 80 MFLOPS Sustained Performance

Dual Data Address Generators with Modulo and Bit-

Reverse Addressing

4 Mbit On-Chip SRAM

Dual-Ported for Independent Access by Core Processor

and DMA

Off-Chip Memory Interfacing

4 Gigawords Addressable

Programmable Wait State Generation, Page-Mode

DRAM Support

DUAL-PORTED SRAM

CORE PROCESSOR

TIMER

INSTRUCTION

JTAG

TWO INDEPENDENT

7

CACHE

DUAL-PORTED BLOCKS

32 x 48-BIT

TEST &

EMULATION

PROCESSOR PORT

I/O PORT

ADDR

DATA

ADDR

DATA

ADDR

DATA

DAG1

DAG2

PROGRAM

SEQUENCER

8 x 4 x 32

8 x 4 x 24

EXTERNAL

PORT

IOD

48

IOA

17

24

PM ADDRESS BUS

32

48

ADDR BUS

MUX

32

DM ADDRESS BUS

MULTIPROCESSOR

INTERFACE

PM DATA BUS

DM DATA BUS

48

BUS

DATA BUS

MUX

CONNECT

(PX)

40/32

HOST PORT

4

DMA

DATA

IOP

REGISTERS

CONTROLLER

REGISTER

FILE

6

(

MEMORY MAPPED)

SERIAL PORTS

(2)

16 x 40-BIT

BARREL

SHIFTER

ALU

MULTIPLIER

CONTROL,

STATUS &

DATA BUFFERS

36

LINK PORTS

(6)

I/O PROCESSOR

Figure 1. Block Diagram

SHARC is a registered trademark of Analog Devices, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-21060C/ADSP-21060LC

Multiprocessing

DMA Controller

Glueless Connection for Scalable DSP Multiprocessing

Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of Up to Six ADSP-2106xs Plus Host

Six Link Ports for Point-to-Point Connectivity and Array

Multiprocessing

10 DMA Channels for Transfers Between ADSP-2106x

Internal Memory and External Memory, External

Peripherals, Host Processor, Serial Ports, or Link

Ports

Background DMA Transfers at 40 MHz, in Parallel with

Full-Speed Processor Execution

240 Mbytes/s Transfer Rate Over Parallel Bus

240 Mbytes/s Transfer Rate Over Link Ports

Host Processor Interface to 16- and 32-Bit Microprocessors

Host Can Directly Read/Write ADSP-2106x Internal

Memory

Serial Ports

Two 40 Mbit/s Synchronous Serial Ports with

Companding Hardware

Independent Transmit and Receive Functions

TABLE OF CONTENTS

ADSP-2106x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. JTAG Clocktree for Multiple ADSP-2106x

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3

ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4

ADSP-21060C/ADSP-21060LC FEATURES . . . . . . . . . . . 4

DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 7

ADDITIONAL INFORMATION . . . . . . . . . . . . . . . . . . . . . 7

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8

TARGET BOARD CONNECTOR FOR EZ-ICE^®

PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

RECOMMENDED OPERATING CONDITIONS (5V) . 13

ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 13

POWER DISSIPATION ADSP-21060C (5 V) . . . . . . . . . . 14

RECOMMENDED OPERATING CONDITIONS (3.3V) 15

ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 15

POWER DISSIPATION ADSP-21060LC (3.3 V) . . . . . . . . 16

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 20

Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 21

Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 22

Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 24

Multiprocessor Bus Request and Host Bus Request . . . . . 25

Asynchronous Read/Write—Host to ADSP-2106x . . . . . . 27

Three-State Timing—Bus Master, Bus Slave,

HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Link Ports: 1 × CLK Speed Operation . . . . . . . . . . . . . . 32

Link Ports: 2 × CLK Speed Operation . . . . . . . . . . . . . . 33

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 38

OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 39

POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 42

240-LEAD METRIC CQFP PIN CONFIGURATIONS . . 43

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 45

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13. Memory Read—Bus Master . . . . . . . . . . . . . . . . 20

Figure 14. Memory Write—Bus Master . . . . . . . . . . . . . . . 21

Figure 15. Synchronous Read/Write—Bus Master . . . . . . . 23

Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 24

Figure 17. Multiprocessor Bus Request and Host Bus

Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 27

Figure 18b. Asynchronous Read/Write—Host to

ADSP-2106x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 19a. Three-State Timing (Bus Transition Cycle,

SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 19b. Three-State Timing (Host Transition Cycle) . . 29

Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 31

Figure 21. Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 22. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 23. External Late Frame Sync . . . . . . . . . . . . . . . . . 37

Figure 24. IEEE 11499.1 JTAG Test Access Port . . . . . . . 38

Figure 25. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 40

Figure 26. Equivalent Device Loading for AC Measurements

(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 27. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . 40

Figure 28. ADSP-2106x Typical Drive Currents

(V_DD= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 29. Typical Output Rise Time (10%–90% V_DD

)

vs. Load Capacitance (V_DD= 5 V) . . . . . . . . . . . . . . . . . . . 41

Figure 30. Typical Output Rise Time (0.8 V–2.0 V)

vs. Load Capacitance (V_DD= 5 V) . . . . . . . . . . . . . . . . . . . 41

Figure 31. Typical Output Delay or Hold vs. Load Capacitance

(at Maximum Case Temperature) (V_DD= 5 V) . . . . . . . . . 41

Figure 32. ADSP-2106x Typical Drive Currents

FIGURES

Figure 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. ADSP-2106x System . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Shared Memory Multiprocessing System . . . . . . . . 6

Figure 4. ADSP-21060C/ADSP-21060LC Memory Map . . . 7

Figure 5. Target Board Connector for ADSP-2106x

EZ-ICE Emulator (Jumpers in Place) . . . . . . . . . . . . . . . 11

Figure 6. JTAG Scan Path Connections for Multiple

(V_DD= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 33. Typical Output Rise Time (10%–90% V_DD

)

vs. Load Capacitance (V_DD= 3.3 V) . . . . . . . . . . . . . . . . . 41

Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs. Load

Capacitance (V_DD= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 35. Typical Output Delay or Hold vs. Load Capacitance

(at Maximum Case Temperature) (V_DD= 3.3 V) . . . . . . . . 42

EZ-ICE is a registered trademark of Analog Devices, Inc.

REV. B

–2–

ADSP-21060C/ADSP-21060LC

DMA controller, serial ports, and link port and parallel bus

connectivity for glueless DSP multiprocessing.

Figure 1 shows a block diagram of the ADSP-21060C/

ADSP-21060LC, illustrating the following architectural features:

Computation Units (ALU, Multiplier and Shifter) with a

Shared Data Register File

Data Address Generators (DAG1, DAG2)

Program Sequencer with Instruction Cache

Interval Timer

On-Chip SRAM

External Port for Interfacing to Off-Chip Memory and

Peripherals

Host Port and Multiprocessor Interface

DMA Controller

Serial Ports and Link Ports

JTAG Test Access Port

S

GENERAL DESCRIPTION

The ADSP-2106x SHARC—Super Harvard Architecture Com-

puter—is a signal processing microcomputer that offers new

capabilities and levels of performance. The ADSP-2106x

SHARCs are 32-bit processors optimized for high performance

DSP applications. The ADSP-2106x builds on the ADSP-

21000 DSP core to form a complete system-on-a-chip, adding a

dual-ported on-chip SRAM and integrated I/O peripherals sup-

ported by a dedicated I/O bus.

Figure 2 shows a typical single-processor system. A multi-

processing system is shown in Figure 3.

Table I. ADSP-21060C/ADSP-21060LC Benchmarks

(@ 40 MHz)

Fabricated in a high speed, low power CMOS process, the

ADSP-2106x has a 25 ns instruction cycle time and operates

at 40 MIPS. With its on-chip instruction cache, the processor

can execute every instruction in a single cycle. Table I shows

performance benchmarks for the ADSP-2106x.

1024-Pt. Complex FFT

(Radix 4, with Digit Reverse)

FIR Filter (per Tap)

IIR Filter (per Biquad)

Divide (y/x)

Inverse Square Root (1/√x)

DMA Transfer Rate

0.46 ms

18,221 cycles

25 ns

100 ns

150 ns

225 ns

1 cycle

4 cycles

6 cycles

9 cycles

The ADSP-2106x SHARC represents a new standard of inte-

gration for signal computers, combining a high performance

floating-point DSP core with integrated, on-chip system features

including a 4 Mbit SRAM memory host processor interface,

240 Mbytes/s

REV. B

–3–

ADSP-21060C/ADSP-21060LC

ADSP-21000 FAMILY CORE ARCHITECTURE

Instruction Cache

The ADSP-2106x includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and two

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

allows full-speed execution of core, looped operations such as

digital filter multiply-accumulates and FFT butterfly processing.

The ADSP-2106x includes the following architectural features

of the ADSP-21000 family core. The ADSP-21060C is code-

and function-compatible with the ADSP-21061 and ADSP-21062.

Independent, Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier and shifter all per-

form single-cycle instructions. The three units are arranged in

parallel, maximizing computational throughput. Single multi-

function instructions execute parallel ALU and multiplier opera-

tions. These computation units support IEEE 32-bit single-

precision floating-point, extended precision 40-bit floating-

point, and 32-bit fixed-point data formats.

Data Address Generators with Hardware Circular Buffers

The ADSP-2106x’s two data address generators (DAGs) imple-

ment circular data buffers in hardware. Circular buffers allow

efficient programming of delay lines and other data structures

required in digital signal processing, and are commonly used in

digital filters and Fourier transforms. The two DAGs of the

ADSP-2106x contain sufficient registers to allow the creation of

up to 32 circular buffers (16 primary register sets, 16 second-

ary). The DAGs automatically handle address pointer wrap-

around, reducing overhead, increasing performance, and

simplifying implementation. Circular buffers can start and end

at any memory location.

ADSP-2106x

CS

BMS

1x CLOCK

3

CLKIN

EBOOT

LBOOT

BOOT

EPROM

(OPTIONAL)

ADDR

DATA

IRQ

2-0

4

FLAG

3-0

ADDR

DATA

31-0

TIMEXP

MEMORY

AND

PERIPHERALS

(OPTIONAL)

DATA

47-0

Flexible Instruction Set

LINK

DEVICES

(6 MAXIMUM)

(OPTIONAL)

LxCLK

LxACK

LxDAT

RD

WR

OE

WE

ACK

CS

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the ADSP-

2106x can conditionally execute a multiply, an add, a subtract

and a branch, all in a single instruction.

3-0

ACK

MS

3-0

TCLK0

RCLK0

TFS0

RSF0

DT0

PAGE

SBTS

SW

SERIAL

DEVICE

(OPTIONAL)

DMA DEVICE

(OPTIONAL)

DATA

ADSP-21060C/ADSP-21060LC FEATURES

Augmenting the ADSP-21000 family core, the ADSP-21060

adds the following architectural features:

ADRCLK

DR0

DMAR1-2

DMAG1-2

TCLK1

RCLK1

TFS1

RFS1

DT1

CS

HBR

HBG

Dual-Ported On-Chip Memory

SERIAL

DEVICE

(OPTIONAL)

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

The ADSP-21060C contains four megabits of on-chip SRAM,

organized as two blocks of 2 Mbits each, which can be config-

ured for different combinations of code and data storage.

Each memory block is dual-ported for single-cycle, independent

accesses by the core processor and I/O processor or DMA con-

troller. The dual-ported memory and separate on-chip buses

allow two data transfers from the core and one from I/O, all in a

single cycle.

REDY

DR1

BR

1-6

ADDR

DATA

RPBA

CPA

JTAG

ID

2-0

RESET

7

Figure 2. ADSP-2106x System

Data Register File

On the ADSP-21060C, the memory can be configured as a

maximum of 128K words of 32-bit data, 256K words of 16-bit

data, 80K words of 48-bit instructions (or 40-bit data), or com-

binations of different word sizes up to four megabits. All of

the memory can be accessed as 16-bit, 32-bit, or 48-bit words.

A general purpose data register file is used for transferring data

between the computation units and the data buses, and for

storing intermediate results. This 10-port, 32-register (16 pri-

mary, 16 secondary) register file, combined with the ADSP-

21000 Harvard architecture, allows unconstrained data flow

between computation units and internal memory.

A 16-bit floating-point storage format is supported that effec-

tively doubles the amount of data that may be stored on-chip.

Conversion between the 32-bit floating-point and 16-bit floating-

point formats is done in a single instruction.

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-2106x features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1). With its separate program and data memory

buses and on-chip instruction cache, the processor can simulta-

neously fetch two operands and an instruction (from the cache),

all in a single cycle.

While each memory block can store combinations of code and

data, accesses are most efficient when one block stores data,

using the DM bus for transfers, and the other block stores

instructions and data, using the PM bus for transfers. Using the

DM bus and PM bus in this way, with one dedicated to each

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache. Single-cycle execution is also maintained when one of the

data operands is transferred to or from off-chip, via the ADSP-

2106x’s external port.

REV. B

–4–

ADSP-21060C/ADSP-21060LC

Off-Chip Memory and Peripherals Interface

Serial Ports

The ADSP-2106x’s external port provides the processor’s inter-

face to off-chip memory and peripherals. The 4-gigaword off-

chip address space is included in the ADSP-2106x’s unified

address space. The separate on-chip buses—for PM addresses,

PM data, DM addresses, DM data, I/O addresses, and I/O

data—are multiplexed at the external port to create an external

system bus with a single 32-bit address bus and a single 48-bit

(or 32-bit) data bus.

The ADSP-2106x features two synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices. The serial ports can operate at

the full clock rate of the processor, providing each with a maxi-

mum data rate of 40 Mbit/s. Independent transmit and receive

functions provide greater flexibility for serial communications.

Serial port data can be automatically transferred to and from

on-chip memory via DMA. Each of the serial ports offers TDM

multichannel mode.

Addressing of external memory devices is facilitated by on-chip

decoding of high-order address lines to generate memory bank

select signals. Separate control lines are also generated for sim-

plified addressing of page-mode DRAM. The ADSP-2106x

provides programmable memory wait states and external

memory acknowledge controls to allow interfacing to DRAM

and peripherals with variable access, hold, and disable time

requirements.

The serial ports can operate with little-endian or big-endian

transmission formats, with word lengths selectable from 3 bits to

32 bits. They offer selectable synchronization and transmit

modes as well as optional µ-law or A-law companding. Serial

port clocks and frame syncs can be internally or externally

generated.

Multiprocessing

Host Processor Interface

The ADSP-2106x offers powerful features tailored to multi-

processing DSP systems. The unified address space (see

Figure 4) allows direct interprocessor accesses of each ADSP-

2106x’s internal memory. Distributed bus arbitration logic is

included on-chip for simple, glueless connection of systems

containing up to six ADSP-2106xs and a host processor. Master

processor changeover incurs only one cycle of overhead. Bus

arbitration is selectable as either fixed or rotating priority. Bus lock

allows indivisible read-modify-write sequences for semaphores. A

vector interrupt is provided for interprocessor commands. Maxi-

mum throughput for interprocessor data transfer is 240 Mbytes/s

over the link ports or external port. Broadcast writes allow simulta-

neous transmission of data to all ADSP-2106xs and can be used

to implement reflective semaphores.

The ADSP-2106x’s host interface allows easy connection to

standard microprocessor buses, both 16-bit and 32-bit, with

little additional hardware required. Asynchronous transfers at

speeds up to the full clock rate of the processor are supported.

The host interface is accessed through the ADSP-2106x’s exter-

nal port and is memory-mapped into the unified address space.

Four channels of DMA are available for the host interface; code

and data transfers are accomplished with low software overhead.

The host processor requests the ADSP-2106x’s external bus

with the host bus request (HBR), host bus grant (HBG), and

ready (REDY) signals. The host can directly read and write the

internal memory of the ADSP-2106x, and can access the DMA

channel setup and mailbox registers. Vector interrupt support is

provided for efficient execution of host commands.

Link Ports

The ADSP-2106x features six 4-bit link ports that provide addi-

tional I/O capabilities. The link ports can be clocked twice per

cycle, allowing each to transfer eight bits per cycle. Link port

I/O is especially useful for point-to-point interprocessor commu-

nication in multiprocessing systems.

DMA Controller

The ADSP-2106x’s on-chip DMA controller allows zero-

overhead data transfers without processor intervention. The

DMA controller operates independently and invisibly to the

processor core, allowing DMA operations to occur while the

core is simultaneously executing its program instructions.

The link ports can operate independently and simultaneously,

with a maximum data throughput of 240 Mbytes/s. Link port

data is packed into 32- or 48-bit words, and can be directly read

by the core processor or DMA-transferred to on-chip memory.

DMA transfers can occur between the ADSP-2106x’s internal

memory and either external memory, external peripherals or a

host processor. DMA transfers can also occur between the

ADSP-2106x’s internal memory and its serial ports or link

ports. DMA transfers between external memory and external

peripheral devices are another option. External bus packing to

16-, 32-, or 48-bit words is performed during DMA transfers.

Each link port has its own double-buffered input and output

registers. Clock/acknowledge handshaking controls link port

transfers. Transfers are programmable as either transmit or

receive.

Ten channels of DMA are available on the ADSP-2106x—two

via the link ports, four via the serial ports, and four via the

processor’s external port (for either host processor, other

ADSP-2106xs, memory or I/O transfers). Four additional link

port DMA channels are shared with serial port 1 and the exter-

nal port. Programs can be downloaded to the ADSP-2106x

using DMA transfers. Asynchronous off-chip peripherals can

control two DMA channels using DMA Request/Grant lines

(DMAR1-2, DMAG1-2). Other DMA features include inter-

rupt generation upon completion of DMA transfers and DMA

chaining for automatic linked DMA transfers.

Program Booting

The internal memory of the ADSP-2106x can be booted at

system power-up from either an 8-bit EPROM, a host proces-

sor, or through one of the link ports. Selection of the boot

source is controlled by the BMS (Boot Memory Select),

EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins.

32-bit and 16-bit host processors can be used for booting.

REV. B

–5–

ADSP-21060C/ADSP-21060LC

ADSP-2106x #6

ADSP-2106x #5

ADSP-2106x #4

ADSP-2106x #3

ADDR

CLKIN

31-0

DATA

47-0

RESET

RPBA

3

011

ID

2-0

CONTROL

CPA

5

BR , BR

1-2 4-6

BR

3

ADSP-2106x #2

CLKIN

RESET

RPBA

ADDR

31-0

DATA

47-0

3

ID

010

2-0

CONTROL

CPA

BR , BR

5

1

3-6

BR

2

ADSP-2106x #1

1x

CLOCK

CLKIN

ADDR

DATA

ADDR

DATA

31-0

RESET

GLOBAL

MEMORY

47-0

AND

PERIPHERALS

(OPTIONAL)

OE

RD

WR

ACK

RPBA

WE

ACK

CS

3

001

ID

2-0

MS

3-0

CS

BMS

PAGE

SBTS

BOOT

EPROM

(OPTIONAL)

ADDR

CONTROL

DATA

SW

ADRCLK

CS

HBR

HBG

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

REDY

ADDR

DATA

CPA

5

BR

2-6

BR

1

Figure 3. Shared Memory Multiprocessing System

REV. B

–6–

ADSP-21060C/ADSP-21060LC

0x0000 0000

0x0002 0000

0x0040 0000

IOP REGISTERS

BANK 0

INTERNAL

MEMORY

SPACE

MS

0

1

2

NORMAL WORD ADDRESSING

SHORT WORD ADDRESSING

DRAM

(OPTIONAL)

0x0004 0000

0x0008 0000

INTERNAL MEMORY SPACE

OF ADSP-2106x

BANK 1

BANK 2

WITH ID=001

0x0010 0000

0x0018 0000

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=010

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=011

EXTERNAL

MEMORY

SPACE

0x0020 0000

0x0028 0000

MULTIPROCESSOR

MEMORY SPACE

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=100

MS

BANK 3

3

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=101

BANK SIZE IS

0x0030 0000

0x0038 0000

0x003F FFFF

SELECTED BY

MSIZE BIT FIELD OF

SYSCON

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=110

REGISTER.

BROADCAST WRITE

TO ALL

NONBANKED

ADSP-2106xs

NORMAL WORD ADDRESSING: 32-BIT DATA WORDS

48-BIT INSTRUCTION WORDS

SHORT WORD ADDRESSING: 16-BIT DATA WORDS

0xFFFF FFFF

Figure 4. ADSP-21060C/ADSP-21060LC Memory Map

DEVELOPMENT TOOLS

Further details and ordering information are available in the

ADSP-21000 Family Hardware and Software Development Tools

data sheet (ADDS-210xx-TOOLS). This data sheet can be

requested from any Analog Devices sales office or distributor.

The ADSP-21060C is supported with a complete set of software

and hardware development tools, including an EZ-ICEIn-

Circuit Emulator, EZ-Kit, and development software. The

SHARC EZ-Kit is a complete low cost package for DSP evalua-

tion and prototyping. The EZ-Kit contains a PC plug-in card

(EZ-LAB^®) with an ADSP-21062 (5 V) processor. The EZ-Kit

also includes an optimizing compiler, assembler, instruction

level simulator, run-time libraries, diagnostic utilities and a

complete set of example programs.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC PC plug-in cards multiprocessor

SHARC VME boards, and daughter and modules with multiple

SHARCs and additional memory. These modules are based on

the SHARCPAC™ module specification. Third Party software

tools include an Ada compiler, DSP libraries, operating systems

and block diagram design tools.

Analog Devices ADSP-21000 Family Development Software

includes an easy to use Assembler based on an algebraic syntax,

Assembly Library/Librarian, Linker, instruction-level Simulator,

an ANSI C optimizing Compiler, the CBug™ C Source—Level

Debugger and a C Runtime Library including DSP and math-

ematical functions. The ADSP-21000 Family Development

Software is available for both the PC and Sun platforms.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21060C

architecture and functionality. For detailed information on the

ADSP-21000 Family core architecture and instruction set, refer to

the ADSP-2106x SHARC User’s Manual, Second Edition.

The ADSP-2106x EZ-ICEEmulator uses the IEEE 1149.1 JTAG

test access port of the ADSP-2106x processor to monitor and

control the target board processor during emulation. The EZ-ICE

provides full-speed emulation, allowing inspection and modifi-

cation of memory, registers, and processor stacks. Nonintrusive

in-circuit emulation is assured by the use of the processor’s

JTAG interface—the emulator does not affect target system

loading or timing.

CBUG and SHARCPAC are trademarks of Analog Devices, Inc.

EZ-LAB is a registered trademark of Analog Devices, Inc.

REV. B

–7–

ADSP-21060C/ADSP-21060LC

PIN FUNCTION DESCRIPTIONS

ADSP-21060C pin definitions are listed below. All pins are

identical on the ADSP-21060C and ADSP-21060LC. Inputs

identified as synchronous (S) must meet timing requirements

with respect to CLKIN (or with respect to TCK for TMS,

TDI). Inputs identified as asynchronous (A) can be asserted

asynchronously to CLKIN (or to TCK for TRST).

DRx, TCLKx, RCLKx, LxDAT_3-0, LxCLK, LxACK, TMS and

TDI)—these pins can be left floating. These pins have a logic-

level hold circuit that prevents the input from floating

internally.

A = Asynchronous

O = Output

G = Ground

P = Power Supply

(O/D) = Open Drain

I = Input

S = Synchronous

(A/D) = Active Drive

Unused inputs should be tied or pulled to VDD or GND,

except for ADDR_31-0, DATA_47-0, FLAG_3-0, SW, and inputs that

have internal pull-up or pull-down resistors (CPA, ACK, DTx,

T = Three-State (when SBTS is asserted, or when the

ADSP-2106x is a bus slave)

Type

Function

ADDR_31-0

I/O/T

External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals on

these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the internal

memory or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host

processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.

DATA_47-0

I/O/T

O/T

External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit

single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the

bus. 40-bit extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short

word data is transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over

bits 23–16. Pull-up resistors on unused DATA pins are not necessary.

MS_3-0

Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of

external memory. Memory bank size must be defined in the ADSP-2106x’s system control register

(SYSCON). The MS_3-0lines are decoded memory address lines that change at the same time as the

other address lines. When no external memory access is occurring the MS_3-0lines are inactive; they are

active however when a conditional memory access instruction is executed, whether or not the condition

is true. MS₀can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a

multiprocessing system the MS_3-0lines are output by the bus master.

RD

I/O/T

O/T

Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memory

devices or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-

2106xs) must assert RD to read from the ADSP-2106x’s internal memory. In a multiprocessing system

RD is output by the bus master and is input by all other ADSP-2106xs.

WR

Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memory

devices or to the internal memory of other ADSP-2106xs. External devices must assert WR to write to

the ADSP-2106x’s internal memory. In a multiprocessing system WR is output by the bus master and

is input by all other ADSP-2106xs.

PAGE

DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM page

boundary has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control

register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can

only be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.

ADRCLK

O/T

Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.

SW

I/O/T

Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous

memory devices (including other ADSP-2106xs). The ADSP-2106x asserts SW (low) to provide an

early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in a

conditional write instruction). In a multiprocessing system, SW is output by the bus master and is

input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write.

SW is asserted at the same time as the address output. A host processor using synchronous writes must

assert this pin when writing to the ADSP-2106x(s).

ACK

I/O/S

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external

memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off

completion of an external memory access. The ADSP-2106x deasserts ACK as an output to add wait

states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-

2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory.

The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was

last driven.

REV. B

–8–

ADSP-21060C/ADSP-21060LC

Type

Function

SBTS

I/S

Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address,

data, selects and strobes in a high impedance state for the following cycle. If the ADSP-2106x

attempts to access external memory while SBTS is asserted, the processor will halt and the memory

access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host

processor/ADSP-2106x deadlock, or used with a DRAM controller.

IRQ_2-0

I/A

Interrupt Request Lines. May be either edge-triggered or level-sensitive.

FLAG_3-0

I/O/A

Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be

tested as a condition. As an output, it can be used to signal external peripherals.

TIMEXP

O

Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to

zero.

HBR

I/A

Host Bus Request. Must be asserted by a host processor to request control of the ADSP-2106x’s

external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master

will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address,

data, select and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus

requests (BR_6-1) in a multiprocessing system.

HBG

CS

I/O

I/A

Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take

control of the external bus. HBG is asserted (held low) by the ADSP-2106x until HBR is released. In a

multiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others.

Chip Select. Asserted by host processor to select the ADSP-2106x.

REDY (O/D) O

Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchro-

nous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can

be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be

output if the CS and HBR inputs are asserted.

DMAR1

DMAR2

DMAG1

DMAG2

BR_6-1

I/A

DMA Request 1 (DMA Channel 7).

DMA Request 2 (DMA Channel 8).

DMA Grant 1 (DMA Channel 7).

DMA Grant 2 (DMA Channel 8).

I/A

O/T

I/O/S

Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-

ship. An ADSP-2106x only drives its own BRx line (corresponding to the value of its ID_2-0inputs) and

monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins

should be pulled high; the processor’s own BRx line must not be pulled high or low because it is an

output.

ID_2-0

I

Multiprocessing ID. Determines which multiprocessing bus request (BR1 – BR6) is used by ADSP-

2106x. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor

systems. These lines are a system configuration selection which should be hardwired or only changed

at reset.

RPBA

I/S

I/O

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor

bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con-

figuration selection which must be set to the same value on every ADSP-2106x. If the value of RPBA is

changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.

CPA (O/D)

Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-2106x bus slave

to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain

output that is connected to all ADSP-2106xs in the system. The CPA pin has an internal 5 kΩ pull-up

resistor. If core access priority is not required in a system, the CPA pin should be left unconnected.

DTx

O

Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.

Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.

Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.

Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.

DRx

I

TCLKx

RCLKx

I/O

REV. B

–9–

ADSP-21060C/ADSP-21060LC

Type

Function

TFSx

I/O

Transmit Frame Sync (Serial Ports 0, 1).

Receive Frame Sync (Serial Ports 0, 1).

RFSx

I/O

LxDAT_3-0

I/O

Link Port Data (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is

enabled or disabled by the LPDRD bit of the LCOM register.

LxCLK

LxACK

EBOOT

I/O

I

Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is

enabled or disabled by the LPDRD bit of the LCOM register.

Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistor

that is enabled or disabled by the LPDRD bit of the LCOM register.

EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-

bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table

below. This signal is a system configuration selection that should be hardwired.

LBOOT

I

Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When

LBOOT is low, the ADSP-2106x is configured for host processor booting or no booting. See table

below. This signal is a system configuration selection that should be hardwired.

BMS

I/O/T*

Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,

LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indi-

cates that no booting will occur and that ADSP-2106x will begin executing instructions from external

memory. See table below. This input is a system configuration selection that should be hardwired.

*Three-statable only in EPROM boot mode (when BMS is an output).

EBOOT

LBOOT

BMS

Booting Mode

1

0

1

0

1

0

1

Output

EPROM (Connect BMS to EPROM chip select.)

Host Processor

Link Port

No Booting. Processor executes from external memory.

Reserved

1 (Input)

0 (Input)

x (Input)

CLKIN

I

Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN.

CLKIN may not be halted, changed, or operated below the minimum specified frequency.

RESET

I/A

Processor Reset. Resets the ADSP-2106x to a known state and begins execution at the program

memory location specified by the hardware reset vector address. This input must be asserted (low) at

power-up.

TCK

TMS

I

Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.

I/S

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up

resistor.

TDI

I/S

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal

pull-up resistor.

TDO

O

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-

up or held low for proper operation of the ADSP-2106x. TRST has a 20 kΩ internal pull-up resistor.

EMU (O/D)

ICSA

O

P

Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.

Reserved, leave unconnected.

VDD

Power Supply; nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins).

Power Supply Return. (30 pins).

GND

G

NC

Do Not Connect. Reserved pins which must be left open and unconnected.

REV. B

–10–

ADSP-21060C/ADSP-21060LC

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1

JTAG test access port of the ADSP-2106x to monitor and control

the target board processor during emulation. The EZ-ICE probe

requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST, TDI,

TDO, EMU, and GND signals be made accessible on the target

system via a 14-pin connector (a 2 row × 7 pin strip header) such

as that shown in Figure 5. The EZ-ICE probe plugs directly onto

this connector for chip-on-board emulation. You must add this

connector to your target board design if you intend to use the

ADSP-2106x EZ-ICE. The total trace length between the EZ-

ICE connector and the furthest device sharing the EZ-ICE

JTAG pins should be limited to 15 inches maximum for guaran-

teed operation. This length restriction must include EZ-ICE

JTAG signals that are routed to one or more ADSP-2106x

devices, or a combination of ADSP-2106x devices and other

JTAG devices on the chain.

The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —

Pin 3 must be removed from the header. The pins must be

0.025 inch square and at least 0.20 inch in length. Pin spacing

should be 0.1 × 0.1 inches. Pin strip headers are available from

vendors such as 3M, McKenzie and Samtec.

The BTMS, BTCK, BTRST and BTDI signals are provided so

the test access port can also be used for board-level testing.

When the connector is not being used for emulation, place

jumpers between the Bxxx pins and the xxx pins. If the test

access port will not be used for board testing, tie BTRST to GND

and tie or pull BTCK up to VDD. The TRST pin must be

asserted after power-up (through BTRST on the connector) or

held low for proper operation of the ADSP-2106x. None of the

Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICEprobe.

The JTAG signals are terminated on the EZ-ICE probe as

follows:

Signal Termination

1

2

TMS

TCK

Driven through 22 Ω Resistor (16 mA Driver)

Driven at 10 MHz through 22 Ω Resistor (16 mA

Driver)

EMU

GND

3

5

4

6

KEY (NO PIN)

CLKIN (OPTIONAL)

TMS

TRST* Active Low Driven through 22 Ω Resistor (16 mA

Driver) (Pulled Up by On-Chip 20 kΩ Resistor)

BTMS

TDI

TDO

Driven by 22 Ω Resistor (16 mA Driver)

7

9

8

One TTL Load, Split Termination (160/220)

TCK

BTCK

CLKIN One TTL Load, Split Termination (160/220)

10

12

EMU

Active Low 4.7 kΩ Pull-Up Resistor, One TTL Load

(Open-Drain Output from the DSP)

BTRST

TRST

9

11

*TRST is driven low until the EZ-ICE probe is turned on by the emulator at

software start-up. After software start-up, TRST is driven high.

BTDI

GND

TDI

13

14

Figure 6 shows JTAG scan path connections for systems that

contain multiple ADSP-2106x processors.

TDO

TOP VIEW

Figure 5. Target Board Connector for ADSP-2106x EZ-ICE

Emulator (Jumpers in Place)

JTAG

DEVICE

(OPTIONAL)

ADSP-2106x

#1

n

TDI

TDO

TDI

EZ-ICE

JTAG

CONNECTOR

OTHER

JTAG

CONTROLLER

TCK

TMS

EMU

TRST

TDO

CLKIN

OPTIONAL

Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems

REV. B

–11–

ADSP-21060C/ADSP-21060LC

Connecting CLKIN to Pin 4 of the EZ-ICEheader is optional.

The emulator only uses CLKIN when directed to perform op-

erations such as starting, stopping and single-stepping multiple

ADSP-21060 in a synchronous manner. If you do not need these

operations to occur synchronously on the multiple processors,

simply tie Pin 4 of the EZ-ICE header to ground.

CLKIN and EMU should be treated as critical signals in terms

of skew, and should be laid out as short as possible on your

board. If TCK, TMS and CLKIN are driving a large number of

ADSP-21060 (more than eight) in your system, then treat them

as a clock tree using multiple drivers to minimize skew. (See

Figure 7, JTAG Clock Tree, and Clock Distribution in the

High Frequency Design Considerations section of the ADSP-

2106x User’s Manual, Second Edition.)

If synchronous multiprocessor operations are needed and CLKIN

is connected, clock skew between the multiple ADSP-21060C/

ADSP-21060LC processors and the CLKIN pin on the EZ-ICE

header must be minimal. If the skew is too large, synchronous

operations may be off by one or more cycles between proces-

sors. For synchronous multiprocessor operation TCK, TMS,

If synchronous multiprocessor operations are not needed (i.e.,

CLKIN is not connected), just use appropriate parallel termina-

tion on TCK and TMS. TDI, TDO, EMU, and TRST are not

critical signals in terms of skew.

For complete information on the SHARC EZ-ICE, see the ADSP-

2100 Family JTAG EZ-ICE User’s Guide and Reference.

TDI

TDO

TDI

TDO

TDI

TDO

5kꢀ

*

TDI

TDO

TDI

TDO

TDI

TDO

TDI

5kꢀ

*

EMU

TCK

TMS

TRST

TDO

SYSTEM

CLKIN

EMU

*

OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,

Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems

REV. B

–12–

ADSP-21060C/ADSP-21060LC

ADSP-21060C–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS (5 V)

K Grade

Parameter

Test Conditions

Min

Max

Unit

V_DD

T_CASE

V_IH1

V_IH2

V_IL

Supply Voltage

4.75

–40

2.0

2.2

–0.5

5.25

+100

V_DD+ 0.5

+0.8

V

°C

V

Case Operating Temperature

High Level Input Voltage¹

High Level Input Voltage²

Low Level Input Voltage^{1, 2}

@ V_DD= max

@ V_DD= min

NOTES

¹Applies to input and bidirectional pins: DATA_47-0, ADDR_31-0, RD, WR, SW, ACK, SBTS, IRQ_2-0, FLAG_3-0, HBG, CS, DMAR1, DMAR2, BR_6-1, ID_2-0, RPBA,

CPA, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.

²Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS (5 V)

Parameter

Test Conditions

Min

Max

Unit

V_OH

V_OL

I_IH

I_IL

I_ILP

I_OZH

I_OZL

I_OZHP

I_OZLC

I_OZLA

I_OZLAR

I_OZLS

C_IN

High Level Output Voltage¹

Low Level Output Voltage¹

High Level Input Current^{3, 4}

Low Level Input Current³

@ V_DD= min, I_OH= –2.0 mA²

@ V_DD= min, I_OL= 4.0 mA²

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= 1.5 V

@ V_DD= max, V_IN= 0 V

4.1

V

0.4

10

150

10

350

1.5

350

4.2

150

4.7

µA

mA

µA

mA

µA

pF

Low Level Input Current⁴

Three-State Leakage Current^{5, 6, 7, 8}

Three-State Leakage Current^{5, 9}

Three-State Leakage Current⁹

Three-State Leakage Current⁷

Three-State Leakage Current¹⁰

Three-State Leakage Current⁸

Three-State Leakage Current⁶

Input Capacitance^{11, 12}

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 2.5 V

NOTES

¹¹Applies to output and bidirectional pins: DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3-0, TIMEXP, HBG, REDY, DMAG1,

DMAG2, BR_6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

¹²See “Output Drive Currents” for typical drive current capabilities.

¹³Applies to input pins: SBTS, IRQ_2-0, HBR, CS, DMAR1, DMAR2, ID_2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

¹⁴Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

¹⁵Applies to three-statable pins: DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR_6–1

,

TFS_X, RFS_X, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID_2-0= 001 and another ADSP-21060 is

not requesting bus mastership.)

¹⁶Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

¹⁷Applies to CPA pin.

¹⁸Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID_2-0= 001 and another

ADSP-21060 is not requesting bus mastership).

¹⁹Applies to three-statable pins with internal pull-downs: LxDAT_3-0, LxCLK, LxACK.

¹⁰Applies to ACK pin when keeper latch enabled.

¹¹Applies to all signal pins.

¹²Guaranteed but not tested.

Specifications subject to change without notice.

–13–

REV. B

ADSP-21060C/ADSP-21060LC

POWER DISSIPATION ADSP-21060C (5 V)

These specifications apply to the internal power portion of V_DDonly. See the Power Dissipation section of this data sheet for calcula-

tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see

the technical note “SHARC Power Dissipation Measurements.”

Specifications are based on the following operating scenarios:

Operation

Peak Activity (I_DDINPEAK

)

High Activity (I_DDINHIGH

)

Low Activity (I_DDINLOW)

Instruction Type

Multifunction

Single Function

Instruction Fetch

Cache

Internal Memory

1 per Cycle (DM)

1 per 2 Cycles

Internal Memory

None

Core Memory Access

Internal Memory DMA

2 per Cycle (DM and PM)

1 per Cycle

1 per 2 Cycles

To estimate power consumption for a specific application, use the following equation where % is the amount of time your program

spends in that state:

%PEAK × I_DDINPEAK+ %HIGH × I_DDINHIGH+ %LOW × I_DDINLOW+ %IDLE × I_DDIDLE= power consumption

Parameter

Test Conditions

Max

Unit

I_DDINPEAK

Supply Current (Internal)¹

Supply Current (Internal)²

Supply Current (Idle)³

t_CK= 30 ns, V_DD= max

t_CK= 25 ns, V_DD= max

745

850

mA

I_DDINHIGH

t_CK= 30 ns, V_DD= max

t_CK= 25 ns, V_DD= max

575

670

mA

I_DDINLOW

t_CK= 30 ns, V_DD= max

t_CK= 25 ns, V_DD= max

340

390

mA

I_DDIDLE

V_DD= max

200

mA

NOTES

¹The test program used to measure I_DDINPEAKrepresents worst case processor operation and is not sustainable under normal application conditions. Actual internal

power measurements made using typical applications are less than specified.

²I_DDINHIGHis a composite average based on a range of high activity code. I_DDINLOWis a composite average based on a range of low activity code.

³Idle denotes ADSP-21060C state during execution of IDLE instruction.

REV. B

–14–

ADSP-21060C/ADSP-21060LC

ADSP-21060LC–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS (3.3 V)

K Grade

Parameter

Test Conditions

Min

Max

Unit

V_DD

T_CASE

V_IH1

V_IH2

V_IL

Supply Voltage

3.15

–40

2.0

2.2

–0.5

3.45

+100

V_DD+ 0.5

0.8

V

°C

V

Case Operating Temperature

High Level Input Voltage¹

High Level Input Voltage²

Low Level Input Voltage^{1, 2}

@ V_DD= max

@ V_DD= min

NOTES

¹Applies to input and bidirectional pins: DATA_47-0, ADDR_31-0, RD, WR, SW, ACK, SBTS, IRQ_2-0, FLAG_3-0, HBG, CS, DMAR1, DMAR2, BR_6-1, ID_2-0, RPBA,

CPA, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0,

RCLK1.

²Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS (3.3 V)

Parameter

Test Conditions

Min

Max

Unit

V_OH

V_OL

I_IH

I_IL

I_ILP

I_OZH

I_OZL

I_OZHP

I_OZLC

I_OZLA

I_OZLAR

I_OZLS

C_IN

High Level Output Voltage¹

Low Level Output Voltage¹

High Level Input Current^{3, 4}

Low Level Input Current³

@ V_DD= min, I_OH= –2.0 mA²

@ V_DD= min, I_OL= 4.0 mA²

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= 2 V

@ V_DD= max, V_IN= 0 V

2.4

V

0.4

10

150

10

350

1.5

350

4.2

150

4.7

µA

mA

µA

mA

µA

pF

Low Level Input Current⁴

Three-State Leakage Current^{5, 6, 7, 8}

Three-State Leakage Current^{5, 9}

Three-State Leakage Current⁹

Three-State Leakage Current⁷

Three-State Leakage Current¹⁰

Three-State Leakage Current⁸

Three-State Leakage Current⁶

Input Capacitance^{11, 12}

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 2.5 V

NOTES

¹¹Applies to output and bidirectional pins: DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3-0, TIMEXP, HBG, REDY, DMAG1,

DMAG2, BR_6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

¹²See “Output Drive Currents” for typical drive current capabilities.

¹³Applies to input pins: ACK SBTS, IRQ_2-0, HBR, CS, DMAR1, DMAR2, ID_2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

¹⁴Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

¹⁵Applies to three-statable pins: DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR_6–1

,

TFS_X, RFS_X, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID_2-0= 001 and another ADSP-21060LC

is not requesting bus mastership.)

¹⁶Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

¹⁷Applies to CPA pin.

¹⁸Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID_2-0= 001 and another

ADSP-21060LC is not requesting bus mastership).

¹⁹Applies to three-statable pins with internal pull-downs: LxDAT_3-0, LxCLK, LxACK.

¹⁰Applies to ACK pin when keeper latch enabled.

¹¹Applies to all signal pins.

¹²Guaranteed but not tested.

Specifications subject to change without notice.

REV. B

–15–

ADSP-21060C/ADSP-21060LC

POWER DISSIPATION ADSP-21060LC (3.3 V)

These specifications apply to the internal power portion of V_DDonly. See the Power Dissipation section of this data sheet for calcula-

tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,

see the technical note “SHARC Power Dissipation Measurements.”

Specifications are based on the following operating scenarios:

Operation

Peak Activity (I_DDINPEAK

Multifunction

)

High Activity (I_DDINHIGH

Multifunction

)

Low Activity (I_DDINLOW

Single Function

Internal Memory

None

)

Instruction Type

Instruction Fetch

Core Memory Access

Internal Memory DMA

Cache

Internal Memory

1 per Cycle (DM)

1 per 2 Cycles

2 per Cycle (DM and PM)

1 per Cycle

1 per 2 Cycles

To estimate power consumption for a specific application, use the following equation where % is the amount of time your program

spends in that state:

%PEAK × I_DDINPEAK+ %HIGH × I_DDINHIGH+ %LOW × I_DDINLOW+ %IDLE × I_DDIDLE= power consumption

Parameter

Test Conditions

Max

Unit

I_DDINPEAK

Supply Current (Internal)¹

Supply Current (Internal)²

Supply Current (Idle)³

t_CK= 30 ns, V_DD= max

t_CK= 25 ns, V_DD= max

540

600

mA

I_DDINHIGH

I_DDINLOW

t_CK= 30 ns, V_DD= max

t_CK= 25 ns, V_DD= max

425

475

mA

t_CK= 30 ns, V_DD= max

t_CK= 25 ns, V_DD= max

250

275

mA

I_DDIDLE

V_DD= max

180

mA

NOTES

¹The test program used to measure I_DDINPEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal

power measurements made using typical applications are less than specified.

²I_DDINHIGHis a composite average based on a range of high activity code. I_DDINLOWis a composite average based on a range of low activity code.

³Idle denotes ADSP-21060LC state during execution of IDLE instruction.

REV. B

–16–

ADSP-21060C/ADSP-21060LC

ABSOLUTE MAXIMUM RATINGS (3.3 V)*

ABSOLUTE MAXIMUM RATINGS (5 V)*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . . 280°C

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . 280°C

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at these

or any other conditions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at these

or any other conditions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-21060C/ADSP-21060LC features proprietary ESD pro-

tection circuitry, permanent damage may occur on devices subjected to high-energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid

performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

See Figure 28 under Test Conditions for voltage reference

levels.

TIMING SPECIFICATIONS

Two speed grades of the ADSP-21060C are offered, 40 MHz

and 33.3 MHz. The specifications shown are based on a

CLKIN frequency of 40 MHz (t_CK= 25 ns). The DT derating

allows specifications at other CLKIN frequencies (within the

min–max range of the t_CKspecification; see Clock Input below).

DT is the difference between the actual CLKIN period and a

CLKIN period of 25 ns:

Switching Characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

DT = t_CK– 25 ns

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a

read operation. Timing requirements guarantee that the proces-

sor operates correctly with other devices.

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add parameters to derive longer times.

(O/D) = Open Drain

(A/D) = Active Drive

REV. B

–17–

ADSP-21060C/ADSP-21060LC

ADSP-21060C

40 MHz 33 MHz

ADSP-21060LC

40 MHz 33 MHz

Min Max Unit

Parameter

Min

Max

Min

Max

Min

Max

Clock Input

Timing Requirements:

t_CK

CLKIN Period

25

7

5

100

3

30

7

5

100

3

25

9.5

5

100

3

30

9.5

5

100

3

ns

t_CKL

t_CKH

t_CKRF

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V–2.0 V)

t_CK

CLKIN

t_CKH

t_CKL

Figure 8. Clock Input

ADSP-21060C

ADSP-21060LC

Max

Parameter

Reset

Min

Max

Min

Unit

Timing Requirements:

t_WRST

RESET Pulsewidth Low¹

t_SRST

RESET Setup before CLKIN High²

4t_CK

14 + DT/2

4t_CK

14 + DT/2 t_CK

ns

t_CK

NOTES

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET

is low, assuming stable V_DDand CLKIN (not including start-up time of external clock oscillator).

²Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required

for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.

CLKIN

t_SRST

t_WRST

RESET

Figure 9. Reset

ADSP-21060C

ADSP-21060LC

Parameter

Min

Max

Min

Max

Unit

Interrupts

Timing Requirements:

t_SIR

t_HIR

t_IPW

IRQ2-0 Setup before CLKIN High¹

18 + 3DT/4

2 + t_CK

18 + 3DT/4

2 + t_CK

ns

IRQ2-0 Hold before CLKIN High¹

IRQ2-0 Pulsewidth²

12 + 3DT/4

NOTES

¹Only required for IRQx recognition in the following cycle.

²Applies only if t_SIRand t_HIRrequirements are not met.

CLKIN

t_SIR

t_HIR

IRQ2-0

t_IPW

Figure 10. Interrupts

REV. B

–18–

ADSP-21060C/ADSP-21060LC

ADSP-21060C

ADSP-21060LC

Parameter

Min

Max

Min

Max

Unit

Timer

Switching Characteristic:

t_DTEX

CLKIN High to TIMEXP

15

ns

CLKIN

t_DTEX

TIMEXP

Figure 11. Timer

ADSP-21060C

ADSP-21060LC

Parameter

Flags

Min

Max

Min

Max

Unit

Timing Requirements:

t_SFI

t_HFI

t_DWRFI

t_HFIWR

FLAG3-0_INSetup before CLKIN High¹

FLAG3-0_INHold after CLKIN High¹

FLAG3-0_INDelay after RD/WR Low¹

FLAG3-0_INHold after RD/WR Deasserted¹

8 + 5DT/16

0 – 5DT/16

8 + 5DT/16

0 – 5DT/16

ns

5 + 7DT/16

0

Switching Characteristics:

t_DFO

FLAG3-0_OUTDelay after CLKIN High

16

14

16

14

ns

t_HFO

t_DFOE

t_DFOD

FLAG3-0_OUTHold after CLKIN High

CLKIN High to FLAG3-0_OUTEnable

CLKIN High to FLAG3-0_OUTDisable

4

3

4

3

NOTE

¹Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.

CLKIN

t_DFOE

t_DFO

t_DFOD

t_HFO

FLAG3-0

OUT

FLAG OUTPUT

CLKIN

t_HFI

t_SFI

FLAG3-0

IN

t_HFIWR

t_DWRFI

RD, WR

FLAG INPUT

Figure 12. Flags

REV. B

–19–

ADSP-21060C/ADSP-21060LC

Memory Read—Bus Master

characteristics also apply for bus master synchronous read/write

timing (see Synchronous Read/Write – Bus Master below). If

these timing requirements are met, the synchronous read/write

timing can be ignored (and vice versa).

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-2106x is

the bus master accessing external memory space. These switching

ADSP-21060C

ADSP-21060LC

Max

Parameter

Min

Max

Min

Unit

Timing Requirements:

t_DAD

t_DRLD

t_HDA

t_HDRH

t_DAAK

t_DSAK

Address, Selects Delay to Data Valid^{1, 2}

18 + DT + W

12 + 5DT/8 + W

18 + DT + W

12 + 5DT/8 + W ns

ns

RD Low to Data Valid¹

Data Hold from Address, Selects³

Data Hold from RD High³

0.5

2.0

0.5

2.0

ns

ACK Delay from Address, Selects^{2, 4}

ACK Delay from RD Low⁴

14 + 7DT/8 + W

8 + DT/2 + W

14 + 7DT/8 + W ns

8 + DT/2 + W

ns

Switching Characteristics:

t_DRHA

t_DARL

t_RW

Address, Selects Hold after RD High

0 + H

2 + 3DT/8

12.5 + 5DT/8 + W

8 + 3DT/8 + HI

0 + H

2 + 3DT/8

12.5 + 5DT/8 + W

8 + 3DT/8 + HI

ns

Address, Selects to RD Low²

RD Pulsewidth

t_RWR

RD High to WR, RD, DMAGx Low

t_SADADCAddress, Selects Setup before

ADRCLK High²

0 + DT/4

ns

W = (number of wait states specified in WAIT register) × t_CK.

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t_CK(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

NOTES

¹Data Delay/Setup: User must meet t_DADor t_DRLDor synchronous spec t_SSDATI

.

²The falling edge of MSx, SW, BMS is referenced.

³Data Hold: User must meet t_HDAor t_HDRHor synchronous spec t_HSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times

given capacitive and dc loads.

⁴ACK Delay/Setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SACKCfor deassertion of ACK (Low), all three specifications must be met for asser-

tion of ACK (High).

ADDRESS

MSx, SW

BMS

t_DRHA

t_DARL

t_RW

RD

t_HDA

t_HDRH

t_DRLD

t_DAD

DATA

t_DSAK

t_RWR

t_DAAK

ACK

WR, DMAG

t_SADADC

ADRCLK

(OUT)

Figure 13. Memory Read—Bus Master

REV. B

–20–

ADSP-21060C/ADSP-21060LC

Memory Write—Bus Master

characteristics also apply for bus master synchronous read/write

timing (see Synchronous Read/Write–Bus Master). If these

timing requirements are met, the synchronous read/write timing

can be ignored (and vice versa).

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-2106x is

the bus master accessing external memory space. These switching

ADSP-21060C

ADSP-21060LC

Max

Parameter

Min

Max

Min

Unit

Timing Requirements:

t_DAAK

t_DSAK

ACK Delay from Address, Selects^{1, 2}

14 + 7DT/8 + W

8 + DT/2 + W

14 + 7DT/8 + W ns

ACK Delay from WR Low¹

8 + DT/2 + W

ns

Switching Characteristics:

t_DAWH

t_DAWL

t_WW

t_DDWH

t_DWHA

Address, Selects to WR Deasserted²

17 + 15DT/16 + W

3 + 3DT/8

17 + 15DT/16 + W

3 + 3DT/8

ns

Address, Selects to WR Low²

WR Pulsewidth

12 + 9DT/16 + W

7 + DT/2 + W

0.5 + DT/16 + H

1 + DT/16 + H

8 + 7DT/16 + H

5 + 3DT/8 + I

–1 + DT/16

12 + 9DT/16 + W

7 + DT/2 + W

0.5 + DT/16 + H

1 + DT/16 + H

8 + 7DT/16 + H

5 + 3DT/8 + I

–1 + DT/16

Data Setup before WR High

Address Hold after WR Deasserted

t_DATRWHData Disable after WR Deasserted³

6 + DT/16 + H

t_WWR

t_DDWR

t_WDE

WR High to WR, RD, DMAGx Low

Data Disable before WR or RD Low

WR Low to Data Enabled

t_SADADCAddress, Selects to ADRCLK High²

0 + DT/4

W = (number of wait states specified in WAIT register) × t_CK

.

H = t_CK(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

I = t_CK(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

NOTES

¹ACK Delay/Setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SACKCfor deassertion of ACK (Low), all three specifications must be met for asser-

tion of ACK (High).

²The falling edge of MSx, SW, BMS is referenced.

³See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

ADDRESS

MSx , SW

BMS

t_DWHA

t_DAWH

t_WW

t_DAWL

WR

t_WWR

t_DDWR

t_DDWH

t_WDE

t_DATRWH

DATA

t_DSAK

t_DAAK

ACK

RD , DMAG

t_SADADC

ADRCLK

(OUT)

Figure 14. Memory Write—Bus Master

REV. B

–21–

ADSP-21060C/ADSP-21060LC

Synchronous Read/Write—Bus Master

When accessing a slave ADSP-2106x, these switching character-

istics must meet the slave’s timing requirements for synchronous

read/writes (see Synchronous Read/Write—Bus Slave). The

slave ADSP-2106x must also meet these (bus master) timing

requirements for data and acknowledge setup and hold times.

Use these specifications for interfacing to external memory

systems that require CLKIN—relative timing or for accessing a

slave ADSP-2106x (in multiprocessor memory space). These

synchronous switching characteristics are also valid during asyn-

chronous memory reads and writes (see Memory Read—Bus

Master and Memory Write—Bus Master).

ADSP-21060C

ADSP-21060LC

Max

Parameter

Min

Max

Min

Unit

Timing Requirements:

t_SSDATIData Setup before CLKIN

t_HSDATIData Hold after CLKIN

3 + DT/8

3.5 – DT/8

3 + DT/8

3.5 – DT/8

ns

t_DAAK

ACK Delay after Address, MSx,

SW, BMS^{1, 2}

14 + 7 DT/8 + W

ns

t_SACKCACK Setup before CLKIN²

6.5 + DT/4

–1 – DT/4

6.5 + DT/4

–1 – DT/4

t_HACK

ACK Hold after CLKIN

Switching Characteristics:

t_DADROAddress, MSx, BMS, SW Delay

after CLKIN¹

7 – DT/8

ns

t_HADROAddress, MSx, BMS, SW Hold

after CLKIN

–1 – DT/8

9 + DT/8

–2 – DT/8

–3 – 3DT/16

8 + DT/4

–1 – DT/8

9 + DT/8

–2 – DT/8

–3 – 3DT/16

8 + DT/4

ns

t_DPGC

t_DRDO

t_DWRO

t_DRWL

PAGE Delay after CLKIN

16 + DT/8

4 – DT/8

4 – 3DT/16

12.5 + DT/4

19 + 5DT/16

7 – DT/8

16 + DT/8

4 – DT/8

4 – 3DT/16

12.5 + DT/4

19.25 + 5DT/16

7 – DT/8

RD High Delay after CLKIN

WR High Delay after CLKIN

RD/WR Low Delay after CLKIN

t_SDDATOData Delay after CLKIN

t_DATTRData Disable after CLKIN³

t_DADCCKADRCLK Delay after CLKIN

t_ADRCKADRCLK Period

t_ADRCKHADRCLK Width High

t_ADRCKLADRCLK Width Low

0 – DT/8

4 + DT/8

t_CK

(t_CK/2 – 2)

0 – DT/8

4 + DT/8

t_CK

(t_CK/2 – 2)

10 + DT/8

W = (number of Wait states specified in WAIT register) × t_CK

.

NOTES

¹The falling edge of MSx, SW, BMS is referenced.

²ACK Delay/Setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SACKCfor deassertion of ACK (Low), all three specifications must be met for assertion

of ACK (High).

³See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

REV. B

–22–

ADSP-21060C/ADSP-21060LC

CLKIN

t_ADRCK

t_ADRCKL

t_ADRCKH

t_DADCCK

ADRCLK

t_HADRO

t_DAAK

t_DADRO

ADDRESS

MSx, SW

t_DPGC

PAGE

t_HACK

t_SACKC

ACK

(IN)

READ CYCLE

t_DRWL

t_DRDO

RD

t_HSDATI

t_SSDATI

DATA

(IN)

WRITE CYCLE

t_DWRO

t_DRWL

WR

t_DATTR

t_SDDATO

DATA

(OUT)

Figure 15. Synchronous Read/Write—Bus Master

REV. B

–23–

ADSP-21060C/ADSP-21060LC

Synchronous Read/Write—Bus Slave

memory space). The bus master must meet these (bus slave)

timing requirements.

Use these specifications for ADSP-2106x bus master accesses of

a slave’s IOP registers or internal memory (in multiprocessor

ADSP-21060C

ADSP-21060LC

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

t_SADRI

t_HADRI

t_SRWLI

t_HRWLI

t_RWHPI

Address, SW Setup before CLKIN

15 + DT/2

ns

Address, SW Hold before CLKIN

RD/WR Low Setup before CLKIN¹

RD/WR Low Hold after CLKIN

RD/WR Pulse High

5 + DT/2

9.5 + 5DT/16

–3.5 – 5DT/16

3

5

1

9.5 + 5DT/16

–3.75 – 5DT/16

3

5

1

8 + 7DT/16

t_SDATWHData Setup before WR High

t_HDATWHData Hold after WR High

Switching Characteristics:

t_SDDATOData Delay after CLKIN

t_DATTRData Disable after CLKIN²

t_DACKADACK Delay after Address, SW³

t_ACKTRACK Disable after CLKIN³

19 + 5DT/16

7 – DT/8

9

19.25 + 5DT/16 ns

0 – DT/8

7 – DT/8

9

ns

–1 – DT/8

6 – DT/8

–1 – DT/8

6 – DT/8

NOTES

¹t_SRWLI(min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t _SRWLI(min)

= 4 + DT/8.

²See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

³t_DACKADis true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have

setup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK

regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t_ACKTR

.

CLKIN

t_SADRI

t_HADRI

ADDRESS

SW

t_DACKAD

t_ACKTR

ACK

READ ACCESS

t_SRWLI

t_HRWLI

t_RWHPI

RD

t_SDDATO

t_DATTR

DATA

(OUT)

WRITE ACCESS

t_RWHPI

t_SRWLI

t_HRWLI

WR

t_HDATWH

t_SDATWH

DATA

(IN)

Figure 16. Synchronous Read/Write—Bus Slave

REV. B

–24–

ADSP-21060C/ADSP-21060LC

Multiprocessor Bus Request and Host Bus Request

Use these specifications for passing of bus mastership between

multiprocessing ADSP-2106xs (BRx) or a host processor

(HBR, HBG).

ADSP-21060C

Max

ADSP-21060LC

Parameter

Min

Max

Unit

Timing Requirements:

t

_HBGRCSVHBG Low to RD/WR/CS Valid¹

20+ 5DT/4

14 + 3DT/4

6 + DT/2

20+ 5DT/4

14 + 3DT/4

6 + DT/2

ns

t_SHBRI

HBR Setup before CLKIN²

20 + 3DT/4

13 + DT/2

21 + 3DT/4

20 + 3DT/4

13 + DT/2

21 + 3DT/4

t_HHBRIHBR Hold before CLKIN²

t_SHBGIHBG Setup before CLKIN

t_HHBGIHBG Hold before CLKIN High

t_SBRI

t_HBRI

BRx, CPA Setup before CLKIN³

BRx, CPA Hold before CLKIN High

6 + DT/2

t_SRPBAIRPBA Setup before CLKIN

t_HRPBAIRPBA Hold before CLKIN

12 + 3DT/4

Switching Characteristics:

t_DHBGOHBG Delay after CLKIN

t_HHBGOHBG Hold after CLKIN

7 – DT/8

ns

–2 – DT/8

t_DBRO

t_HBRO

BRx Delay after CLKIN

BRx Hold after CLKIN

t_DCPAOCPA Low Delay after CLKIN

t_TRCPACPA Disable after CLKIN

t_DRDYCSREDY (O/D) or (A/D) Low from CS

and HBR Low⁴

8 – DT/8

4.5 – DT/8

8.5 – DT/8

4.5 – DT/8

8.5

11.0

ns

t_TRDYHGREDY (O/D) Disable or REDY (A/D)

High from HBG⁴

40 + 23DT/16

t_ARDYTRREDY (A/D) Disable from CS or

HBR High⁴

10

NOTES

¹For first asynchronous access after HBR and CS asserted, ADDR_31-0must be a non-MMS value 1/2 t_CKbefore RD or WR goes low or by t_HBGRCSVafter HBG goes

low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the

ADSP-2106x SHARC User’s Manual, Second Edition.

²Only required for recognition in the current cycle.

³CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.

⁴(O/D) = open drain, (A/D) = active drive.

REV. B

–25–

ADSP-21060C/ADSP-21060LC

CLKIN

t_SHBRI

t_HHBRI

HBR

t_DHBGO

t_HHBGO

HBG

(OUT)

t_DBRO

t_HBRO

BRx

(OUT)

t_TRCPA

t_DCPAO

CPA (OUT)

(O/D)

t_SHBGI

t_HHBGI

HBG (IN)

t_SBRI

t_HBRI

BRx (IN)

CPA (IN) (O/D)

t_SRPBAI

t_HRPBAI

RPBA

HBR AND CS

t_TRDYHG

t_DRDYCS

REDY (O/D)

t_ARDYTR

REDY (A/D)

t_HBGRCSV

HBG (OUT)

RD

WR

CS

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 17. Multiprocessor Bus Request and Host Bus Request

REV. B

–26–

ADSP-21060C/ADSP-21060LC

drive the RD and WR pins to access the ADSP-2106x’s internal

memory or IOP registers. HBR and HBG are assumed low for

this timing.

Asynchronous Read/Write—Host to ADSP-2106x

Use these specifications for asynchronous host processor accesses

of an ADSP-2106x, after the host has asserted CS and HBR

(low). After HBG is returned by the ADSP-2106x, the host can

ADSP-21060C

Max

ADSP-21060LC

Max

Parameter

Min

Unit

Read Cycle

Timing Requirements:

t_SADRDL

t_HADRDH

t_WRWH

Address Setup/CS Low before RD Low¹

Address Hold/CS Hold Low after RD

RD/WR High Width

0

6

0

6

0

ns

t_DRDHRDY

RD High Delay after REDY (O/D) Disable

RD High Delay after REDY (A/D) Disable

Switching Characteristics:

t_SDATRDY

t_DRDYRDL

t_RDYPRD

Data Valid before REDY Disable from Low

2

ns

REDY (O/D) or (A/D) Low Delay after RD Low

REDY (O/D) or (A/D) Low Pulsewidth

for Read

10

12.5

45 + 21DT/16

2

45 + 21DT/16

2

ns

t_HDARWH

Data Disable after RD High

8

8.5

Write Cycle

Timing Requirements:

t_SCSWRL

t_HCSWRH

t_SADWRH

t_HADWRH

t_WWRL

CS Low Setup before WR Low

0

5

2

7

6

0

5

2

7

6

ns

CS Low Hold after WR High

Address Setup before WR High

Address Hold after WR High

WR Low Width

t_WRWH

RD/WR High Width

t_DWRHRDY

WR High Delay after REDY

(O/D) or (A/D) Disable

Data Setup before WR High

Data Hold after WR High

0

5

1

0

5

1

ns

t_SDATWH

t_HDATWH

Switching Characteristics:

t_DRDYWRLREDY (O/D) or (A/D) Low Delay

after WR/CS Low

REDY (O/D) or (A/D) Low Pulsewidth

for Write

10

12.5

ns

t_RDYPWR

15 + 7DT/16

t_SRDYCK

REDY (O/D) or (A/D) Disable to CLKIN

1 + 7DT/16 8 + 7DT/16

1 + 7DT/16 8 + 7DT/16 ns

NOTE

¹Not required if RD and address are valid t_HBGRCSVafter HBG goes low. For first access after HBR asserted, ADDR_31-0must be a non-MMS value 1/2 t_CLKbefore RD

or WR goes low or by t_HBGRCSVafter HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces-

sor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Second Edition.

CLKIN

t_SRDYCK

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 18a. Synchronous REDY Timing

REV. B

–27–

ADSP-21060C/ADSP-21060LC

READ CYCLE

ADDRESS/CS

t_HADRDH

t_SADRDL

t_WRWH

RD

t_HDARWH

DATA (OUT)

t_DRDHRDY

t_SDATRDY

t_RDYPRD

t_DRDYRDL

REDY (O/D)

REDY (A/D)

WRITE CYCLE

ADDRESS

t_HADWRH

t_SADWRH

t_HCSWRH

t_SCSWRL

CS

t_WWRL

t_WRWH

WR

t_HDATWH

t_SDATWH

DATA (IN)

t_DWRHRDY

t_RDYPWR

t_DRDYWRL

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 18b. Asynchronous Read/Write—Host to ADSP-2106x

REV. B

–28–

ADSP-21060C/ADSP-21060LC

and the SBTS pin. This timing is applicable to bus master tran-

sition cycles (BTC) and host transition cycles (HTC) as well as

the SBTS pin.

Three-State Timing—Bus Master, Bus Slave, HBR, SBTS

These specifications show how the memory interface is disabled

(stops driving) or enabled (resumes driving) relative to CLKIN

ADSP-21060C

ADSP-21060LC

Max

Parameter

Min

Max

Min

Unit

Timing Requirements:

t_STSCK

t_HTSCK

SBTS Setup before CLKIN

SBTS Hold before CLKIN

12 + DT/2

ns

6 + DT/2

Switching Characteristics:

t_MIENA

t_MIENS

t_MIENHG

t_MITRA

t_MITRS

t_MITRHG

t_DATEN

t_DATTR

t_ACKEN

t_ACKTR

t_ADCEN

t_ADCTR

Address/Select Enable after CLKIN

–1.5 – DT/8

–1.25 – DT/8

–1.5 – DT/8

ns

Strobes Enable after CLKIN¹

HBG Enable after CLKIN

Address/Select Disable after CLKIN

Strobes Disable after CLKIN¹

HBG Disable after CLKIN

Data Enable after CLKIN²

Data Disable after CLKIN²

ACK Enable after CLKIN²

ACK Disable after CLKIN²

ADRCLK Enable after CLKIN

ADRCLK Disable after CLKIN

0 – DT/4

1.5 – DT/4

2.0 – DT/4

0.25 – DT/4

1.5 – DT/4

2.0 – DT/4

9 + 5DT/16

0 – DT/8

7.5 + DT/4

–1 – DT/8

–2 – DT/8

9 + 5DT/16

0 – DT/8

7.5 + DT/4

–1 – DT/8

–2 – DT/8

7 – DT/8

6 – DT/8

8 – DT/4

7 – DT/8

6 – DT/8

8 – DT/4

t_MTRHBGMemory Interface Disable before

HBG Low³

t_MENHBGMemory Interface Enable after

HBG High³

0 + DT/8

19 + DT

0 + DT/8

19 + DT

ns

NOTES

¹Strobes = RD, WR, SW, PAGE, DMAG.

²In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

³Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).

CLKIN

t_STSCK

t_HTSCK

SBTS

t_MITRA,t_MITRS,t_MITRHG

t_MIENA,t_MIENS,t_MIENHG

MEMORY

INTERFACE

t_DATTR

t_DATEN

DATA

t_ACKTR

t_ACKEN

ACK

t_ADCEN

t_ADCTR

ADRCLK

Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion)

HBG

t_MTRHBG

t_MENHBG

MEMORY

INTERFACE

MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)

Figure 19b. Three-State Timing (Host Transition Cycle)

REV. B

–29–

ADSP-21060C/ADSP-21060LC

DMA Handshake

transfer is controlled by ADDR_31-0, RD, WR, MS_3-0, and ACK

(not DMAG). For Paced Master mode, the Memory Read–Bus

Master, Memory Write–Bus Master, and Synchronous Read/

Write–Bus Master timing specifications for ADDR_31-0, RD, WR,

MS_3-0, SW, PAGE, DATA_47-0, and ACK also apply.

These specifications describe the three DMA handshake modes.

In all three modes DMAR is used to initiate transfers. For hand-

shake mode, DMAG controls the latching or enabling of data

externally. For external handshake mode, the data transfer is

controlled by the ADDR_31-0, RD, WR, SW, PAGE, MS_3-0

,

ACK, and DMAG signals. For Paced Master mode, the data

ADSP-21060C

ADSP-21060LC

Max

Parameter

Min

Max

Min

Unit

Timing Requirements:

t_SDRLC

t_SDRHC

t_WDR

DMARx Low Setup before CLKIN¹

5

ns

DMARx High Setup before CLKIN¹

DMARx Width Low

(Nonsynchronous)

6

2

6

2

ns

t_SDATDGLData Setup after DMAGx Low²

t_HDATIDGData Hold after DMAGx High

t_DATDRHData Valid after DMARx High²

t_DMARLLDMARx Low Edge to Low Edge

10 + 5DT/8

16 + 7DT/8

10 + 5DT/8 ns

ns

16 + 7DT/8 ns

23 + 7DT/8

6

23 + 7DT/8

6

ns

t_DMARH

DMARx Width High

Switching Characteristics:

t_DDGL

t_WDGH

t_WDGL

t_HDGC

DMAGx Low Delay after CLKIN

DMAGx High Width

DMAGx Low Width

9 + DT/4

6 + 3DT/8

12 + 5DT/8

–2 – DT/8

8 + 9DT/16

0

10 + 5DT/8 + W

1 + DT/16

0

11 + 9DT/16 + W

0

15 + DT/4

6 – DT/8

9 + DT/4

6 + 3DT/8

12 + 5DT/8

–2 – DT/8

8 + 9DT/16

0

10 + 5DT/8 + W

1 + DT/16

0

11 + 9DT/16 + W

0

15 + DT/4

6 – DT/8

ns

DMAGx High Delay after CLKIN

t_VDATDGHData Valid before DMAGx High³

t_DATRDGHData Disable after DMAGx High⁴

7

2

7

2

t_DGWRL

t_DGWRH

t_DGWRR

t_DGRDL

t_DRDGH

t_DGRDR

t_DGWR

WR Low before DMAGx Low

DMAGx Low before WR High

WR High before DMAGx High

RD Low before DMAGx Low

RD Low before DMAGx High

RD High before DMAGx High

DMAGx High to WR, RD, DMAGx

Low

3 + DT/16

2

3 + DT/16

2

3

5 + 3DT/8 + HI

17 + DT

ns

t_DADGH

t_DDGHA

Address/Select Valid to DMAGx High 17 + DT

Address/Select Hold after DMAGx

High

–0.5

ns

W = (number of wait states specified in WAIT register) × t_CK

.

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

NOTES

¹Only required for recognition in the current cycle.

²t_SDATDGLis the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the

data can be driven t_DATDRHafter DMARx is brought high.

³t_VDATDGHis valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t_VDATDGH= 8 + 9DT/16 + (n × t_CK) where

n equals the number of extra cycles that the access is prolonged.

⁴See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

REV. B

–30–

ADSP-21060C/ADSP-21060LC

CLKIN

t_SDRLC

t_DMARLL

t_SDRHC

t_WDR

t_DMARH

DMARx

DMAGx

t_HDGC

t_DDGL

t_WDGL

t_WDGH

TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE

t_DATRDGH

t_VDATDGH

DATA (FROM

ADSP-2106x TO

EXTERNAL DRIVE)

t_DATDRH

t_HDATIDG

t_SDATDGL

DATA (FROM

EXTERNAL DRIVE

TO ADSP-2106x)

TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

t_DGWRL

WR

t_DGWRH

t_DGWRR

(EXTERNAL DEVICE

TO EXTERNAL

MEMORY)

t_DGRDR

t_DGRDL

RD

(EXTERNAL

MEMORY TO

EXTERNAL DEVICE)

t_DRDGH

t_DADGH

t_DDGHA

ADDRESS

MSx, SW

*

MEMORY READ – BUS MASTER, MEMORY WRITE – BUS MASTER, AND SYNCHRONOUS READ/WRITE – BUS MASTER

TIMING SPECIFICATIONS FOR ADDR

, RD, WR, SW, MS AND ACK ALSO APPLY HERE.

31-0

3-0

Figure 20. DMA Handshake Timing

REV. B

–31–

ADSP-21060C/ADSP-21060LC

Link Ports: 1 ꢁ CLK Speed Operation

ADSP-21060C

Max

ADSP-21060LC

Max

Parameter

Min

Unit

Receive

Timing Requirements:

t_SLDCL

t_HLDCL

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

Data Setup before LCLK Low

Data Hold after LCLK Low

LCLK Period (1 × Operation)

LCLK Width Low

3.5

3

t_CK

6

3

t_CK

6

5

ns

LCLK Width High

5

Switching Characteristics:

t_DLAHC

t_DLALC

t_ENDLK

t_TDLK

LACK High Delay after CLKIN High

18 + DT/2

–3

5 + DT/2

28.5 + DT/2

13

18 + DT/2

–3

5 + DT/2

29.0 + DT/2

13

ns

LACK Low Delay after LCLK High¹

LACK Enable from CLKIN

LACK Disable from CLKIN

20 + DT/2

Transmit

Timing Requirements:

t_SLACHLACK Setup before LCLK High

t_HLACHLACK Hold after LCLK High

18

–7

20

–7

ns

Switching Characteristics:

t_DLCLK

LCLK Delay after CLKIN (1 × Operation)

15.5

3

16.75

2.5

ns

t_DLDCH

t_HLDCH

t_LCLKTWL

t_LCLKTWH

t_DLACLK

t_ENDLK

t_TDLK

Data Delay after LCLK High

Data Hold after LCLK High

LCLK Width Low

–3

(t_CK/2) – 2

(t_CK/2) + 8.5

5 + DT/2

(t_CK/2) + 2

(3 × t_CK/2) + 17 (t_CK/2) + 8.0

5 + DT/2

(t_CK/2) – 1

(t_CK/2) – 2.25

(t_CK/2) + 2.25

(t_CK/2) + 1.0

(3 × t_CK/2) + 18.5 ns

LCLK Width High

LCLK Low Delay after LACK High

LDAT, LCLK Enable after CLKIN

LDAT, LCLK Disable after CLKIN

ns

20 + DT/2

Link Port Service Request Interrupts: 1 × and

2 × Speed Operations

Timing Requirements:

t_SLCK

t_HLCK

LACK/LCLK Setup before CLKIN Low²

LACK/LCLK Hold after CLKIN Low²

10

2

10

2

ns

NOTES

¹LACK will go low with t_DLALCrelative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.

²Only required for interrupt recognition in the current cycle.

REV. B

–32–

ADSP-21060C/ADSP-21060LC

Link Ports: 2 ꢁ CLK Speed Operation

Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can

be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in

LDATA relative to LCLK, (setup skew = t_LCLKTWHmin – t_DLDCH– t_SLDCL). Hold skew is the maximum delay that can be intro-

duced in LCLK relative to LDATA, (hold skew = t_LCLKTWLmin – t_HLDCH– t_HLDCL). Calculations made directly from 2 × speed

specifications will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skew

times shown below are calculated to include only one tester guardband.

ADSP-21060C Setup Skew

ADSP-21060C Hold Skew

=

0.62 ns max (If port 2 is transmitter, setup skew is 0.39)

2.40 ns max

ADSP-21060LC Setup Skew

ADSP-21060LC Hold Skew

=

1.23 ns max

2.76 ns max

ADSP-21060C

Max

ADSP-21060LC

Parameter

Min

Max

Unit

Receive

Timing Requirements:

t_SLDCL

t_HLDCL

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

Data Setup before LCLK Low

Data Hold after LCLK Low

LCLK Period (2 × Operation)

LCLK Width Low

2.5

2.25

t_CK/2

5.25

4.5

ns

2.25

t_CK/2

4.5

LCLK Width High

4.25

Switching Characteristics:

t_DLAHCLACK High Delay after CLKIN High

t_DLALC

LACK Low Delay after LCLK High¹

18 + DT/2

6

28.5 + DT/2

16.5

18 + DT/2

6

29.5 + DT/2

18.5

ns

Transmit

Timing Requirements:

t_SLACHLACK Setup before LCLK High

t_HLACHLACK Hold after LCLK High

19

–6.75

19

–6.5

ns

Switching Characteristics:

t_DLCLK

t_DLDCH

t_HLDCH

t_LCLKTWL

t_LCLKTWH

t_DLACLK

LCLK Delay after CLKIN

8

2.5

8

2.25

ns

Data Delay after LCLK High

Data Hold after LCLK High

LCLK Width Low

LCLK Width High

LCLK Low Delay after LACK High

–2.0

(t_CK/4) – 1

–2.0

(t_CK/4) + 1.5

(t_CK/4) – 1.5 (t_CK/4) + 1

(t_CK/4) + 9 (3 _*t_CK/4) + 16.5

(t_CK/4) – 0.75 (t_CK/4) + 1.5

(t_CK/4) – 1.5 (t_CK/4) + 1

(t_CK/4) + 9

(3 _*t_CK/4) + 16.5

NOTE

¹LACK will go low with t_DLALCrelative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.

REV. B

–33–

ADSP-21060C/ADSP-21060LC

TRANSMIT

CLKIN

t_DLCLK

t_LCLKTWL

t_LCLKTWH

LAST NIBBLE

TRANSMITTED

FIRST NIBBLE

TRANSMITTED

LCLK INACTIVE

(HIGH)

LCLK 1x

OR

LCLK 2x

t_DLDCH

t_HLDCH

LDAT(3:0)

LACK (IN)

OUT

t_DLACLK

t_SLACH

t_HLACH

THE t_SLACHREQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

RECEIVE

CLKIN

t_LCLKIW

t_LCLKRWH

t_LCLKRWL

LCLK 1x

OR

LCLK 2x

t_HLDCL

t_SLDCL

LDAT(3:0)

IN

t_DLALC

t_DLAHC

LACK (OUT)

LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION

CLKIN

t_ENDLK

t_TDLK

LCLK

LDAT(3:0)

LACK

LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.

LINK PORT INTERRUPT SETUP TIME

CLKIN

t_HLCK

t_SLCK

LCLK

LACK

Figure 21. Link Ports

REV. B

–34–

ADSP-21060C/ADSP-21060LC

Serial Ports

Parameter

ADSP-21060C

Max

ADSP-21060LC

Min

Max

Unit

External Clock

Timing Requirements:

t_SFSE

TFS/RFS Setup before TCLK/RCLK¹

3.5

4

1.5

4

9.5

t_CK

3.5

4

1.5

4

9.5

t_CK

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

TFS/RFS Hold after TCLK/RCLK^{1, 2}

Receive Data Setup before RCLK¹

Receive Data Hold after RCLK¹

TCLK/RCLK Width

TCLK/RCLK Period

Internal Clock

Timing Requirements:

t_SFSI

TFS Setup before TCLK¹; RFS Setup

before RCLK¹

8

1

3

8

1

3

ns

t_HFSI

t_SDRI

t_HDRI

TFS/RFS Hold after TCLK/RCLK^{1, 2}

Receive Data Setup before RCLK¹

Receive Data Hold after RCLK¹

External or Internal Clock

Switching Characteristics:

t_DFSE

RFS Delay after RCLK (Internally

Generated RFS)³

13

ns

t_HOFSE

RFS Hold after RCLK (Internally

Generated RFS)³

3

External Clock

Switching Characteristics:

t_DFSE

TFS Delay after TCLK (Internally

Generated TFS)³

13

16

13

16

ns

t_HOFSE

TFS Hold after TCLK (Internally

Generated TFS)³

3

5

3

5

ns

t_DDTE

t_HODTE

Transmit Data Delay after TCLK³

Transmit Data Hold after TCLK³

Internal Clock

Switching Characteristics:

t_DFSI

TFS Delay after TCLK (Internally

Generated TFS)³

4.5

7.5

4.5

7.5

ns

t_HOFSI

TFS Hold after TCLK (Internally

Generated TFS)³

–1.5

0

–1.5

0

ns

t_DDTI

t_HDTI

t_SCLKIW

Transmit Data Delay after TCLK³

Transmit Data Hold after TCLK³

TCLK/RCLK Width

(t_SCLK/2) – 2

(t_SCLK/2) + 2

(t_SCLK/2) – 2.5 (t_SCLK/2) + 2.5

Enable and Three-State

Switching Characteristics:

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

t_DCLK

Data Enable from External TCLK³

3.5

0

4.0

ns

Data Disable from External TCLK³

Data Enable from Internal TCLK³

Data Disable from Internal TCLK³

TCLK/RCLK Delay from CLKIN

SPORT Disable after CLKIN

10.5

0

3

22 + 3DT/8

17

22 + 3DT/8

17

t_DPTR

Gated SCLK with External TFS

(Mesh Multiprocessing)⁴

Timing Requirements:

t_STFSCK

t_HTFSCK

TFS Setup before CLKIN

TFS Hold after CLKIN

5

ns

t_CK/2

External Late Frame Sync

Switching Characteristics:

t_DDTLFSEData Delay from Late External TFS or

External RFS with MCE = 1, MFD = 0⁵

t_DDTENFSData Enable from late FS or MCE = 1,

MFD = 0⁵

12

12.8

ns

3

3.5

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay & frame sync setup

and hold, 2) data delay & data setup and hold, and 3) SCLK width.

REV. B

–35–

ADSP-21060C/ADSP-21060LC

NOTES

¹Referenced to sample edge.

²RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.

³Referenced to drive edge.

⁴Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.

⁵MCE = 1, TFS enable and TFS valid follow t_DDTLFSEand t_DDTENFS

.

DATA RECEIVE– INTERNAL CLOCK

DATA RECEIVE– EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKW

RCLK

t_DFSE

t_HOFSE

t_DFSE

t_HOFSE

t_HFSE

t_SFSI

t_HFSI

t_SFSE

RFS

DR

RFS

DR

t_SDRE

t_HDRE

t_SDRI

t_HDRI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT– INTERNAL CLOCK

DATA TRANSMIT– EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKW

TCLK

t_DFSI

t_HOFSI

t_DFSE

t_HOFSE

t_SFSI

t_HFSI

t_HFSE

t_SFSE

TFS

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DT

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE DRIVE EDGE

TCLK / RCLK

TCLK (EXT)

DT

t_DDTEN

t_DDTTE

DRIVE

EDGE

DRIVE

EDGE

TCLK / RCLK

TCLK (INT)

t_DDTIN

t_DDTTI

DT

CLKIN

t_HTFSCK

t_DPTR

t_STFSCK

SPORT ENABLE AND

THREE-STATE

LATENCY

TCLK, RCLK

SPORT DISABLE DELAY

FROM INSTRUCTION

TFS (EXT)

TFS, RFS, DT

IS TWO CYCLES

t_DCLK

NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH

EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR

MESH MULTIPROCESSING.

TCLK (INT)

RCLK (INT)

LOW TO HIGH ONLY

Figure 22. Serial Ports

REV. B

–36–

ADSP-21060C/ADSP-21060LC

EXTERNAL RFS with MCE = 1, MFD = 0

DRIVE

t_HOFSE/I

DRIVE

SAMPLE

RCLK

RFS

(SEE NOTE 2)

t_SFSE/I

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TFS

DRIVE

SAMPLE

TCLK

t_{HOFSE/I (SEE NOTE 2)}

t_SFSE/I

TFS

DT

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

2ND BIT

t_DDTLFSE

Figure 23. External Late Frame Sync

REV. B

–37–

ADSP-21060C/ADSP-21060LC

JTAG Test Access Port and Emulation

ADSP-21060C

ADSP-21060LC

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

t_TCK

TCK Period

t_CK

5

6

7

18

t_CK

5

6

7

18.5

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup before TCK High

TDI, TMS Hold after TCK High

System Inputs Setup before TCK Low¹

System Inputs Hold after TCK Low¹

TRST Pulsewidth

4t_CK

Switching Characteristics:

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay after TCK Low²

13

18.5

13

18.5

ns

NOTES

¹System Inputs = DATA_47-0, ADDR_31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR_6-1, ID_2-0, RPBA, IRQ_2-0, FLAG_3-0, DR0, DR1,

TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.

²System Outputs = DATA_47-0, ADDR_31-0, MS_3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR_6-1, CPA, FLAG_3-0, TIMEXP, DT0,

DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT_3-0, LxCLK, LxACK, BMS.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 24. IEEE 11499.1 JTAG Test Access Port

REV. B

–38–

ADSP-21060C/ADSP-21060LC

Table III. External Power Calculations (3.3 V Device)

OUTPUT DRIVE CURRENTS

Figure 28 shows typical I-V characteristics for the output drivers

of the ADSP-2106x. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Type

# of

%

2

Pins Switching ꢁ C

ꢁ f

ꢁ V_DD= P_EXT

Address

MS0

WR

Data

ADDRCLK

15

1

32

1

50

0

–

50

–

× 44.7 pF × 10 MHz × 10.9 V = 0.037 W

× 44.7 pF × 10 MHz × 10.9 V = 0.000 W

× 44.7 pF × 20 MHz × 10.9 V = 0.010 W

× 14.7 pF × 10 MHz × 10.9 V = 0.026 W

× 4.7 pF × 20 MHz × 10.9 V = 0.001 W

POWER DISSIPATION

Total power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved. Inter-

nal power dissipation is calculated in the following way:

P_EXT= 0.074 W

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

P

_INT= I_DDIN× V_DD

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

P

_TOTAL= P_EXT+ (I_DDIN2× 5.0 V )

Note that the conditions causing a worst-case P_EXTare different

from those causing a worst-case P_INT. Maximum P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching simultaneously.

– the number of output pins that switch during each cycle (O)

– the maximum frequency at which they can switch (f)

– their load capacitance (C)

– their voltage swing (V_DD

)

and is calculated by:

TEST CONDITIONS

Output Disable Time

P

_EXT= O × C × V_DD²× f

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from

their output high or low voltage. The time for the voltage on the

bus to decay by ∆V is dependent on the capacitive load, C_Land

the load current, I_L. This decay time can be approximated by

the following equation:

The load capacitance should include the processor’s package

capacitance (C_IN). The switching frequency includes driving the

load high and then back low. Address and data pins can drive

high and low at a maximum rate of 1/(2t_CK). The write strobe

can switch every cycle at a frequency of 1/t_CK. Select pins switch

at 1/(2t_CK), but selects can switch on each cycle.

C

∆V

L

Example:

t

=

DECAY

I

L

Estimate P_EXTwith the following assumptions:

The output disable time t_DISis the difference between t_MEASURED

and t_DECAYas shown in Figure 25. The time t_MEASUREDis the

interval from when the reference signal switches to when the

output voltage decays ∆V from the measured output high or

output low voltage. t_DECAYis calculated with test loads C_Land

I_L, and with ∆V equal to 0.5 V.

–A system with one bank of external data memory RAM (32-bit)

–Four 128K × 8 RAM chips are used, each with a load of 10 pF

–External data memory writes occur every other cycle, a rate

of 1/(4t_CK), with 50% of the pins switching

–The instruction cycle rate is 40 MHz (t_CK= 25 ns).

The P_EXTequation is calculated for each class of pins that can

drive:

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start

driving. The output enable time t_ENAis the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram (Figure 25). If multiple

pins (such as the data bus) are enabled, the measurement value

is that of the first pin to start driving.

Table II. External Power Calculations (5 V Device)

Type

# of

%

2

Pins Switching ꢁ C

ꢁ f

ꢁ V_DD= P_EXT

Address

MS0

15

1

32

1

50

0

–

50

–

× 44.7 pF × 10 MHz × 25 V = 0.084 W

× 44.7 pF × 10 MHz × 25 V = 0.000 W

× 44.7 pF × 20 MHz × 25 V = 0.022 W

× 14.7 pF × 10 MHz × 25 V = 0.059 W

× 4.7 pF × 20 MHz × 25 V = 0.002 W

WR

Data

ADDRCLK

P_EXT= 0.167 W

REV. B

–39–

ADSP-21060C/ADSP-21060LC

Example System Hold Time Calculation

I

OL

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose ∆V

to be the difference between the ADSP-2106x’s output voltage

and the input threshold for the device requiring the hold time. A

typical ∆V will be 0.4 V. C_Lis the total bus capacitance (per

data line), and I_Lis the total leakage or three-state current (per

data line). The hold time will be t_DECAYplus the minimum

disable time (i.e., t_DATRWHfor the write cycle).

TO

OUTPUT

+1.5V

50pF

I

OH

REFERENCE

SIGNAL

Figure 26. Equivalent Device Loading for AC Measure-

ments (Includes All Fixtures)

t_MEASURED

t_ENA

t_DIS

V

OH (MEASURED)

V

OH (MEASURED)

V

– ꢂV

+ ꢂV

2.0V

1.0V

1.5V

OH (MEASURED)

OL (MEASURED)

Figure 27. Voltage Reference Levels for AC Measure-

ments (Except Output Enable/Disable)

t_DECAY

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

50 pF on all pins (see Figure 26). The delay and hold specifica-

tions given should be derated by a factor of 1.5 ns/50 pF for

loads other than the nominal value of 50 pF. Figures 29–30,

33–34 show how output rise time varies with capacitance. Fig-

ures 31, 35 show graphically how output delays and holds vary

with load capacitance. (Note that this graph or derating does

not apply to output disable delays; see the previous section

Output Disable Time under Test Conditions.) The graphs of

Figures 29, 30 and 31 may not be linear outside the ranges

shown.

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE

THIS VOLTAGE TO BE

APPROXIMATELY 1.5V

Figure 25. Output Enable/Disable

REV. B

–40–

ADSP-21060C/ADSP-21060LC

5

4

3

2

1

75

50

25

5.25V, –40ꢃC

5.0V, +25ꢃC

0

Y = 0.03X –1.45

4.75V, +100ꢃC

–25

4.75V, +100ꢃC

–50

–75

5.0V, +25ꢃC

5.25V, –40ꢃC

–100

NOMINAL

–125

–150

–1

25

50

75

100

125

150

175

200

0

0.75

1.50

2.25

3.00

3.75

4.50

5.25

LOAD CAPACITANCE – pF

SOURCE VOLTAGE – V

Figure 31. Typical Output Delay or Hold vs. Load Capaci-

tance (at Maximum Case Temperature) (V_DD= 5 V)

Figure 28. ADSP-2106x Typical Drive Currents (V_DD= 5 V)

16.0

14.0

12.0

120

100

V

3.3V, +25°C

OH

80

60

40

3.6V, –40°C

RISE TIME

10.0

20

0

3.0V, +100°C

Y = 0.005X + 3.7

8.0

6.0

4.0

3.0V, +100°C

FALL TIME

3.3V, +25°C

–20

–40

3.6V, –40°C

–60

–80

V

OL

2.0

0

Y = 0.0031X + 1.1

–100

–120

0

20

40

60

80

100 120 140 160 180 200

0

0.5

1

1.5

2

2.5

3

3.5

LOAD CAPACITANCE – pF

SOURCE VOLTAGE – V

Figure 32. ADSP-2106x Typical Drive Currents (V_DD= 3.3 V)

Figure 29. Typical Output Rise Time (10%–90% V_DD) vs.

Load Capacitance (V_DD= 5 V)

18

16

3.5

3.0

2.5

14

Y = 0.0796X + 1.17

12

10

RISE TIME

2.0

Y = 0.009X + 1.1

RISE TIME

8

1.5

6

4

2

Y = 0.0467X + 0.55

FALL TIME

1.0

FALL TIME

Y = 0.005X + 0.6

0.5

0

20

40

60

80 100 120 140 160 180 200

0

20

40

60

80

100 120 140 160 180 200

LOAD CAPACITANCE – pF

Figure 33. Typical Output Rise Time (10%–90% V_DD) vs.

Load Capacitance (V_DD= 3.3 V)

Figure 30. Typical Output Rise Time (0.8 V–2.0 V) vs.

Load Capacitance (V_DD= 5 V)

REV. B

–41–

ADSP-21060C/ADSP-21060LC

5

4

3

2

1

9

8

7

Y = 0.0329X –1.65

Y = 0.0391X + 0.36

6

5

4

RISE TIME

Y = 0.0305X + 0.24

3

2

1

0

FALL TIME

NOMINAL

–1

0

20

40

60

80 100 120 140 160 180 200

25

50

75

100

125

150

175

200

LOAD CAPACITANCE – pF

Figure 35. Typical Output Delay or Hold vs. Load Capaci-

tance (at Maximum Case Temperature) (V_DD= 3.3 V)

Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs.

Load Capacitance (V_DD= 3.3 V)

ENVIRONMENTAL CONDITIONS

Thermal Characteristics

source may be used. A heatsink should be attached with a ther-

mal adhesive.

The ADSP-2106x is packaged in a 240-lead thermally enhanced

ceramic QFP (CQFP). There are two package versions, one

with a copper/tungsten heat slug on top of the package (CZ) for

air cooling, and one with the heat slug on the bottom (CW) for

cooling through the board. The ADSP-2106x is specified for a

case temperature (T_CASE). To ensure that the T_CASEdata sheet

specification is not exceeded, a heatsink and/or an air flow

T_{CASE =}T_AMB+ (PD × θ_CA

)

T

PD =

_CASE= Case temperature (measured on the heat slug surface)

Power dissipation in W (this value depends upon the

specific application; a method for calculating PD is

shown under Power Dissipation).

θ_CA

=

Value from the following table.

Airflow

(Linear Ft./Min.)

0

100

200

14

400

600

θ_CA(°C/W)

21060CW/LCW

21060CZ/LCZ

19.5 16

20 16

12

10

14

11.5 9.5

NOTES

This represents thermal resistance at total power of 5 W. With air flow, no variance is seen in θ_CAof 5 W.

θ

_CAat 0 LFM varies with power

21060CW/LCW: at 2 W, θ_CA= 23°C/W; at 3 W, θ_CA= 21.5°C/W.

21060CZ/LCZ: at 2 W, θ_CA= 24°C/W; at 3 W, θ_CA= 21.5°C/W.

_JC= 0.24°C/W.

θ

REV. B

–42–

ADSP-21060C/ADSP-21060LC

240-LEAD METRIC CQFP PIN CONFIGURATION

HEAT SLUG UP VERSION (CZ)

240

181

1

180

TOP VIEW

PINS DOWN

HEAT SLUG

60

121

61

120

THE 240–LEAD PACKAGE CONTAINS A COPPER/TUNGSTEN

HEAT SLUG ON ITS TOP SURFACE. HEAT SLUG AND

PACKAGE LID ARE ELECTRICALLY ISOLATED.

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

1

2

3

4

5

6

7

8

TDI

TRST

VDD

TDO

TIMEXP

EMU

ICSA

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

ADDR20

ADDR21

GND

ADDR22

ADDR23

ADDR24

VDD

GND

VDD

ADDR25

ADDR26

ADDR27

GND

MS3

MS2

MS1

MS0

SW

BMS

ADDR28

GND

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

TCLK0

TFS0

DR0

201 L2DAT0

202 L2CLK

203 L2ACK

204 NC

161 DATA14

162 DATA13

163 DATA12

164 GND

165 DATA11

166 DATA10

167 DATA9

168 VDD

169 DATA8

170 DATA7

171 DATA6

172 GND

173 DATA5

174 DATA4

175 DATA3

176 VDD

121 DATA41

122 DATA40

123 DATA39

124 VDD

125 DATA38

126 DATA37

127 DATA36

128 GND

RCLK0

RFS0

VDD

GND

ADRCLK

REDY

HBG

CS

205 VDD

206 L3DAT3

207 L3DAT2

208 L3DAT1

209 L3DAT0

210 L3CLK

211 L3ACK

212 GND

213 L4DAT3

214 L4DAT2

215 L4DAT1

216 L4DAT0

217 L4CLK

218 L4ACK

219 VDD

FLAG3

FLAG2

FLAG1

FLAG0

GND

ADDR0

ADDR1

VDD

ADDR2

ADDR3

ADDR4

GND

ADDR5

ADDR6

ADDR7

VDD

ADDR8

ADDR9

ADDR10

GND

ADDR11

ADDR12

ADDR13

VDD

ADDR14

ADDR15

GND

ADDR16

ADDR17

ADDR18

VDD

9

129 NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

130 DATA35

131 DATA34

132 DATA33

133 VDD

134 VDD

135 GND

136 DATA32

137 DATA31

138 DATA30

139 GND

140 DATA29

141 DATA28

142 DATA27

143 VDD

RD

WR

GND

VDD

GND

CLKIN

ACK

177 DATA2

178 DATA1

179 DATA0

180 GND

100 DMAG2

101 DMAG1

102 PAGE

103 VDD

104 BR6

105 BR5

106 BR4

107 BR3

108 BR2

109 BR1

110 GND

111 VDD

112 GND

113 DATA47

114 DATA46

115 DATA45

116 VDD

117 DATA44

118 DATA43

119 DATA42

120 GND

220 GND

221 VDD

181 GND

VDD

ADDR29

ADDR30

ADDR31

GND

222 L5DAT3

223 L5DAT2

224 L5DAT1

225 L5DAT0

226 L5CLK

227 L5ACK

228 GND

229 ID2

230 ID1

231 ID0

232 LBOOT

233 RPBA

234 RESET

235 EBOOT

236 IRQ2

237 IRQ1

238 IRQ0

182 L0DAT3

183 L0DAT2

184 L0DAT1

185 L0DAT0

186 L0CLK

187 L0ACK

188 VDD

189 L1DAT3

190 L1DAT2

191 L1DAT1

192 L1DAT0

193 L1CLK

194 L1ACK

195 GND

144 VDD

145 DATA26

146 DATA25

147 DATA24

148 GND

149 DATA23

150 DATA22

151 DATA21

152 VDD

153 DATA20

154 DATA19

155 DATA18

156 GND

157 DATA17

158 DATA16

159 DATA15

160 VDD

SBTS

DMAR2

DMAR1

HBR

DT1

TCLK1

TFS1

DR1

RCLK1

RFS1

GND

CPA

196 GND

197 VDD

198 L2DAT3

199 L2DAT2

200 L2DAT1

VDD

ADDR19

239 TCK

240 TMS

DT0

REV. B

–43–

ADSP-21060C/ADSP-21060LC

240-LEAD METRIC CQFP PIN CONFIGURATION

HEAT SLUG DOWN VERSION (CW)

240

181

1

180

TOP VIEW

PINS DOWN

HEAT SLUG

60

121

61

120

THE 240–LEAD PACKAGE CONTAINS A COPPER/TUNGSTEN

HEAT SLUG ON ITS BOTTOM SURFACE. HEAT SLUG AND

PACKAGE LID ARE ELECTRICALLY ISOLATED.

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

Pin Pin

No. Name

1

2

3

4

5

6

7

8

GND

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

DATA29

GND

DATA30

DATA31

DATA32

GND

VDD

DATA33

DATA34

DATA35

NC

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

DMAG2

ACK

CLKIN

GND

VDD

GND

WR

201 GND

202 VDD

161 ADDR5

162 GND

163 ADDR4

164 ADDR3

165 ADDR2

166 VDD

167 ADDR1

168 ADDR0

169 GND

170 FLAG0

171 FLAG1

172 FLAG2

173 FLAG3

174 ICSA

175 EMU

176 TIMEXP

177 TDO

178 VDD

179 TRST

180 TDI

121 ADDR28

122 BMS

123 SW

124 MS0

125 MS1

126 MS2

127 MS3

128 GND

129 ADDR27

130 ADDR26

131 ADDR25

132 VDD

133 GND

134 VDD

135 ADDR24

136 ADDR23

137 ADDR22

138 GND

139 ADDR21

140 ADDR20

141 ADDR19

142 VDD

DATA0

DATA1

DATA2

VDD

DATA3

DATA4

DATA5

GND

DATA6

DATA7

DATA8

VDD

DATA9

DATA10

DATA11

GND

DATA12

DATA13

DATA14

VDD

DATA15

DATA16

DATA17

GND

DATA18

DATA19

DATA20

VDD

DATA21

DATA22

DATA23

GND

203 L4ACK

204 L4CLK

205 L4DAT0

206 L4DAT1

207 L4DAT2

208 L4DAT3

209 GND

210 L3ACK

211 L3CLK

212 L3DAT0

213 L3DAT1

214 L3DAT2

215 L3DAT3

216 VDD

RD

CS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

HBG

REDY

ADRCLK

GND

VDD

RFS0

RCLK0

DR0

GND

DATA36

DATA37

DATA38

VDD

DATA39

DATA40

DATA41

GND

DATA42

DATA43

DATA44

VDD

DATA45

DATA46

DATA47

GND

VDD

GND

BR1

BR2

BR3

BR4

BR5

BR6

217 NC

218 L2ACK

219 L2CLK

220 L2DAT0

221 L2DAT1

222 L2DAT2

223 L2DAT3

224 VDD

TFS0

100 TCLK0

101 DT0

102 CPA

103 GND

104 RFS1

105 RCLK1

106 DR1

107 TFS1

108 TCLK1

109 DT1

181 TMS

182 TCK

183 IRQ0

184 IRQ1

143 VDD

144 ADDR18

145 ADDR17

146 ADDR16

147 GND

148 ADDR15

149 ADDR14

150 VDD

151 ADDR13

152 ADDR12

153 ADDR11

154 GND

155 ADDR10

156 ADDR9

157 ADDR8

158 VDD

225 GND

226 GND

185 IRQ2

186 EBOOT

187 RESET

188 RPBA

189 LBOOT

190 ID0

191 ID1

192 ID2

193 GND

194 L5ACK

195 L5CLK

196 L5DAT0

197 L5DAT1

198 L5DAT2

199 L5DAT3

200 VDD

227 L1ACK

228 L1CLK

229 L1DAT0

230 L1DAT1

231 L1DAT2

232 L1DAT3

233 VDD

234 L0ACK

235 L0CLK

236 L0DAT0

237 L0DAT1

238 L0DAT2

239 L0DAT3

240 GND

110 HBR

111 DMAR1

112 DMAR2

113 SBTS

114 GND

115 ADDR31

116 ADDR30

117 ADDR29

118 VDD

DATA24

DATA25

DATA26

VDD

DATA27

DATA28

VDD

PAGE

DMAG1

119 VDD

120 GND

159 ADDR7

160 ADDR6

REV. B

–44–

ADSP-21060C/ADSP-21060LC

OUTLINE DIMENSIONS

Dimensions shown in inches and (millimeters within parentheses).

240-Lead CQFP with Heat Slug Up and Formed Leads (QS-240)

1.441 (36.60)

1.422 (36.13) SQ

1.404 (35.65)

1.270 (32.25)

1.260 (32.00) SQ

1.250 (31.75)

1.104 (28.05)

1.094 (27.80) SQ

1.085 (27.55)

PIN 1

ID

240

181

180

181

180

240

1

SEAL RING

LID

0.837 (21.25)

0.827 (21.00) SQ

0.817 (20.75)

TOP VIEW

PINS DOWN

BOTTOM VIEW

HEAT SLUG

60

121

120

121

120

60

61

0.758 (19.25)

0.748 (19.00) SQ

0.738 (18.75)

0.146 (3.70)

0.127 (3.22)

0.108 (2.75)

0.169 (4.30) MAX

-C- SEATING PLANE

0.004 (0.10)

7ꢃ

–3ꢃ

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

0.020 (0.50)

TYP

LEAD PITCH

0.024 (0.60)

0.008 (0.20)

0.035 (0.90)

0.030 (0.75)

0.024 (0.60)

C

0.067 (1.70)

0.006 (0.15)

0.014 (0.35)

NOTES:

0.012 (0.30)

0.010 (0.25)

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER

EQUIVALENTS FOR REFERENCE ONLY AND ARE

NOT APPROPRIATE FOR USE IN DESIGN.

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)

3. LEAD SWEEP/LEAD OFFSET = 0.005 (0.127) MAX

LEAD THICKNESS

0.007 (0.180)

0.006 (0.155)

0.005 (0.130)

0.018 (0.45)

0.010 (0.25)

0.002 (0.05)

REV. B

–45–

ADSP-21060C/ADSP-21060LC

OUTLINE DIMENSIONS

Dimensions shown in inches and (millimeters within parentheses).

240-Lead Metric CQFP with Heat Slug Up and Unformed Leads (QS-240)

0.665 (16.88)

8 ꢁ 0.650 (16.50)

0.635 (16.12)

2.953 (75.00) SQ

1.161 (29.50) BSC

61

120

121

61

60

120

121

60

SEAL RING

LID

2 ꢁ

2.594

(65.90)

TOP VIEW

BOTTOM VIEW

HEAT SLUG

180

181

1

180

181

INDEX 1

GOLD

PLATED

240

INDEX 2

0.079 (2.00)

NO GOLD

2.972 (75.50) SQ

NONCONDUCTIVE

CERAMIC TIE BAR

0.067 (1.70)

0.006 (0.15)

0.014 (0.35)

NOTES:

0.012 (0.30)

0.010 (0.25)

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER

EQUIVALENTS FOR REFERENCE ONLY AND ARE

NOT APPROPRIATE FOR USE IN DESIGN.

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)

3. LEAD SWEEP/LEAD OFFSET = 0.005 (0.127) MAX

LEAD THICKNESS

0.007 (0.180)

0.006 (0.155)

0.005 (0.130)

0.018 (0.45)

0.010 (0.25)

0.002 (0.05)

REV. B

–46–

ADSP-21060C/ADSP-21060LC

OUTLINE DIMENSIONS

Dimensions shown in inches and (millimeters within parentheses).

240-Lead Metric CQFP with Heat Slug Down and Formed Leads (QS-240A)

0.837 (21.25)

0.827 (21.00) SQ

0.817 (20.75)

1.441 (36.60)

1.422 (36.13) SQ

1.404 (35.65)

0.758 (19.25)

0.748 (19.00) SQ

0.738 (18.75)

1.270 (32.25)

1.260 (32.00) SQ

1.250 (31.75)

181

180

240

PIN 1

ID

240

181

180

1

SEAL RING

LID

TOP VIEW

PINS DOWN

BOTTOM VIEW

HEAT SLUG

121

120

60

121

120

60

61

1.104 (28.05)

1.094 (27.80) SQ

1.085 (27.55)

0.146 (3.70)

0.127 (3.22)

0.108 (2.75)

0.165 (4.20) MAX

-C- SEATING PLANE

0.004 (0.10)

7ꢃ

–3ꢃ

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

0.020 (0.50)

TYP

LEAD PITCH

0.035 (0.90)

0.030 (0.75)

0.024 (0.60)

0.020 (0.50)

0.004 (0.10)

C

0.067 (1.70)

0.006 (0.15)

0.014 (0.35)

NOTES:

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER

EQUIVALENTS FOR REFERENCE ONLY AND ARE

NOT APPROPRIATE FOR USE IN DESIGN.

0.012 (0.30)

0.010 (0.25)

2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)

3. LEAD SWEEP/LEAD OFFSET = 0.005 (0.127) MAX

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

LEAD THICKNESS

0.007 (0.180)

0.006 (0.155)

0.005 (0.130)

0.018 (0.45)

0.010 (0.25)

0.002 (0.05)

REV. B

–47–

ADSP-21060C/ADSP-21060LC

OUTLINE DIMENSIONS

Dimensions shown in inches and (millimeters within parentheses).

240-Lead Metric CQFP with Heat Slug Down and Unformed Leads (QS-240A)

0.665 (16.88)

8 ꢁ 0.650 (16.50)

0.635 (16.12)

2.953 (75.00) SQ

1.161 (29.50) BSC

120

121

61

60

61

121

60

SEAL RING

LID

2 ꢁ

2.594

(65.90)

BOTTOM VIEW

HEAT SLUG

TOP VIEW

1

180

181

180

181

1

INDEX 1

GOLD

PLATED

INDEX 2

0.079 (2.00)

NO GOLD

240

2.972 (75.50) SQ

0.067 (1.70)

NONCONDUCTIVE

CERAMIC TIE BAR

0.006 (0.15)

0.014 (0.35)

NOTES:

0.012 (0.30)

0.010 (0.25)

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER

EQUIVALENTS FOR REFERENCE ONLY AND ARE

NOT APPROPRIATE FOR USE IN DESIGN.

0.009 (0.23)

0.008 (0.20)

0.007 (0.17)

2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)

3. LEAD SWEEP/LEAD OFFSET = 0.005 (0.127) MAX

LEAD THICKNESS

0.007 (0.180)

0.006 (0.155)

0.005 (0.130)

0.018 (0.45)

0.010 (0.25)

0.002 (0.05)

ORDERING GUIDE

Part Number

Case Temperature Range

Heat Slug Orientation

Instruction Rate

Operating Voltage

ADSP-21060CZ-133

ADSP-21060CZ-160

ADSP-21060CW-133

ADSP-21060CW-160

ADSP-21060LCW-133

ADSP-21060LCW-160

–40°C to +100°C

Heat Slug Up

Heat Slug Down

33 MHz

40 MHz

33 MHz

40 MHz

33 MHz

40 MHz

5 V

3.3 V

REV. B

–48–


型号：	ADSP-21060CW-133
厂家：	ADI
描述：	ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP- 21060 SHARC工业DSP单片机系列微控制器和处理器外围集成电路数字信号处理器时钟
文件：	总48页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21060CW-133 [ADI]

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