ADSP-21060LKSZ-160 [ADI]
SHARC Processor; SHARC处理器型号: | ADSP-21060LKSZ-160 |
厂家: | ADI |
描述: | SHARC Processor |
文件: | 总64页 (文件大小:817K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SHARC Processor
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
SUMMARY
KEY FEATURES—PROCESSOR CORE
High performance signal processor for communications,
graphics and imaging applications
40 MIPS, 25 ns instruction rate, single-cycle instruction
execution
Super Harvard Architecture
4 independent buses for dual data fetch, instruction fetch,
and nonintrusive I/O
120 MFLOPS peak, 80 MFLOPS sustained performance
Dual data address generators with modulo and bit-reverse
addressing)
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Efficient program sequencing with zero-overhead looping:
Single-cycle loop setup
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
IEEE JTAG Standard 1149.1 Test Access Port and on-chip
emulation
Integrated multiprocessing features
240-lead thermally enhanced MQFP_PQ4 package, 225-ball
plastic ball grid array (PBGA), 240-lead hermetic CQFP
package
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
RoHS compliant packages
CORE PROCESSOR
DUAL-PORTED SRAM
INSTRUCTION
TIMER
JTAG
TWO INDEPENDENT
DUAL-PORTED BLOCKS
7
CACHE
TEST AND
EMULATION
32 ꢀ 48-BIT
PROCESSOR PORT
ADDR DATA
ADDR
I/O PORT
ADDR
ADDR
DATA
DATA
DATA
DAG1
DAG2
PROGRAM
SEQUENCER
8 ꢀ 4 ꢀ 32 8 ꢀ 4 ꢀ 24
EXTERNAL
PORT
IOD
48
IOA
17
24
PM ADDRESS BUS
32
48
ADDR BUS
MUX
DM ADDRESS BUS
32
MULTIPROCESSOR
INTERFACE
48
40/32
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DATA BUS
MUX
HOST PORT
S
DATA
REGISTER
FILE
DMA
CONTROLLER
4
IOP
REGISTERS
(MEMORY
MAPPED)
6
SERIAL PORTS
(2)
BARREL
SHIFTER
16 ꢀ 40-BIT
6
MULT
ALU
CONTROL,
STATUS AND
DATA BUFFERS
36
LINK PORTS
(6)
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel : 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
HOST PROCESSOR INTERFACE TO 16- AND 32-BIT
MICROPROCESSORS
PROCESSOR FEATURES (Continued)
The processor family provides a variety of features. For a com-
parison across family members, see Table 1.
Host can directly read/write ADSP-2106x internal memory
and IOP registers
PARALLEL COMPUTATIONS
MULTIPROCESSING
Single-cycle multiply and ALU operations in parallel with
dual memory read/writes and instruction fetch
Multiply with add and subtract for accelerated FFT butterfly
computation
Glueless connection for scalable DSP multiprocessing
architecture
Distributed on-chip bus arbitration for parallel bus connect
of up to six ADSP-2106xs plus host
6 link ports for point-to-point connectivity and array
multiprocessing
240 MBps transfer rate over parallel bus
240 MBps transfer rate over link ports
UP TO 4M BIT ON-CHIP SRAM
Dual-ported for independent access by core processor and
DMA
OFF-CHIP MEMORY INTERFACING
4 gigawords addressable
SERIAL PORTS
Programmable wait state generation, page-mode DRAM
support
Two 40 Mbps synchronous serial ports with companding
hardware
DMA CONTROLLER
Independent transmit and receive functions
10 DMA channels for transfers between ADSP-2106x internal
memory and external memory, external peripherals, host
processor, serial ports, or link ports
Background DMA transfers at up to 40 MHz, in parallel with
full-speed processor execution
Table 1. ADSP-2106x SHARC Processor Family Features
Feature
ADSP-21060
4M bits
5 V
ADSP-21062
2M bits
5 V
ADSP-21060L
4M bits
ADSP-21062L
2M bits
ADSP-21060C
4M bits
ADSP-21060LC
4M bits
SRAM
Operating
Voltage
3.3 V
3.3 V
5 V
3.3 V
Instruction 33 MHz
33 MHz
40 MHz
33 MHz
40 MHz
33 MHz
40 MHz
33 MHz
40 MHz
33 MHz
40 MHz
Rate
40 MHz
Package
MQFP_PQ4
PBGA
MQFP_PQ4
PBGA
MQFP_PQ4
PBGA
MQFP_PQ4
PBGA
CQFP
CQFP
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
CONTENTS
Summary ............................................................... 1
Key Features—Processor Core .................................... 1
Processor Features (Continued) .................................. 2
Parallel Computations .............................................. 2
Up to 4M Bit On-Chip SRAM ..................................... 2
Off-Chip Memory Interfacing ..................................... 2
DMA Controller ...................................................... 2
Host Processor Interface to 16- and 32-Bit Microprocessors 2
Multiprocessing ....................................................... 2
Serial Ports ............................................................. 2
Contents ................................................................ 3
Revision History ...................................................... 3
General Description ................................................. 4
SHARC Family Core Architecture ............................ 4
Memory and I/O Interface Features ........................... 5
Development Tools ............................................... 8
Evaluation Kit ...................................................... 9
Designing an Emulator-Compatible DSP Board (Target) 9
Additional Information .......................................... 9
Pin Function Descriptions ........................................ 10
Target Board Connector for EZ-ICE Probe ................ 13
ADSP-21060/ADSP-21062 Specifications ..................... 15
Operating Conditions (5 V) ................................... 15
Electrical Characteristics (5 V) ................................ 15
Internal Power Dissipation (5 V) ............................. 16
External Power Dissipation (5 V) ............................ 17
ADSP-21060L/ADSP-21062L Specifications ................. 18
Operating Conditions (3.3 V) ................................. 18
Electrical Characteristics (3.3 V) ............................. 18
Internal Power Dissipation (3.3 V) .......................... 19
External Power Dissipation (3.3 V) .......................... 20
Absolute Maximum Ratings ................................... 20
ESD Caution ...................................................... 21
Package Marking Information ................................ 21
Timing Specifications ........................................... 21
Test Conditions .................................................. 47
Environmental Conditions .................................... 50
225-Ball PBGA Ball Configurations ............................ 51
240-Lead MQFP_PQ4/CQFP Pin Configurations ........... 53
Outline Dimensions ................................................ 55
Surface-Mount Design .......................................... 60
Ordering Guide ..................................................... 61
REVISION HISTORY
3/08—Rev. E to Rev. F
Revised Absolute Maximum Ratings ............................ 20
Corrected model package descriptions.
See Ordering Guide.................................................. 61
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
GENERAL DESCRIPTION
The ADSP-2106x SHARC®—Super Harvard Architecture Com-
puter—is a 32-bit signal processing microcomputer that offers
high levels of DSP performance. The ADSP-2106x builds on the
ADSP-21000 DSP core to form a complete system-on-a-chip,
adding a dual-ported on-chip SRAM and integrated I/O periph-
erals supported by a dedicated I/O bus.
• Serial ports and link ports
• JTAG Test Access Port
ADSP-2106x
CS
BMS
CLKIN
BOOT
EPROM
(OPTIONAL)
1 ϫ CLOCK
Fabricated in a high speed, low power CMOS process, the
ADSP-2106x has a 25 ns instruction cycle time and operates at
40 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table 2 shows perfor-
mance benchmarks for the ADSP-2106x.
ADDR
DATA
EBOOT
LBOOT
IRQ2–0
3
4
ADDR31–0
ADDR
FLAG3–0
MEMORY-
MAPPED
DEVICES
DATA47–0
DATA
TIMEXP
OE
RD
LINK
DEVICES
(6 MAX)
(OPTIONAL)
The ADSP-2106x SHARC represents a new standard of integra-
tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea-
tures including up to 4M bit SRAM memory (see Table 1), a
host processor interface, DMA controller, serial ports and link
port, and parallel bus connectivity for glueless DSP
multiprocessing.
LxCLK
WE
ACK
WR
ACK
(OPTIONAL)
LxACK
LxDAT3–0
CS
MS3–0
TCLK0
RCLK0
TFS0
RSF0
DT0
PAGE
SERIAL
DEVICE
(OPTIONAL)
DMA DEVICE
(OPTIONAL)
SBTS
DATA
ADRCLK
DR0
DMAR1–2
DMAG1–2
CS
TCLK1
RCLK1
TFS1
RSF1
DT1
Table 2. Benchmarks (at 40 MHz)
SERIAL
DEVICE
(OPTIONAL)
HOST
HBR
HBG
PROCESSOR
INTERFACE
(OPTIONAL)
Benchmark Algorithm
Speed
Cycles
DR1
REDY
BR1–6
PA
1024 Point Complex FFT (Radix 4, with 0.46 ꢀs
reversal)
18,221
RPBA
ID2–0
ADDR
DATA
RESET JTAG
FIR Filter (per tap)
IIR Filter (per biquad)
Divide (y/x)
25 ns
1
4
6
9
6
100 ns
150 ns
Figure 2. ADSP-2106x System Sample Configuration
Inverse Square Root
DMA Transfer Rate
225 ns
240 Mbytes/s
SHARC FAMILY CORE ARCHITECTURE
The ADSP-2106x continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The ADSP-2106x includes the following architectural features
of the ADSP-21000 family core. The ADSP-2106x processors
are code- and function-compatible with the ADSP-21020.
The block diagram on Page 1 illustrates the following architec-
tural features:
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier oper-
ations. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
• Computation units (ALU, multiplier and shifter) with a
shared data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
Data Register File
• Interval timer
A general–purpose data register file is used for transferring data
between the computation units and the data buses, and for stor-
ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
• On-chip SRAM
• External port for interfacing to off-chip memory and
peripherals
• Host port and multiprocessor Interface
• DMA controller
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
On the ADSP-21060/ADSP-21060L, the memory can be config-
ured as a maximum of 128k words of 32-bit data, 256k words of
16-bit data, 80k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to four megabits. All of
the memory can be accessed as 16-bit, 32-bit or 48-bit words.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-2106x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With its separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch two operands and an instruction (from the
cache), all in a single cycle.
A 16-bit floating-point storage format is supported, which effec-
tively doubles the amount of data that can be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit float-
ing-point formats is done in a single instruction.
Instruction Cache
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the
ADSP-2106x’s external port.
The ADSP-2106x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-2106x’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-2106x contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any mem-
ory location.
On-Chip Memory and Peripherals Interface
The ADSP-2106x’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-2106x’s unified
address space. The separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses, and I/O
data—are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-2106x
provides programmable memory wait states and external mem-
ory acknowledge controls to allow interfacing to DRAM and
peripherals with variable access, hold and disable time
requirements.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example, the
ADSP-2106x can conditionally execute a multiply, an add, a
subtract and a branch, all in a single instruction.
MEMORY AND I/O INTERFACE FEATURES
The ADSP-2106x processors add the following architectural
features to the SHARC family core.
Host Processor Interface
The ADSP-2106x’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with lit-
tle additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-2106x’s exter-
nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead.
Dual-Ported On-Chip Memory
The ADSP-21062/ADSP-21062L contains two megabits of on-
chip SRAM, and the ADSP-21060/ADSP-21060L contains
4M bits of on-chip SRAM. The internal memory is organized as
two equal sized blocks of 1M bit each for the ADSP-21062/
ADSP-21062L and two equal sized blocks of 2M bits each for
the ADSP-21060/ADSP-21060L. Each can be configured for dif-
ferent combinations of code and data storage. Each memory
block is dual-ported for single-cycle, independent accesses by
the core processor and I/O processor or DMA controller. The
dual-ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle.
The host processor requests the ADSP-2106x’s external bus with
the host bus request (HBR), host bus grant (HBG), and ready
(REDY) signals. The host can directly read and write the inter-
nal memory of the ADSP-2106x, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
On the ADSP-21062/ADSP-21062L, the memory can be config-
ured as a maximum of 64k words of 32-bit data, 128k words of
16-bit data, 40k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to two megabits. All of
the memory can be accessed as 16-bit, 32-bit, or 48-bit words.
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
ADSP-2106x #6
ADSP-2106x #5
ADSP-2106x #4
ADSP-2106x #3
ADDR31–0
CLKIN
DATA47–0
RESET
RPBA
3
ID2–0
CONTROL
011
5
BR1–2, BR4–6
BR3
ADSP-2106x #2
ADDR31–0
DATA47–0
CLKIN
RESET
RPBA
3
ID2–0
CONTROL
010
CPA
BR1, BR3–6
BR2
5
ADSP-2106x #1
CLKIN
RESET
RPBA
ADDR31–0
DATA47–0
ADDR
DATA
GLOBAL MEMORY
AND
PERIPHERAL (OPTIONAL)
RDx
WRx
OE
WE
ACK
CS
3
ACK
MS3–0
ID2–0
BMS
PAGE
CS
001
BOOT EPROM (OPTIONAL)
ADDR
SBTS
DATA
BUS
PRIORITY
CS
HBR
RESET
CLOCK
HBG
HOST PROCESSOR
INTERFACE (OPTIONAL)
REDY
ADDR
DATA
CPA
BR2–6
BR1
5
Figure 3. Shared Memory Multiprocessing System
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
control two DMA channels using DMA request/grant lines
(DMAR1–2, DMAG1–2). Other DMA features include inter-
rupt generation upon completion of DMA transfers and DMA
chaining for automatic linked DMA transfers.
DMA Controller
The ADSP-2106x’s on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions.
Multiprocessing
The ADSP-2106x offers powerful features tailored to multipro-
cessor DSP systems. The unified address space (see Figure 4)
allows direct interprocessor accesses of each ADSP-2106x’s
internal memory. Distributed bus arbitration logic is included
on-chip for simple, glueless connection of systems containing
up to six ADSP-2106xs and a host processor. Master processor
changeover incurs only one cycle of overhead. Bus arbitration is
selectable as either fixed or rotating priority. Bus lock allows
indivisible read-modify-write sequences for semaphores. A vec-
tor interrupt is provided for interprocessor commands. Maxi-
mum throughput for interprocessor data transfer is
240M bytes/s over the link ports or external port. Broadcast
writes allow simultaneous transmission of data to all
ADSP-2106xs and can be used to implement reflective
semaphores.
DMA transfers can occur between the ADSP-2106x’s internal
memory and external memory, external peripherals, or a host
processor. DMA transfers can also occur between the ADSP-
2106x’s internal memory and its serial ports or link ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-,
32-, or 48-bit words is performed during DMA transfers.
Ten channels of DMA are available on the ADSP-2106x—two
via the link ports, four via the serial ports, and four via the
processor’s external port (for either host processor, other
ADSP-2106xs, memory, or I/O transfers). Four additional link
port DMA channels are shared with Serial Port 1 and the exter-
nal port. Programs can be downloaded to the ADSP-2106x
using DMA transfers. Asynchronous off-chip peripherals can
ADDRESS
ADDRESS
0x0000 0000
0x0002 0000
0x0040 0000
MS0
IOP REGISTERS
INTERNAL
MEMORY
SPACE
NORMAL WORD ADDRESSING
(32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS)
BANK 0
0x0004 0000
SDRAM
(OPTIONAL)
SHORT WORD ADDRESSING
(16-BIT DATA WORDS)
0x0008 0000
0x0010 0000
INTERNAL MEMORY SPACE
WITH ID = 001
BANK 1
BANK 2
BANK 3
MS1
MS2
INTERNAL MEMORY SPACE
WITH ID = 010
0x0018 0000
0x0012 0000
EXTERNAL
MEMORY
SPACE
INTERNAL MEMORY SPACE
WITH ID = 011
MULTIPROCESSOR
MEMORY
SPACE
INTERNAL MEMORY SPACE
WITH ID = 100
0x0028 0000
0x0030 0000
0x0038 0000
MS3
INTERNAL MEMORY SPACE
WITH ID = 101
INTERNAL MEMORY SPACE
WITH ID = 110
BROADCAST WRITE
TO ALL ADSP-21061s
NONBANKED
0x003F FFFF
0x0FFF FFFF
NOTE: BANK SIZES ARE SELECTED BY
MSIZE BITS IN THE SYSCON REGISTER
Figure 4. Memory Map
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Link Ports
The ADSP-2106x features six 4-bit link ports that provide addi-
tional I/O capabilities. The link ports can be clocked twice per
cycle, allowing each to transfer eight bits of data per cycle. Link-
port I/O is especially useful for point-to-point interprocessor
communication in multiprocessing systems.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
The link ports can operate independently and simultaneously,
with a maximum data throughput of 240M bytes/s. Link port
data is packed into 32- or 48-bit words, and can be directly read
by the core processor or DMA-transferred to on-chip memory.
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
Program Booting
The internal memory of the ADSP-2106x can be booted at sys-
tem power-up from an 8-bit EPROM, a host processor, or
through one of the link ports. Selection of the boot source is
controlled by the BMS (boot memory select), EBOOT (EPROM
Boot), and LBOOT (link/host boot) pins. 32-bit and 16-bit host
processors can be used for booting. The processor also sup-
ports a no-boot mode in which instruction execution is sourced
from the external memory.
• Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-2106x
development tools, including the color syntax highlighting in
the VisualDSP++ editor. This capability permits:
DEVELOPMENT TOOLS
• Control in how the development tools process inputs and
generate outputs
The ADSP-2106x is supported by a complete set of
CROSSCORE®† software development tools, including Analog
Devices emulators and VisualDSP++®‡ development environ-
ment. The same emulator hardware that supports other SHARC
processors also fully emulates the ADSP-2106x.
• Maintenance of a one-to-one correspondence with the
tools’ command line switches
The VisualDSP++ kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre-
emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-2106x
SHARC DSP has architectural features that improve the effi-
ciency of compiled C/C++ code.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with a drag of
the mouse, and examine run-time stack and heap usage. The
† CROSSCORE is a registered trademark of Analog Devices, Inc.
‡ VisualDSP++ is a registered trademark of Analog Devices, Inc.
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
expert linker is fully compatible with existing linker definition
file (LDF), allowing the developer to move between the graphi-
cal and textual environments.
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
In addition to the software development tools available from
Analog Devices, third parties provide a wide range of tools sup-
porting the SHARC processor family. Third party software tools
include DSP libraries, real-time operating systems, and block
diagram design tools.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-2106x
architecture and functionality. For detailed information on the
ADSP-21000 family core architecture and instruction set, refer
to the ADSP-2106x SHARC User’s Manual, Revision 2.1.
EVALUATION KIT
Analog Devices offers a range of EZ-KIT Lite®† evaluation plat-
forms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces-
sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a standal-
one unit, without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus-
tom-defined system. Connecting an Analog Devices JTAG
emulator to the EZ-KIT Lite board enables high speed, nonin-
trusive emulation.
DESIGNING AN EMULATOR-COMPATIBLE DSP
BOARD (TARGET)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect target system loading or tim-
ing. The emulator uses the TAP to access the internal features of
the DSP, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
DSP must be halted to send data and commands, but once an
operation has been completed by the emulator, the DSP system
is set running at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
† EZ-KIT Lite is a registered trademark of Analog Devices, Inc.
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
PIN FUNCTION DESCRIPTIONS
The ADSP-2106x pin definitions are listed below. Inputs identi-
fied as synchronous (S) must meet timing requirements with
respect to CLKIN (or with respect to TCK for TMS, TDI).
Inputs identified as asynchronous (A) can be asserted asynchro-
nously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31–0, DATA47–0, FLAG3–0, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
TCLKx, RCLKx, LxDAT3–0, LxCLK, LxACK, TMS, and
TDI)—these pins can be left floating. These pins have a
logic-level hold circuit that prevents the input from floating
internally.
Table 3. Pin Descriptions
Pin
Type
Function
ADDR31–0
I/O/T
External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals on these
pins. In a multiprocessor system, the bus master outputs addresses for read/write of the internal memory
or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host processor or multi-
processing bus master is reading or writing its internal memory or IOP registers.
DATA47–0
MS3–0
I/O/T
O/T
External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit single-
precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the bus. 40-bit
extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short word data is
transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over bits 23–16. Pull-up
resistors on unused DATA pins are not necessary.
Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of external
memory. Memory bank size must be defined in the ADSP-2106x’s system control register (SYSCON). The
MS3–0 lines are decoded memory address lines that change at the same time as the other address lines.
When no external memory access is occurring, the MS3–0 lines are inactive; they are active however when
a conditional memory access instruction is executed, whether or not the condition is true. MS0 can be used
with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system the MS3–0
lines are output by the bus master.
RD
I/O/T
I/O/T
O/T
Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memory devices
or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-2106xs) must
assert RD to read from the ADSP-2106x’s internal memory. In a multiprocessing system, RD is output by the
bus master and is input by all other ADSP-2106xs.
WR
Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memory devices
or to the internal memory of other ADSP-2106xs. External devices must assert WR to write to the ADSP-
2106x’s internal memory. In a multiprocessing system, WR is output by the bus master and is input by all
other ADSP-2106xs.
PAGE
DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM page boundary
has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control register (WAIT).
DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for Bank
0 accesses. In a multiprocessing system, PAGE is output by the bus master
ADRCLK
SW
O/T
Clock Output Reference. In a multiprocessing system, ADRCLK is output by the bus master.
I/O/T
Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous memory devices
(including other ADSP-2106xs). The ADSP-2106x asserts SW (low) to provide an early indication of an
impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write
instruction). In a multiprocessing system, SW is output by the bus master and is input by all other
ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same
time as the address output. A host processor using synchronous writes must assert this pin when writing to
the ADSP-2106x(s).
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
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Table 3. Pin Descriptions (Continued)
Pin
Type
Function
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-2106x deasserts ACK as an output to add waitstates to a synchronous
access of its internal memory. In a multiprocessing system, a slave ADSP-2106x deasserts the bus master’s
ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.
SBTS
I/S
Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data,
selects, and strobes in a high impedance state for the following cycle. If the ADSP-2106x attempts to access
externalmemorywhileSBTSisasserted, theprocessorwillhaltandthememoryaccesswillnotbecompleted
until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-2106x deadlock,
or used with a DRAM controller.
IRQ2–0
I/A
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG3–0
I/O/A
Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as
a condition. As an output, they can be used to signal external peripherals.
TIMEXP
HBR
O
Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.
I/A
Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-2106x’s
external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master will
relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address, data, select
and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests BR6–1 in a
multiprocessing system.
HBG
I/O
Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the
externalbus. HBGisasserted(heldlow)bytheADSP-2106xuntilHBRisreleased. Inamultiprocessingsystem,
HBG is output by the ADSP-2106x bus master and is monitored by all others.
CS
I/A
Chip Select. Asserted by host processor to select the ADSP-2106x.
REDY
O (O/D)
HostBusAcknowledge. TheADSP-2106xdeassertsREDY(low)toaddwaitstatestoanasynchronousaccess
of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be
programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if
the CS and HBR inputs are asserted.
DMAR2–1
DMAG2–1
BR6–1
I/A
DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 8).
DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 8).
O/T
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-ship. An
ADSP-2106x only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all
others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be pulled
high; the processor’s own BRx line must not be pulled high or low because it is an output.
ID2–0
RPBA
O (O/D)
I/S
Multiprocessing ID. Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-2106x.
ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor systems. These
lines are a system configuration selection that should be hardwired or changed at reset only.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed during
system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
CPA
I/O (O/D)
Core Priority Access. Asserting its CPA pin allows the core processor ofan ADSP-2106x bus slave to interrupt
backgroundDMAtransfersandgainaccesstotheexternalbus. CPAisanopendrainoutputthatisconnected
to all ADSP-2106xs in the system. The CPA pin has an internal 5 kꢁ pull-up resistor. If core access priority is
not required in a system, the CPA pin should be left unconnected.
DTx
O
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kꢁ internal pull-up resistor.
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kꢁ internal pull-up resistor.
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kꢁ internal pull-up resistor.
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kꢁ internal pull-up resistor.
DRx
I
TCLKx
RCLKx
I/O
I/O
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
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Table 3. Pin Descriptions (Continued)
Pin
Type
I/O
Function
TFSx
Transmit Frame Sync (Serial Ports 0, 1).
Receive Frame Sync (Serial Ports 0, 1).
RFSx
I/O
LxDAT3–0
I/O
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kꢁ internal pull-down resistor that is enabled or
disabled by the LPDRD bit of the LCOM register.
LxCLK
LxACK
EBOOT
I/O
I/O
I
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kꢁ internal pull-down resistor that is enabled or
disabled by the LPDRD bit of the LCOM register.
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kꢁ internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-bit EPROM.
When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin
description below. This signal is a system configuration selection that should be hardwired.
LBOOT
BMS
I
Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When LBOOT is low,
the ADSP-2106x is configured for host processor booting or no booting. See the table in the BMS pin
description below. This signal is a system configuration selection that should be hardwired.
I/OT
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1, LBOOT = 0).
In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will
occur and that ADSP-2106x will begin executing instructions from external memory. See table below. This
input is a system configuration selection that should be hardwired. *Three-statable only in EPROM boot
mode (when BMS is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
CLKIN
RESET
I
Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN. CLKIN should
not be halted, changed, or operated below the minimum specified frequency.
I/A
Processor Reset. Resets the ADSP-2106x to a known state and begins program execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
TCK
TMS
TDI
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
I/S
I/S
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kꢁ internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kꢁ internal pull-up
resistor.
TDO
TRST
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
I/A
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held
low for proper operation of the ADSP-2106x. TRST has a 20 kꢁ internal pull-up resistor.
EMU
ICSA
VDD
GND
NC
O
O
P
Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.
Reserved, leave unconnected.
Power Supply; nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins).
Power Supply Return. (30 pins).
G
Do Not Connect. Reserved pins which must be left open and unconnected.
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
The JTAG signals are terminated on the EZ-ICE probe as shown
in Table 4.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE® Emulator uses the IEEE
1149.1JTAG test access port of the ADSP-2106x to monitor and
control the target board processor during emulation. The
EZ-ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK,
TRST, TDI, TDO, EMU, and GND signals be made accessible
on the target system via a 14-pin connector (a 2-row 7-pin strip
header) such as that shown in Figure 5. The EZ-ICE probe plugs
directly onto this connector for chip-on-board emulation. You
must add this connector to your target board design if you
intend to use the ADSP-2106x EZ-ICE. The total trace length
between the EZ-ICE connector and the furthest device sharing
the EZ-ICE JTAG pin should be limited to 15 inches maximum
for guaranteed operation. This length restriction must include
EZ-ICE JTAG signals that are routed to one or more
Table 4. Core Instruction Rate/CLKIN Ratio Selection
Signal
TMS
Termination
Driven Through 22 ꢁ Resistor (16 mA Driver)
TCK
Driven at 10 MHz Through 22 ꢁ Resistor (16 mA
Driver)
TRST1
Active Low Driven Through 22 ꢁ Resistor (16 mA
Driver) (Pulled-Up by On-Chip 20 kꢁ Resistor)
TDI
Driven by 22 ꢁ Resistor (16 mA Driver)
One TTL Load, Split Termination (160/220)
One TTL Load, Split Termination (160/220)
TDO
CLKIN
EMU
Active Low 4.7 kꢁ Pull-Up Resistor, One TTL Load
ADSP-2106x devices, or a combination of ADSP-2106x devices
and other JTAG devices on the chain.
(Open-Drain Output from the DSP)
1 TRSTis driven low until the EZ-ICE probe is turned on by the emulator at software
start-up. After software start-up, is driven high.
1
3
5
2
4
6
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
EMU
GND
TMS
GND
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform oper-
ations such as starting, stopping, and single-stepping multiple
ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces-
sors, simply tie Pin 4 of the EZ-ICE header to ground.
KEY (NO PIN)
BTMS
7
9
8
BTCK
TCK
10
12
BTRST
TRST
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple
ADSP-2106x processors and the CLKIN pin on the EZ-ICE
header must be minimal. If the skew is too large, synchronous
operations may be off by one or more cycles between proces-
sors. For synchronous multiprocessor operation TCK, TMS,
CLKIN, and EMU should be treated as critical signals in terms
of skew, and should be laid out as short as possible on your
board. If TCK, TMS, and CLKIN are driving a large number of
ADSP-2106xs (more than eight) in your system, then treat them
as a “clock tree” using multiple drivers to minimize skew. (See
Figure 7 and “JTAG Clock Tree” and “Clock Distribution” in
the “High Frequency Design Considerations” section of the
ADSP-2106x User’s Manual, Revision 2.1.)
9
11
BTDI
GND
TDI
13
14
TDO
TOP VIEW
Figure 5. Target Board Connector for ADSP-2106x EZ-ICE Emulator
(Jumpers in Place)
The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca-
tion—Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 ꢂ 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK,
BTRST, and BTDI signals are provided so that the test access
port can also be used for board-level testing.
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 5. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
VDD. The TRST pin must be asserted (pulsed low) after power-
up (through BTRST on the connector) or held low for proper
operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7,
9, and 11) are connected on the EZ-ICE probe.
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
JTAG
DEVICE
(OPTIONAL)
ADSP-2106x
ADSP-2106x
#1
n
TDI
TDO
TDO
TDO
TDI
TDI
TDI
EZ-ICE
JTAG
CONNECTOR
OTHER
JTAG
CONTROLLER
TCK
TMS
EMU
TRST
TDO
CLKIN
OPTIONAL
Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems
TDI
TDO
TDI
TDO
TDI
TDO
5k⍀
*
TDI
TDO
TDI
TDO
TDI
TDO
TDI
5k⍀
*
EMU
TCK
TMS
TRST
TDO
SYSTEM
CLKIN
CLKIN
EMU
*OPEN-DRAIN DRIVER OR EQUIVALENT, i.e.,
Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
ADSP-21060/ADSP-21062 SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS (5 V)
A Grade
Min Max
C Grade
Min Max
K Grade
Min Max
Parameter
Description
Unit
VDD
Supply Voltage
4.75 5.25
–40 +85
4.75 5.25
–40 +100
4.75 5.25
–40 +85
V
ꢃC
V
V
V
TCASE
VIH11
VIH22
Case Operating Temperature
High Level Input Voltage @ VDD = Max
High Level Input Voltage @ VDD = Max
Low Level Input Voltage @ VDD = Min
2.0
2.2
VDD + 0.5
VDD + 0.5
2.0
2.2
VDD + 0.5
VDD + 0.5
2.0
2.2
VDD + 0.5
VDD + 0.5
1, 2
VIL
–0.5 +0.8
–0.5 +0.8
–0.5 +0.8
1 Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA, TFS0,
TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
2 Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (5 V)
Parameter
Description
Test Conditions
Min
Max
Unit
1, 2
VOH
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
@ VDD = Min, IOH = –2.0 mA
@ VDD = Min, IOL = 4.0 mA
@ VDD = Max, VIN = VDD Max
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = VDD Max
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = VDD Max
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = 1.5 V
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = 0 V
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
4.1
V
V
1, 2
VOL
0.4
10
10
150
10
10
350
1.5
350
4.2
150
4.7
3, 4
IIH
μA
μA
μA
μA
μA
μA
mA
μA
mA
μA
pF
3
IIL
4
IILP
Low Level Input Current
5, 6, 7, 8
IOZH
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Input Capacitance
5, 9
IOZL
9
IOZHP
IOZLC
IOZLA
7
10
8
IOZLAR
6
IOZLS
11, 12
CIN
1 Applies to output and bidirectional pins: DATA47–0, ADDR31-0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2,
BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
2 See “Output Drive Currents” for typical drive current capabilities.
3 Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
4 Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
5 Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx,
TDO, EMU. (Note that ACK is pulled up internally with 2 kꢁ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus
mastership.)
6 Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
7 Applies to CPA pin.
8 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kꢁ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL
is not requesting bus mastership).
9 Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK.
10Applies to ACK pin when keeper latch enabled.
11Applies to all signal pins.
12Guaranteed but not tested.
Rev. F
|
Page 15 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
INTERNAL POWER DISSIPATION (5 V)
These specifications apply to the internal power portion of VDD
only. For a complete discussion of the code used to measure
power dissipation, see the technical note “SHARC Power Dissi-
pation Measurements.”
Specifications are based on the operating scenarios.
Operation
Peak Activity (IDDINPEAK
Multifunction
)
High Activity (IDDINHIGH
Multifunction
)
Low Activity (IDDINLOW
Single Function
Internal Memory
None
)
Instruction Type
Instruction Fetch
Core memory Access
Internal Memory DMA
Cache
Internal Memory
1 per Cycle (DM)
1 per 2 Cycles
2 per Cycle (DM and PM)
1 per Cycle
1 per 2 Cycles
To estimate power consumption for a specific application, use
the following equation where % is the amount of time your pro-
gram spends in that state:
%PEAK IDDINPEAK +%HIGH IDDINHIGH +%LOW IDDINLOW
%IDLE IDDIDLE = Power Consumption
+
Parameter
DDINPEAK Supply Current (Internal)1
Test Conditions
Max
Units
I
tCK = 30 ns, VDD = Max
tCK = 25 ns, VDD = Max
745
850
mA
mA
IDDINHIGH Supply Current (Internal)2
tCK = 30 ns, VDD = Max
tCK = 25 ns, VDD = Max
575
670
mA
mA
I
I
DDINLOW Supply Current (Internal)2
DDIDLE Supply Current (Idle)3
tCK = 30 ns, VDD = Max
340
390
mA
mA
t
CK = 25 ns, VDD = Max
VDD = Max
200
mA
1 The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified.
2 IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code.
3 Idle denotes ADSP-2106x state during execution of IDLE instruction.
Rev. F
|
Page 16 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
drive high and low at a maximum rate of 1/(2tCK). The write
strobe can switch every cycle at a frequency of 1/tCK. Select pins
switch at 1/(2tCK), but selects can switch on each cycle.
EXTERNAL POWER DISSIPATION (5 V)
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
Example: Estimate PEXT with the following assumptions:
• A system with one bank of external data memory RAM
(32-bit)
P
INT = IDDIN ꢂ VDD
• Four 128K ꢂ 8 RAM chips are used, each with a load of
10 pF
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• External data memory writes occur every other cycle, a rate
of 1/(4tCK), with 50% of the pins switching
• the number of output pins that switch during each cycle
(O)
• The instruction cycle rate is 40 MHz (tCK = 25 ns)
• the maximum frequency at which they can switch (f)
• their load capacitance (C)
The PEXT equation is calculated for each class of pins that can
drive:
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
• their voltage swing (VDD)
and is calculated by:
P
TOTAL = PEXT + (IDDIN2 ꢂ 5.0 V)
P
EXT = O ꢂ C ꢂ VDD2 ꢂ f
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
Table 5. External Power Calculations (5 V Devices)
2
Pin Type
Address
MS0
No. of Pins % Switching
ꢂ C
ꢂ f
ꢂ VDD
ꢂ 25 V
ꢂ 25 V
ꢂ 25 V
ꢂ 25 V
ꢂ 25 V
= PEXT
15
1
50
0
ꢂ 44.7 pF
ꢂ 44.7 pF
ꢂ 44.7 pF
ꢂ 14.7 pF
ꢂ 4.7 pF
ꢂ 10 MHz
ꢂ 10 MHz
ꢂ 20 MHz
ꢂ 10 MHz
ꢂ 20 MHz
= 0.084 W
= 0.000 W
= 0.022 W
= 0.059 W
= 0.002 W
WR
1
–
Data
32
1
50
–
ADDRCLK
P
EXT = 0.167 W
Rev. F
|
Page 17 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
ADSP-21060L/ADSP-21062L SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS (3.3 V)
A Grade
Min Max
C Grade
Min Max
K Grade
Min Max
Parameter
Description
Unit
VDD
Supply Voltage
3.15 3.45
–40 +85
3.15 3.45
–40 +100
3.15 3.45
–40 +85
V
ꢃC
V
V
V
TCASE
VIH11
VIH22
Case Operating Temperature
High Level Input Voltage @ VDD = Max
High Level Input Voltage @ VDD = Max
Low Level Input Voltage @ VDD = Min
2.0
2.2
VDD + 0.5
VDD + 0.5
2.0
2.2
VDD + 0.5
VDD + 0.5
2.0
2.2
VDD + 0.5
VDD + 0.5
1, 2
VIL
–0.5 +0.8
–0.5 +0.8
–0.5 +0.8
1 Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA,
TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1
2 Applies to input pins: CLKIN, RESET, TRST
ELECTRICAL CHARACTERISTICS (3.3 V)
Parameter
Description
Test Conditions
Min
Max
Unit
1, 2
VOH
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
@ VDD = Min, IOH = –2.0 mA
@ VDD = Min, IOL = 4.0 mA
@ VDD = Max, VIN = VDD Max
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = VDD Max
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = VDD Max
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = 1.5 V
@ VDD = Max, VIN = 0 V
@ VDD = Max, VIN = 0 V
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
2.4
V
V
1, 2
VOL
0.4
10
10
150
10
10
350
1.5
350
4.2
150
4.7
3, 4
IIH
μA
μA
μA
μA
μA
μA
mA
μA
mA
μA
pF
3
IIL
4
IILP
Low Level Input Current
5, 6, 7, 8
IOZH
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Input Capacitance
5, 9
IOZL
9
IOZHP
IOZLC
IOZLA
7
10
8
IOZLAR
6
IOZLS
11, 12
CIN
1 Applies to output and bidirectional pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2,
BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
2 See “Output Drive Currents” for typical drive current capabilities.
3 Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
4 Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
5 Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx,
TDO, EMU. (Note that ACK is pulled up internally with 2 kꢁ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus
mastership.)
6 Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
7 Applies to CPA pin.
8 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kꢁ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL
is not requesting bus mastership).
9 Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK.
10Applies to ACK pin when keeper latch enabled.
11Applies to all signal pins.
12Guaranteed but not tested.
Rev. F
|
Page 18 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
INTERNAL POWER DISSIPATION (3.3 V)
These specifications apply to the internal power portion of VDD
only. For a complete discussion of the code used to measure
power dissipation, see the technical note “SHARC Power Dissi-
pation Measurements.”
Specifications are based on the operating scenarios.
Operation
Peak Activity (IDDINPEAK
Multifunction
)
High Activity (IDDINHIGH
Multifunction
)
Low Activity (IDDINLOW
Single Function
Internal Memory
None
)
Instruction Type
Instruction Fetch
Core memory Access
Internal Memory DMA
Cache
Internal Memory
1 per Cycle (DM)
1 per 2 Cycles
2 per Cycle (DM and PM)
1 per Cycle
1 per 2 Cycles
To estimate power consumption for a specific application, use
the following equation where % is the amount of time your pro-
gram spends in that state:
%PEAK IDDINPEAK + %HIGH IDDINHIGH + %LOW IDDINLOW
%IDLE IDDIDLE = Power Consumption
+
Parameter
DDINPEAK Supply Current (Internal)1
Test Conditions
Max
Units
I
tCK = 30 ns, VDD = Max
tCK = 25 ns, VDD = Max
540
600
mA
mA
IDDINHIGH Supply Current (Internal)2
tCK = 30 ns, VDD = Max
tCK = 25 ns, VDD = Max
425
475
mA
mA
I
I
DDINLOW Supply Current (Internal)2
DDIDLE Supply Current (Idle)3
tCK = 30 ns, VDD = Max
250
275
mA
mA
t
CK = 25 ns, VDD = Max
VDD = Max
180
mA
1 The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified.
2 IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code.
3 Idle denotes ADSP-2106xL state during execution of IDLE instruction.
Rev. F
|
Page 19 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
drive high and low at a maximum rate of 1/(2tCK). The write
strobe can switch every cycle at a frequency of 1/tCK. Select pins
switch at 1/(2tCK), but selects can switch on each cycle.
EXTERNAL POWER DISSIPATION (3.3 V)
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
Example: Estimate PEXT with the following assumptions:
• A system with one bank of external data memory RAM
(32-bit)
P
INT = IDDIN ꢂ VDD
• Four 128K ꢂ 8 RAM chips are used, each with a load of
10 pF
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• External data memory writes occur every other cycle, a rate
of 1/(4tCK), with 50% of the pins switching
• the number of output pins that switch during each cycle
(O)
• The instruction cycle rate is 40 MHz (tCK = 25 ns)
• the maximum frequency at which they can switch (f)
• their load capacitance (C)
The PEXT equation is calculated for each class of pins that can
drive:
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
• their voltage swing (VDD
and is calculated by:
)
P
TOTAL = PEXT + (IDDIN2 ꢂ 5.0 V)
P
EXT = O ꢂ C ꢂ VDD2 ꢂ f
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
Table 6. External Power Calculations (3.3 V Devices)
2
Pin Type
Address
MS0
No. of Pins
% Switching
ꢂ C
ꢂ f
ꢂ VDD
= PEXT
15
1
50
0
ꢂ 44.7 pF
ꢂ 44.7 pF
ꢂ 44.7 pF
ꢂ 14.7 pF
ꢂ 4.7 pF
ꢂ 10 MHz
ꢂ 10 MHz
ꢂ 20 MHz
ꢂ 10 MHz
ꢂ 20 MHz
ꢂ 10.9 V
ꢂ 10.9 V
ꢂ 10.9 V
ꢂ 10.9 V
ꢂ 10.9 V
= 0.037 W
= 0.000 W
= 0.010 W
= 0.026 W
= 0.001 W
WR
1
–
Data
32
1
50
–
ADDRCLK
P
EXT = 0.074 W
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed Table 7 may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table 7. Absolute Maximum Ratings
ADSP-21060/ADSP-21060C
ADSP-21062
ADSP-21060L/ADSP-21060LC
ADSP-21062L
Parameter
5 V
3.3 V
Supply Voltage (VDD)
Input Voltage
–0.3 V to +7.0 V
–0.5 V to VDD + 0.5 V
–0.5 V to VDD + 0.5 V
200 pF
–0.3 V to +4.6 V
–0.5 V to VDD +0.5 V
–0.5 V to VDD + 0.5 V
200 pF
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Lead Temperature (5 seconds)
Junction Temperature Under Bias
–65ꢃC to +150ꢃC
280ꢃC
130ꢃC
–65ꢃC to +150ꢃC
280ꢃC
130ꢃC
Rev. F
|
Page 20 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
ESD CAUTION
TIMING SPECIFICATIONS
The ADSP-2106x processors are available at maximum proces-
sor speeds of 33 MHz (–133), and 40 MHz (–160). The timing
specifications are based on a CLKIN frequency of 40 MHz
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
t
CK = 25 ns). The DT derating factor enables the calculation for
timing specifications within the min to max range of the tCK
specification (see Table 9). DT is the difference between the der-
ated CLKIN period and a CLKIN period of 25 ns:
DT = tCK – 25 ns
PACKAGE MARKING INFORMATION
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, you
cannot meaningfully add parameters to derive longer times.
Figure 8 and Table 8 provide information on detail contained
within the package marking for the ADSP-2106x processors
(actual marking format may vary). For a complete listing of
product availability, see Ordering Guide on Page 61.
For voltage reference levels, see Figure 28 on Page 47 under Test
Conditions.
a
ADSP-2106x
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices. (O/D) = Open Drain,
(A/D) = Active Drive.
tppZccc
vvvvvv.x n.n
yyww country_of_origin
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
S
Figure 8. Typical Package Brand
Table 8. Package Brand Information
Brand Key
Field Description
Temperature Range
Package Type
t
pp
Z
Lead (Pb) Free Option
See Ordering Guide
Assembly Lot Code
Silicon Revision
ccc
vvvvvv.x
n.n
yyww
Date Code
Rev. F
|
Page 21 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Clock Input
Table 9. Clock Input
ADSP-21060
ADSP-21062
40 MHz, 5 V
ADSP-21060
ADSP-21062
33 MHz, 5 V
ADSP-21060L
ADSP-21062L
40 MHz, 3.3 V
ADSP-21060L
ADSP-21062L
33 MHz, 3.3 V
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Timing Requirements
tCK
CLKIN Period
25
7
100
30
7
100
25
8.75
5
100
30
8.751
100
ns
ns
ns
ns
tCKL
CLKIN Width Low
tCKH CLKIN Width High
5
5
5
tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V)
3
3
3
3
1 For the ADSP-21060LC, this specification is 9.5 ns min.
tCK
CLKIN
tCKH
tCKL
Figure 9. Clock Input
Reset
Table 10. Reset
5 V and 3.3 V
Max
Unit
Parameter
Min
Timing Requirements
tWRST
tSRST
RESET Pulse Width Low1
RESET Setup Before CLKIN High2
4tCK
ns
ns
14 + DT/2
tCK
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
2 Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-2106xs commu-
nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
tSRST
tWRST
RESET
Figure 10. Reset
Rev. F
|
Page 22 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Interrupts
Table 11. Interrupts
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSIR
tHIR
tIPW
IRQ2–0 Setup Before CLKIN High1
IRQ2–0 Hold Before CLKIN High1
IRQ2–0 Pulse Width2
18 + 3DT/4
2+tCK
ns
ns
ns
12 + 3DT/4
1 Only required for IRQx recognition in the following cycle.
2 Applies only if tSIR and tHIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ2–0
tIPW
Figure 11. Interrupts
Timer
Table 12. Timer
5 V and 3.3 V
Unit
Parameter
Min
Max
Switching Characteristic
tDTEX
CLKIN High to TIMEXP
15
ns
CLKIN
tDTEX
tDTEX
TIMEXP
Figure 12. Timer
Rev. F
|
Page 23 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Flags
Table 13. Flags
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSFI
FLAG3–0 IN Setup Before CLKIN High1
FLAG3–0 IN Hold After CLKIN High1
FLAG3–0 IN Delay After RD/WR Low1
FLAG3–0 IN Hold After RD/WR Deasserted1
8 + 5DT/16
0 – 5DT/16
ns
ns
ns
ns
tHFI
tDWRFI
tHFIWR
Switching Characteristics
5 + 7DT/16
0
tDFO
FLAG3–0 OUT Delay After CLKIN High
16
14
ns
ns
ns
ns
tHFO
FLAG3–0 OUT Hold After CLKIN High
CLKIN High to FLAG3–0 OUT Enable
CLKIN High to FLAG3–0 OUT Disable
4
3
tDFOE
tDFOD
1 Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.
CLKIN
tDFO
tDFOE
tDFO
tDFOD
tHFO
FLAG3–0 OUT
FLAG OUTPUT
CLKIN
tSFI
tHFI
FLAG3–0 IN
tDWRFI
tHFIWR
RD/WR
FLAG INPUT
Figure 13. Flags
Rev. F
|
Page 24 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is the
Table 14. Memory Read—Bus Master
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tDAD
Address Selects Delay to Data Valid1, 2
RD Low to Data Valid1
Data Hold from Address, Selects3
Data Hold from RD High3
ACK Delay from Address, Selects2, 4
ACK Delay from RD Low4
18 + DT+W
ns
ns
ns
ns
ns
ns
tDRLD
tHDA
12 + 5DT/8 + W
0.5
2.0
tHDRH
tDAAK
tDSAK
14 + 7DT/8 + W
8 + DT/2 + W
Switching Characteristics
tDRHA
tDARL
tRW
Address Selects Hold After RD High
Address Selects to RD Low2
0+H
ns
ns
ns
ns
ns
2 + 3DT/8
RD Pulse Width
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0 + DT/4
tRWR
RD High to WR, RD, DMAGx Low
Address, Selects Setup Before ADRCLK High2
tSADADC
W = (number of wait states specified in WAIT register)
؋
tCK .
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1 Data delay/setup: user must meet tDAD or tDRLD or synchronous spec tSSDATI
.
2 The falling edge of MSx, SW, BMS is referenced.
3 Data hold: user must meet tHDA or tHDRH or synchronous spec tHSDATI. See Example System Hold Time Calculation on Page 47 for the calculation of hold times given capacitive
and dc loads.
4 ACK delay/setup: user must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (low), all three specifications must be met for assertion of ACK (high).
ADDRESS
MSx, SW
BMS
tDRHA
tDARL
tRW
RD
tHDA
tHDRH
tDRLD
tDAD
DATA
tDSAK
tRWR
tDAAK
ACK
WR, DMAG
tSADADC
ADRCLK
(OUT)
Figure 14. Memory Read—Bus Master
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is the
Table 15. Memory Write—Bus Master
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tDAAK
tDSAK
ACK Delay from Address, Selects1, 2
ACK Delay from WR Low1
14 + 7DT/8 + W
8 + DT/2 + W
ns
ns
Switching Characteristics
tDAWH
tDAWL
tWW
Address Selects to WR Deasserted2
Address Selects to WR Low2
17 + 15DT/16 + W
3 + 3DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR Pulse Width
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 +H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
tDDWH
tDWHA
tDATRWH
tWWR
Data Setup Before WR High
Address Hold After WR Deasserted
Data Disable After WR Deasserted3
WR High to WR, RD, DMAGx Low
Data Disable Before WR or RD Low
WR Low to Data Enabled
6 + DT/16+H
tDDWR
tWDE
tSADADC
Address, Selects Setup Before ADRCLK High2
0 + DT/4
W = (number of wait states specified in WAIT register) × tCK
.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1 ACK delay/setup: user must meet tDAAK or tDSAK or synchronous specification tSAKC for deassertion of ACK (low), all three specifications must be met for assertion of ACK
(High).
2 The falling edge of MSx, SW, BMS is referenced.
3 See Example System Hold Time Calculation on Page 47 for calculation of hold times given capacitive and dc loads.
ADDRESS
MSx, SW
BMS
tDWHA
tDAWH
tWW
tDAWL
WR
tWWR
tDDWR
tDDWH
tWDE
tDATRWH
DATA
tDSAK
tDAAK
ACK
RD, DMAG
tSADADC
ADRCLK
(OUT)
Figure 15. Memory Write—Bus Master
Rev. F
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Page 26 of 64
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Bus Master on Page 26). When accessing a slave ADSP-2106x,
these switching characteristics must meet the slave’s timing
requirements for synchronous read/writes (see Synchronous
Read/Write—Bus Slave on Page 29). The slave ADSP-2106x
must also meet these (bus master) timing requirements for data
and acknowledge setup and hold times.
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory sys-
tems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes except where noted (see
Memory Read—Bus Master on Page 25 and Memory Write—
Table 16. Synchronous Read/Write—Bus Master
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSSDATI
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Delay After Address, Selects1, 2
ACK Setup Before CLKIN2
ACK Hold After CLKIN
3 + DT/8
ns
ns
ns
ns
ns
tHSDATI
3.5 – DT/8
tDAAK
14 + 7DT/8 + W
tSACKC
6.5+DT/4
–1 – DT/4
tHACK
Switching Characteristics
tDADRO
tHADRO
tDPGC
Address, MSx, BMS, SW Delay After CLKIN1
Address, MSx, BMS, SW Hold After CLKIN
PAGE Delay After CLKIN
7 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–1 – DT/8
9 + DT/8
16 + DT/8
4 – DT/8
tDRDO
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
Data Disable After CLKIN3
ADRCLK Delay After CLKIN
ADRCLK Period
–2 – DT/8
–3 – 3DT/16
8 + DT/4
tDWRO
4 – 3DT/16
12.5 + DT/4
19 + 5DT/16
7 – DT/8
tDRWL
tSDDATO
tDATTR
tDADCCK
tADRCK
tADRCKH
tADRCKL
0 – DT/8
4 + DT/8
tCK
10 + DT/8
ADRCLK Width High
(tCK/2 – 2)
(tCK/2 – 2)
ADRCLK Width Low
1 The falling edge of MSx, SW, BMS is referenced.
2 ACK delay/setup: user must meet tDAAK or tDSAK or synchronous specification tSAKC for deassertion of ACK (low), all three specifications must be met for assertion of ACK
(high).
3 See Example System Hold Time Calculation on Page 47 for calculation of hold times given capacitive and dc loads.
Rev. F
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Page 27 of 64
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
CLKIN
tADRCK
tADRCKH
tDADCCK
tADRCKL
ADDRCLK
tDADRO
tDAAK
tHADRO
ADDRESS,
BMS, SW, MSx
tDPGC
PAGE
tHACK
tSACKC
ACK
(IN)
READ CYCLE
tDRWL
tDRDO
RD
tHSDATI
tSSDATI
DATA (IN)
WRITE CYCLE
tDWRO
tDRWL
WR
tDATTR
tSDDATO
DATA
(OUT)
Figure 16. Synchronous Read/Write—Bus Master
Rev. F
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Page 28 of 64
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Synchronous Read/Write—Bus Slave
Use these specifications for bus master accesses of a slave’s IOP
registers or internal memory (in multiprocessor memory space).
The bus master must meet the bus slave timing requirements.
Table 17. Synchronous Read/Write—Bus Slave
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSADRI
Address, SW Setup Before CLKIN
15 + DT/2
ns
ns
ns
ns
ns
ns
ns
tHADRI
tSRWLI
Address, SW Hold After CLKIN
RD/WR Low Setup Before CLKIN1
RD/WR Low Hold After CLKIN2
RD/WR Pulse High
5 + DT/2
9.5 + 5DT/16
tHRWLI
tRWHPI
tSDATWH
tHDATWH
–4 – 5DT/16
8 + 7DT/16
3
5
1
Data Setup Before WR High
Data Hold After WR High
Switching Characteristics
tSDDATO
Data Delay After CLKIN3
tDATTR
tDACKAD
tACKTR
18 + 5DT/16
7 – DT/8
9
ns
ns
ns
ns
Data Disable After CLKIN4
ACK Delay After Address, SW5
ACK Disable After CLKIN5
0 – DT/8
–1 – DT/8
6 – DT/8
1 tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min)= 4 + DT/8.
2 For ADSP-21060C specification is –3.5 – 5DT/16 ns min, 8 + 7DT/16 ns max; for ADSP-21060LC specification is –3.75 – 5DT/16 ns min, 8 + 7DT/16 ns max.
3 For ADSP-21062/ADSP-21062L/ADSP-21060C specification is 19 + 5DT/16 ns max; for ADSP-21060LC specification is 19.25 + 5DT/16 ns max.
4 See Example System Hold Time Calculation on Page 47 for calculation of hold times given capacitive and dc loads.
5 tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup times
greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state
of MMSWS or strobes. A slave will three-state ACK every cycle with tACKTR
.
CLKIN
tSADRI
tHADRI
ADDRESS
tACKTR
tDACKAD
ACK
tSRWLI
tHRWLI
tRWHPI
READ ACCESS
RD
tDATTR
tSDDATO
DATA
(OUT)
WRITE ACCESS
tHRWLI
tRWHPI
tSRWLI
WR
DATA
(IN)
tHDATWH
tSDATWH
Figure 17. Synchronous Read/Write—Bus Slave
Rev. F
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Page 29 of 64
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106xs (BRx) or a host processor, both
synchronous and asynchronous (HBR, HBG).
Table 18. Multiprocessor Bus Request and Host Bus Request
5 V and 3.3 V
Unit
Parameter
Timing Requirements
tHBGRCSV
tSHBRI
Min
Max
HBG Low to RD/WR/CS Valid1
HBR Setup Before CLKIN2
HBR Hold After CLKIN2
20 + 5DT/4
14 + 3DT/4
6 + DT/2
6 + DT/2
12 + 3DT/4
7 – DT/8
7 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
20 + 3DT/4
13 + DT/2
13 + DT/2
21 + 3DT/4
tHHBRI
tSHBGI
HBG Setup Before CLKIN
HBG Hold After CLKIN High
BRx, CPA Setup Before CLKIN3
BRx, CPA Hold After CLKIN High
RPBA Setup Before CLKIN
RPBA Hold After CLKIN
tHHBGI
tSBRI
tHBRI
tSRPBAI
tHRPBAI
Switching Characteristics
tDHBGO
tHHBGO
tDBRO
HBG Delay After CLKIN
ns
ns
ns
ns
ns
ns
ns
ns
ns
HBG Hold After CLKIN
–2 – DT/8
BRx Delay After CLKIN
tHBRO
BRx Hold After CLKIN
CPA Low Delay After CLKIN4
–2 – DT/8
tDCPAO
tTRCPA
8 – DT/8
4.5 – DT/8
8.5
CPA Disable After CLKIN
–2 – DT/8
tDRDYCS
tTRDYHG
tARDYTR
REDY (O/D) or (A/D) Low from CS and HBR Low5, 6
REDY (O/D) Disable or REDY (A/D) High from HBG6, 7
REDY (A/D) Disable from CS or HBR High6
44 + 23DT/16
10
1 For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes low. This is
easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC
User’s Manual, Revision 2.1.
2 Only required for recognition in the current cycle.
3 CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4 For ADSP-21060LC, specification is 8.5 – DT/8 ns max.
5 For ADSP-21060L, specification is 9.5 ns max, For ADSP-21060LC, specification is 11.0 ns max, For ADSP-21062L, specification is 8.75 ns max.
6 (O/D) = open drain, (A/D) = active drive.
7 For ADSP-21060C/ADSP-21060LC, specification is 40 + 23DT/16 ns min.
Rev. F
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Page 30 of 64
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
CLKIN
tSHBRI
tHHBRI
HBR
tDHBGO
tHHBGO
HBG (OUT)
tDBRO
tHBRO
BRx (OUT)
tTRCP A
tDCPAO
CPA (OUT, O/D)
tSHBGI
tHHBGI
HBG (I N)
tSBRI
tHBRI
BRx, CPA (IN, O/D)
tSRPBAI
tHRPBAI
RP BA
HBR
CS
tTRDYHG
tDRDY CS
REDY
(O /D)
tARDY TR
REDY
(A/D)
tHBGRCSV
HBG (OUT)
RD
WR
CS
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18. Multiprocessor Bus Request and Host Bus Request
Rev. F
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Page 31 of 64
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
after goes low. For first access after asserted, ADDR31–0 must
be a non-MMS value 1/2 tCLK before or goes low or by tHBGRCSV
after goes low. This is easily accomplished by driving an upper
address signal high when is asserted. See the “Host Processor
Control of the ADSP-2106x” section in the ADSP-2106x
SHARC User’s Manual, Revision 2.1.
Asynchronous Read/Write—Host to ADSP-2106x
Use these specifications for asynchronous host processor
accesses of an ADSP-2106x, after the host has asserted CS and
HBR (low). After HBG is returned by the ADSP-2106x, the host
can drive the RD and WR pins to access the ADSP-2106x’s
internal memory or IOP registers. HBR and HBG are assumed
low for this timing. Not required if and address are valid tHBGRCSV
Table 19. Read Cycle
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSADRDL
tHADRDH
tWRWH
Address Setup/CS Low Before RD Low1
Address Hold/CS Hold Low After RD
RD/WR High Width
0
0
6
0
0
ns
ns
ns
ns
ns
tDRDHRDY
tDRDHRDY
Switching Characteristics
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
tSDATRDY
tDRDYRDL
tRDYPRD
tHDARWH
Data Valid Before REDY Disable from Low
2
ns
ns
ns
ns
REDY (O/D) or (A/D) Low Delay After RD Low2
REDY (O/D) or (A/D) Low Pulse Width for Read
Data Disable After RD High3
10
8
45 + 21DT/16
2
1 Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD or WR goes
low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the
ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1.
2 For ADSP-21060L, specification is 10.5 ns max; for ADSP-21060LC, specification is 12.5 ns max.
3 For ADSP-21060L/ADSP-21060LC, specification is 2 ns min, 8.5 ns max.
Table 20. Write Cycle
5 V and 3.3 V
Unit
Parameter
Timing Requirements
tSCSWRL
Min
Max
CS Low Setup Before WR Low
CS Low Hold After WR High
Address Setup Before WR High
Address Hold After WR High
WR Low Width
0
0
5
2
7
6
0
5
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHCSWRH
tSADWRH
tHADWRH
tWWRL
tWRWH
RD/WR High Width
tDWRHRDY
tSDATWH
WR High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WR High
Data Hold After WR High
tHDATWH
Switching Characteristics
tDRDYWRL
tRDYPWR
tSRDYCK
REDY (O/D) or (A/D) Low Delay After WR/CS Low
10
ns
ns
ns
REDY (O/D) or (A/D) Low Pulse Width for Write
REDY (O/D) or (A/D) Disable to CLKIN
15 + 7DT/16
1 + 7DT/16
8 + 7DT/16
Rev. F
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Page 32 of 64
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
CLKIN
tSRDYCK
RE DY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19. Synchronous REDY Timing
READ CYCLE
ADDRESS/CS
tHADRDH
tS ADRDL
tW RW H
RD
tHDARWH
DATA (OUT)
tDRDHRDY
tSDATRDY
tRDYPRD
tDRDY R DL
REDY (O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
tHADWRH
tSADWRH
tHCS WRH
tS CSWRL
CS
tW WRL
tWRWH
WR
tHDATWH
tSDATWH
DATA (IN)
tDWRHRDY
tDRDYWRL
tRDYPWR
RE DY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 20. Asynchronous Read/Write—Host to ADSP-2106x
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Three-State Timing—Bus Master/ Bus Slave
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master transi-
tion cycles (BTC) and host transition cycles (HTC) as well as the
SBTS pin.
Table 21. Three-State Timing—Bus Master, Bus Slave
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSTSCK
tHTSCK
Switching Characteristics
tMIENA
Address/Select Enable After CLKIN1
tMIENS
tMIENHG
tMITRA
SBTS Setup Before CLKIN
12 + DT/2
ns
ns
SBTS Hold Before CLKIN
6 + DT/2
–1.5 – DT/8
–1.5 – DT/8
–1.5 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Strobes Enable After CLKIN2
HBG Enable After CLKIN
Address/Select Disable After CLKIN3
Strobes Disable After CLKIN2
HBG Disable After CLKIN
0 – DT/4
tMITRS
1.5 – DT/4
2.0 – DT/4
tMITRHG
tDATEN
tDATTR
tACKEN
tACKTR
tADCEN
tADCTR
tMTRHBG
tMENHBG
Data Enable After CLKIN4
Data Disable After CLKIN4
ACK Enable After CLKIN4
ACK Disable After CLKIN4
9 + 5DT/16
0 – DT/8
7 – DT/8
6 – DT/8
8 – DT/4
7.5 + DT/4
–1 – DT/8
–2 – DT/8
ADRCLK Enable After CLKIN
ADRCLK Disable After CLKIN
Memory Interface Disable Before HBG Low5
Memory Interface Enable After HBG High5
0 + DT/8
19 + DT
1 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is –1.25 – DT/8 ns min, for ADSP-21062, specification is –1 – DT/8 ns min.
2 Strobes = RD, WR, PAGE, DMAG, BMS, SW.
3 For ADSP-21060LC, specification is 0.25 – DT/4 ns max.
4 In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
5 Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode).
HBG
tMTRHBG
tMENHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
Rev. F
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Page 34 of 64
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
CLKIN
tSTSCK
tHTSCK
SBTS
tMIENA, tMIENS, tMIENHG
tMITRA, tMITRS, tMITRHG
MEMORY
INTERFACE
tDATTR
tDATEN
DATA
tACKTR
tACKEN
ACK
tADCEN
tADCTR
ADRCLK
Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
and DMAGx signals. For Paced Master mode, the data transfer
is controlled by ADDR31–0, RD, WR, MS3–0, and ACK (not
DMAG). For Paced Master mode, the Memory Read-Bus Mas-
ter, Memory Write-Bus Master, and Synchronous Read/Write-
Bus Master timing specifications for ADDR31–0, RD, WR,
MS3–0, PAGE, DATA63–0, and ACK also apply.
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes, DMARx is used to initiate transfers. For
Handshake mode, DMAGx controls the latching or enabling of
data externally. For External handshake mode, the data transfer
is controlled by the ADDR31–0, RD, WR, PAGE, MS3–0, ACK,
Table 22. DMA Handshake
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSDRLC
DMARx Low Setup Before CLKIN1
DMARx High Setup Before CLKIN1
DMARx Width Low (Nonsynchronous)
Data Setup After DMAGx Low2
Data Hold After DMAGx High
Data Valid After DMARx High2
DMARx Low Edge to Low Edge
DMARx Width High2
5
5
6
ns
ns
ns
ns
ns
ns
ns
ns
tSDRHC
tWDR
tSDATDGL
tHDATIDG
tDATDRH
tDMARLL
tDMARH
10 + 5DT/8
16 + 7DT/8
2
23 + 7DT/8
6
Switching Characteristics
tDDGL
DMAGx Low Delay After CLKIN
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
15 + DT/4
6 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWDGH
tWDGL
DMAGx High Width
DMAGx Low Width
tHDGC
DMAGx High Delay After CLKIN
Data Valid Before DMAGx High3
Data Disable After DMAGx High4
WR Low Before DMAGx Low5
DMAGx Low Before WR High
WR High Before DMAGx High
RD Low Before DMAGx Low
RD Low Before DMAGx High
RD High Before DMAGx High
DMAGx High to WR, RD, DMAGx Low
Address/Select Valid to DMAGx High
Address/Select Hold After DMAGx High6
tVDATDGH
tDATRDGH
tDGWRL
tDGWRH
tDGWRR
tDGRDL
tDRDGH
tDGRDR
tDGWR
7
2
0
10 + 5DT/8 +W
1 + DT/16
0
3 + DT/16
2
11 + 9DT/16 + W
0
3
5 + 3DT/8 + HI
17 + DT
–0.5
tDADGH
tDDGHA
W = (number of wait states specified in WAIT register)
؋
tCK .
HI = tCK (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1 Only required for recognition in the current cycle.
2 tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can
be driven tDATDRH after DMARx is brought high.
3 tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = tCK – 0.25tCCLK – 8 + (n × tCK) where n equals
the number of extra cycles that the access is prolonged.
4 See Example System Hold Time Calculation on Page 47 for calculation of hold times given capacitive and dc loads.
5 For ADSP-21062/ADSP-21062L specification is –2.5 ns min, 2 ns max.
6 For ADSP-21060L/ADSP-21062L specification is –1 ns min.
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
CLKIN
tSDRLC
tDMARLL
tSDRHC
tWDR
tDMARH
DMARx
DMAGx
tHDGC
tDDGL
tWDGL
tWDGH
TRANSFERS BETWEEN ADSP-2106x
INTERNAL MEMORY AND EXTERNAL DEVICE
tDATRDGH
tVDATDGH
DATA
(OUT)
(FROM ADSP-2106x TO EXTERNAL DEVICE)
tDATDRH
tSDATDGL
tHDATIDG
DATA
(IN)
(FROM EXTERNAL DEVICE TO ADSP-2106x)
TRANSFERS BETWEEN EXTERNAL DEVICE AND
EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
tDGWRL
tDGWRR
tDGWRH
WR
(EXTERNAL DEVICE TO EXTERNAL MEMORY)
(EXTERNAL MEMORY TO EXTERNAL DEVICE)
tDGRDR
tDGRDL
RD
tDRDGH
tDADGH
tDDGHA
ADDR
MSx, SW
*MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER
TIMING SPECIFICATIONS FOR ADDR31–0, RD, WR, SW MS3–0, AND ACK ALSO APPLY HERE.
Figure 23. DMA Handshake
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Link Ports —1 × CLK Speed Operation
Table 23. Link Ports—Receive
5 V
Max
3.3 V
Max
Unit
Parameter
Min
Min
Timing Requirements
tSLDCL
Data Setup Before LCLK Low1
3.5
3
3
ns
ns
ns
ns
ns
tHLDCL
Data Hold After LCLK Low
LCLK Period (1ꢂ Operation)
LCLK Width Low
3
tLCLKIW
tLCLKRWL
tLCLKRWH
tCK
6
tCK
6
LCLK Width High
5
5
Switching Characteristics
tDLAHC
tDLALC
tENDLK
tTDLK
LACK High Delay After CLKIN High2, 3
18 + DT/2
–3
28.5 + DT/2
+13
18 + DT/2
–3
28.5 + DT/2
+13
ns
ns
ns
ns
LACK Low Delay After LCLK High
LACK Enable From CLKIN
5 + DT/2
5 + DT/2
LACK Disable From CLKIN
20 + DT/2
20 + DT/2
1 For ADSP-21062, specification is 3 ns min.
2 LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.
3 For ADSP-21060C, specification is 18 + DT/2 ns min, 29 + DT/2 ns max.
Table 24. Link Ports—Transmit
5 V
3.3 V
Max
Unit
Parameter
Min
Max
Min
Timing Requirements
tSLACH
tHLACH
Switching Characteristics
LACK Setup Before LCLK High1
18
–7
18
–7
ns
ns
LACK Hold After LCLK High
tDLCLK
Data Delay After CLKIN (1ꢂ
15.5
3
15.5
2.5
ns
Operation)2
tDLDCH
tHLDCH
tLCLKTWL
tLCLKTWH
tDLACLK
tENDLK
Data Delay After LCLK High3
Data Hold After LCLK High
LCLK Width Low4
ns
ns
ns
ns
–3
–3
(tCK/2) – 2
(tCK/2) – 2
(tCK/2) + 8.5
5 + DT/2
(tCK/2) + 2
(tCK/2) + 2
(tCK/2) – 1
(tCK/2) – 1.25
(tCK/2) + 1.25
(tCK/2) + 1
LCLK Width High5
LCLK Low Delay After LACK High6
LACK Enable From CLKIN
LACK Disable From CLKIN
(3 ꢂ tCK/2) + 17 (tCK/2) + 8
5 + DT/2
(3 ꢂ tCK/2) + 17.5 ns
ns
tTDLK
20 + DT/2
20 + DT/2
ns
1 For ADSP-21060L/ADSP-21060LC, specification is 20 ns min.
2 For ADSP-21060L, specification is 16.5 ns max; for ADSP-21060LC, specification is 16.75 ns max.
3 For ADSP-21062, specification is 2.5 ns max.
4 For ADSP-21062, specification is (tCK/2) – 1 ns min, (tCK/2) + 1.25 ns max; for ADSP-21062L, specification is (tCK/2) – 1 ns min, (tCK/2) + 1.5 ns max; for ADSP-21060LC
specification is (tCK/2) – 1 ns min, (tCK/2) + 2.25 ns max.
5 For ADSP-21062, specification is (tCK/2) – 1.25 ns min, (tCK/2) + 1 ns max; for ADSP-21062L, specification is (tCK/2) – 1.5 ns min, (tCK/2) + 1 ns max; for ADSP-21060C
specification is (tCK/2) – 2.25 ns min, (tCK/2) + 1 ns max.
6 For ADSP-21062, specification is (tCK/2) + 8.75 ns min, (3 × tCK/2) + 17 ns max; for ADSP-21062L, specification is (tCK/2) + 8 ns min, (3 × tCK/2) + 17 ns max; for
ADSP-21060LC specification is (tCK/2) + 8 ns min, (3 × tCK/2) + 18.5 ns max.
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 25. Link Port Service Request Interrupts:1ꢂ and 2ꢂ Speed Operations
5 V
Max
3.3 V
Max
Unit
Parameter
Min
Min
Timing Requirements
tSLCK
tHLCK
LACK/LCLK Setup Before CLKIN Low1 10
LACK/LCLK Hold After CLKIN Low1
10
2
ns
ns
2
1 Only required for interrupt recognition in the current cycle.
Hold skew is the maximum delay that can be introduced in
LCLK relative to LDATA:
Link Ports —2 × CLK Speed Operation
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK:
Hold Skew = tLCLKTWL min – tHLDCH – tHLDCL
Calculations made directly from 2 speed specifications will
result in unrealistically small skew times because they include
multiple tester guardbands.
Setup Skew = tLCLKTWH min – tDLDCH – tSLDCL
Note that link port transfers at 2× CLK speed at 40 MHz
(tCK = 25 ns) may fail. However, 2× CLK speed link port trans-
fers at 33 MHz (tCK = 30 ns) work as specified.
Table 26. Link Ports—Receive
5 V
Max
3.3 V
Max
Unit
Parameter
Min
Min
Timing Requirements
tSLDCL
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (2ꢂ Operation)
LCLK Width Low1
2.5
2.25
2.25
tCK/2
5.25
4
ns
ns
ns
ns
ns
tHLDCL
2.25
tCK/2
4.5
tLCLKIW
tLCLKRWL
tLCLKRWH
LCLK Width High2
4.25
Switching Characteristics
tDLAHC
LACK High Delay After CLKIN High3
tDLALC
LACK Low Delay After LCLK High4
18 + DT/2
6
28.5 + DT/2
16
18 + DT/2
6
29.5 + DT/2
16
ns
ns
1 For ADSP-21060L, specification is 5 ns min.
2 For ADSP-21062, specification is 4 ns min, for ADSP-21060LC, specification is 4.5 ns min.
3 LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.
4 For ADSP-21060L, specification is 6 ns min, 18 ns max. For ADSP-21060C, specification is 6 ns min, 16.5 ns max. For ADSP-21060LC, specification is 6 ns min, 18.5 ns max.
Rev. F
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 27. Link Ports—Transmit
5 V
Max
3.3 V
Max
Unit
Parameter
Min
Min
Timing Requirements
tSLACH
tHLACH
Switching Characteristics
LACK Setup Before LCLK High
19
19
ns
ns
LACK Hold After LCLK High
–6.75
–6.5
tDLCLK
Data Delay After CLKIN
8
8
ns
ns
ns
ns
ns
tDLDCH
tHLDCH
tLCLKTWL
tLCLKTWH
tDLACLK
Data Delay After LCLK High1
Data Hold After LCLK High2
LCLK Width Low3
2.25
2.25
–2.0
–2
(tCK/4) – 1
(tCK/4) – 1.25
(tCK/4) + 9
(tCK/4) + 1.25
(tCK/4) + 1
(tCK/4) – 0.75
(tCK/4) – 1.5
(tCK/4) + 1.5
(tCK/4) + 1
LCLK Width High4
LCLK Low Delay After LACK High
(3 ꢂ tCK/4) + 16.5 (tCK/4) + 9
(3 ꢂ tCK/4) + 16.5 ns
1 For ADSP-21060/ADSP-21060C, specification is 2.5 ns max.
2 For ADSP-21062L, specification is –2.25 ns min.
3 For ADSP-21060, specification is (tCK/4) – 1ns min, (tCK/4) + 1 ns max; for ADSP-21060C/ADSP-21062L, specification is (tCK/4) – 1 ns min, (tCK/4) + 1.5 ns max.
4 For ADSP-21060, specification is (tCK/4) – 1 ns min, (tCK/4) + 1 ns max; for ADSP-21060C, specification is (tCK/4) – 1.5 ns min, (tCK/4) + 1 ns max.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
TRANSMIT
CLKIN
tDLCLK
tLCLKTWL
tLCLKTWH
LAST NIBBLE
TRANSMITTED
FIRST NIBBLE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LCLK 1x
OR
LCLK 2x
tDLDCH
tHLDCH
LDAT(3:0)
LACK (IN)
OUT
tDLACLK
tSLACH
tHLACH
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
RECEIVE
CLKIN
tLCLKIW
tLCLKRWH
tLCLKRWL
LCLK 1x
OR
LCLK 2x
tHLDCL
tSLDCL
IN
LDAT(3:0)
tDLALC
tDLAHC
LACK (OUT)
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
CLKIN
tENDLK
tTDLK
LCLK
LDAT(3:0)
LACK
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
LINK PORT INTERRUPT SETUPTIME
CLKIN
tHLCK
tSLCK
LCLK
LACK
Figure 24. Link Ports—Receive
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
at clock speed n, the following specifications must be confirmed:
1) frame sync delay and frame sync setup and hold, 2) data delay
and data setup and hold, and 3) SCLK width.
Serial Ports
For serial ports, see Table 28, Table 29, Table 30, Table 31,
Table 32, Table 33, Table 35, Figure 26, and Figure 25. To deter-
mine whether communication is possible between two devices
Table 28. Serial Ports—External Clock
5 V and 3.3 V
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
TFS/RFS Hold After TCLK/RCLK1, 2
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
TCLK/RCLK Width3
3.5
4
ns
ns
ns
ns
ns
ns
tHFSE
tSDRE
tHDRE
tSCLKW
tSCLK
1.5
6.5
9
TCLK/RCLK Period
2tCLK
1 Referenced to sample edge.
2 RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
3 For ADSP-21060/ADSP-21060C/ADSP-21060LC, specification is 9.5 ns min.
Table 29. Serial Ports—Internal Clock
5 V and 3.3 V
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
tHFSI
tSDRI
tHDRI
TFS Setup Before TCLK1; RFS Setup Before RCLK1
8
1
3
3
ns
ns
ns
ns
TFS/RFS Hold After TCLK/RCLK1, 2
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
1 Referenced to sample edge.
2 RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 30. Serial Ports—External or Internal Clock
5 V and 3.3 V
Parameter
Min
Max
Unit
Switching Characteristics
tDFSE
RFS Delay After RCLK (Internally Generated RFS)1
RFS Hold After RCLK (Internally Generated RFS)1
13
ns
ns
tHOFSE
3
1 Referenced to drive edge.
Table 31. Serial Ports—External Clock
5 V and 3.3 V
Max
Parameter
Min
Unit
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFS Delay After TCLK (Internally Generated TFS)1
TFS Hold After TCLK (Internally Generated TFS)1
Transmit Data Delay After TCLK1
13
16
ns
ns
ns
ns
3
5
Transmit Data Hold After TCLK1
1 Referenced to drive edge.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 32. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Switching Characteristics
tDFSI
TFS Delay After TCLK (Internally Generated TFS)1
4.5
ns
ns
ns
ns
ns
tHOFSI
TFS Hold After TCLK (Internally Generated TFS)1
Transmit Data Delay After TCLK1
Transmit Data Hold After TCLK1
TCLK/RCLK Width2
–1.5
tDDTI
7.5
tHDTI
0
tSCLKIW
0.5tSCLK –2.5
0.5tSCLK+2.5
1 Referenced to drive edge.
2 For ADSP-21060L/ADSP-21060C, specification is 0.5TSCLK – 2 ns min, 0.5tSCLK + 2 ns max.
Table 33. Serial Ports—Enable and Three-State
Parameter
Min
4
Max
Unit
Switching Characteristics
tDDTEN
Data Enable from External TCLK1, 2
Data Disable from External TCLK1, 3
Data Enable from Internal TCLK1
Data Disable from Internal TCLK1, 4
TCLK/RCLK Delay from CLKIN
SPORT Disable After CLKIN
ns
ns
ns
ns
ns
ns
tDDTTE
10.5
tDDTIN
0
tDDTTI
3
tDCLK
22 + 3 DT/8
17
tDPTR
1 Referenced to drive edge.
2 For ADSP-21060L/ADSP-21060C, specification is 3.5 ns min; for ADSP-21062 specification is 4.5 ns min.
3 For ADSP-21062L, specification is 16 ns max.
4 For ADSP-21062L, specification is 7.5 ns max.
Table 34. Serial Ports—GATED SCLK with External TFS (Mesh Multiprocessing)1
Parameter
Min
Max
Unit
Switching Characteristics
tSTFSCK
tHTFSCK
TFS Setup Before CLKIN
TFS Hold After CLKIN
4
ns
ns
tCK/2
1 Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.
Table 35. Serial Ports—External Late Frame Sync
Parameter
Min
Max
Unit
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1,
MFD = 01, 2
Data Enable from Late FS or MCE = 1, MFD = 01, 3
12
ns
ns
tDDTENFS
3.5
1 MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS
.
2 For ADSP-21062/ADSP-21062L, specification is 12.75 ns max; for ADSP-21060L/ADSP-21060LC, specification is 12.8 ns max.
3 For ADSP-21060/ADSP-21060C, specification is 3 ns min.
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
DATA RECEIVE— INTERNAL CLOCK
DATA RECEIVE— EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKW
tSCLKIW
RCLK
RCLK
tDFSE
tDFSE
tHOFSE
tHFSE
tSFSI
tHFSI
tSFSE
tHOFSE
RFS
DR
RFS
DR
tSDRI
tSDRE
tHDRI
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT— INTERNAL CLOCK
DATA TRANSMIT— EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
TFS
tDFSE
tDFSI
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
TFS
DT
tDDTI
tDDTE
tHDTE
tHDTI
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE DRIVE EDGE
TCLK/RCLK
TCLK
(EXT)
tDDTTE
tDDTEN
DT
DRIVE
EDGE
DRIVE
EDGE
TCLK/RCLK
TCLK
(INT)
tDDTIN
tDDTTI
DT
CLKIN
CLKIN
tHTFSCK
tDPTR
SPORT ENABLE AND
THREE-STATE
LATENCY
TCLK, RCLK
TFS, RFS, DT
tSTFSCK
SPORT DISABLE DELAY
FROM INSTRUCTION
TFS (EXT)
IS TWO CYCLES
tDCLK
TCLK (INT)
RCLK (INT)
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O
FOR MESH MULTIPROCESSING.
LOW TO HIGH ONLY
Figure 25. Serial Ports
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RCLK
RFS
tSFSE/I
tHOFSE/I
tDDTE/I
tHDTE/I
1ST BIT
tDDTENFS
DT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TCLK
tHOFSE/I
tSFSE/I
TFS
tDDTE/I
TDDTENFS
tHDTE/I
1ST BIT
DT
2ND BIT
tDDTLFSE
Figure 26. Serial Ports—External Late Frame Sync
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
JTAG Test Access Port and Emulation
For JTAG Test Access Port and Emulation, see Table 36 and
Figure 27.
Table 36. JTAG Test Access Port and Emulation
Parameter
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
tCK
5
ns
ns
ns
ns
ns
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1, 2
TRST Pulse Width
6
7
18
4tCK
Switching Characteristics
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
13
ns
ns
18.5
1 System Inputs = DATA63–0, ADDR31–0, RD, WR, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, PA, BRST, DR0, DR1, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
2 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is 18.5 ns min.
3 System Outputs = DATA63–0, ADDR31–0, MS3–0, RD, WR, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 27. JTAG Test Access Port and Emulation
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 29). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
TEST CONDITIONS
For the ac signal specifications (timing parameters), see Timing
Specifications on Page 21. These specifications include output
disable time, output enable time, and capacitive loading. The
timing specifications for the DSP apply for the voltage reference
levels in Figure 28.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ꢄV
to be the difference between the ADSP-2106x’s output voltage
and the input threshold for the device requiring the hold time. A
typical ꢄV will be 0.4 V. CL is the total bus capacitance (per data
line), and IL is the total leakage or three-state current (per data
line). The hold time will be tDECAY plus the minimum disable
time (i.e., tDATRWH for the write cycle).
INPUT
OR
OUTPUT
1.5V
1.5V
Figure 28. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 30). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figure 32,
Figure 33, Figure 37, and Figure 38 show how output rise time
varies with capacitance. Figure 34 and Figure 36 show
graphically how output delays and holds vary with load capaci-
tance. (Note that this graph or derating does not apply to output
disable delays; see the previous section Output Disable Time
under Test Conditions.) The graphs of Figure 32, Figure 33,
Figure 37, and Figure 38 may not be linear outside the ranges
shown.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ꢄV is dependent on the capacitive load, CL, and the
load current, IL. This decay time can be approximated by the fol-
lowing equation:
CLꢄV
IL
-------------
PEXT
=
The output disable time tDIS is the difference between
MEASURED and tDECAY as shown in Figure 29. The time tMEASURED is
the interval from when the reference signal switches to when the
output voltage decays ꢄV from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and IL,
and with ꢄV equal to 0.5 V.
t
IOL
TO
OUTPUT
PIN
+1.5V
50pF
REFERENCE
SIGNAL
tMEASURED
tENA
tDIS
VOH (MEASURED)
IOH
VOH (MEASURED)
VOH (MEASURED) - ⌬V
VOL (MEASURED) + ⌬V
tDECAY
2.0V
1.0V
Figure 30. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
VOL (MEASURED)
VOL (MEASURED)
OUTPUT STARTS
DRIVING
Output Drive Characteristics
OUTPUT STOPS
DRIVING
Figure 31 shows typical I-V characteristics for the output driv-
ers of the ADSP-2106x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
Figure 29. Output Enable/Disable
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
Rev. F
|
Page 47 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Output Characteristics (5 V)
3.5
3.0
2.5
2.0
1.5
75
50
25
5.25V, -40°C
5.0V, +25°C
0
RISE TIME
Y = 0.009x + 1.1
4.75V, +100°C
-25
4.75V,+100°C
-50
5.0V, +25°C
-75
5.25V,
-40°C
FALL TIME
1.0
-
-
-
100
Y = 0.005x + 0.6
0.5
0
125
150
0
20
40
60
80
100 120 140 160 180 200
0
0.75
1.50
2.25
3.00
3.75
V
4.50
5.25
LOAD CAPACITANCE
-pF
SOURCE VOLTAGE
-
Figure 33. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance
(VDD = 5 V)
Figure 31. ADSP-21062 Typical Output Drive Currents (VDD = 5 V)
5
16.0
14.0
12.0
Y = 0.03x
-
1.45
4
3
2
1
RISE TIME
10.0
Y = 0.005x + 3.7
8.0
FALL TIME
6.0
4.0
NOMINAL
2.0
0
Y = 0.0031x + 1.1
-1
25
50
75
100
125
150
pF
175
200
0
20
40
60
80
100 120 140 160 180 200
pF
LOAD CAPACITANCE
-
LOAD CAPACITANCE
-
Figure 34. Typical Output Delay or Hold vs. Load Capacitance (at Maximum
Case Temperature) (VDD = 5 V)
Figure 32. Typical Output Rise Time (10% to 90% VDD) vs. Load Capacitance
(VDD = 5 V)
Rev. F
|
Page 48 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Output Characteristics (3.3 V)
18
100
16
3.3V, +25°C
80
60
40
14
12
10
8
3.6V, -40°C
Y = 0.0796x + 1.17
3.0V, +85°C
VOH
20
0
RISE TIME
3.0V, +85°C
3.3V, +25°C
6
4
2
0
-
40
60
Y = 0.0467x + 0.55
3.6V, -40°C
-
FALL TIME
VOL
-
100
120
-
0
20
40
60
80 100 120 140 160 180 200
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CAPACITANCE
-pF
Figure 37. Typical Output Rise Time (10% to 90% VDD) vs. Load Capacitance
(VDD = 3.3 V)
Figure 35. ADSP-21062 Typical Output Drive Currents (VDD = 3.3 V)
5
4
3
9
8
7
Y = 0.0391x + 0.36
6
Y = 0.0329x
- 1.65
5
2
1
RISE TIME
4
3
2
1
0
Y = 0.0305x + 0.24
FALL TIME
NOMINAL
-
1
25
50
75
100
125
150
pF
175
200
0
20
40
60
80 100 120 140 160 180 200
pF
LOAD CAPACITANCE
-
LOAD CAPACITANCE
-
Figure 36. Typical Output Delay or Hold vs. Load Capacitance (at Maximum
Case Temperature) (VDD = 3.3 V)
Figure 38. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance
(VDD = 3.3 V)
Rev. F
|
Page 49 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Thermal Characteristics for CQFP Package
ENVIRONMENTAL CONDITIONS
The ADSP-21060C/ADSP-21060LC are available in 240-lead
thermally enhanced ceramic QFP (CQFP). There are two pack-
age versions, one with a copper/tungsten heat slug on top of the
package (CZ) for air cooling, and one with the heat slug on the
bottom (CW) for cooling through the board. The ADSP-2106x
is specified for a case temperature (TCASE). To ensure that the
The ADSP-2106x processors are rated for performance under
T
CASE environmental conditions specified in the Operating Con-
ditions (5 V) on Page 15 and Operating Conditions (3.3 V) on
Page 18.
Thermal Characteristics for MQFP_PQ4 and PBGA
Packages
T
CASE data sheet specification is not exceeded, a heatsink and/or
an air flow source may be used. A heatsink should be attached
with a thermal adhesive.
The ADSP-21060/ADSP-21060L and ADSP-21062/ADSP-
21062L are available in 240-lead thermally enhanced
MQFP_PQ4 and 225-ball plastic ball grid array packages. The
top surface of the thermally enhanced MQFP_PQ4 contains a
metal slug from which most of the die heat is dissipated. The
slug is flush with the top surface of the package. Note that the
metal slug is internally connected to GND through the device
substrate.
T
CASE = TAMB + (PD ꢂ ꢅCA)
TCASE = Case temperature (measured on top surface of package)
PD = Power dissipation in W (this value depends upon the spe-
cific application; a method for calculating PD is shown under
Power Dissipation).
ꢅCA =Value from Table 38 below.
Both packages are specified for a case temperature (TCASE). To
ensure that the TCASE is not exceeded, a heatsink and/or an air-
flow source may be used. A heatsink should be attached with a
thermal adhesive.
Table 39. Thermal Characteristics for Thermally Enhanced
240-Lead CQFP1
Parameter
ADSP-21060CW/ADSP-21060LCW
Airflow (LFM2)
Typical
Unit
T
CASE = TAMB + (PD ꢂ ꢅCA)
TCASE = Case temperature (measured on top surface of package)
ꢅCA
ꢅCA
ꢅCA
ꢅCA
ꢅCA
0
19.5
16
°C/W
°C/W
°C/W
°C/W
°C/W
PD =Power dissipation in W (this value depends upon the spe-
cific application; a method for calculating PD is shown under
Power Dissipation).
100
200
400
600
14
ꢅCA =Value from Table 37 below.
12
10
Table 37. Thermal Characteristics for Thermally Enhanced
240-Lead MQFP_PQ41
ADSP-21060CZ/ADSP-21060LCZ
ꢅCA
ꢅCA
ꢅCA
ꢅCA
ꢅCA
0
20
°C/W
°C/W
°C/W
°C/W
°C/W
Parameter
Airflow (LFM2)
Typical
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
100
200
400
600
16
ꢅCA
ꢅCA
ꢅCA
ꢅCA
ꢅCA
0
10
9
14
100
200
400
600
11.5
8
9.5
7
1 This represents thermal resistance at total power of 5 W. With airflow, no
variance is seen in ꢅCA at 5W.
6
ꢅCA at 0 LFM varies with power.
ADSP-21060CW/ADSP-21060LCW:
at 2 W, ꢅCA = 23°C/W
1 This represents thermal resistance at total power of 5 W. With airflow, no
variance is seen in ꢅCA at 5 W.
ꢅCA at 0 LFM varies with power:
at 3 W, ꢅCA = 21.5°C/W
at 2 W, ꢅCA = 14°C/W
ADSP-21060CZ/ADSP-21060LCZ:
at 2 W, ꢅCA = 24°C/W
at 3 W, ꢅCA = 11°C/W
2 LFM = Linear feet per minute of airflow.
at 3 W, ꢅCA = 21.5°C/W
ꢅJC = 0.24°C/W for all CQFP models.
2 LFM = Linear feet per minute of airflow.
Table 38. Thermal Characteristics for BGA
Parameter
ꢅCA
ꢅCA
Airflow (LFM1)
Typical
20.70
15.30
12.90
Unit
°C/W
°C/W
°C/W
0
200
400
ꢅCA
1 LFM = Linear feet per minute of airflow.
Rev. F
|
Page 50 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
225-BALL PBGA BALL CONFIGURATIONS
Table 40. ADSP-2106x 225-Ball Metric PBGA Ball Assignments (B-225-2)
Pin
Name
BMS
ADDR30 A02
DMAR2
DT1
RCLK1
TCLK0
RCLK0
ADRCLK A08
CS
CLKIN
PAGE
BR3
DATA47
DATA44
DATA42
MS0
PBGA
Pin Number Name
A01 ADDR25 D01
ADDR26 D02
MS2 D03
ADDR29 D04
Pin
PBGA
Pin Number Name
ADDR14 G01
ADDR15 G02
Pin
PBGA
Pin Number Name
Pin
PBGA
Pin Number Name
Pin
PBGA
Pin Number
N01
ADDR6
ADDR5
ADDR3
ADDR0
ICSA
GND
VDD
VDD
VDD
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
EMU
TDO
IRQ0
IRQ1
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
A03
A04
A05
A06
A07
ADDR16 G03
ADDR19 G04
DMAR1
TFS1
CPA
HBG
DMAG2
BR5
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
GND
VDD
VDD
VDD
VDD
VDD
GND
DATA22
DATA25
DATA24
DATA23
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
ID2
L5DAT1
L4CLK
L3CLK
L3DAT3
L2DAT0
L1ACK
L1DAT3
L0DAT3
DATA1
DATA3
TRST
A09
A10
A11
A12
A13
A14
A15
B01
B02
GND
GND
BR1
DATA40
DATA37
DATA35
DATA34
DATA8
DATA11
DATA13
DATA14
ADDR2
ADDR1
FLAG0
FLAG3
RPBA
GND
GND
GND
GND
ADDR21 E01
ADDR22 E02
ADDR24 E03
ADDR27 E04
ADDR12 H01
ADDR11 H02
ADDR13 H03
ADDR10 H04
SW
TMS
EBOOT
ID0
ADDR31 B03
HBR
DR1
DT0
DR0
REDY
RD
ACK
BR6
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
C01
C02
GND
GND
GND
GND
GND
GND
NC
DATA33
DATA30
DATA32
DATA31
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
GND
VDD
VDD
VDD
VDD
VDD
GND
DATA18
DATA19
DATA21
DATA20
ADDR9
ADDR8
ADDR7
ADDR4
GND
VDD
VDD
VDD
VDD
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
L5CLK
L5DAT3
L4DAT0
L4DAT3
L3DAT2
L2CLK
L2DAT2
L1DAT0
L0ACK
L0DAT1
DATA0
TCK
GND
NC
BR2
DATA4
DATA7
DATA9
DATA10
FLAG1
FLAG2
TIMEXP
TDI
LBOOT
L5ACK
L5DAT2
L4DAT2
L3DAT0
L2DAT3
L1DAT1
L0DAT0
DATA2
DATA5
DATA6
DATA45
DATA43
DATA39
MS3
MS1
ADDR28 C03
SBTS
TCLK1
RFS1
TFS0
RFS0
WR
DMAG1
BR4
DATA46
DATA41
DATA38
DATA36
ADDR17 F01
ADDR18 F02
ADDR20 F03
ADDR23 F04
IRQ2
RESET
ID1
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
GND
GND
VDD
VDD
VDD
GND
GND
DATA29
DATA26
DATA28
DATA27
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
L5DAT0
L4ACK
L4DAT1
L3ACK
L3DAT1
L2ACK
L2DAT1
L1CLK
L1DAT2
L0CLK
L0DAT2
VDD
GND
DATA12
DATA15
DATA16
DATA17
Rev. F
|
Page 51 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
DATA42 DATA44 DATA47
BR3
PAGE
CLKIN
CS
ADRCLK RCLK0 TCLK0
RCLK1
DT1
ADDR30
BMS
DMAR2
A
B
C
D
E
F
DATA39 DATA43 DATA45
BR2
BR6
ACK
RD
REDY
DR0
DT0
DR1
HBR
ADDR31
SW
MS0
MS1
MS3
DATA36 DATA38 DATA41 DATA46
DATA34 DATA35 DATA37 DATA40
BR4
BR1
DMAG1
BR5
WR
RFS0
TFS0
CPA
GND
RFS1
TFS1
TCLK1
ADDR28
SBTS
ADDR26 ADDR25
DMAG2
ADDR29
DMAR1
MS2
HBG
DATA31 DATA32 DATA30 DATA33
NC
GND
GND
GND
GND
GND
ADDR27 ADDR24 ADDR22 ADDR21
DATA27 DATA28 DATA26 DATA29
DATA23 DATA24 DATA25 DATA22
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
VDD
GND
GND
ADDR23 ADDR20 ADDR18 ADDR17
ADDR19 ADDR16 ADDR15 ADDR14
G
H
J
DATA20 DATA21 DATA19 DATA18
DATA17 DATA16 DATA15 DATA12
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
ADDR10 ADDR13 ADDR11 ADDR12
ADDR4 ADDR7 ADDR8 ADDR9
DATA14 DATA13 DATA11 DATA8
GND
NC
GND
GND
VDD
GND
VDD
GND
VDD
GND
GND
GND
ICSA
ADDR0 ADDR3 ADDR5 ADDR6
K
L
DATA10 DATA9
DATA7
DATA2
DATA4
RPBA
FLAG3
TDI
FLAG0 ADDR1 ADDR2
DATA6
DATA5
DATA1
L0DAT0 L1DAT1 L2DAT3 L3DAT0 L4DAT2 L5DAT2 L5ACK LBOOT
TIMEXP FLAG2
FLAG1
EMU
M
N
P
R
DATA3
DATA0
L0DAT3 L1DAT3 L1ACK L2DAT0 L3DAT3 L3CLK
L4CLK L5DAT1
ID2
IRQ0
TDO
TMS
IRQ1
L0DAT1 L0ACK L1DAT0 L2DAT2 L2CLK L3DAT2 L4DAT3 L4DAT0 L5DAT3 L5CLK
L0CLK L1DAT2 L1CLK L2DAT1 L2ACK L3DAT1 L3ACK L4DAT1 L4ACK L5DAT0
ID0
EBOOT
TRST
L0DAT2
ID1
TCK
RESET
IRQ2
Figure 39. ADSP-21060/ADSP-21062 BGA Pin Assignments (Top View, Summary)
Rev. F
|
Page 52 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
240-LEAD MQFP_PQ4/CQFP PIN CONFIGURATIONS
Table 41. ADSP-2106x MQFP_PQ4, ADSP-21060CW, and ADSP-21060LCW CQFP Pin Assignments (SP-240-2, QS-240-2)
Pin Name Pin No. Pin Name Pin No. Pin Name
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
TDI
1
ADDR20
ADDR21
GND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
TCLK0
TFS0
DR0
81
DATA41
DATA40
DATA39
VDD
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
DATA14
DATA13
DATA12
GND
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
L2DAT0
L2CLK
L2ACK
NC
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
TRST
2
82
VDD
3
83
TDO
4
ADDR22
ADDR23
ADDR24
VDD
RCLK0
RFS0
VDD
84
TIMEXP
EMU
5
85
DATA38
DATA37
DATA36
GND
DATA11
DATA10
DATA9
VDD
VDD
6
86
L3DAT3
L3DAT2
L3DAT1
L3DAT0
L3CLK
L3ACK
GND
ICSA
7
VDD
87
FLAG3
FLAG2
FLAG1
FLAG0
GND
8
GND
GND
ADRCLK
REDY
HBG
88
9
VDD
89
NC
DATA8
DATA7
DATA6
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ADDR25
ADDR26
ADDR27
GND
90
DATA35
DATA34
DATA33
VDD
91
CS
92
ADDR0
ADDR1
VDD
RD
93
DATA5
DATA4
DATA3
VDD
L4DAT3
L4DAT2
L4DAT1
L4DAT0
L4CLK
L4ACK
VDD
MS3
WR
94
VDD
MS2
GND
VDD
95
GND
ADDR2
ADDR3
ADDR4
GND
MS1
96
DATA32
DATA31
DATA30
GND
MS0
GND
CLKIN
ACK
97
DATA2
DATA1
DATA0
GND
SW
98
BMS
99
ADDR5
ADDR6
ADDR7
VDD
ADDR28
GND
DMAG2
DMAG1
PAGE
VDD
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DATA29
DATA28
DATA27
VDD
GND
GND
VDD
VDD
L0DAT3
L0DAT2
L0DAT1
L0DAT0
L0CLK
L0ACK
VDD
L5DAT3
L5DAT2
L5DAT1
L5DAT0
L5CLK
L5ACK
GND
VDD
ADDR8
ADDR9
ADDR10
GND
ADDR29
ADDR30
ADDR31
GND
BR6
VDD
BR5
DATA26
DATA25
DATA24
GND
BR4
BR3
ADDR11
ADDR12
ADDR13
VDD
SBTS
BR2
DMAR2
DMAR1
HBR
BR1
DATA23
DATA22
DATA21
VDD
L1DAT3
L1DAT2
L1DAT1
L1DAT0
L1CLK
L1ACK
GND
ID2
GND
VDD
ID1
ID0
ADDR14
ADDR15
GND
DT1
GND
DATA47
DATA46
DATA45
VDD
LBOOT
RPBA
TCLK1
TFS1
DATA20
DATA19
DATA18
GND
RESET
EBOOT
IRQ2
ADDR16
ADDR17
ADDR18
VDD
DR1
RCLK1
RFS1
GND
DATA44
DATA43
DATA42
GND
DATA17
DATA16
DATA15
VDD
VDD
IRQ1
GND
L2DAT3
L2DAT2
L2DAT1
IRQ0
VDD
CPA
TCK
ADDR19
DT0
TMS
Rev. F
|
Page 53 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 42. ADSP-21060CZ/21060LCZ CQFP Pin Assignments (QS-240-1)
Pin Name Pin No. Pin Name Pin No. Pin Name
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
GND
1
DATA29
GND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DMAG2
ACK
81
ADDR28
BMS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
ADDR5
GND
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
GND
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
DATA0
DATA1
DATA2
VDD
2
82
VDD
3
DATA30
DATA31
DATA32
GND
CLKIN
GND
VDD
83
SW
ADDR4
ADDR3
ADDR2
VDD
L4ACK
L4CLK
L4DAT0
L4DAT1
L4DAT2
L4DAT3
GND
4
84
MS0
5
85
MS1
DATA3
DATA4
DATA5
GND
6
GND
WR
86
MS2
7
VDD
87
MS3
ADDR1
ADDR0
GND
8
VDD
RD
88
GND
9
DATA33
DATA34
DATA35
NC
CS
89
ADDR27
ADDR26
ADDR25
VDD
DATA6
DATA7
DATA8
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
HBG
90
FLAG0
FLAG1
FLAG2
FLAG3
ICSA
L3ACK
L3CLK
L3DAT0
L3DAT1
L3DAT2
L3DAT3
VDD
REDY
ADRCLK
GND
VDD
91
92
GND
93
GND
DATA9
DATA10
DATA11
GND
DATA36
DATA37
DATA38
VDD
94
VDD
VDD
95
ADDR24
ADDR23
ADDR22
GND
EMU
RFS0
RCLK0
DR0
96
TIMEXP
TDO
97
NC
DATA12
DATA13
DATA14
VDD
DATA39
DATA40
DATA41
GND
98
VDD
L2ACK
L2CLK
L2DAT0
L2DAT1
L2DAT2
L2DAT3
VDD
TFS0
TCLK0
DT0
99
ADDR21
ADDR20
ADDR19
VDD
TRST
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
TDI
TMS
DATA15
DATA16
DATA17
GND
DATA42
DATA43
DATA44
VDD
CPA
TCK
GND
RFS1
RCLK1
DR1
VDD
IRQ0
ADDR18
ADDR17
ADDR16
GND
IRQ1
IRQ2
GND
DATA18
DATA19
DATA20
VDD
DATA45
DATA46
DATA47
GND
EBOOT
RESET
RPBA
LBOOT
ID0
GND
TFS1
TCLK1
DT1
L1ACK
L1CLK
L1DAT0
L1DAT1
L1DAT2
L1DAT3
VDD
ADDR15
ADDR14
VDD
DATA21
DATA22
DATA23
GND
VDD
HBR
GND
DMAR1
DMAR2
SBTS
GND
ADDR31
ADDR30
ADDR29
VDD
ADDR13
ADDR12
ADDR11
GND
ID1
BR1
ID2
BR2
GND
DATA24
DATA25
DATA26
VDD
BR3
L5ACK
L5CLK
L5DAT0
L5DAT1
L5DAT2
L5DAT3
VDD
L0ACK
L0CLK
L0DAT0
L0DAT1
L0DAT2
L0DAT3
GND
BR4
ADDR10
ADDR9
ADDR8
VDD
BR5
BR6
VDD
VDD
DATA27
DATA28
PAGE
VDD
ADDR7
ADDR6
DMAG1
GND
Rev. F
|
Page 54 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
OUTLINE DIMENSIONS
23.20
23.00 SQ
22.80
A1 CORNER
INDEX AREA
15 13 11
14 12 10
9
7
5
3
1
8
6
4
2
A
B
C
D
E
F
BALL A1
INDICATOR
18.00
20.10
20.00 SQ
19.90
BSC SQ
G
H
J
TOP VIEW
DETAIL A
K
L
1.27
BSC
M
N
P
R
0.50 R
BOTTOM VIEW
3 PLACES
2.70 MAX
1.30
1.20
1.10
DETAIL A
0.70
0.60
0.50
0.15 MAX
COPLANARITY
SEATING
PLANE
0.90
0.75
0.60
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MS-034-AAJ-2
Figure 40. 225-Ball Plastic Ball Grid Array [PBGA]
(B-225-2)
Dimensions shown in millimeters
Rev. F
|
Page 55 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
34.60 BSC
SQ
29.50 REF
SQ
4.10
3.78
3.55
0.66
0.56
0.46
181
180
240
1
SEATING
PLANE
PIN 1
24.00 REF
SQ
HEAT SLUG
TOP VIEW
(PINS DOWN)
32.00 BSC
SQ
121
120
60
3.50
3.40
3.30
61
3.92 u 45°
0.20
0.09
(4 PLACES)
VIEW A
0.27 MAX
0.17 MIN
0.50
BSC
0.38
0.25
7°
0°
LEAD PITCH
0.076
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT WITH JEDEC STANDARDS MS-029-GA
Figure 41. 240-Lead Metric Quad Flat Package, Thermally Enhanced “PowerQuad” [MQFP_PQ4]
(SP-240-2)
Dimensions shown in millimeters
Rev. F
|
Page 56 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
36.60
36.13 SQ
35.65
28.05
27.80 SQ
27.55
32.00 BSC SQ
PIN 1
240
181
180
181
180
240
1
INDICATOR
1
SEAL RING
LID
TOP VIEW
BOTTOM VIEW
(PINS UP)
(PINS DOWN)
HEAT SLUG
121
120
121
120
60
60
61
61
VIEW A
19.00
REF SQ
4.30
3.62
2.95
3.70
3.22
2.75
1.70
0.15
0.15
0.35
0.30
0.25
0.175
0.156
0.137
0.60
0.40
0.20
7°
-3°
0.90
0.75
0.60
0.23
0.20
0.17
0.50 BSC
NOTES:
1. LEAD FINISH = GOLD PLATE
2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX
(Sweep and/or Offset can be used as the controlling dimension).
0.180
0.155
0.130
LEAD THICKNESS
2.06 REF
VIEW A
Figure 42. 240-Lead Ceramic Quad Flat Package, Heat Slug Up [CQFP]
(QS-240-2A)
Dimensions shown in millimeters
Rev. F
|
Page 57 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
2.60
2.55
2.50
75.00 BSC SQ
29.50 BSC
16.50 (8×)
2.05
3.60
3.55
3.50
61
120
121
120
121
61
60
60
SEAL RING
LID
65.90
BSC
29.50
BSC
BOTTOM VIEW
TOP VIEW
HEAT SLUG
180
181
1
1
180
181
240
INDEX 1
GOLD
240
INDEX 2
1.50 DIA
PLATED
NO GOLD
1.22 (4×)
NONCONDUCTIVE
CERAMIC TIE BAR
75.50 BSC SQ
SIDE VIEW
70.00 BSC SQ
0.50
0.90
0.80
0.70
3.42
3.17
2.92
Figure 43. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Down [CQFP]
(QS-240-2B)
Dimensions shown in millimeters
Rev. F
|
Page 58 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
36.60
36.13 SQ
35.65
19.00
32.00 BSC SQ
REF SQ
PIN 1
240
181
180
181
180
240
1
INDICATOR
1
SEAL RING
LID
TOP VIEW
BOTTOM VIEW
(PINS UP)
(PINS DOWN)
HEAT SLUG
121
120
121
120
60
60
61
61
28.05
27.80 SQ
27.55
VIEW A
4.20
3.52
2.85
3.70
3.22
2.75
1.70
0.15
0.15
0.35
0.30
0.25
0.175
0.156
0.137
0.50
0.30
0.10
7°
-3°
0.90
0.75
0.60
0.23
0.20
0.17
0.50 BSC
NOTES:
1. LEAD FINISH = GOLD PLATE
2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX
(Sweep and/or Offset can be used as the controlling dimension).
0.180
0.155
0.130
LEAD THICKNESS
2.06 REF
VIEW A
Figure 44. 240-Lead Ceramic Quad Flat Package, Heat Slug Down [CQFP]
(QS-240-1A)
Dimensions shown in millimeters
Rev. F
|
Page 59 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
2.60
2.55
2.50
75.00 BSC SQ
29.50 BSC
16.50 (8×)
2.05
3.60
3.55
3.50
61
120
121
120
121
61
60
60
SEAL RING
LID
65.90
BSC
29.50
BSC
BOTTOM VIEW
HEAT SLUG
TOP VIEW
180
181
1
1
180
181
240
INDEX 1
GOLD
240
INDEX 2
2.00 DIA
PLATED
NO GOLD
1.22 (4×)
NONCONDUCTIVE
CERAMIC TIE BAR
75.50 BSC SQ
SIDE VIEW
70.00 BSC SQ
0.50
3.42
3.17
2.92
0.90
0.80
0.70
Figure 45. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Up [CQFP]
(QS-240-1B)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
Table 43 is provided as an aide to PCB design. For industry-
standard design recommendations, refer to IPC-7351, Generic
Requirements for Surface-Mount Design and Land Pattern
Standard.
Table 43. BGA Data for Use with Surface-Mount Design
Package
Ball Attach Type
Solder Mask Opening
Ball Pad Size
225-Ball Grid Array (PBGA)
Solder Mask Defined
0.63 mm diameter
0.76 mm diameter
Rev. F
|
Page 60 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
ORDERING GUIDE
Temperature
Range
Instruction On-Chip Operating
Model
Rate
SRAM
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
4M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
2M Bit
Voltage
Package Description
Package Option
QS-240-2A
ASDP-21060CZ-1331
ASDP-21060CZZ-1331, 2
ASDP-21060CZ-1601
ASDP-21060CZZ-1601, 2
ASDP-21060CW-1331
–40ꢃC to +100ꢃC 33 MHz
–40ꢃC to +100ꢃC 33 MHz
–40ꢃC to +100ꢃC 40 MHz
–40ꢃC to +100ꢃC 40 MHz
–40ꢃC to +100ꢃC 33 MHz
5 V
240-Lead CQFP [Heat Slug Up]
240-Lead CQFP [Heat Slug Up]
240-Lead CQFP [Heat Slug Up]
240-Lead CQFP [Heat Slug Up]
5 V
QS-240-2A
5 V
QS-240-2A
5 V
QS-240-2A
5 V
240-Lead CQFP [Heat Slug Down] QS-240-1A
240-Lead CQFP [Heat Slug Down] QS-240-1A
240-Lead CQFP [Heat Slug Down] QS-240-1A
240-Lead CQFP [Heat Slug Down] QS-240-1A
ASDP-21060CWZ-1331, 2 –40ꢃC to +100ꢃC 33 MHz
ASDP-21060CW-1601
–40ꢃC to +100ꢃC 40 MHz
ASDP-21060CWZ-1601, 2 –40ꢃC to +100ꢃC 40 MHz
5 V
5 V
5 V
ADSP-21060KS-133
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
33 MHz
33 MHz
40 MHz
40 MHz
40 MHz
40 MHz
33 MHz
33 MHz
40 MHz
40 MHz
40 MHz
40 MHz
5 V
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
225-Ball PBGA
SP-240-2
SP-240-2
SP-240-2
SP-240-2
B-225-2
B-225-2
SP-240-2
SP-240-2
SP-240-2
SP-240-2
B-225-2
B-225-2
B-225-2
B-225-2
B-225-2
B-225-2
ADSP-21060KSZ-1332
ADSP-21060KS-160
5 V
5 V
ADSP-21060KSZ-1602
ADSP-21060KB-160
ADSP-21060KBZ-1602
ADSP-21060LKS-133
ADSP-21060LKSZ-1332
ADSP-21060LKS-160
ADSP-21060LKSZ-1602
ADSP-21060LKB-160
ADSP-21060LKBZ-1602
ADSP-21060LAB-160
ADSP-21060LABZ-1602
ADSP-21060LCB-133
ADSP-21060LCBZ-1332
ASDP-21060LCW-1331
ASDP-21060LCW-1601
5 V
5 V
5 V
225-Ball PBGA
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
5 V
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
225-Ball PBGA
225-Ball PBGA
–40ꢃC to +85ꢃC 40 MHz
–40ꢃC to +85ꢃC 40 MHz
–40ꢃC to +100ꢃC 33 MHz
–40ꢃC to +100ꢃC 33 MHz
–40ꢃC to +100ꢃC 33 MHz
–40ꢃC to +100ꢃC 40 MHz
225-Ball PBGA
225-Ball PBGA
225-Ball PBGA
225-Ball PBGA
240-Lead CQFP [Heat Slug Down] QS-240-1A
240-Lead CQFP [Heat Slug Down] QS-240-1A
240-Lead CQFP [Heat Slug Down] QS-240-1A
ASDP-21060LCWZ-1601, 2 –40ꢃC to +100ꢃC 40 MHz
ADSP-21062KS-133
ADSP-21062KSZ-1332
ADSP-21062KS-160
ADSP-21062KSZ-1602
ADSP-21062KB-160
ADSP-21062KBZ-1602
ADSP-21062CS-160
ADSP-21062CSZ-1602
ADSP-21062LKS-133
ADSP-21062LKSZ-1332
ADSP-21062LKS-160
ADSP-21062LKSZ-1602
ADSP-21062LKB-160
ADSP-21062LKBZ-1602
ADSP-21062LAB-160
ADSP-21062LABZ-1602
ADSP-21062LCS-160
ADSP-21062LCSZ-1602
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
33 MHz
33 MHz
40 MHz
40 MHz
40 MHz
40 MHz
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
225-Ball PBGA
SP-240-2
SP-240-2
SP-240-2
SP-240-2
B-225-2
B-225-2
SP-240-2
SP-240-2
SP-240-2
SP-240-2
SP-240-2
SP-240-2
B-225-2
B-225-2
B-225-2
B-225-2
SP-240-2
SP-240-2
5 V
5 V
5 V
5 V
5 V
225-Ball PBGA
–40ꢃC to +100ꢃC 40 MHz
–40ꢃC to +100ꢃC 40 MHz
5 V
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
225-Ball PBGA
5 V
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
0ꢃC to 85ꢃC
–40ꢃC to 85ꢃC
–40ꢃC to 85ꢃC
33 MHz
33 MHz
40 MHz
40 MHz
40 MHz
40 MHz
40 MHz
40 MHz
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
225-Ball PBGA
225-Ball PBGA
225-Ball PBGA
–40ꢃC to +100ꢃC 40 MHz
–40ꢃC to +100ꢃC 40 MHz
240-Lead MQFP_PQ4
240-Lead MQFP_PQ4
1 Model refers to package with formed leads. For model numbers of unformed lead versions (QS-240-1B, QS-240-2B), contact Analog Devices or an Analog Devices sales
representative.
2 Z = RoHS Compliant Part.
Rev. F
|
Page 61 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F
|
Page 62 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F
|
Page 63 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00167-0-3/08(F)
Rev. F
|
Page 64 of 64
|
March 2008
相关型号:
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