ADSP-21061LKBZ-160_技术文档

Commercial Grade

SHARC DSP Microcomputer

a

ADSP-21061/ADSP-21061L

Dual data address generators with modulo and bit-reverse

addressing

Efficient program sequencing with zero-overhead looping:

single-cycle loop setup

IEEE JTAG Standard 1149.1 test access port and on-chip

emulation

32-bit single-precision and 40-bit extended-precision IEEE

floating-point data formats or 32-bit fixed-point data

format

240-lead MQFP package, thermally enhanced MQFP, 225-ball

plastic ball grid array (PBGA)

Lead (Pb) free packages. For more information, see Ordering

Guide on Page 52.

SUMMARY

High performance signal processor for communications,

graphics, and imaging applications

Super Harvard Architecture

Four independent buses for dual data fetch, instruction

fetch, and nonintrusive I/O

32-bit IEEE floating-point computation units—multiplier,

ALU, and shifter

Dual-ported on-chip SRAM and integrated I/O peripherals—a

complete system-on-a-chip

Integrated multiprocessing features

KEY FEATURES—PROCESSOR CORE

50 MIPS, 20 ns instruction rate, single-cycle instruction

execution

120 MFLOPS peak, 80 MFLOPS sustained performance

CORE PROCESSOR

DUAL-PORTED SRAM

INSTRUCTION

TIMER

JTAG

TWO INDEPENDENT

DUAL-PORTED BLOCKS

7

CACHE

TEST AND

EMULATION

32 ϫ 48-BIT

PROCESSOR PORT

ADDR DATA

ADDR

I/O PORT

ADDR

DATA

DAG1

DAG2

PROGRAM

SEQUENCER

8 ϫ 4 ϫ 32 8 ϫ 4 ϫ 24

EXTERNAL

PORT

IOD

48

IOA

17

24

PM ADDRESS BUS

32

48

ADDR BUS

MUX

DM ADDRESS BUS

32

MULTIPROCESSOR

INTERFACE

48

40/32

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DATA BUS

MUX

HOST PORT

S

DATA

REGISTER

FILE

IOP

4

DMA

CONTROLLER

REGISTERS

(MEMORY

MAPPED)

6

BARREL

SHIFTER

16 ϫ 40-BIT

MULT

ALU

CONTROL,

STATUS AND

DATA BUFFERS

SERIAL PORTS

(2)

I/O PROCESSOR

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADSP-21061/ADSP-21061L

TABLE OF CONTENTS

Summary ............................................................... 1

Key Features—Processor Core ................................. 1

General Description ................................................. 3

SHARC Family Core Architecture ............................ 3

Memory and I/O Interface Features ........................... 4

ADSP-21061L Specifications ..................................... 17

Operating Conditions (3.3 V) ................................. 17

Electrical Characteristics (3.3 V) ............................. 17

Internal Power Dissipation (3.3 V) .......................... 18

External Power Dissipation (3.3 V) .......................... 19

Absolute Maximum Ratings ................................... 20

ESD Caution ...................................................... 20

Package Marking Information ................................ 20

Timing Specifications ........................................... 20

Test Conditions .................................................. 43

Environmental Conditions .................................... 46

225-Ball PBGA Pin Configurations ............................. 47

240-Lead MQFP Pin Configurations ........................... 49

Outline Dimensions ................................................ 50

Surface-Mount Design .......................................... 52

Ordering Guide ..................................................... 52

Porting Code From the ADSP-21060 or

ADSP-21062 ..................................................... 7

Development Tools ............................................... 7

Additional Information .......................................... 8

Related Signal Chains ............................................ 8

Pin Function Descriptions ......................................... 9

Target Board Connector For EZ-ICE Probe ............... 12

ADSP-21061 Specifications ...................................... 14

Operating Conditions (5 V) ................................... 14

Electrical Characteristics (5 V) ............................... 14

Internal Power Dissipation (5 V) ............................ 15

External Power Dissipation (5 V) ............................ 16

REVISION HISTORY

5/13—Rev C to Rev D

Updated Development Tools .......................................7

Added Related Signal Chains .......................................8

Removed the ADSP-21061LAS-176, ADSP-21061LKS-160, and

ADSP-21061LKS-176 models from Ordering Guide ........ 52

GENERAL NOTE

This data sheet represents production released specifications for

the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for

33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The

product name“ADSP-21061” is used throughout this data sheet

to represent all devices, except where expressly noted.

Rev. D

| Page 2 of 52 | May 2013

ADSP-21061/ADSP-21061L

GENERAL DESCRIPTION

The ADSP-21061 SHARC—Super Harvard Architecture Com-

puter—is a signal processing microcomputer that offers new

capabilities and levels of performance. The ADSP-21061

SHARC is a 32-bit processor optimized for high performance

DSP applications. The ADSP-21061 builds on the ADSP-21000

DSP core to form a complete system-on-a-chip, adding a dual-

ported on-chip SRAM and integrated I/O peripherals supported

by a dedicated I/O bus.

• Serial ports

• JTAG test access port

ADSP-21061

CS

BMS

CLKIN

BOOT

EPROM

(OPTIONAL)

1 ϫ CLOCK

ADDR

DATA

EBOOT

LBOOT

IRQ_2–0

TO GND

Fabricated in a high speed, low power CMOS process, the

ADSP-21061 has a 20 ns instruction cycle time and operates at

50 MIPS. With its on-chip instruction cache, the processor can

execute every instruction in a single cycle. Table 1 shows perfor-

mance benchmarks for the ADSP-21061/ADSP-21061L.

3

4

ADDR_31–0

ADDR

FLAG_3–0

TIMEXP

MEMORY-

MAPPED

DEVICES

DATA_47–0

RD

DATA

OE

WE

ACK

WR

ACK

(OPTIONAL)

TCLK0

RCLK0

TFS0

RSF0

DT0

SERIAL

DEVICE

(OPTIONAL)

The ADSP-21061 SHARC represents a new standard of integra-

tion for signal computers, combining a high performance

floating-point DSP core with integrated, on-chip system fea-

tures including 1M bit SRAM memory, a host processor

interface, a DMA controller, serial ports, and parallel bus con-

nectivity for glueless DSP multiprocessing.

CS

MS_3–0

PAGE

SW

DMA DEVICE

(OPTIONAL)

DATA

DR0

SBTS

ADRCLK

DMAR_1–2

TCLK1

RCLK1

TFS1

RSF1

DT1

SERIAL

DEVICE

(OPTIONAL)

DMAG_1–2

CS

HOST

Table 1. Benchmarks (at 50 MHz)

DR1

HBR

HBG

PROCESSOR

INTERFACE

(OPTIONAL)

REDY

Benchmark Algorithm

Speed

Cycles

BR_1–6

CPA

RPBA

ID_2–0

ADDR

DATA

1024 Point Complex FFT (Radix 4,

with reversal)

.37 ms

18,221

RESET JTAG

7

FIR Filter (per tap)

IIR Filter (per biquad)

Divide (y/x)

20 ns

1

4

6

9

80 ns

120 ns

180 ns

300M bps

Figure 2. ADSP-21061/ADSP-21061L System Sample Configuration

Inverse Square Root

DMA Transfer Rate

SHARC FAMILY CORE ARCHITECTURE

The ADSP-21061 includes the following architectural features

of the ADSP-21000 family core. The ADSP-21061 processors

are code- and function-compatible with the ADSP-21020,

ADSP-21060, and ADSP-21062 SHARC processors.

The ADSP-21061 continues SHARC’s industry-leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features.

The block diagram on Page 1, illustrates the following architec-

tural features:

Independent, Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier, and shifter all per-

form single-cycle instructions. The three units are arranged in

parallel, maximizing computational throughput. Single multi-

function instructions execute parallel ALU and multiplier oper-

ations. These computation units support IEEE 32-bit single-

precision floating-point, extended-precision 40-bit floating-

point, and 32-bit fixed-point data formats.

• Computation units (ALU, multiplier, and shifter) with a

shared data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

Data Register File

• Interval timer

A general-purpose data register file is used for transferring data

between the computation units and the data buses, and for stor-

ing intermediate results. This 10-port, 32-register (16 primary,

16 secondary) register file, combined with the ADSP-21000

Harvard architecture, allows unconstrained data flow between

computation units and internal memory.

• On-chip SRAM

• External port for interfacing to off-chip memory and

peripherals

• Host port and multiprocessor interface

• DMA controller

Rev. D

| Page 3 of 52 | May 2013

ADSP-21061/ADSP-21061L

A 16-bit floating-point storage format is supported, which effec-

tively doubles the amount of data that may be stored on-chip.

Conversion between the 32-bit floating-point and 16-bit float-

ing-point formats is done in a single instruction.

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-21061 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(Figure 1 on Page 1). With its separate program and data mem-

ory buses and on-chip instruction cache, the processor can

simultaneously fetch two operands and an instruction (from the

cache), all in a single cycle.

While each memory block can store combinations of code and

data, accesses are most efficient when one block stores data,

using the DM bus for transfers, and the other block stores

instructions and data, using the PM bus for transfers. Using the

DM bus and PM bus in this way, with one dedicated to each

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache. Single-cycle execution is also maintained when one of the

data operands is transferred to or from off-chip, via the

ADSP-21061’s external port.

Instruction Cache

The ADSP-21061 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and two

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

allows full-speed execution of core, looped operations such as

digital filter multiply-accumulates and FFT butterfly processing.

Off-Chip Memory and Peripherals Interface

The ADSP-21061’s external port provides the processor’s inter-

face to off-chip memory and peripherals. The 4-gigaword off-

chip address space is included in the ADSP-21061’s unified

address space. The separate on-chip buses—for program mem-

ory, data memory, and I/O—are multiplexed at the external port

to create an external system bus with a single 32-bit address bus

and a single 48-bit (or 32-bit) data bus. The on-chip Super Har-

vard Architecture provides three-bus performance, while the

off-chip unified address space gives flexibility to the designer.

Data Address Generators with Hardware Circular Buffers

The ADSP-21061’s two data address generators (DAGs) imple-

ment circular data buffers in hardware. Circular buffers allow

efficient programming of delay lines and other data structures

required in digital signal processing, and are commonly used in

digital filters and Fourier transforms. The two DAGs of the

ADSP-21061 contain sufficient registers to allow the creation of

up to 32 circular buffers (16 primary register sets, 16 secondary).

The DAGs automatically handle address pointer wraparound,

reducing overhead, increasing performance and simplifying

implementation. Circular buffers can start and end at any mem-

ory location.

Addressing of external memory devices is facilitated by on-chip

decoding of high order address lines to generate memory bank

select signals. Separate control lines are also generated for sim-

plified addressing of page-mode DRAM. The ADSP-21061

provides programmable memory wait states and external mem-

ory acknowledge controls to allow interfacing to DRAM and

peripherals with variable access, hold, and disable time

requirements.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21061 can conditionally execute a multiply, an add, a

subtract, and a branch, all in a single instruction.

Host Processor Interface

The ADSP-21061’s host interface allows easy connection to

standard microprocessor buses, both 16-bit and 32-bit, with lit-

tle additional hardware required. Asynchronous transfers at

speeds up to the full clock rate of the processor are supported.

The host interface is accessed through the ADSP-21061’s exter-

nal port and is memory-mapped into the unified address space.

Two channels of DMA are available for the host interface; code

and data transfers are accomplished with low software

overhead.

MEMORY AND I/O INTERFACE FEATURES

The ADSP-21061 processors add the following architectural

features to the SHARC family core.

Dual-Ported On-Chip Memory

The ADSP-21061 contains one megabit of on-chip SRAM, orga-

nized as two blocks of 0.5M bits each. Each bank has eight 16-bit

columns with 4k 16-bit words per column. Each memory block

is dual-ported for single-cycle, independent accesses by the core

processor and I/O processor or DMA controller. The dual-

ported memory and separate on-chip buses allow two data

transfers from the core and one from I/O, all in a single cycle

(see Figure 4 for the ADSP-21061 memory map).

The host processor requests the ADSP-21061’s external bus

with the host bus request (HBR), host bus grant (HBG), and

ready (REDY) signals. The host can directly read and write the

internal memory of the ADSP-21061, and can access the DMA

channel setup and mailbox registers. Vector interrupt support is

provided for efficient execution of host commands.

On the ADSP-21061, the memory can be configured as a maxi-

mum of 32k words of 32-bit data, 64k words for 16-bit data, 16k

words of 48-bit instructions (and 40-bit data) or combinations

of different word sizes up to 1 megabit. All the memory can be

accessed as 16-bit, 32-bit, or 48-bit.

DMA Controller

The ADSP-21061’s on-chip DMA controller allows zero-

overhead data transfers without processor intervention. The

DMA controller operates independently and invisibly to the

processor core, allowing DMA operations to occur while the

core is simultaneously executing its program instructions.

Rev. D

| Page 4 of 52 | May 2013

ADSP-21061/ADSP-21061L

ADSP-21061 #6

ADSP-21061 #5

ADSP-21061 #4

ADSP-21061 #3

ADDR31–0

CLKIN

DATA47–0

RESET

RPBA

3

ID2–0

CONTROL

011

5

BR1–2, BR4–6

BR3

ADSP-21061 #2

ADDR31–0

CLKIN

RESET

RPBA

DATA47–0

3

ID2–0

CONTROL

010

CPA

BR1, BR3–6

BR2

5

ADSP-21061 #1

CLKIN

RESET

RPBA

ADDR31–0

ADDR

DATA

GLOBAL MEMORY

AND

PERIPHERAL (OPTIONAL)

DATA47–0

RDx

WRx

OE

WE

ACK

CS

3

ACK

MS3–0

ID2–0

BMS

PAGE

CS

001

BOOT EPROM (OPTIONAL)

ADDR

SBTS

DATA

BUS

PRIORITY

CS

HBR

RESET

CLOCK

HBG

HOST PROCESSOR

INTERFACE (OPTIONAL)

REDY

ADDR

DATA

CPA

BR2–6

BR1

5

Figure 3. Shared Memory Multiprocessing System

DMA transfers can occur between the ADSP-21061’s internal

memory and either external memory, external peripherals, or a

host processor. DMA transfers can also occur between the

ADSP-21061’s internal memory and its serial ports.

DMA transfers between external memory and external periph-

eral devices are another option. External bus packing to 16-,

32-, or 48-bit words is performed during DMA transfers.

Rev. D

| Page 5 of 52 | May 2013

ADSP-21061/ADSP-21061L

Six channels of DMA are available on the ADSP-21061—four

via the serial ports, and two via the processor’s external port (for

either host processor, other ADSP-21061s, memory or I/O

transfers). Programs can be downloaded to the ADSP-21061

using DMA transfers. Asynchronous off-chip peripherals can

control two DMA channels using DMA request/grant lines

(DMAR_1–2, DMAG_1–2). Other DMA features include interrupt

generation upon completion of DMA transfers and DMA

chaining for automatic linked DMA transfers.

The serial ports can operate with little-endian or big-endian

transmission formats, with word lengths selectable from 3 bits

to 32 bits. They offer selectable synchronization and transmit

modes as well as optional μ-law or A-law companding. Serial

port clocks and frame syncs can be internally or externally gen-

erated. The serial ports also include keyword and key mask

features to enhance interprocessor communication.

Multiprocessing

The ADSP-21061 offers powerful features tailored to multipro-

cessor DSP systems. The unified address space (see Figure 4)

allows direct interprocessor accesses of each ADSP-21061’s

internal memory. Distributed bus arbitration logic is included

on-chip for simple, glueless connection of systems containing

up to six ADSP-21061s and a host processor. Master processor

changeover incurs only one cycle of overhead. Bus arbitration is

selectable as either fixed or rotating priority. Bus lock allows

indivisible read-modify-write sequences for semaphores. A vec-

tor interrupt is provided for interprocessor commands. Maxi-

mum throughput for interprocessor data transfer is 500 Mbps

over the external port. Broadcast writes allow simultaneous

transmission of data to all ADSP-21061s and can be used to

implement reflective semaphores.

Serial Ports

The ADSP-21061 features two synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices. The serial ports can operate at

the full clock rate of the processor, providing each with a maxi-

mum data rate of up to 50 Mbps. Independent transmit and

receive functions provide greater flexibility for serial communi-

cations. Serial port data can be automatically transferred to and

from on-chip memory via DMA. Each of the serial ports offers

TDM multichannel mode.

ADDRESS

0x0000 0000

0x0002 0000

0x0040 0000

IOP REGISTERS

INTERNAL

MEMORY

SPACE

NORMAL WORD ADDRESSING

(32-BIT DATA WORDS

48-BIT INSTRUCTION WORDS)

BANK 0

MS0

0x0004 0000

SDRAM

(OPTIONAL)

SHORT WORD ADDRESSING

(16-BIT DATA WORDS)

0x0008 0000

INTERNAL MEMORY SPACE

BANK 1

BANK 2

MS1

MS2

WITH ID = 001

0x0010 0000

INTERNAL MEMORY SPACE

WITH ID = 010

0x0018 0000

EXTERNAL

MEMORY

SPACE

INTERNAL MEMORY SPACE

MULTIPROCESSOR

MEMORY

SPACE

WITH ID = 011

0x0012 0000

INTERNAL MEMORY SPACE

WITH ID = 100

0x0028 0000

0x0030 0000

0x0038 0000

BANK

3

MS3

INTERNAL MEMORY SPACE

WITH ID = 101

INTERNAL MEMORY SPACE

WITH ID = 110

BROADCAST WRITE

TO ALL ADSP-21061s

NONBANKED

0x003F FFFF

0x0FFF FFFF

NOTE: BANK SIZES ARE SELECTED BY

MSIZE BITS OF THE SYSCON REGISTER

Figure 4. Memory Map

Rev. D

|

Page 6 of 52

|

May 2013

ADSP-21061/ADSP-21061L

The newest IDE, CrossCore Embedded Studio, is based on the

Eclipse^TMframework. Supporting most Analog Devices proces-

sor families, it is the IDE of choice for future processors,

including multicore devices. CrossCore Embedded Studio

seamlessly integrates available software add-ins to support real

time operating systems, file systems, TCP/IP stacks, USB stacks,

algorithmic software modules, and evaluation hardware board

support packages. For more information visit

Program Booting

The internal memory of the ADSP-21061 can be booted at sys-

tem power-up from either an 8-bit EPROM, or a host processor.

Selection of the boot source is controlled by the BMS (boot

memory select), EBOOT (EPROM boot), and LBOOT (host

boot) pins. 32-bit and 16-bit host processors can be used for

booting.

www.analog.com/cces.

PORTING CODE FROM THE ADSP-21060 OR

ADSP-21062

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

The ADSP-21061 is pin compatible with the ADSP-21060/

ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins

that correspond to the link port pins of the ADSP-21060/

ADSP-21062 are no-connects.

The ADSP-21061 is object code compatible with the

ADSP-21060/ADSP-21062 processors except for the following

functional elements:

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite^®evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders^®, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

• The ADSP-21061 memory is organized into two blocks

with eight columns that are 4k deep per block. The

ADSP-21060/ADSP-21062 memory has 16 columns per

block.

• Link port functions are not available.

• Handshake external port DMA pins DMAR2 and DMAG2

are assigned to external port DMA Channel 6 instead of

Channel 8.

EZ-KIT Lite Evaluation Kits

• 2-D DMA capability of the SPORT is not available.

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

• The modify registers in SPORT DMA are not

programmable.

On the ADSP-21061, Block 0 starts at the beginning of internal

memory, normal word address 0x0002 0000. Block 1 starts at

the end of Block 0, with contiguous addresses. The remaining

addresses in internal memory are divided into blocks that alias

into Block 1. This allows any code or data stored in Block 1 on

the ADSP-21062 to retain the same addresses on the

ADSP- 21061—these addresses will alias into the actual Block 1

of each processor.

If you develop your application using the ADSP-21062, but will

migrate to the ADSP-21061, use only the first eight columns of

each memory bank. Limit your application to 8k of instructions

or up to 16k of data in each bank of the ADSP-21062, or any

combination of instructions or data that does not exceed the

memory bank.

Software Add-Ins for CrossCore Embedded Studio

DEVELOPMENT TOOLS

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore^®Embed-

ded Studio and/or VisualDSP++^®), evaluation products,

emulators, and a wide variety of software add-ins.

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

Rev. D

| Page 7 of 52 | May 2013

ADSP-21061/ADSP-21061L

Board Support Packages for Evaluation Hardware

RELATED SIGNAL CHAINS

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

A signal chain is a series of signal conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Middleware Packages

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

• www.analog.com/ucos3

• www.analog.com/ucfs

• www.analog.com/ucusbd

• www.analog.com/lwip

TM

The Circuits from the Lab site (www.analog.com/signal

chains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com and

search on “Blackfin software modules” or “SHARC software

modules”.

• Reference designs applying best practice design techniques

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21061

architecture and functionality. For detailed information on the

ADSP-21000 Family core architecture and instruction set, refer

to the ADSP- 2106x SHARC User’s Manual.

Rev. D

| Page 8 of 52 | May 2013

ADSP-21061/ADSP-21061L

PIN FUNCTION DESCRIPTIONS

ADSP-21061 pin definitions are listed below. All pins are identi-

cal on the ADSP-21061 and ADSP-21061L. Inputs identified as

synchronous (S) must meet timing requirements with respect to

CLKIN (or with respect to TCK for TMS, TDI). Inputs identi-

fied as asynchronous (A) can be asserted asynchronously to

CLKIN (or to TCK for TRST).

Unused inputs should be tied or pulled to VDD or GND, except

for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs that have

internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,

TCLKx, RCLKx, TMS, and TDI)—these pins can be left float-

ing. These pins have a logic-level hold circuit that prevents the

input from floating internally.

Table 2. Pin Descriptions

Type

Function

ADDR_31–0

I/O/T

External Bus Address. The ADSP-21061 outputs addresses for external memory and peripherals on these

pins. In a multiprocessor system the bus master outputs addresses for read/write of the internal memory or

IOP registers of other ADSP-21061s. The ADSP-21061 inputs addresses when a host processor or multipro-

cessing bus master is reading or writing its internal memory or IOP registers.

DATA_47–0

I/O/T

O/T

External Bus Data. The ADSP-21061 inputs and outputs data and instructions on these pins. 32-bit single-

precision floating-point data and 32-bit fixed-point data is transferred over Bits 47 to 16 of the bus. 40-bit

extended-precision floating-point data is transferred over Bits 47 to 8 of the bus. 16-bit short word data is

transferred over Bits 31 to 16 of the bus. In PROM boot mode, 8-bit data is transferred over Bits 23 to 16. Pull-

up resistors on unused DATA pins are not necessary.

MS_3–0

Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of external

memory. Memory bank size must be defined in the ADSP-21061’s system control register (SYSCON). The

MS_3–0lines are decoded memory address lines that change at the same time as the other address lines.

When no external memory access is occurring the MS_3–0lines are inactive; they are active however when a

conditional memory access instruction is executed, whether or not the condition is true. MS₀can be used

with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system the MS_3–0

lines are output by the bus master.

RD

I/O/T

O/T

Memory Read Strobe. This pin is asserted (low) when the ADSP-21061 reads from external memory devices

or from the internal memory of other ADSP-21061s. External devices (including other ADSP-21061s) must

assert RD to read from the ADSP-21061’s internal memory. In a multiprocessing system RD is output by the

bus master and is input by all other ADSP-21061s.

WR

Memory Write Strobe. This pin is asserted (low) when the ADSP-21061 writes to external memory devices

or to the internal memory of other ADSP-21061s. External devices must assert WR to write to the

ADSP-21061’s internal memory. In a multiprocessing system WR is output by the bus master and is input by

all other ADSP-21061s.

PAGE

DRAM Page Boundary. The ADSP-21061 asserts this pin to signal that an external DRAM page boundary

has been crossed. DRAM page size must be defined in the ADSP-21061’s memory control register (WAIT).

DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for

Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.

ADRCLK

SW

O/T

Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.

I/O/T

Synchronous Write Select. This signal is used to interface theADSP-21061 to synchronousmemory devices

(including other ADSP-21061s). The ADSP-21061 asserts SW (low) to provide an early indication of an

impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write

instruction). In a multiprocessing system, SW is output by the bus master and is input by all other

ADSP-21061s to determine if the multiprocessor memory access is a read or write. SWis asserted at the same

time as the address output. A host processor using synchronous writes must assert this pin when writing to

the ADSP-21061(s).

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)

Rev. D

| Page 9 of 52 | May 2013

ADSP-21061/ADSP-21061L

Table 2. Pin Descriptions (Continued)

Type

Function

ACK

I/O/S

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory

access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an

external memory access. The ADSP-21061 deasserts ACK as an output to add wait states to a synchronous

access of its internal memory. In a multiprocessing system, a slave ADSP-21061 deasserts the bus master’s

ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its

ACK pin that maintains the input at the level to which it was last driven.

SBTS

I/S

Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data,

selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061 attempts to access

external memory while SBTS is asserted, the processor halts and the memory access is not complete until

SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21061 deadlock, or used

with a DRAM controller.

IRQ_2–0

I/A

Interrupt Request Lines. May be either edge-triggered or level-sensitive.

FLAG_3–0

I/O/A

Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as

a condition. As an output, they can be used to signal external peripherals.

TIMEXP

HBR

O

Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.

I/A

Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-21061’s

external bus. When HBR is asserted in a multiprocessing system, the ADSP-21061 that is bus master will

relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address, data, select,

and strobe lines in a high impedance state. HBR has priority over all ADSP-21061 bus requests BR_6–1in a

multiprocessing system.

HBG

I/O

Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the

externalbus. HBGisasserted(heldlow)bytheADSP-21061untilHBR isreleased. Inamultiprocessingsystem,

HBG is output by the ADSP-21061 bus master and is monitored by all others.

CS

I/A

Chip Select. Asserted by host processor to select the ADSP-21061.

REDY

O (O/D)

HostBusAcknowledge. TheADSP-21061deassertsREDY(low)toaddwaitstatestoanasynchronousaccess

of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be

programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if

the CS and HBR inputs are asserted.

DMAR_2–1

DMAG_2–1

BR_6–1

I/A

DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 6).

DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 6).

O/T

I/O/S

Multiprocessing Bus Requests. Used by multiprocessing ADSP-21061 processors to arbitrate for bus

mastership. An ADSP-21061 only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and

monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BRx pins should

be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output.

ID2–0

RPBA

O (O/D)

I/S

Multiprocessing ID. Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-21061.

ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc., ID = 000 in single-processor systems. These

lines are a system configuration selection which should be hardwired or changed at reset only.

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus

arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration

selection which must be set to the same value on every ADSP-21061. If the value of RPBA is changed during

system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.

CPA

I/O (O/D)

CorePriority Access. AssertingitsCPApinallows the coreprocessor of anADSP-21061bus slaveto interrupt

background DMA transfers and gain access to the external bus. CPA is an open-drain output that is

connected to all ADSP-21061s in the system. The CPA pin has an internal 5 k pull-up resistor. If core access

priority is not required in a system, the CPA pin should be left unconnected.

DTx

O

Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k internal pull-up resistor.

Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k internal pull-up resistor.

Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k internal pull-up resistor.

Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k internal pull-up resistor.

DRx

I

TCLKx

RCLKx

I/O

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)

Rev. D

| Page 10 of 52 | May 2013

ADSP-21061/ADSP-21061L

Table 2. Pin Descriptions (Continued)

Type

I/O

I

Function

TFSx

RFSx

EBOOT

Transmit Frame Sync (Serial Ports 0, 1).

Receive Frame Sync (Serial Ports 0, 1).

EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-bit EPROM.

When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin

description below. This signal is a system configuration selection that should be hardwired.

LBOOT

BMS

I

Link Boot. Must be tied to GND.

I/O/T*

Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,

LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no

booting will occur and that ADSP-21061 will begin executing instructions from external memory. See table

below. This input is a system configuration selection that should be hardwired. *Three-statable only in

EPROM boot mode (when BMS is an output).

EBOOT

LBOOT

BMS

Booting Mode

1

0

Output

1(Input)

0 (Input)

EPROM (Connect BMS to EPROM chip select.)

Host Processor.

No Booting. Processor executes from external memory.

CLKIN

RESET

I

Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN. CLKIN may

not be halted, changed, or operated below the minimum specified frequency.

I/A

Processor Reset. Resets the ADSP-21061 to a known state and begins program execution at the program

memory location specified by the hardware reset vector address. This input must be asserted (low) at

power-up.

TCK

TMS

TDI

I

Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.

I/S

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up

resistor.

TDO

TRST

O

Test Data Output (JTAG). Serial scan output of the boundary scan path.

I/A

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held

low for proper operation of the ADSP-21061. TRST has a 20 k internal pull-up resistor.

EMU

O

Emulation Status. Must be connected to the ADSP-21061 EZ-ICE target board connector only. EMU has a

50 k internal pull-up resistor.

ICSA

VDD

GND

NC

O

P

Reserved. Leave unconnected.

Power Supply. (30 pins). See Operating Conditions (5 V) and Operating Conditions (3.3 V).

Power Supply Return. (30 pins)

G

Do Not Connect. Reserved pins which must be left open and unconnected.

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)

Rev. D

| Page 11 of 52 | May 2013

ADSP-21061/ADSP-21061L

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The JTAG signals are terminated on the EZ-ICE probe as shown

in Table 3.

The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG

test access port of the ADSP-2106x to monitor and control the

target board processor during emulation. The EZ-ICE probe

requires the ADSP-2106x’s CLKIN, TMS, TCK, TDI, TDO, and

GND signals be made accessible on the target system via a

14-pin connector (a 2-row, 7-pin strip header) such as that

shown in Figure 5. The EZ-ICE probe plugs directly onto this

connector for chip-on-board emulation. You must add this con-

nector to your target board design if you intend to use the

ADSP-2106x EZ-ICE. The total trace length between the EZ-

ICE connector and the farthest device sharing the EZ-ICE JTAG

pin should be limited to 15 inches maximum for guaranteed

operation. This length restriction must include EZ-ICE JTAG

signals that are routed to one or more ADSP-2106x devices, or a

combination of ADSP-2106x devices and other JTAG devices

on the chain.

Table 3. Core Instruction Rate/CLKIN Ratio Selection

Signal

TMS

Termination

Driven Through 22 Resistor (16 mA Driver)

TCK

Driven at 10 MHz Through 22 Resistor (16 mA

Driver)

TRST¹

Active Low Driven Through 22  Resistor (16 mA

Driver) (Pulled Up by On-Chip 20 k Resistor)

TDI

Driven by 22 Resistor (16 mA Driver)

One TTL Load, Split Termination (160/220)

TDO

CLKIN

EMU

Active Low, 4.7 k Pull-Up Resistor, One TTL Load

(Open-Drain Output from the DSP)

¹TRSTis driven low until the EZ-ICE probe is turned on by the emulator at software

startup. After software startup, is driven high.

1

3

5

2

4

6

Figure 6 shows JTAG scan path connections for systems that

contain multiple ADSP-2106x processors.

EMU

GND

TMS

GND

Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.

The emulator only uses CLKIN when directed to perform oper-

ations such as starting, stopping, and single-stepping multiple

ADSP-2106xs in a synchronous manner. If you do not need

these operations to occur synchronously on the multiple proces-

sors, simply tie Pin 4 of the EZ-ICE header to ground.

KEY (NO PIN)

BTMS

7

9

8

BTCK

TCK

10

12

BTRST

TRST

If synchronous multiprocessor operations are needed and

CLKIN is connected, clock skew between the multiple

ADSP-21061 processors and the CLKIN pin on the EZ-ICE

header must be minimal. If the skew is too large, synchronous

operations may be off by one or more cycles between proces-

sors. For synchronous multiprocessor operation TCK, TMS,

CLKIN, and EMU should be treated as critical signals in terms

of skew, and should be laid out as short as possible on your

board. If TCK, TMS, and CLKIN are driving a large number of

ADSP-21061s (more than eight) in your system, then treat them

as a “clock tree” using multiple drivers to minimize skew. (See

Figure 7 below and “JTAG Clock Tree” and “Clock Distribu-

tion” in the “High Frequency Design Considerations” section of

the ADSP-2106x SHARC User’s Manual.)

9

11

BTDI

GND

TDI

13

14

TDO

TOP VIEW

Figure 5. Target Board Connector For ADSP-2106x EZ-ICE Emulator

(Jumpers in Place)

The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca-

tion—Pin 3 must be removed from the header. The pins must be

0.025 inch square and at least 0.20 inches in length. Pin spacing

should be 0.1  0.1 inches. Pin strip headers are available from

vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK,

BTRST, and BTDI signals are provided so that the test access

port can also be used for board-level testing.

If synchronous multiprocessor operations are not needed (i.e.,

CLKIN is not connected), just use appropriate parallel termina-

tion on TCK and TMS. TDI, TDO, EMU, and TRST are not

critical signals in terms of skew.

When the connector is not being used for emulation, place

jumpers between the Bxxx pins and the xxx pins as shown in

Figure 5. If you are not going to use the test access port for

board testing, tie BTRST to GND and tie or pull up BTCK to

V_DD. The TRST pin must be asserted (pulsed low) after power-

up (through BTRST on the connector) or held low for proper

operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7,

9, and 11) are connected on the EZ-ICE probe.

Rev. D

| Page 12 of 52 | May 2013

ADSP-21061/ADSP-21061L

JTAG

DEVICE

(OPTIONAL)

ADSP-2106x

n

#1

TDI

TDO

TDI

EZ-ICE

JTAG

CONNECTOR

OTHER

JTAG

CONTROLLER

TCK

TMS

EMU

TRST

TDO

CLKIN

OPTIONAL

Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems

TDI

TDO

TDI

TDO

TDI

TDO

5k⍀

*

TDI

TDO

TDI

TDO

TDI

TDO

TDI

5k⍀

*

EMU

TCK

TMS

TRST

TDO

SYSTEM

CLKIN

EMU

*OPEN-DRAIN DRIVER OR EQUIVALENT, i.e,

Figure 7. JTAG Clock Tree for Multiple ADSP-2106x Systems

Rev. D

| Page 13 of 52 | May 2013

ADSP-21061/ADSP-21061L

ADSP-21061 SPECIFICATIONS

OPERATING CONDITIONS (5 V)

K Grade

Parameter

Description

Min

Nom

5.0

Max

Unit

V_DD

Supply Voltage

4.75

0

5.25

V

T_CASE

V_IH1¹

V_IH2²

Case Operating Temperature

High Level Input Voltage @ V_DD= Max

Low Level Input Voltage @ V_DD= Min

85

C

V

2.0

2.2

–0.5

V_DD+ 0.5

+0.8

V

1, 2

V_IL

V

¹Applies to input and bidirectional pins: DATA_47–0, ADDR_31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR_6–1, ID_2–0, RPBA, CPA, TFS0,

TFS1, RFS0, RFS1, EBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.

²Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS (5 V)

Parameter

Description

Test Conditions

Min

Max

Unit

1, 2

V_OH

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

Low Level Input Current

@ V_DD= Min, I_OH= –2.0 mA

@ V_DD= Min, I_OL= 4.0 mA

@ V_DD= Max, V_IN= V_DDMax

@ V_DD= Max, V_IN= 0 V

4.1

V

1, 2

V_OL

0.4

10

V

3, 4

I_IH

μA

mA

μA

mA

μA

pF

3

I_IL

10

4

I_ILP

Low Level Input Current

@ V_DD= Max, V_IN= 0 V

150

10

5, 6, 7, 8

I_OZH

Three-State Leakage Current

Input Capacitance

@ V_DD= Max, V_IN= V_DDMax

@ V_DD= Max, V_IN= 0 V

5

I_OZL

10

I_OZHP

@ V_DD= Max, V_IN= V_DDMax

@ V_DD= Max, V_IN= 0 V

350

1.5

350

4.2

150

4.7

7

I_OZLC

9

I_OZLA

@ V_DD= Max, V_IN= 1.5 V

@ V_DD= Max, V_IN= 0 V

8

I_OZLAR

6

I_OZLS

@ V_DD= Max, V_IN= 0 V

10, 11

C_IN

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 2.5 V

¹Applies to output and bidirectional pins: DATA_47-0, ADDR_31-0, 3-0, MS_3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2,

BR_6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, TDO, EMU, ICSA.

²See “Output Drive Currents” on Page 44 for typical drive current capabilities.

³Applies to input pins: ACK, SBTS, IRQ_2–0, HBR, CS, DMAR1, DMAR2, ID_2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

⁴Applies to input pins with internal pull-ups:DR0, DR1, TRST, TMS, TDI, EMU.

⁵Applies to three-statable pins: DATA_47–0, ADDR_31–0, MS_3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR_6–1, TFSx, RFSx,

TDO, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID_2–0= 001 and another ADSP-21061 is not requesting bus

mastership.)

⁶Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

⁷Applies to CPA pin.

⁸Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID_2–0= 001 and another ADSP-21061L

is not requesting bus mastership).

⁹Applies to ACK pin when keeper latch enabled.

¹⁰Applies to all signal pins.

¹¹Guaranteed but not tested.

Rev. D

| Page 14 of 52 | May 2013

ADSP-21061/ADSP-21061L

a complete discussion of the code used to measure power dissi-

pation, see the technical note “SHARC Power Dissipation

Measurements.”

INTERNAL POWER DISSIPATION (5 V)

These specifications apply to the internal power portion of V_DD

only. See the Power Dissipation section of this data sheet for cal-

culation of external supply current and total supply current. For

Specifications are based on the operating scenarios:

Operation

Peak Activity (I_DDINPEAK

)

High Activity (I_DDINHIGH

)

Low Activity (I_DDINLOW

Single Function

Internal Memory

None

)

Instruction Type

Instruction Fetch

Core Memory Access

Internal Memory DMA

Multifunction

Cache

Multifunction

Internal Memory

1 per Cycle (DM)

1 per 2 Cycles

2 per Cycle (DM and PM)

1 per Cycle

1 per 2 Cycles

To estimate power consumption for a specific application, use

the following equation where % is the amount of time your pro-

gram spends in that state:

%PEAK I_DDINPEAK+ %HIGH I_DDINHIGH+ %LOW I_DDINLOW

%IDLE I_DDIDLE= power consumption

+

Parameter

Test Conditions

Max

Unit

I

_DDINPEAKSupply Current (Internal)¹

_DDINHIGHSupply Current (Internal)²

_DDINLOWSupply Current (Internal)³

_DDIDLESupply Current (Idle)⁴

t_CK= 30 ns, V_DD= Max

t_CK= 25 ns, V_DD= Max

t_CK= 20 ns, V_DD= Max

595

680

850

mA

t_CK= 30 ns, V_DD= Max

t_CK= 25 ns, V_DD= Max

t_CK= 20 ns, V_DD= Max

460

540

670

mA

t_CK= 30 ns, V_DD= Max

t_CK= 25 ns, V_DD= Max

t_CK= 20 ns, V_DD= Max

270

320

390

mA

V_DD= Max

200

55

mA

I_DDIDLESupply Current (Idle16)⁵

¹The test program used to measure I_DDINPEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power

measurements made using typical applications are less than specified.

²I_DDINHIGHis a composite average based on a range of high activity code. I_DDINLOWis a composite average based on a range of low activity code.

³I_DDINLOWis a composite average based on a range of low activity code.

⁴Idle denotes ADSP-21061L state during execution of IDLE instruction.

⁵Idle16 denotes ADSP-2106x state during execution of IDLE16 instruction.

Rev. D

| Page 15 of 52 | May 2013

ADSP-21061/ADSP-21061L

EXTERNAL POWER DISSIPATION (5 V)

The load capacitance should include the processor’s package

capacitance (CIN). The switching frequency includes driving

the load high and then back low. Address and data pins can

drive high and low at a maximum rate of 1/(2t_CK). The write

strobe can switch every cycle at a frequency of 1/t_CK. Select pins

switch at 1/(2t_CK), but selects can switch on each cycle.

Total power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved.

Internal power dissipation is calculated in the following way:

P_INT= I_DDINV_DD

Example: Estimate P_EXTwith the following assumptions:

• A system with one bank of external data memory RAM

(32-bit)

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• Four 128k  8 RAM chips are used, each with a load of

10 pF

—the number of output pins that switch during each cycle

(O)

• External data memory writes occur every other cycle, a rate

of 1/(4t_CK), with 50% of the pins switching

—the maximum frequency at which they can switch (f)

—their load capacitance (C)

• The instruction cycle rate is 40 MHz (t_CK= 25 ns)

—their voltage swing (V_DD

and is calculated by:

)

The P_EXTequation is calculated for each class of pins that can

drive:

PEXT = O  C  V_DD² f

Table 4. External Power Calculations

2

Pin Type

Address

MS0

No. of Pins % Switching

 C

 f

 V_DD

 25 V

= P_EXT

15

1

50

0

 44.7 pF

 14.7 pF

 4.7 pF

 10 MHz

 20 MHz

 10 MHz

 20 MHz

= 0.084 W

= 0.000 W

= 0.022 W

= 0.059 W

= 0.002 W

WR

1

—

50

—

Data

32

1

ADDRCLK

P

_EXT= 0.167 W

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

P_TOTAL= P_EXT+ (I_DDIN2 5.0 V)

Note that the conditions causing a worst-case P_EXTare different

from those causing a worst-case P_INT. Maximum P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching

simultaneously.

Rev. D

| Page 16 of 52 | May 2013

ADSP-21061/ADSP-21061L

ADSP-21061L SPECIFICATIONS

OPERATING CONDITIONS (3.3 V)

A Grade

K Grade

Parameter Description

Min

Nom

3.3

Max

Min

Nom

Max

Unit

V_DD

Supply Voltage

3.15

–40

2.0

3.45

3.15

0

3.3

3.45

V

T_CASE

V_IH1¹

V_IH2²

Case Operating Temperature

High Level Input Voltage @ V_DD= Max

Low Level Input Voltage @ V_DD= Min

+85

C

V

V_DD+ 0.5

+0.8

2.0

2.2

–0.5

V_DD+ 0.5

+0.8

2.2

V

1, 2

V_IL

–0.5

V

¹Applies to input and bidirectional pins: DATA_47–0, ADDR_31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR_6–1, ID_2–0, RPBA, CPA, TFS0,

TFS1, RFS0, RFS1, EBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1

²Applies to input pins: CLKIN, RESET, TRST

ELECTRICAL CHARACTERISTICS (3.3 V)

Parameter

Description

Test Conditions

Min

Max

Unit

1,2

V_OH

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

Low Level Input Current

@ V_DD= Min, I_OH= –2.0 mA

@ V_DD= Min, I_OL= 4.0 mA

@ V_DD= Max, V_IN= V_DDMax

@ V_DD= Max, V_IN= 0 V

2.4

V

1, 2

V_OL

0.4

10

V

3, 4

I_IH

μA

mA

μA

mA

μA

pF

3

I_IL

10

4

I_ILP

Low Level Input Current

@ V_DD= Max, V_IN= 0 V

150

10

5, 6, 7, 8

I_OZH

Three-State Leakage Current

Input Capacitance

@ V_DD= Max, V_IN= V_DDMax

@ V_DD= Max, V_IN= 0 V

5

I_OZL

10

I_OZHP

@ V_DD= Max, V_IN= V_DDMax

@ V_DD= Max, V_IN= 0 V

350

1.5

350

4.2

150

4.7

7

I_OZLC

9

I_OZLA

@ V_DD= Max, V_IN= 1.5 V

@ V_DD= Max, V_IN= 0 V

8

I_OZLAR

6

I_OZLS

@ V_DD= Max, V_IN= 0 V

10, 11

C_IN

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 2.5 V

¹Applies to output and bidirectional pins: DATA_47–0, ADDR_31–0, 3-0, MS_3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2,

BR_6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, TDO, EMU, ICSA.

²See “Output Drive Currents” on Page 45 for typical drive current capabilities.

³Applies to input pins: ACK, SBTS, IRQ_2–0, HBR, CS, DMAR1, DMAR2, ID_2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

⁴Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI, EMU.

⁵Applies to three-statable pins: DATA_47–0, ADDR_31–0, MS_3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG_3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR_6–1, TFSx, RFSx,

TDO, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID_2–0= 001 and another ADSP-21061 is not requesting bus

mastership.)

⁶Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

⁷Applies to CPA pin.

⁸Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID_2–0= 001 and another ADSP-21061L

is not requesting bus mastership).

⁹Applies to ACK pin when keeper latch enabled.

¹⁰Applies to all signal pins.

¹¹Guaranteed but not tested.

Rev. D

| Page 17 of 52 | May 2013

ADSP-21061/ADSP-21061L

INTERNAL POWER DISSIPATION (3.3 V)

a complete discussion of the code used to measure power dissi-

pation, see the technical note “SHARC Power Dissipation

Measurements.”

These specifications apply to the internal power portion of V_DD

only. See the Power Dissipation section of this data sheet for cal-

culation of external supply current and total supply current. For

Specifications are based on the operating scenarios:

Operation

Peak Activity (I_DDINPEAK

)

High Activity (I_DDINHIGH

)

Low Activity (I_DDINLOW

Single Function

Internal Memory

None

)

Instruction Type

Instruction Fetch

Core memory Access

Internal Memory DMA

Multifunction

Cache

Multifunction

Internal Memory

1 per Cycle (DM)

1 per 2 Cycles

2 per Cycle (DM and PM)

1 per Cycle

1 per 2 Cycles

To estimate power consumption for a specific application, use

the following equation where % is the amount of time your pro-

gram spends in that state:

%PEAK I_DDINPEAK+ %HIGH I_DDINHIGH+ %LOW I_DDINLOW+ %IDLE

I_DDIDLE= power consumption

Parameter

_DDINPEAKSupply Current (Internal)¹

Test Conditions

Max

Unit

I

t_CK= 25 ns, V_DD= Max

t_CK= 22.5 ns, V_DD= Max

480

535

mA

I_DDINHIGHSupply Current (Internal)²

t_CK= 25 ns, V_DD= Max

t_CK= 22.5 ns, V_DD= Max

380

425

mA

I

_DDINLOWSupply Current (Internal)³

_DDIDLESupply Current (Idle)⁴

t_CK= 25 ns, V_DD= Max

t_CK= 22.5 ns, V_DD= Max

220

245

mA

V_DD= Max

180

50

mA

I_DDIDLESupply Current (Idle)⁵

¹The test program used to measure I_DDINPEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power

measurements made using typical applications are less than specified.

²I_DDINHIGHis a composite average based on a range of high activity code. I_DDINLOWis a composite average based on a range of low activity code.

3

_IDDINLOWis a composite average based on a range of low activity code.

⁴Idle denotes ADSP-21061L state during execution of IDLE instruction.

⁵Idle16 denotes ADSP-21061L state during execution of IDLE16 instruction.

Rev. D

| Page 18 of 52 | May 2013

ADSP-21061/ADSP-21061L

The load capacitance should include the processor’s package

capacitance (CIN). The switching frequency includes driving

the load high and then back low. Address and data pins can

drive high and low at a maximum rate of 1/(2t_CK). The write

strobe can switch every cycle at a frequency of 1/t_CK. Select pins

switch at 1/(2t_CK), but selects can switch on each cycle.

EXTERNAL POWER DISSIPATION (3.3 V)

Total power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved.

Internal power dissipation is calculated in the following way:

P_INT= I_DDINV_DD

Example: Estimate P_EXTwith the following assumptions:

• A system with one bank of external data memory RAM

(32-bit)

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• Four 128k  8 RAM chips are used, each with a load of

10 pF

—the number of output pins that switch during each cycle

(O)

• External data memory writes occur every other cycle, a rate

of 1/(4t_CK), with 50% of the pins switching

—the maximum frequency at which they can switch (f)

—their load capacitance (C)

• The instruction cycle rate is 40 MHz (t_CK= 25 ns)

—their voltage swing (V_DD

and is calculated by:

)

The P_EXTequation is calculated for each class of pins that can

drive:

PEXT = O  C  V_DD² f

Table 5. External Power Calculations

2

Pin Type

Address

MS0

No. of Pins

% Switching

 C

 f

 V_DD

= P_EXT

15

1

50

0

 44.7 pF

 14.7 pF

 4.7 pF

 10 MHz

 20 MHz

 10 MHz

 20 MHz

 10.9 V

= 0.037 W

= 0.000 W

= 0.010 W

= 0.026 W

= 0.001 W

WR

1

—

50

—

Data

32

1

ADDRCLK

P

_EXT= 0.074 W

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

P_TOTAL= P_EXT+ (I_DDIN2 3.3 V)

Note that the conditions causing a worst-case P_EXTare different

from those causing a worst-case P_INT. Maximum P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching

simultaneously.

Rev. D

| Page 19 of 52 | May 2013

ADSP-21061/ADSP-21061L

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed below may cause permanent

damage to the device. These are stress ratings only; functional

operation of the device at these or any other conditions greater

than those indicated in the operational sections of this specifica-

tion is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Parameter

5 V

3.3 V

Supply Voltage (V_DD)

Input Voltage

–0.3 V to +7.0 V

–0.5 V to V_DD+0.5 V

200 pF

–0.3 V to +4.6 V

–0.5 V to V_DD+0.5 V

200 pF

Output Voltage Swing

Load Capacitance

Storage Temperature Range

Lead Temperature (5 seconds)

Junction Temperature Under Bias

–65C to +150C

280C

130C

–65C to +150C

280C

130C

ESD CAUTION

TIMING SPECIFICATIONS

The timing specifications shown are based on a CLKIN fre-

quency of 50 MHz (t_CK= 20 ns). The DT derating enables the

calculation of timing specifications within the min to max range

of the t_CKspecification (see Table 7). DT is the difference

between the derated CLKIN period (t_CK) and a CLKIN period of

25 ns:

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

DT = t_CK– 20 ns

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, you

cannot meaningfully add parameters to derive longer times.

PACKAGE MARKING INFORMATION

The information presented in Figure 8 provides details about

the package branding for the ADSP-21061 processor. For a

complete listing of product availability, see Ordering Guide on

Page 52.

For voltage reference levels, see Figure 29 under Test

Conditions.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices. (O/D) = Open Drain,

(A/D) = Active Drive.

a

ADSP-21061

tppZccc

vvvvvv.x n.n

Switching Characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

yyww country_of_origin

S

Figure 8. Typical Package Marking (Actual Marking Format May Vary)

Table 6. Package Brand Information

Brand Key

Field Description

Temperature Range

Package Type

t

pp

Z

Lead Free Option

See Ordering Guide

Assembly Lot Code

Silicon Revision

Date Code

ccc

vvvvvv.x

n.n

yyww

Rev. D

| Page 20 of 52 | May 2013

ADSP-21061/ADSP-21061L

Clock Input

Table 7. Clock Input

ADSP-21061/

ADSP-21061L

ADSP-21061

50 MHz, 5 V

ADSP-21061L

44 MHz, 3.3 V

40 MHz,

5 V and 3.3 V

ADSP-21061

33 MHz, 5 V

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

t_CK

CLKIN Period

20

7

100

22.5

7

100

25

7

100

30

7

100

ns

t_CKL

t_CKH

t_CKRF

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V to 2.0 V)

5

3

t_CK

CLKIN

t_CKH

t_CKL

Figure 9. Clock Input

Reset

Table 8. Reset

5 V and 3.3 V

Max

Unit

Parameter

Min

Timing Requirements

t_WRST

t_SRST

RESET Pulse Width Low¹

RESET Setup Before CLKIN High²

4t_CK

ns

14 + DT/2

t_CK

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

V_DDand CLKIN (not including startup time of external clock oscillator).

²Only required if multiple ADSP-21061s must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21061s commu-

nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.

CLKIN

t_SRST

t_WRST

RESET

Figure 10. Reset

Rev. D

| Page 21 of 52 | May 2013

ADSP-21061/ADSP-21061L

Interrupts

Table 9. Interrupts

5 V and 3.3 V

Max

Unit

Parameter

Min

Timing Requirements

t_SIR

t_HIR

t_IPW

IRQ2–0 Setup Before CLKIN High¹

IRQ2–0 Hold Before CLKIN High¹

IRQ2–0 Pulsewidth²

18 + 3DT/4

2+t_CK

ns

12 + 3DT/4

¹Only required for IRQx recognition in the following cycle.

²Applies only if t_SIRand t_HIRrequirements are not met.

CLKIN

t_SIR

t_HIR

IRQ2–0

t_IPW

Figure 11. Interrupts

Timer

Table 10. Timer

5 V and 3.3 V

Max

Unit

Parameter

Min

Switching Characteristic

t_DTEX

CLKIN High to TIMEXP

15

ns

CLKIN

t_DTEX

TIMEXP

Figure 12. Timer

Rev. D

|

Page 22 of 52

|

May 2013

ADSP-21061/ADSP-21061L

Flags

Table 11. Flags

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

t_SFI

FLAG3–0 IN Setup Before CLKIN High¹

8 + 5DT/16

0 – 5DT/16

ns

t_HFI

FLAG3–0 IN Hold After CLKIN High¹

FLAG3–0 IN Delay After RD/WR Low¹

FLAG3–0 IN Hold After RD/WR Deasserted¹

t_DWRFI

t_HFIWR

5 + 7DT/16

0

Switching Characteristics

t_DFO

FLAG3–0 OUT Delay After CLKIN High

16

14

ns

t_HFO

FLAG3–0 OUT Hold After CLKIN High

CLKIN High to FLAG3–0 OUT Enable

CLKIN High to FLAG3–0 OUT Disable

4

3

t_DFOE

t_DFOD

¹Flag inputs meeting these setup and hold times for Instruction Cycle N will affect conditional instructions in Instruction Cycle N+2.

CLKIN

t_DFO

t_DFOE

t_DFO

t_DFOD

t_HFO

FLAG3–0 _OUT

FLAG OUTPUT

CLKIN

t_SFI

t_HFI

FLAG3–0 _IN

t_DWRFI

t_HFIWR

RD WR

FLAG INPUT

Figure 13. Flags

Rev. D

| Page 23 of 52 | May 2013

ADSP-21061/ADSP-21061L

bus master accessing external memory space in asynchronous

access mode. Note that timing for ACK, DATA, RD, WR, and

DMAGx strobe timing parameters only applies to asynchronous

access mode.

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-21061 is the

Table 12. Memory Read—Bus Master

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

t_DAD

Address, Selects Delay to Data Valid^{1, 2}

RD Low to Data Valid¹

Data Hold from Address, Selects³

Data Hold from RD High³

ACK Delay from Address, Selects^{2, 4}

ACK Delay from RD Low⁴

18 + DT+W

ns

t_DRLD

t_HDA

12 + 5DT/8 + W

0.5

2.0

t_HDRH

t_DAAK

t_DSAK

15 + 7DT/8 + W

8 + DT/2 + W

Switching Characteristics

t_DRHA

t_DARL

t_RW

Address, Selects Hold After RD High

Address, Selects to RD Low²

0+H

ns

2 + 3DT/8

RD Pulse Width

12.5 + 5DT/8 + W

8 + 3DT/8 + HI

0 + DT/4

t_RWR

RD High to WR, RD, DMAGx Low

Address, Selects Setup Before ADRCLK High²

t_SADADC

W = (number of wait states specified in WAIT register)

؋

t_CK

.

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t_CK(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

¹Data delay/setup: user must meet t_DADor t_DRLDor synchronous spec t_SSDATI

.

²The falling edge of MSx, SW, BMS is referenced.

³Data hold: user must meet t_HDAor t_HDRHor synchronous spec t_HSDATI. See Example System Hold Time Calculation on Page 43 for the calculation of hold times given capacitive

and dc loads.

⁴ACK delay/setup: user must meet t_DAAKor t_DSAKor synchronous specification t_SACKC(Table 13 on Page 25) for deassertion of ACK (Low), all three specifications must be met

for assertion of ACK (High).

ADDRESS

MSX, SW

BMS

t_DRHA

t_DARL

t_RW

RD

t_HDA

t_HDRH

t_DRLD

t_DAD

DATA

t_DSAK

t_RWR

t_DAAK

ACK

WR, DMAG

t_SADADC

ADDRCLK

(OUT)

Figure 14. Memory Read—Bus Master

Rev. D

| Page 24 of 52 | May 2013

ADSP-21061/ADSP-21061L

bus master accessing external memory space in asynchronous

access mode. Note that timing for ACK, DATA, RD, WR, and

DMAGx strobe timing parameters only applies to asynchronous

access mode.

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-21061 is the

Table 13. Memory Write—Bus Master

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

t_DAAK

t_DSAK

ACK Delay from Address, Selects^{1, 2}

ACK Delay from WR Low¹

15 + 7DT/8 + W

8 + DT/2 + W

ns

Switching Characteristics

t_DAWH

t_DAWL

t_WW

Address, Selects to WR Deasserted²

Address, Selects to WR Low²

17 + 15DT/16 + W

3 + 3DT/8

ns

WR Pulse Width

13 + 9DT/16 + W

7 + DT/2 + W

1 + DT/16 + H

1 + DT/16 +H

8 + 7DT/16 + H

5 + 3DT/8 + I

–1 + DT/16

t_DDWH

Data Setup Before WR High

Address Hold After WR Deasserted

t_DWHA

t_DATRWHData Disable After WR Deasserted³

6 + DT/16+H

t_WWR

t_DDWR

t_WDE

WR High to WR, RD, DMAGx Low

Data Disable Before WR or RD Low

WR Low to Data Enabled

t_SADADCAddress, Selects to ADRCLK High²

0 + DT/4

W = (number of wait states specified in WAIT register) × t_CK

.

H = t_CK(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

I = t_CK(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

¹ACK delay/setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SAKCfor deassertion of ACK (low), all three specifications must be met for assertion of ACK

(high).

²The falling edge of MSx, SW, BMS is referenced.

³For more information, see Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.

ADDRESS

MSX, SW

BMS

t_DWHA

t_DAWH

t_WW

t_DAWL

WR

t_WWR

t_DDWR

t_DDWH

t_WDE

t_DATRWH

DATA

t_DSAK

t_DAAK

ACK

RD, DMAG

t_SADADC

ADRCLK

(OUT)

Figure 15. Memory Write—Bus Master

Rev. D

| Page 25 of 52 | May 2013

ADSP-21061/ADSP-21061L

Bus Master on Page 25). When accessing a slave ADSP-21061,

these switching characteristics must meet the slave’s timing

requirements for synchronous read/writes (see Synchronous

Read/Write—Bus Slave on Page 28). The slave ADSP-21061

must also meet these (bus master) timing requirements for data

and acknowledge setup and hold times.

Synchronous Read/Write—Bus Master

Use these specifications for interfacing to external memory sys-

tems that require CLKIN—relative timing or for accessing a

slave ADSP-21061 (in multiprocessor memory space). These

synchronous switching characteristics are also valid during

asynchronous memory reads and writes except where noted (see

Memory Read—Bus Master on Page 24 and Memory Write—

Table 14. Synchronous Read/Write—Bus Master

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

t_SSDATI

Data Setup Before CLKIN

(50 MHz, t_CK= 20 ns)¹

2 + DT/8

1.5 + DT/8

ns

t_HSDATI

t_DAAK

t_SACKC

t_HACK

Data Hold After CLKIN

3.5 – DT/8

ns

ACK Delay After Address, Selects^{2, 3}

ACK Setup Before CLKIN³

ACK Hold After CLKIN

15 + 7DT/8 + W

6.5 – DT/8

6.5+DT/4

–1 – DT/4

Switching Characteristics

t_DADRO

t_HADRO

t_DPGC

Address, MSx, BMS, SW Delay After CLKIN²

ns

Address, MSx, BMS, SW Hold After CLKIN

PAGE Delay After CLKIN

–1 – DT/8

9 + DT/8

16 + DT/8

4 – DT/8

t_DRDO

t_DWRO

RD High Delay After CLKIN

–1.5 – DT/8

WR High Delay After CLKIN

(50 MHz, t_CK= 20 ns)

–2.5 – 3DT/16

–1.5 – 3DT/16

4 – 3DT/16

t_DRWL

RD/WR Low Delay After CLKIN

Data Delay After CLKIN

Data Disable After CLKIN⁴

ADRCLK Delay After CLKIN

ADRCLK Period

8 + DT/4

12 + DT/4

19 + 5DT/16

7 – DT/8

ns

t_SDDATO

t_DATTR

0 – DT/8

4 + DT/8

t_CK

t_DADCCK

t_ADRCK

t_ADRCKH

t_ADRCKL

10 + DT/8

ADRCLK Width High

(t_CK/2 – 2)

ADRCLK Width Low

(t_CK/2 – 2)

¹This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t_CK< 25 ns. For all other devices, use the preceding timing specification of the same name.

²The falling edge of MSx, SW, BMS is referenced.

³ACK delay/setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SAKCfor deassertion of ACK (low), all three specifications must be met for assertion of ACK

(high).

⁴See Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.

Rev. D

| Page 26 of 52 | May 2013

ADSP-21061/ADSP-21061L

CLKIN

t_ADRCK

t_ADRCKH

t_DADCCK

t_ADRCKL

ADDRCLK

t_DADRO

t_DAAK

t_HADRO

ADDRESS, BMS,

SW, MSx

t_DPGC

PAGE

t_HACK

t_SACKC

ACK

(IN)

READ CYCLE

t_DRWL

t_DRDO

RD

t_HSDATI

t_SSDATI

DATA (IN)

WRITE CYCLE

t_DWRO

t_DRWL

WR

t_DATTR

t_SDDATO

DATA

(OUT)

Figure 16. Synchronous Read/Write—Bus Master

Rev. D

| Page 27 of 52 | May 2013

ADSP-21061/ADSP-21061L

Synchronous Read/Write—Bus Slave

Use these specifications for ADSP-21061 bus master accesses of

a slave’s IOP registers or internal memory (in multiprocessor

memory space). The bus master must meet these (bus slave)

timing requirements.

Table 15. Synchronous Read/Write—Bus Slave

5 V and 3.3 V

Max

Unit

Parameter

Min

Timing Requirements

t_SADRI

t_HADRI

t_SRWLI

t_HRWLI

Address, SW Setup Before CLKIN

Address, SW Hold After CLKIN

RD/WR Low Setup Before CLKIN¹

14 + DT/2

ns

5 + DT/2

8.5 + 5DT/16

RD/WR Low Hold After CLKIN

44 MHz/50 MHz²

–4 – 5DT/16

–3.5 – 5DT/16

8 + 7DT/16

t_RWHPI

RD/WR Pulse High

3

1

ns

t_SDATWH

t_HDATWH

Switching Characteristics

t_SDDATOData Delay After CLKIN

t_DATTR

t_DACKAD

t_ACKTR

Data Setup Before WR High

Data Hold After WR High

19 + 5DT/16

7 – DT/8

8

ns

Data Disable After CLKIN³

ACK Delay After Address, SW⁴

ACK Disable After CLKIN²

0 – DT/8

–1 – DT/8

6 – DT/8

¹t_SRWLI(min) = 9.5 + 5DT/16 when multiprocessor memory space wait state (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t_SRWLI(min)= 4 + DT/8.

²This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), operating at t_CK< 25 ns. For all other devices, use the

preceding timing specification of the same name.

³See Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.

⁴t_DACKADis true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup

times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of

the state of MMSWS or strobes. A slave will three-state ACK every cycle with t_ACKTR

.

Rev. D

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ADSP-21061/ADSP-21061L

CLKIN

t_SADRI

t_HADRI

ADDRESS, SW

t_ACKTR

t_DACKAD

ACK

t_SRWLI

t_HRWLI

t_RWHPI

READ ACCESS

RD

t_DATTR

t_SDDATO

DATA

(OUT)

WRITE ACCESS

t_HRWLI

t_RWHPI

t_SRWLI

WR

DATA

(IN)

t_HDATWH

t_SDATWH

Figure 17. Synchronous Read/Write—Bus Slave

Rev. D

| Page 29 of 52 | May 2013

ADSP-21061/ADSP-21061L

Multiprocessor Bus Request and Host Bus Request

Use these specifications for passing of bus mastership between

multiprocessing ADSP-21061s (BRx) or a host processor, both

synchronous and asynchronous (HBR, HBG).

Table 16. Multiprocessor Bus Request and Host Bus Request

5 V and 3.3 V

Max

Unit

Parameter

Min

Timing Requirements

t_HBGRCSV

t_SHBRI

t_HHBRI

t_SHBGI

t_HHBGI

t_SBRI

HBG Low to RD/WR/CS Valid¹

HBR Setup Before CLKIN²

HBR Hold After CLKIN²

20 + 5DT/4

ns

20 + 3DT/4

13 + DT/2

20 + 3DT/4

14 + 3DT/4

6 + DT/2

HBG Setup Before CLKIN

HBG Hold After CLKIN High

BRx, CPA Setup Before CLKIN³

BRx, CPA Hold After CLKIN High

RPBA Setup Before CLKIN

RPBA Hold After CLKIN

t_HBRI

6 + DT/2

t_SRPBAI

t_HRPBAI

Switching Characteristics

12 + 3DT/4

7 – DT/8

t_DHBGO

t_HHBGO

t_DBRO

HBG Delay After CLKIN

ns

HBG Hold After CLKIN

–2 – DT/8

BRx Delay After CLKIN

5.5 – DT/8

t_HBRO

BRx Hold After CLKIN

CPA Low Delay After CLKIN⁴

–2 – DT/8

t_DCPAO

t_TRCPA

6.5 – DT/8

4.5 – DT/8

8

CPA Disable After CLKIN

–2 – DT/8

t_DRDYCS

t_TRDYHG

t_ARDYTR

REDY (O/D) or (A/D) Low from CS and HBR Low^{5, 6}

REDY (O/D) Disable or REDY (A/D) High from HBG^{5, 7}

REDY (A/D) Disable from CS or HBR High⁵

44 + 27DT/16

10

¹For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 t_CKbefore RD or WR goes low or by t_HBGRCSVafter HBG goes low. This is

easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-21061” section in the ADSP-2106x SHARC

User’s Manual.

²Only required for recognition in the current cycle.

³CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.

⁴For the ADSP-21061L (3.3 V), this specification is 8.5 – DT/8 ns max.

⁵(O/D) = open drain, (A/D) = active drive.

⁶For the ADSP-21061L (3.3 V), this specification is 12 ns max.

⁷For the ADSP-21061L (3.3 V), this specification is 40 + 23DT/16 ns min.

Rev. D

| Page 30 of 52 | May 2013

ADSP-21061/ADSP-21061L

CLKIN

t_SHBRI

t_HHBRI

HBR

t_DHBGO

t_HHBGO

HBG (OUT)

t_DBRO

t_HBRO

BRx (OUT)

t_TRCPA

t_DCPAO

CP A (OUT, O/D)

t_SHBGI

t_HHBGI

HBG (IN)

t_SBRI

t_HBRI

BRx, CPA (IN, O/D)

t_SRPBAI

t_HRPBAI

RPBA

HBR

CS

t_TRDYHG

t_DRDYCS

REDY

(O/D)

t_ARDYTR

REDY

(A/D)

t_HBGRCSV

HBG (OUT)

RD

WR

CS

O/D = OPEN-DRAIN, A/D = ACTIVEDRIVE

Figure 18. Multiprocessor Bus Request and Host Bus Request

Rev. D

| Page 31 of 52 | May 2013

ADSP-21061/ADSP-21061L

Asynchronous Read/Write—Host to ADSP-21061

Use these specifications for asynchronous host processor

accesses of an ADSP-21061, after the host has asserted CS and

HBR (low). After HBG is returned by the ADSP-21061, the host

can drive the RD and WR pins to access the ADSP-21061’s

internal memory or IOP registers. HBR and HBG are assumed

low for this timing.

Table 17. Read Cycle

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

t_SADRDL

t_HADRDH

t_WRWH

Address Setup/CS Low Before RD Low¹

Address Hold/CS Hold Low After RD

RD/WR High Width

0

6

0

ns

t_DRDHRDY

Switching Characteristics

RD High Delay After REDY (O/D) Disable

RD High Delay After REDY (A/D) Disable

t_SDATRDY

t_DRDYRDL

t_RDYPRD

Data Valid Before REDY Disable from Low

2

ns

REDY (O/D) or (A/D) Low Delay After RD Low²

REDY (O/D) or (A/D) Low Pulsewidth for Read

Data Disable After RD High

10

8

45 + DT

2

t_HDARWH

¹Not required if RD and address are valid t_HBGRCSVafter HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 t_CLKbefore RD or WR goes

low or by t_HBGRCSVafter HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the

ADSP-21061” section in the ADSP-2106x SHARC User’s Manual.

²For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.

Table 18. Write Cycle

5 V and 3.3 V

Unit

Parameter

Timing Requirements

t_SCSWRL

Min

Max

CS Low Setup Before WR Low

CS Low Hold After WR High

Address Setup Before WR High

Address Hold After WR High

WR Low Width

0

5

2

8

6

0

ns

t_HCSWRH

t_SADWRH

t_HADWRH

t_WWRL

t_WRWH

RD/WR High Width

t_DWRHRDY

t_SDATWH

WR High Delay After REDY (O/D) or (A/D) Disable

Data Setup Before WR High

50 MHz, t_CK= 20 ns¹

3

2.5

t_HDATWH

Data Hold After WR High

1

ns

Switching Characteristics

t_DRDYWRL

t_RDYPWR

t_SRDYCK

REDY (O/D) or (A/D) Low Delay After WR/CS Low²

11

ns

REDY (O/D) or (A/D) Low Pulsewidth for Write

REDY (O/D) or (A/D) Disable to CLKIN

15

1 + 7DT/16

8 + 7DT/16 ns

¹This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t_CK< 25 ns. For all other devices, use the preceding timing specification of the same name.

²For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.

Rev. D

| Page 32 of 52 | May 2013

ADSP-21061/ADSP-21061L

CLKIN

t_SRDYCK

REDY (O/D)

REDY (A/D)

O/D = OPEN-DRAIN, A/D = ACTIVE DRIVE

Figure 19. Synchronous REDY Timing

READ CYCLE

ADDRESS/CS

t_HADRDH

t_{W RWH}

t_SADRDL

RD

t_HDARWH

DATA (OUT)

t_{S DATR D Y}

t_RDYPRD

t_DRDHRDY

t_DRDYRDL

REDY (O/D)

REDY (A/D)

WRITE CYCLE

ADDRESS

t_HADWRH

t_{SADW RH}

t_{SCS WRL}

t_{HCSW RH}

CS

t_{WW RL}

t_{W RW H}

WR

t_HDATWH

t_SDATWH

DATA (IN)

t_{DRDY WRL}

t_{RDY PW R}

t_DWRHRDY

RE DY (O/D)

REDY (A/D)

O/D = OPEN-DRAIN, A/D = ACTIVE DRIVE

Figure 20. Asynchronous Read/Write—Host to ADSP-21061

Rev. D

| Page 33 of 52 | May 2013

ADSP-21061/ADSP-21061L

Three-State Timing—Bus Master, Bus Slave, HBR, SBTS

These specifications show how the memory interface is disabled

(stops driving) or enabled (resumes driving) relative to CLKIN

and the SBTS pin. This timing is applicable to bus master transi-

tion cycles (BTC) and host transition cycles (HTC) as well as the

SBTS pin.

Table 19. Three-State Timing—Bus Master, Bus Slave

5 V and 3.3 V

Max

Unit

Parameter

Min

Timing Requirements

t_STSCK

t_HTSCK

SBTS Setup Before CLKIN

SBTS Hold Before CLKIN

12 + DT/2

ns

6 + DT/2

Switching Characteristics

t_MIENAAddress/Select Enable After CLKIN

t_MIENS

t_MIENHG

t_MITRA

–1 – DT/8

ns

Strobes Enable After CLKIN¹

HBG Enable After CLKIN

–1.5 – DT/8

Address/Select Disable After CLKIN

Strobes Disable After CLKIN¹

HBG Disable After CLKIN

0 – DT/4

t_MITRS

1.5 – DT/4

2.0 – DT/4

t_MITRHG

t_DATEN

t_DATTR

t_ACKEN

t_ACKTR

t_ADCEN

t_ADCTR

t_MTRHBG

t_MENHBG

Data Enable After CLKIN²

Data Disable After CLKIN²

ACK Enable After CLKIN²

ACK Disable After CLKIN²

9 + 5DT/16

0 – DT/8

7 – DT/8

6 – DT/8

8 – DT/4

7.5 + DT/4

–1 – DT/8

–2 – DT/8

ADRCLK Enable After CLKIN

ADRCLK Disable After CLKIN

Memory Interface Disable Before HBG Low³

Memory Interface Enable After HBG High³

0 + DT/8

19 + DT

¹Strobes = RD, WR, PAGE, DMAGx, MSx, BMS, SW.

²In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

³Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode).

CLKIN

t_STSCK

t_HTSCK

SBTS

t_MIENA,t_MIENS,t_MIENHG

t_MITRA,t_MITRS,t_MITRHG

MEMORY

INTERFACE

t_DATTR

t_DATEN

DATA

t_ACKTR

t_ACKEN

ACK

t_ADCEN

t_ADCTR

CLKOUT

Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion)

Rev. D

| Page 34 of 52 | May 2013

ADSP-21061/ADSP-21061L

HBG

t_MTRHBG

t_MENHBG

MEMORY

INTERFACE

MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)

Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion)

Rev. D

| Page 35 of 52 | May 2013

ADSP-21061/ADSP-21061L

ACK, and DMAGx signals. For Paced Master mode, the data

transfer is controlled by ADDR31–0, RD, WR, MS3–0, and

ACK (not DMAG). For Paced Master mode, the Memory Read-

Bus Master, Memory Write-Bus Master, and Synchronous

Read/Write-Bus Master timing specifications for ADDR31–0,

RD, WR, MS3–0, SW, PAGE, DATA47–0, and ACK also apply.

DMA Handshake

These specifications describe the three DMA handshake modes.

In all three modes, DMARx is used to initiate transfers. For

Handshake mode, DMAGx controls the latching or enabling of

data externally. For External Handshake mode, the data transfer

is controlled by the ADDR31–0, RD, WR, SW, PAGE, MS3–0,

Table 20. DMA Handshake

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

t_SDRLC

DMARx Low Setup Before CLKIN¹

DMARx High Setup Before CLKIN¹

DMARx Width Low (Nonsynchronous)

Data Setup After DMAGx Low²

Data Hold After DMAGx High

Data Valid After DMARx High²

DMARx Low Edge to Low Edge³

DMARx Width High

5

6

ns

t_SDRHC

t_WDR

t_SDATDGL

t_HDATIDG

t_DATDRH

t_DMARLL

t_DMARH

10 + 5DT/8

16 + 7DT/8

2

23 + 7DT/8

6

Switching Characteristics

t_DDGL

t_WDGH

t_WDGL

t_HDGC

DMAGx Low Delay After CLKIN

9 + DT/4

6 + 3DT/8

12 + 5DT/8

–2 – DT/8

8 + 9DT/16

0

15 + DT/4

6 – DT/8

ns

DMAGx High Width

DMAGx Low Width

DMAGx High Delay After CLKIN

t_VDATDGHData Valid Before DMAGx High⁴

t_DATRDGH

t_DGWRL

t_DGWRH

t_DGWRR

t_DGRDL

t_DRDGH

t_DGRDR

t_DGWR

Data Disable After DMAGx High⁵

7

2

WR Low Before DMAGx Low

0

DMAGx Low Before WR High

10 + 5DT/8 +W

1 + DT/16

0

WR High Before DMAGx High

RD Low Before DMAGx Low

3 + DT/16

2

RD Low Before DMAGx High

11 + 9DT/16 + W

0

RD High Before DMAGx High

DMAGx High to WR, RD, DMAGx Low

Address/Select Valid to DMAGx High

Address/Select Hold after DMAGx High⁶

3

5 + 3DT/8 + HI

17 + DT

–0.5

t_DADGH

t_DDGHA

W = (number of wait states specified in WAIT register)

؋

t_CK

.

HI = t_CK(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

¹Only required for recognition in the current cycle.

²t_SDATDGLis the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can

be driven t_DATDRHafter DMARx is brought high.

³For the ADSP-21061L (3.3 V), this specification is 23.5 + 7DT/8 ns min.

⁴t_VDATDGHis valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t_VDATDGH= t_CK– .25t_CCLK– 8 + (n × t_CK) where n equals

the number of extra cycles that the access is prolonged.

⁵See Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.

⁶For the ADSP-21061L (3.3 V), this specification is –1.0 ns min.

Rev. D

| Page 36 of 52 | May 2013

ADSP-21061/ADSP-21061L

CLKIN

t_SDRLC

t_DMARLL

t_SDRHC

t_WDR

t_DMARH

DMARx

DMAGx

t_HDGC

t_DDGL

t_WDGL

t_WDGH

TRANSFERS BETWEEN ADSP-2106x

INTERNAL MEMORY AND EXTERNAL DEVICE

t_DATRDGH

t_VDATDGH

DATA

(FROM ADSP-2106x TO EXTERNAL DEVICE)

t_DATDRH

t_SDATDGL

t_HDATIDG

(FROM EXTERNAL DEVICE TO ADSP-2106x)

TRANSFERS BETWEEN EXTERNAL DEVICE AND

EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

t_DGWRL

t_DGWRR

t_DGWRH

WR

(EXTERNAL DEVICE TO EXTERNAL MEMORY)

t_DGRDR

t_DGRDL

RD

(EXTERNAL MEMORY TO EXTERNAL DEVICE)

t_DRDGH

t_DADGH

t_DDGHA

ADDR

MSx, SW

*MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER

TIMING SPECIFICATIONS FOR ADDR31–0, RD, WR, SW MS3–0, AND ACK ALSO APPLY HERE.

Figure 23. DMA Handshake

Rev. D

| Page 37 of 52 | May 2013

ADSP-21061/ADSP-21061L

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 21. Serial Ports—External Clock

5 V and 3.3 V

Max

Parameter

Unit

Min

Timing Requirements

t_SFSE

TFS/RFS Setup Before TCLK/RCLK¹

TFS/RFS Hold After TCLK/RCLK^{1, 2}

Receive Data Setup Before RCLK¹

Receive Data Hold After RCLK¹

TCLK/RCLK Width

3.5

4

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

1.5

4

9

TCLK/RCLK Period

t_CK

¹Referenced to sample edge.

²RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.

Table 22. Serial Ports—Internal Clock

5 V and 3.3 V

Parameter

Unit

Min

Max

Timing Requirements

t_SFSI

t_HFSI

t_SDRI

t_HDRI

TFS Setup Before TCLK¹; RFS Setup Before RCLK¹

TFS/RFS Hold After TCLK/RCLK^{1, 2}

Receive Data Setup Before RCLK¹

Receive Data Hold After RCLK¹

8

1

3

ns

¹Referenced to sample edge.

²RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.

Table 23. Serial Ports—External or Internal Clock

5 V and 3.3 V

Parameter

Unit

Min

Max

Switching Characteristics

t_DFSE

RFS Delay After RCLK (Internally Generated RFS)¹

RFS Hold After RCLK (Internally Generated RFS)¹

13

ns

t_HOFSE

3

¹Referenced to drive edge.

Table 24. Serial Ports—External Clock

5 V and 3.3 V

Max

Parameter

Unit

Min

Switching Characteristics

t_DFSE

TFS Delay After TCLK (Internally Generated TFS)¹

TFS Hold After TCLK (Internally Generated TFS)¹

Transmit Data Delay After TCLK¹

13

16

ns

t_HOFSE

3

5

t_DDTE

t_HODTE

Transmit Data Hold After TCLK¹

¹Referenced to drive edge.

Rev. D

| Page 38 of 52 | May 2013

ADSP-21061/ADSP-21061L

Table 25. Serial Ports—Internal Clock

5 V and 3.3 V

Parameter

Unit

Min

Max

Switching Characteristics

t_DFSI

TFS Delay After TCLK (Internally Generated TFS)¹

4.5

ns

t_HOFSI

TFS Hold After TCLK (Internally Generated TFS)¹

Transmit Data Delay After TCLK¹

Transmit Data Hold After TCLK¹

TCLK/RCLK Width

–1.5

t_DDTI

7.5

t_HDTI

0

t_SCLKIW

t_SCLK/2 –1.5

t_SCLK/2+1.5

¹Referenced to drive edge.

Table 26. Serial Ports—Enable and Three-State

5 V and 3.3 V

Parameter

Unit

Min

4.5

0

Max

Switching Characteristics

t_DDTEN

Data Enable from External TCLK^{1, 2}

Data Disable from External TCLK¹

Data Enable from Internal TCLK¹

Data Disable from Internal TCLK¹

TCLK/RCLK Delay from CLKIN

SPORT Disable After CLKIN

ns

t_DDTTE

10.5

t_DDTIN

t_DDTTI

3

t_DCLK

22 + 3DT/8

17

t_DPTR

¹Referenced to drive edge.

²For the ADSP-21061L (3.3 V), this specification is 3.5 ns min.

Table 27. Serial Ports—External Late Frame Sync

5 V and 3.3 V

Parameter

Unit

Min

Max

Switching Characteristics

t_DDTLFSE

t_DDTENFS

Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0¹

Data Enable from Late FS or MCE = 1, MFD = 0¹

12

ns

3.5

¹MCE = 1, TFS enable and TFS valid follow t_DDTLFSEand t_DDTENFS

.

Rev. D

| Page 39 of 52 | May 2013

ADSP-21061/ADSP-21061L

DATA RECEIVE— INTERNAL CLOCK

DATA RECEIVE— EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKW

t_SCLKIW

RCLK

t_DFSE

t_HOFSE

t_HFSE

t_SFSI

t_HFSI

t_SFSE

t_HOFSE

RFS

t_SDRI

t_SDRE

t_HDRI

t_HDRE

DR

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT— INTERNAL CLOCK

DATA TRANSMIT— EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKW

TCLK

t_DFSE

t_DFSI

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

TFS

t_DDTI

t_DDTE

t_HDTE

t_HDTI

DT

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE DRIVE EDGE

TCLK/RCLK

TCLK

(EXT)

t_DDTTE

t_DDTEN

DT

DRIVE

EDGE

DRIVE

EDGE

TCLK/RCLK

TCLK

(INT)

t_DDTIN

t_DDTTI

DT

CLKIN

t_HTFSCK

t_DPTR

SPORT ENABLE AND

THREE-STATE

LATENCY

TCLK, RCLK

t_STFSCK

SPORT DISABLE DELAY

FROM INSTRUCTION

TFS (EXT)

TFS, RFS, DT

IS TWO CYCLES

t_DCLK

TCLK (INT)

RCLK (INT)

NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH

EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O

FOR MESH MULTIPROCESSING.

LOW TO HIGH ONLY

Figure 24. Serial Ports

Rev. D

| Page 40 of 52 | May 2013

ADSP-21061/ADSP-21061L

EXTERNAL RFS WITH MCE = 1, MFD = 0

SAMPLE DRIVE

DRIVE

RCLK

RFS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_HDTE/I

t_DDTENFS

DT

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TFS

DRIVE

SAMPLE

DRIVE

TCLK

t_HOFSE/I

t_SFSE/I

TFS

t_DDTE/I

t_DDTENFS

t_HDTE/I

DT

1ST BIT

2ND BIT

t_DDTLFSE

Figure 25. Serial Ports—External Late Frame Sync

Rev. D

| Page 41 of 52 | May 2013

ADSP-21061/ADSP-21061L

JTAG Test Access Port and Emulation

For JTAG Test Access Port and Emulation, see Table 28 and

Figure 26.

Table 28. JTAG Test Access Port and Emulation

5 V and 3.3 V

Max

Parameter

Unit

Min

Timing Requirements

t_TCK

TCK Period

t_CK

6

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low¹

TRST Pulse Width

7

18

4t_CK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low²

13

ns

18.5

¹System Inputs = DATA47–0, ADDR31–0, RD, WR, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, CPA, DR0, DR1, TCLK0,

TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, EBOOT, LBOOT, BMS, CLKIN, RESET.

²System Outputs = DATA47–0, ADDR31–0, MS3–0, RD, WR, SW, ACK, ADRCLK, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, CPA, FLAG3–0, TIMEXP, DT0, DT1,

TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 26. JTAG Test Access Port and Emulation

Rev. D

| Page 42 of 52 | May 2013

ADSP-21061/ADSP-21061L

TEST CONDITIONS

I_OL

Output Disable Time

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by V is dependent on the capacitive load, C_L, and the

load current, I_L. This decay time can be approximated by the

following equation:

TO

OUTPUT

1.5V

50pF

C V

I_L

L

--------------

P_EXT

=

I_OH

The output disable time t_DISis the difference between

_MEASUREDand t_DECAYas shown in Figure 27. The time t_MEASUREDis

Figure 28. Equivalent Device Loading for AC Measurements (Includes All

Fixtures)

t

the interval from when the reference signal switches to when the

output voltage decays V from the measured output high or

output low voltage. t_DECAYis calculated with test loads C_Land I_L,

and with V equal to 0.5 V.

INPUT

OR

OUTPUT

1.5V

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start driv-

ing. The output enable time t_ENAis the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram (Figure 27). If multiple

pins (such as the data bus) are enabled, the measurement value

is that of the first pin to start driving.

Figure 29. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

Output Drive Characteristics

Figure 30 through Figure 37 show typical characteristics for the

output drivers of the ADSP-21061 (5 V) and ADSP-21061L

(3 V). The curves represent the current drive capability and

switching behavior of the output drivers as a function of

resistive and capacitive loading.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose V

to be the difference between the ADSP-21061’s output voltage

and the input threshold for the device requiring the hold time. A

typical V will be 0.4 V. C_Lis the total bus capacitance (per data

line), and I_Lis the total leakage or three-state current (per data

line). The hold time will be t_DECAYplus the minimum disable

time (i.e., t_DATRWHfor the write cycle).

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

50 pF on all pins (see Figure 28). The delay and hold specifica-

tions given should be derated by a factor of 1.5 ns/50 pF for

loads other than the nominal value of 50 pF. Figure 31,

Figure 32, Figure 35, and Figure 36 show how output rise time

varies with capacitance. Figure 33 and Figure 37 show graphi-

cally how output delays and holds vary with load capacitance.

(Note that this graph or derating does not apply to output dis-

able delays; see the previous section Output Disable Time under

Test Conditions.) The graphs of Figure 31, Figure 32, Figure 35,

and Figure 36 may not be linear outside the ranges shown.

REFERENCE

SIGNAL

t_MEASURED

t_ENA

t_DIS

V_{OH (MEASURED)}

V

_{OH (MEASURED)}- ⌬V

2.0V

1.0V

V_{OL (MEASURED)}+ ⌬V

V_{OL (MEASURED)}

t_DECAY

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE

THIS VOLTAGE TO BE

APPROXIMATELY 1.5V.

Figure 27. Output Enable/Disable

Rev. D

| Page 43 of 52 | May 2013

ADSP-21061/ADSP-21061L

Output Characteristics (5 V)

3.5

3.0

2.5

2.0

1.5

75

50

25

RISE TIME

Y = 0.009x + 1.1

5.25V, -40°C

5.0V, +25°C

0

4.75V, +100°C

-

25

FALL TIME

1.0

4.75V,+ 100°C

50

75

Y = 0.005x + 0.6

5.0V, +25°C

0.5

0

5.25V, -40°C

-

100

0

20

40

60

80

100 120 140 160 180 200

LOAD CAPACITANCE (pF)

125

150

Figure 32. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance

(V_DD= 5 V)

0

0.75

1.50

2.25

3.00

3.75

4.50

5.25

SOURCE VOLTAGE (V)

Figure 30. Typical Output Drive Currents (V_DD= 5 V)

5

4

3

16.0

14.0

12.0

10.0

8.0

Y = 0.03X

- 1.45

2

1

RISE TIME

Y = 0.005x + 3.7

FALL TIME

6.0

NOMINAL

4.0

-

1

25

50

75

100

125

150

175

200

2.0

0

Y = 0.0031x + 1.1

LOAD CAPACITANCE (pF)

0

20

40

60

80

100 120 140 160 180 200

Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Maximum

Case Temperature) (V_DD= 5 V)

LOAD CAPACITANCE (pF)

Figure 31. Typical Output Rise Time (10% to 90% V_DD) vs. Load Capacitance

(V_DD= 5 V)

Rev. D

| Page 44 of 52 | May 2013

ADSP-21061/ADSP-21061L

Input/Output Characteristics (3.3 V)

9

8

7

6

120

100

3.3V, +25°C

80

60

40

Y = 0.0391x + 0.36

3.6V, -40°C

5

4

3.0V, +85°C

V_OH

20

0

RISE TIME

Y = 0.0305x + 0.24

3

2

1

0

3.0V, +85°C

-

20

40

60

3.3V, +25°C

FALL TIME

-

3.6V, -40°C

-

80

V_OL

-

100

120

0

20

40

60

80 100 120 140 160 180 200

-

LOAD CAPACITANCE (pF)

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 36. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance

(V_DD= 3.3 V)

Figure 34. Typical Drive Currents (V_DD= 3.3 V)

5

18

4

3

2

1

Y = 0.0329x - 1.65

16

14

12

10

8

Y = 0.0796x + 1.17

RISETIME

6

4

2

0

Y = 0.0467x + 0.55

FALL TIME

NOMINAL

-1

25

50

75

100

125

150

175

200

LOAD CAPACITANCE (pF)

0

20

40

60

80 100 120 140 160 180 200

LOAD CAPACITANCE (pF)

Figure 37. Typical Output Delay or Hold vs. Load Capacitance (at Maximum

Case Temperature) (V_DD= 3.3 V)

Figure 35. Typical Output Rise Time (10% to 90% V_DD) vs. Load Capacitance

(V_DD= 3.3 V)

Rev. D

| Page 45 of 52 | May 2013

ADSP-21061/ADSP-21061L

ENVIRONMENTAL CONDITIONS

Thermal Characteristics

The ADSP-21061 is available in 240-lead thermally enhanced

MQFP package. The top surface of the thermally enhanced

MQFP contains a metal slug from which most of the die heat is

dissipated. The slug is flush with the top surface of the package.

Note that the metal slug is internally connected to GND

through the device substrate.

The ADSP-21061L is available in 240-lead MQFP and 225-ball

plastic BGA packages.

All packages are specified for a case temperature (T_CASE). To

ensure that the T_CASEis not exceeded, a heatsink and/or an air-

flow source may be used. A heat sink should be attached with a

thermal adhesive.

T_CASE= T_AMB+ (PD _CA)

T_CASE= Case temperature (measured on top surface of package)

T_AMB= Ambient temperature C

PD =Power dissipation in W (this value depends upon the spe-

cific application; a method for calculating PD is shown under

Power Dissipation).

_CA=Value from tables below.

Table 29. ADSP-21061 (5 V Thermally Enhanced ED/MQFP

Package)

Parameter Condition (Linear Ft./Min.) Typical Unit

_CA

Airflow = 0

10

9

8

7

6

°C/W

Airflow = 100

Airflow = 200

Airflow = 400

Airflow = 600

Table 30. ADSP-21061L (3.3 V MQFP Package)

Parameter Condition (Linear Ft./Min.) Typical Unit

_CA

Airflow = 0

19.6

17.6

15.6

13.9

12.2

°C/W

Airflow = 100

Airflow = 200

Airflow = 400

Airflow = 600

Table 31. ADSP-21061L (3.3 V PBGA Package)

Parameter Condition (Linear Ft./Min.) Typical Unit

_CA

Airflow = 0

Airflow = 200

Airflow = 400

19.0

13.6

11.2

°C/W

Rev. D

| Page 46 of 52 | May 2013

ADSP-21061/ADSP-21061L

225-BALL PBGA PIN CONFIGURATIONS

Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments

Name

PBGA

Pin Number Name

A01 ADDR25 D01

ADDR26 D02

MS2 D03

ADDR29 D04

PBGA

Pin Number Name

ADDR14 G01

ADDR15 G02

PBGA

Pin Number Name

PBGA

Pin Number Name

PBGA

Pin Number

BMS

ADDR6

ADDR5

ADDR3

ADDR0

ICSA

K01

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

K12

K13

K14

K15

L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

L12

L13

L14

L15

M01

M02

M03

M04

EMU

TDO

IRQ0

IRQ1

ID2

NC

N01

N02

N03

N04

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

N15

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

P15

R01

R02

R03

R04

R05

R06

R07

R08

R09

R10

R11

R12

ADDR30 A02

DMAR2

DT1

A03

A04

A05

A06

A07

ADDR16 G03

ADDR19 G04

RCLK1

TCLK0

RCLK0

DMAR1

TFS1

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

GND

G05

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

V_DD

GND

CPA

V_DD

NC

ADRCLK A08

HBG

V_DD

NC

CS

A09

A10

A11

A12

A13

A14

A15

B01

B02

DMAG2

BR5

V_DD

NC

CLKIN

PAGE

BR3

V_DD

GND

NC

BR1

GND

NC

DATA40

DATA37

DATA35

DATA34

DATA22

DATA25

DATA24

DATA23

DATA8

DATA11

DATA13

DATA14

ADDR2

ADDR1

FLAG0

FLAG3

RPBA

NC

DATA47

DATA44

DATA42

MS0

NC

DATA1

DATA3

TRST

TMS

EBOOT

ID0

NC

ADDR21 E01

ADDR22 E02

ADDR24 E03

ADDR27 E04

ADDR12 H01

ADDR11 H02

ADDR13 H03

ADDR10 H04

SW

ADDR31 B03

HBR

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

C01

C02

DR1

GND

E05

E06

E07

E08

E09

E10

E11

E12

E13

E14

E15

GND

H05

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

J01

J02

J03

J04

J05

J06

J07

J08

J09

J10

J11

J12

DT0

GND

V_DD

GND

NC

DR0

GND

V_DD

GND

NC

REDY

RD

GND

V_DD

GND

NC

GND

V_DD

GND

NC

ACK

GND

V_DD

GND

NC

BR6

NC

GND

NC

BR2

DATA33

DATA30

DATA32

DATA31

DATA18

DATA19

DATA21

DATA20

ADDR9

ADDR8

ADDR7

ADDR4

GND

DATA4

DATA7

DATA9

DATA10

FLAG1

FLAG2

TIMEXP

TDI

NC

DATA45

DATA43

DATA39

MS3

NC

DATA0

TCK

IRQ2

RESET

ID1

NC

ADDR17 F01

ADDR18 F02

ADDR20 F03

ADDR23 F04

MS1

ADDR28 C03

SBTS

C04

C05

C06

C07

C08

C09

C10

C11

C12

TCLK1

RFS1

TFS0

GND

V_DD

F05

F06

F07

F08

F09

F10

F11

F12

LBOOT (GND) M05

V_DD

NC

M06

M07

M08

M09

M10

M11

M12

NC

V_DD

NC

RFS0

WR

V_DD

NC

V_DD

NC

DMAG1

BR4

GND

DATA29

V_DD

NC

GND

NC

DATA46

DATA12

NC

Rev. D

|

Page 47 of 52

|

May 2013

ADSP-21061/ADSP-21061L

Table 32. ADSP-21061L 225-Lead Metric PBGA (B-225-2) Pin Assignments (Continued)

PBGA

Name

Pin Number Name

Pin Number

DATA41

DATA38

DATA36

C13

C14

C15

DATA26

DATA28

DATA27

F13

F14

F15

DATA15

DATA16

DATA17

J13

J14

J15

DATA2

DATA5

DATA6

M13

M14

M15

NC

R13

R14

R15

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BR3

CS

DMAR2

BMS

A

B

C

DATA42 DATA44 DATA47

PAGE

CLKIN

ADRCLK RCLK0

TCLK0

RCLK1

DT1

ADDR30

BR2

BR6

RD

WR

HBR

SBTS

SW

MS0

MS3

DATA39 DATA43 DATA45

ACK

DMAG1

BR5

REDY

DR0

DT0

RFS1

TFS1

GND

DR1

ADDR31

BR4

BR1

NC

MS1

DATA36 DATA38 DATA41 DATA46

DATA34 DATA35 DATA37 DATA40

DATA31 DATA32 DATA30 DATA33

RFS0

TFS0

TCLK1

ADDR28

DMAG2

GND

HBG

CPA

DMAR1

MS2

ADDR29

ADDR26 ADDR25

D

E

F

GND

ADDR27 ADDR24 ADDR22 ADDR21

DATA27 DATA28 DATA26 DATA29

DATA23 DATA24 DATA25 DATA22

GND

V

GND

ADDR23 ADDR20 ADDR18 ADDR17

ADDR19 ADDR16 ADDR15 ADDR14

DD

V

G

H

J

DD

DATA20 DATA21 DATA19 DATA18

DATA17 DATA16 DATA15 DATA12

GND

V

GND

ADDR10 ADDR13 ADDR11 ADDR12

DD

GND

NC

V

GND

ICSA

RPBA

ADDR4

ADDR0

FLAG3

ADDR7

ADDR3

FLAG0

ADDR8

ADDR5

ADDR1

ADDR9

ADDR6

ADDR2

DD

DATA14 DATA13 DATA11

DATA8

DATA4

GND

V

GND

K

L

DD

DATA10

DATA6

DATA9

DATA5

DATA7

DATA2

GND

NC

GND

NC

GND

NC

LBOOT

(GND)

NC

TDI

IRQ1

ID0

TIMEXP

FLAG2

FLAG1

EMU

M

N

P

R

IRQ0

DATA3

DATA0

NC

DATA1

NC

ID2

NC

TDO

TMS

IRQ2

TRST

TCK

EBOOT

RESET

NC

ID1

NC = NO CONNECT

Figure 38. BGA Pin Assignments (Top View, Summary)

Rev. D

| Page 48 of 52 | May 2013

ADSP-21061/ADSP-21061L

240-LEAD MQFP PIN CONFIGURATIONS

Table 33. ADSP-21061 MQFP/ED (SP-240); ADSP-21061L MQFP (S-240) Pin Assignments

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

Pin No.

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

TDI

1

ADDR20

ADDR21

GND

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

TCLK0

TFS0

DR0

81

DATA41

DATA40

DATA39

V_DD

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

DATA14

DATA13

DATA12

GND

DATA11

DATA10

DATA9

V_DD

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

NC

V_DD

NC

GND

NC

V_DD

GND

V_DD

NC

GND

ID2

ID1

ID0

TRST

2

82

V_DD

3

83

TDO

4

ADDR22

ADDR23

ADDR24

V_DD

RCLK0

RFS0

V_DD

84

TIMEXP

EMU

5

85

DATA38

DATA37

DATA36

GND

6

86

ICSA

7

V_DD

87

FLAG3

FLAG2

FLAG1

FLAG0

GND

8

GND

ADRCLK

REDY

HBG

88

9

V_DD

89

NC

DATA8

DATA7

DATA6

GND

DATA5

DATA4

DATA3

V_DD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

ADDR25

ADDR26

ADDR27

GND

90

DATA35

DATA34

DATA33

V_DD

91

CS

92

ADDR0

ADDR1

V_DD

RD

93

MS3

WR

94

V_DD

MS2

GND

V_DD

95

GND

ADDR2

ADDR3

ADDR4

GND

MS1

96

DATA32

DATA31

DATA30

GND

MS0

GND

CLKIN

ACK

97

DATA2

DATA1

DATA0

GND

NC

SW

98

BMS

99

ADDR5

ADDR6

ADDR7

V_DD

ADDR28

GND

DMAG2

DMAG1

PAGE

V_DD

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

DATA29

DATA28

DATA27

V_DD

NC

ADDR8

ADDR9

ADDR10

GND

ADDR29

ADDR30

ADDR31

GND

BR6

V_DD

NC

BR5

DATA26

DATA25

DATA24

GND

NC

BR4

NC

BR3

NC

ADDR11

ADDR12

ADDR13

V_DD

SBTS

BR2

V_DD

DMAR2

DMAR1

HBR

BR1

DATA23

DATA22

DATA21

V_DD

NC

GND

V_DD

NC

ADDR14

ADDR15

GND

DT1

GND

DATA47

DATA46

DATA45

V_DD

NC

LBOOT (GND) 232

TCLK1

TFS1

DATA20

DATA19

DATA18

GND

NC

RPBA

RESET

EBOOT

IRQ2

IRQ1

IRQ0

TCK

233

234

235

236

237

238

239

240

NC

ADDR16

ADDR17

ADDR18

V_DD

DR1

GND

V_DD

RCLK1

RFS1

DATA44

DATA43

DATA42

GND

DATA17

DATA16

DATA15

V_DD

GND

NC

V_DD

CPA

NC

ADDR19

DT0

NC

TMS

Rev. D

| Page 49 of 52 | May 2013

ADSP-21061/ADSP-21061L

OUTLINE DIMENSIONS

34.60 BSC

SQ

29.50 REF

SQ

4.10

3.78

3.55

0.66

0.56

0.46

181

180

240

1

SEATING

PLANE

PIN 1

24.00 REF

SQ

HEAT SLUG

TOP VIEW

(PINS DOWN)

32.00 BSC

SQ

121

120

60

3.50

3.40

3.30

61

3.92 × 45°

0.20

0.09

(4 PLACES)

VIEW A

0.27 MAX

0.17 MIN

0.50

BSC

0.38

0.25

COPLANARITY

7°

0°

LEAD PITCH

0.076

VIEW A

ROTATED 90° CCW

Figure 39. 240-Lead Metric Quad Flat Package, Thermally Enhanced [MQFP/ED] (SP-240-2)

Rev. D

| Page 50 of 52 | May 2013

ADSP-21061/ADSP-21061L

34.85

34.60 SQ

34.35

4.10

MAX

32.00 BSC

SQ

0.75

0.60

0.45

240

181

180

1

SEATING

PLANE

PIN 1

0.50

BSC

29.50

REF

SQ

0.27

0.17

60

121

120

0.08 MAX

COPLANARITY

61

0.50

0.25

3.50

3.40

3.20

Figure 40. 240-Lead Metric Quad Flat Package, [MQFP] (S-240)

23.20

23.00 SQ

22.80

A1 CORNER

INDEX AREA

15 13 11

14 12 10

9

7

5

3

1

8

6

4

2

A

B

C

D

E

F

BALL A1

INDICATOR

18.00

20.10

20.00 SQ

19.90

BSC SQ

G

H

J

TOP VIEW

DETAIL A

K

L

1.27

BSC

M

N

P

R

0.50 R

BOTTOM VIEW

3 PLACES

2.70 MAX

1.30

1.20

1.10

DETAIL A

0.70

0.60

0.50

0.15 MAX

COPLANARITY

SEATING

PLANE

0.90

0.75

0.60

BALL DIAMETER

Figure 41. 225-Ball Plastic Ball Grid Array [PBGA] (B-225-2)

Rev. D

| Page 51 of 52 | May 2013

ADSP-21061/ADSP-21061L

SURFACE-MOUNT DESIGN

Table 34 is provided as an aide to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements

for Surface-Mount Design and Land Pattern Standard.

Table 34. BGA Data for Use with Surface-Mount Design

Package

Ball Attach Type

Solder Mask Opening

Ball Pad Size

225-Ball Grid Array (PBGA)

Solder Mask Defined

0.63 mm diameter

0.73 mm diameter

ORDERING GUIDE

Temperature

Range

Instruction On-Chip Operating

Package

Option

Model

Notes

Rate

SRAM

1M Bit

Voltage

Package Description

ADSP-21061KS-133

ADSP-21061KSZ-133

ADSP-21061KS-160

ADSP-21061KSZ-160

ADSP-21061KS-200

ADSP-21061KSZ-200

ADSP-21061LKB-160

ADSP-21061LKBZ-160

ADSP-21061LKSZ-160

ADSP-21061LASZ-176

ADSP-21061LKSZ-176

¹Z = RoHS Compliant Part.

0C to 85C

33 MHz

40 MHz

50 MHz

40 MHz

5 V

240-Lead MQFP_ED

225-Ball PBGA

SP-240-2

B-225-2

S-240

1

5 V

1

5 V

3.3 V

1

225-Ball PBGA

240-Lead MQFP

–40C to +85C 44 MHz

0C to 85C 44 MHz

240-Lead MQFP

S-240

240-Lead MQFP

S-240

registered trademarks are the property of their respective owners.

D00170-0-5/13(D)

Rev. D

| Page 52 of 52 | May 2013


型号：	ADSP-21061LKBZ-160
厂家：	ADI
描述：	Commercial Grade SHARC DSP Microcomputer 商业级SHARC DSP单片机微控制器和处理器外围集成电路数字信号处理器时钟
文件：	总52页 (文件大小：870K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21061LKBZ-160 [ADI]

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