ADSP-21160M_技术文档

®

SHARC

a

DSP Microcomputer

ADSP-21160M

SUMMARY

KEY FEATURES

High-Performance 32-Bit DSP—Applications in Audio,

Medical, Military, Graphics, Imaging, and

Communication

Super Harvard Architecture—Four Independent Buses

for Dual Data Fetch, Instruction Fetch, and

Nonintrusive, Zero-Overhead I/O

Backwards-Compatible—Assembly Source Level

Compatible with Code for ADSP-2106x DSPs

Single-Instruction-Multiple-Data (SIMD) Computational

Architecture—Two 32-Bit IEEE Floating-Point

Computation Units, Each with a Multiplier, ALU,

Shifter, and Register File

80 MHz (12.5 ns) Core Instruction Rate

Single-Cycle Instruction Execution, Including SIMD

Operations in Both Computational Units

480 MFLOPS Peak and 320 MFLOPS Sustained

Performance (Based on FIR)

Dual Data Address Generators (DAGs) with Modulo and

Bit-Reverse Addressing

Zero-Overhead Looping and Single-Cycle Loop Setup,

Providing Efficient Program Sequencing

IEEE 1149.1 JTAG Standard Test Access Port and

On-Chip Emulation

400-Ball 27

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27 mm Metric PBGA Package

Integrated Peripherals—Integrated I/O Processor,

4M Bit On-Chip Dual-Ported SRAM, Glueless

Multiprocessing Features, and Ports (Serial, Link,

External Bus, and JTAG)

FUNCTIONAL BLOCK DIAGRAM

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SHARC is a registered trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:781/329-4700

Fax:781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-21160M

FEATURES (CONTINUED)

GENERAL DESCRIPTION

The ADSP-21160M SHARC DSP is the first processor in

a new family featuring Analog Devices’ Super Harvard

Architecture. Easing portability, the ADSP-21160M is

application source code compatible with first generation

ADSP-2106x SHARC DSPs in SISD (Single Instruction,

Single Data) mode. To take advantage of the processor’s

SIMD(Single Instruction, Multiple Data) capability, some

code changes are needed. Like other SHARCs, the

ADSP-21160M is a 32-bit processor that is optimized for

high performance DSP applications. The ADSP-21160M

includes an80 MHz core, a dual-portedon-chipSRAM, an

integratedI/Oprocessor withmultiprocessing support, and

multiple internal buses to eliminate I/O bottlenecks.

Single Instruction Multiple Data (SIMD)

Architecture Provides:

Two Computational Processing Elements

Concurrent Execution—Each Processing Element

Executes the Same Instruction, but Operates on

Different Data

Code Compatibility—at Assembly Level, Uses the

Same Instruction Set as the ADSP-2106x

SHARC DSPs

Parallelism in Buses and Computational Units Allows:

Single-cycle Execution (with or without SIMD) of: A

Multiply Operation, An ALU Operation, A Dual

Memory Read or Write, and An Instruction Fetch

Transfers Between Memory and Core at up to Four

32-Bit Floating- or Fixed-Point Words per Cycle

Accelerated FFT Butterfly Computation Through a

Multiply with Add and Subtract

4M Bit On-Chip Dual-Ported SRAM for Independent

Access by Core Processor, Host, and DMA

DMA Controller supports:

14 Zero-Overhead DMA Channels for Transfers Between

ADSP-21160M Internal Memory and External

Memory, External Peripherals, Host Processor, Serial

Ports, or Link Ports

The ADSP-21160M introduces Single-Instruction,

Multiple-Data (SIMD) processing. Using two computa-

tional units (ADSP-2106x SHARC DSPs have one), the

ADSP-21160M can double performance versus the

ADSP-2106x on a range of DSP algorithms.

Fabricated in a state of the art, high speed, low power

CMOS process, the ADSP-21160M has a 12.5 ns instruc-

tion cycle time. With its SIMD computational hardware

running at 80 MHz, the ADSP-21160M can perform 480

million math operations per second.

64-Bit Background DMA Transfers at Core Clock Speed,

in Parallel with Full-Speed Processor Execution

560M Bytes/s Transfer Rate Over IOP Bus

Host Processor Interface to 16- and 32-Bit

Microprocessors

Table 1 shows performance benchmarks for the

ADSP-21160M.

Table 1. ADSP-21160M Benchmarks

4G Word Address Range for Off-Chip Memory

Memory Interface Supports Programmable Wait State

Generation and Page-Mode for Off-Chip Memory

Multiprocessing Support Provides:

Glueless Connection for Scalable DSP Multiprocessing

Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of up to Six ADSP-21160Ms plus Host

Six Link Ports for Point-To-Point Connectivity and Array

Multiprocessing

Serial Ports Provide:

Two 40M Bit/s Synchronous Serial Ports with

Companding Hardware

Independent Transmit and Receive Functions

TDM Support for T1 and E1 Interfaces

64-Bit Wide Synchronous External Port Provides:

Glueless Connection to Asynchronous and SBSRAM

External Memories

Benchmark Algorithm

Speed

1024 Point Complex FFT(Radix 4, with 115 µs

reversal)

FIR Filter (per tap)

IIR Filter (per biquad)

Matrix Multiply (pipelined)

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Matrix Multiply (pipelined)

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Divide (y/x)

6.25 ns

25 ns

56.25 ns

100 ns

37.5 ns

56.25 ns

560M Bytes/s

Inverse Square Root

DMA Transfer Rate

Thesebenchmarksprovidesingle-channel extrapolationsof

measured dual-channel processing performance. For more

informationonbenchmarkingandoptimizingDSPcodefor

single- and dual-channel processing, see Analog Devices’s

website.

Up to 40 MHz Operation

The ADSP-21160M continues SHARC’s industry-leading

standards of integration for DSPs, combining a

high-performance32-bitDSPcorewithintegrated,on-chip

system features. These features include a 4M bit dual

ported SRAM memory, host processor interface, I/O

processor that supports 14 DMAchannels, twoserial ports,

six link ports, external parallel bus, and glueless

multiprocessing.

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ADSP-21160M

ADSP-21160M Family Core Architecture

The functional block diagram on page 1 shows a block

diagram of the ADSP-21160M, illustrating the following

architectural features:

The ADSP-21160M includes the following archi-

tectural features of the ADSP-2116x family core. The

ADSP-21160M is code compatible at the assembly level

with the ADSP-21060, ADSP-21061, and ADSP-21062.

• Two processing elements, each made up of an ALU, Mul-

tiplier, Shifter, and Data Register File

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

SIMD Computational Engine

The ADSP-21160M contains two computational process-

ing elements that operate as a Single Instruction Multiple

Data (SIMD) engine. The processing elements are referred

to as PEX and PEY, and each contains an ALU, multiplier,

shifter, and register file. PEX is always active, and PEY may

be enabled by setting the PEYEN mode bit in the MODE1

register. When this mode is enabled, the same instruction

isexecutedinbothprocessingelements,buteachprocessing

element operates on different data. This architecture is

efficient at executing math-intensive DSP algorithms.

• PMandDMbuses capable of supporting four 32-bit data

transfers between memory and the core every core

processor cycle

• Interval timer

• On-Chip SRAM (4 Mbit)

• External port that supports:

• Interfacing to off-chip memory peripherals

• Glueless multiprocessing support for six

ADSP-21160M SHARCs

Entering SIMD mode also has an effect on the way data is

transferred between memory and the processing elements.

When in SIMD mode, twice the data bandwidth is required

to sustain computational operation in the processing

elements. Because of this requirement, entering SIMD

mode also doubles the bandwidth between memory and the

processingelements. Whenusingthe DAGs totransfer data

in SIMD mode, two data values are transferred with each

access of memory or the register file.

• Host port

• DMA controller

• Serial ports and link ports

• JTAG test access port

Figure 1 shows a typical single-processor system. A multi-

processing system appears in Figure 4.

Independent, Parallel Computation Units

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Within each processing element is a set of computational

units. The computational units consist of an arith-

metic/logic unit (ALU), multiplier, and shifter. These units

perform single-cycle instructions. The three units within

each processing element are arranged in parallel, maximiz-

ing computational throughput. Single multifunction

instructions execute parallel ALU and multiplier opera-

tions. In SIMD mode, the parallel ALU and multiplier

operations occur in both processing elements. These com-

putation units support IEEE 32-bit single-precision

floating-point, 40-bit extended precision floating-point,

and 32-bit fixed-point data formats.

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A general-purpose data register file is contained in each

processing element. The register files transfer data between

the computation units and the data buses, and store inter-

mediate results. These 10-port, 32-register (16 primary, 16

secondary) register files, combined with the ADSP-2116x

enhanced Harvard architecture, allow unconstrained data

flow between computation units and internal memory. The

registers in PEX are referred to as R0–R15 and in PEY

as S0–S15.

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Figure 1. Single-Processor System

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21160M features an enhanced Harvard archi-

tecture in which the data memory (DM) bus transfers data,

and the program memory (PM) bus transfers both instruc-

tionsanddata(seethefunctional blockdiagramon page 1).

REV. 0

–3–

ADSP-21160M

With the ADSP-21160M’s separate program and data

memory buses and on-chip instructioncache, the processor

can simultaneously fetch four operands and an instruction

(from the cache), all in a single cycle.

between the 32-bit floating-point and 16-bit floating-point

formats is done in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data, using the DM

bus fortransfers, andthe otherblockstoresinstructionsand

data, using the PMbus for transfers. Using the DMbus and

PM bus in this way, with one dedicated to each memory

block, assures single-cycle execution with two data trans-

fers. In this case, the instruction must be available in

the cache.

Instruction Cache

The ADSP-21160M includes an on-chip instruction cache

that enables three-bus operation for fetching an instruction

and four data values. The cache is selective—only the

instructions whose fetches conflict with PM bus data

accesses are cached. This cache allows full-speed execution

of core, providing looped operations such as digital filter

multiply- accumulates and FFT butterfly processing.

Off-Chip Memory and Peripherals Interface

The ADSP-21160M’s external port provides the proces-

sor’s interface to off-chip memory and peripherals. The

4G word off-chip address space is included in the

ADSP-21160M’s unified address space. The separate

on-chip buses—forPMaddresses, PMdata, DMaddresses,

DM data, I/O addresses, and I/O data—are multiplexed at

the external port to create an external system bus with a

single 32-bit address bus and a single 64-bit data bus. The

lower 32 bits of the external data bus connect to even

addresses and the upper 32 bits of the 64 connect to odd

addresses. Every access to external memory is based on an

address that fetches a 32-bit word, and with the 64-bit bus,

two address locations can be accessed at once. When

fetching an instruction from external memory, two 32-bit

data locations are being accessed (16 bits are unused).

Figure 3 shows the alignment of various accesses to

external memory.

Data Address Generators with Hardware

Circular Buffers

The ADSP-21160M’s two data address generators (DAGs)

are used for indirect addressing and provide for implement-

ing circular data buffers in hardware. Circular buffers allow

efficient programming of delay lines and other data struc-

tures required in digital signal processing, and are

commonly used in digital filters and Fourier transforms.

The two DAGs of the ADSP-21160M contain sufficient

registers to allow the creation of up to 32 circular buffers

(16 primary register sets, 16 secondary). The DAGs auto-

matically handle address pointer wraparound, reducing

overhead, increasing performance, and simplifying imple-

mentation. Circular buffers can start and end at any

memory location.

Flexible Instruction Set

The external port supports asynchronous, synchronous,

and synchronous burst accesses. ZBT synchronous burst

SRAM can be interfaced gluelessly. Addressing of external

memory devices is facilitated by on-chip decoding of

high-order address lines to generate memory bank select

signals. Separate control lines are also generated for simpli-

fiedaddressing of page-mode DRAM. TheADSP-21160M

provides programmable memory wait states and external

memory acknowledge controls to allow interfacing to

DRAM and peripherals with variable access, hold, and

disable time requirements.

The 48-bit instruction word accommodates a variety of

parallel operations, forconciseprogramming. Forexample,

theADSP-21160Mcanconditionallyexecuteamultiply, an

add, and subtract, in both processing elements, while

branching, all in a single instruction.

ADSP-21160M Memory and I/O Interface Features

Augmenting the ADSP-2116x family core, the

ADSP-21160M adds the following architectural features:

Dual-Ported On-Chip Memory

The ADSP-21160M contains four megabits of on-chip

SRAM, organized as two blocks of 2 Mbits each, which can

be configured for different combinations of code and data

storage. Eachmemoryblockisdual-portedfor single-cycle,

independent accesses by the core processor and I/O proces-

sor. The dual-ported memory in combination with three

separate on-chip buses allows two data transfers from the

core and one from I/O processor, in a single cycle. On the

ADSP-21160M, the memory can be configured as a

maximum of 128K words of 32-bit data, 256K words of

16-bit data, 85K words of 48-bit instructions (or 40-bit

data), or combinations of different word sizes up to four

megabits. All of the memory can be accessed as 16-bit,

32-bit, 48-bit, or 64-bit words. A 16-bit floating-point

storage format is supported that effectively doubles the

amount of data that may be stored on-chip. Conversion

DMA Controller

The ADSP-21160M’s on-chip DMA controller allows

zero-overhead data transfers without processor interven-

tion. The DMA controller operates independently and

invisibly to the processor core, allowing DMA operations to

occurwhilethecoreissimultaneouslyexecutingitsprogram

instructions. DMA transfers can occur between the

ADSP-21160M’s internal memory and external memory,

externalperipherals,orahostprocessor.DMAtransferscan

also occur between the ADSP-21160M’s internal memory

and its serial ports or link ports. External bus packing to

16-, 32-, 48-, or 64-bit words is performed during DMA

transfers. Fourteen channels of DMA are available on the

ADSP-21160M—six via the link ports, four via the serial

ports, and four via the processor’s external port (for either

–4–

REV. 0

ADSP-21160M

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or rotating priority. Bus lock allows indivisible read-mod-

ify-write sequences for semaphores. A vector interrupt is

provided for interprocessor commands. Maximum

throughput for interprocessor data transfer is 320M bytes/s

over the external port. Broadcast writes allow simultaneous

transmissionof data toall ADSP-21160Ms and can be used

to implement reflective semaphores.

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Six link ports provide for a second method of multiprocess-

ing communications. Each link port can support

communications to another ADSP-21160M. Using the

links, a large multiprocessor systemcan be constructed in a

2Dor3Dfashion. Systemscanusethelinkportsandcluster

multiprocessing concurrently or independently.

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Figure 2. ADSP-21160M Memory Map

Link Ports

The ADSP-21160M features six 8-bit link ports that

provide additional I/O capabilities. With the capability of

running at 80 MHz rates, each link port can support 80M

bytes/s. Link port I/O is especially useful for point-to-point

interprocessor communication in multiprocessing systems.

The link ports can operate independently and simulta-

neously. Link port data is packed into 48- or 32-bit words,

and can be directly read by the core processor or

DMA-transferredtoon-chipmemory. Eachlinkport hasits

own double-buffered input and output registers.

Clock/acknowledge handshaking controls link port trans-

fers. Transfers are programmable as either transmit

or receive. For data throughput information, see link port

timing details in Table 18 on page 34.

host processor, other ADSP-21160Ms, memory or I/O

transfers). Programs can be downloaded to the

ADSP-21160M using DMA transfers. Asynchronous

off-chip peripherals can control two DMA channels using

DMA Request/Grant lines (DMAR1–2, DMAG1–2).

Other DMA features include interrupt generation upon

completion of DMA transfers, two-dimensional DMA, and

DMA chaining for automatic linked DMA transfers.

Multiprocessing

The ADSP-21160M offers powerful features tailored to

multiprocessing DSP systems as shown in Figure 4. The

external port and link ports provide integrated glueless mul-

tiprocessing support.

The external port supports a unified address space (see

Figure 2) that allows direct interprocessor accesses of each

ADSP-21160M’sinternalmemory.Distributedbusarbitra-

tionlogicisincludedon-chipforsimple,gluelessconnection

of systems containing up to six ADSP-21160Ms and a host

processor. Master processor changeover incurs only one

cycleofoverhead. Busarbitrationisselectableaseitherfixed

Serial Ports

The ADSP-21160M features two synchronous serial ports

that provide an inexpensive interface to a wide variety of

digital andmixed-signal peripheral devices. Theserial ports

can operate up to half the clock rate of the core, providing

each with a maximum data rate of 40M bit/s. Independent

REV. 0

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ADSP-21160M

tle-endian or big-endian transmission formats, with word

lengthsselectablefrom3bitsto32bits.Theyofferselectable

synchronization and transmit modes as well as optional

µ-law or A-law companding. Serial port clocks and frame

syncs can be internally or externally generated.

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Host Processor Interface

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The ADSP-21160M host interface allows easy connection

to standard microprocessor buses, both 16-bit and 32-bit,

with little additional hardware required. The host interface

is accessed through the ADSP-21160M’s external port and

is memory-mapped into the unified address space. Four

channels of DMA are available for the host interface; code

and data transfers are accomplished with low software

overhead. The host processor communicates with the

ADSP-21160M’s external bus with host bus request

(HBR),hostbutgrant(HBG),ready(REDY),acknowledge

(ACK), and chip select (CS) signals. The host can directly

read and write the internal memory of the ADSP-21160M,

and can access the DMA channel setup and mailbox regis-

ters. Vector interrupt support provides efficient execution

of host commands.

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The internal memory of the ADSP-21160M can be booted

at system power-up from an 8-bit EPROM, a host proces-

sor, or through one of the link ports. Selection of the boot

source is controlled by the BMS (Boot Memory Select),

EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)

pins. 32-bit and 16-bit host processors can be used

for booting.

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The ADSP-21160M uses an on-chip PLL to generate the

internal clock for the core. Ratios of 2:1, 3:1, and 4:1

between the core and CLKIN are supported. The

CLK_CFG pins are used to select the ratio. The CLKIN

rate is the rate at which the synchronous external

port operates.

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Power Supplies

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TheADSP-21160Mhasseparatepowersupplyconnections

for the internal (V_DDINT), external (V_DDEXT), and analog

(AV_DD/AGND) power supplies. The internal and analog

supplies must meet the 2.5 V requirement. The external

supplymustmeetthe3.3 Vrequirement.Allexternalsupply

pins must be connected to the same supply.

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Note that the analog supply (AV_DD) powers the

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ADSP-21160M’s clockgenerator PLL. To producea stable

clock, the system must provide an external circuit to filter

the power input to the AV_DDpin. Place the filter as close as

possible to the pin. For an example circuit, see Figure 5. To

prevent noise coupling, use a wide trace for the analog

ground (AGND) signal and install a decoupling capacitor

as close as possible to the pin.

Figure 4. Shared Memory Multiprocessing System

transmit and receive functions provide greater flexibility for

serial communications. Serial port data can be automati-

cally transferred to and from on-chip memory via a

dedicated DMA. Each of the serial ports offers a TDM

multichannel mode. The serial ports can operate with lit-

–6–

REV. 0

ADSP-21160M

oftheADSP-2116xdevelopmenttools,includingthesyntax

highlighting in the VisualDSP++ editor. This capability

permits:

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• Control how the development tools process inputs and

generate outputs.

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• Maintain a one-to-one correspondence with the tool’s

command line switches.

Figure 5. Analog Power (AV_DD) Filter Circuit

Development Tools

AnalogDevices’DSPemulatorsusetheIEEE1149.1JTAG

test access port of the ADSP-21160Mprocessor tomonitor

and control the target board processor during emulation.

The emulator provides full-speed emulation, allowing

inspection and modification of memory, registers, and

processor stacks. Nonintrusive in-circuit emulation is

assured by the use of the processor’s JTAG interface—the

emulator does not affect target system loading or timing.

The ADSP-21160M is supported with a complete set of

softwareandhardwaredevelopmenttools,includingAnalog

Devices’ emulators and VisualDSP++¹development envi-

ronment. The same emulator hardware that supports other

ADSP-2116x DSPs, also fully emulates the

ADSP-21160M.

The VisualDSP++ project management environment lets

programmers develop and debug an application. This envi-

ronment includes an easy-to-use assembler that is based on

an algebraic syntax; an archiver (librarian/library builder),

a linker, a loader, a cycle-accurate instruction-level simula-

tor, a C/C++ compiler, and a C/C++ run-time library that

includes DSP and mathematical functions. Two key points

for these tools are:

In addition tothe software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the ADSP-2116x processor

family. Hardware tools include ADSP-2116x PC plug-in

cards. Third Party software tools include DSP libraries,

real-time operating systems, and block diagram

design tools.

• Compiled ADSP-2116x C/C++ code efficiency—the

compiler has been developed for efficient translation of

C/C++ code to ADSP-2116x assembly. The DSP has

architectural features that improve the efficiency of

compiled C/C++ code.

Designing an Emulator-Compatible DSP Board

(Target)

The White Mountain DSP (Product Line of Analog

Devices, Inc.) family of emulators are tools that every DSP

developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG DSP. The

emulator uses the TAP to access the internal features of the

DSP, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers.

The DSP must be halted to send data and commands, but

once an operation has been completed by the emulator, the

DSP system is set running at full speed with no impact on

system timing.

• ADSP-2106x family code compatibility—The assembler

has legacy features to ease the conversion of existing

ADSP-2106x applications to the ADSP-2116x.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

To use these emulators, the target’s design must include the

interface between an Analog Devices’ JTAG DSP and the

emulation header on a custom DSP target board.

• Trace instruction execution

• Perform linear or statistical profiling of program

execution

Target Board Header

The emulator interface to an Analog Devices’ JTAG DSP

isa14-pinheader, asshowninFigure 6.Thecustomermust

supply this header on the target board in order to commu-

nicate with the emulator. The interface consists of a

standard dual row 0.025" square post header, set on

0.1"

؋

0.1" spacing, with a minimumpost length of 0.235".

Pin 3 is the key position used to prevent the pod from being

inserted backwards. This pin must be clipped on the

target board.

• Fill, dump, and graphically plot the contents of memory

• Source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and

manage DSP software development. Its dialog boxes and

property pages let programmers configure and manage all

¹VisualDSP++ is a registered trademark of Analog Devices, Inc.

REV. 0

–7–

ADSP-21160M

Also, the clearance (length, width, and height) around the

header must be considered. Leave a clearance of at least

0.15" and 0.10" around the length and width of the header,

and reserve a height clearance to attach and detach the pod

connector.

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Figure 7. JTAG Target Board Connector with No Local

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Figure 6. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in Place)

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As can be seen in Figure 6, there are two sets of signals on

the header. There are the standard JTAG signals TMS,

TCK, TDI, TDO, TRST, and EMU used for emulation

purposes (via an emulator). There are also secondary JTAG

signals BTMS, BTCK, BTDI, and BTRSTthat are option-

ally used for board-level (boundary scan) testing.

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Figure 8. JTAG Pod Connector Dimensions

When the emulator is not connected to this header, place

jumpers across BTMS, BTCK, BTRST, and BTDI as

shown in Figure 7. This holds the JTAG signals in the

correct state to allow the DSP to run free. Remove all the

jumpers whenconnectingthe emulator tothe JTAGheader.

Design-for-Emulation Circuit Information

For details on target board design issues including: single

processor connections, multiprocessor scan chains, signal

buffering, signal termination, and emulator pod logic, see

the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website—use site searchon

“EE-68” (www.analog.com). This document is updated

regularly to keep pace with improvements to emulator

support.

JTAG Emulator Pod Connector

Figure 8 details the dimensions of the JTAG pod connector

at the 14-pin target end. Figure 9 displays the keep-out area

for a target board header. The keep-out area allows the pod

connector to properly seat onto the target board header.

This board area should contain no components (chips,

resistors, capacitors, etc.). The dimensions are referenced

to the center of the 0.25" square post pin.

Additional Information

This data sheet provides a general overview of the

ADSP-21160Marchitectureandfunctionality. Fordetailed

information on the ADSP-2116x Family core architecture

and instruction set, refer to the ADSP-2116x SHARC DSP

Hardware Reference.

ꢁꢏꢂꢁC

PIN FUNCTION DESCRIPTIONS

ADSP-21160M pin definitions are listed below. Inputs

identified as synchronous (S) must meet timing require-

ments with respect to CLKIN (or with respect to TCK for

TMS, TDI). Inputs identified as asynchronous (A) can be

asserted asynchronously to CLKIN (or to TCKfor TRST).

ꢁꢏꢂꢍC

Figure 9. JTAG Pod Connector Keep-Out Area

–8–

REV. 0

ADSP-21160M

Unused inputs should be tied or pulled to VDD or GND,

except for ADDR31–0, DATA63–0, FLAG3–0, and inputs

that have internal pull-up or pull-down resistors (PA, ACK,

BRST, PAGE, CLKOUT, MS3–0, RDx, WRx, DMARx,

DMAGx, DTx, DRx, TCLKx, RCLKx, LxDAT7–0,

LxCLK, LxACK, TMS, TRST and TDI)—these pins can

be left floating. These pins have a logic-level hold circuit

(only enabled on the ADSP-21160M with ID2–0 = 00x)

that prevents input from floating internally.

The following symbols appear in the Type column of

Table 2: A = Asynchronous, G = Ground, I = Input,

O = Output, P = Power Supply, S = Synchronous,

(A/D) = Active Drive, (O/D) = Open Drain, and

T = Three-State (when SBTS is asserted, or when the

ADSP-21160M is a bus slave).

Table 2. Pin Function Descriptions

Type

Function

ADDR31–0

I/O/T

External BusAddress. TheADSP-21160Moutputsaddressesforexternal memoryand

peripherals on these pins. In a multiprocessor system, the bus master outputs addresses

for read/writes of the internal memory or IOP registers of other ADSP-21160Ms. The

ADSP-21160M inputs addresses when a host processor or multiprocessing bus master

is reading or writing its internal memory or IOP registers. A keeper latch on the DSP’s

ADDR31–0 pins maintains the input at the level it was last driven (only enabled on the

ADSP-21160M with ID2–0 = 00x).

DATA63–0

MS3–0

I/O/T

O/T

External Bus Data. The ADSP-21160M inputs and outputs data and instructions on

these pins. Pull-up resistors on unused DATA pins are not necessary. A keeper latch on

the DSP’s DATA63-0 pins maintains the input at the level it was last driven (only

enabled on the ADSP-21160M with ID2–0 = 00x).

Memory Select Lines. These outputs are asserted (low) as chip selects for the corre-

sponding banks of external memory. Memory bank size must be defined in the

SYSCON control register. The MS3–0 outputs are decoded memory address lines. In

asyn- chronous access mode, the MS3–0 outputs transition with the other address

outputs. Insynchronousaccessmodes, theMS3–0outputsassertwiththeotheraddress

lines; however, they de-assert after the first CLKIN cycle in which ACK is

sampled asserted.

RDL

RDH

I/O/T

Memory Read Low Strobe. RDL is asserted whenever ADSP-21160M reads from the

low word of external memory or from the internal memory of other ADSP-21160Ms.

External devices, including other ADSP-21160Ms, must assert RDL for reading from

the low word of ADSP-21160M internal memory. In a multiprocessing system, RDL

is driven by the bus master.

Memory Read High Strobe. RDHis asserted whenever ADSP-21160M reads from the

high word of external memory or from the internal memory of other ADSP-21160Ms.

External devices, including other ADSP-21160Ms, must assert RDH for reading from

the high word of ADSP-21160M internal memory. In a multiprocessing system, RDH

is driven by the bus master.

WRL

WRH

I/O/T

Memory Write Low Strobe. WRL is asserted when ADSP-21160M writes to the low

word of external memory or internal memory of other ADSP-21160Ms. External

devices must assertWRLfor writing to ADSP-21160M’slowwordofinternal memory.

In a multiprocessing system, WRL is driven by the bus master.

Memory Write High Strobe. WRH is asserted when ADSP-21160M writes to the high

word of external memory or internal memory of other ADSP-21160Ms. External

devices must assert WRH for writing to ADSP-21160M’s high word of internal

memory. In a multiprocessing system, WRH is driven by the bus master.

PAGE

O/T

DRAM Page Boundary. The ADSP-21160M asserts this pin to signal that an external

DRAM page boundary has been crossed. DRAM page size must be defined in the

ADSP-21160M’s memory control register (WAIT). DRAM can only be implemented

in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses.

In a multiprocessing system PAGE is output by the bus master. A keeper latch on the

DSP’s PAGE pin maintains the output at the level it was last driven (only enabled on

the ADSP-21160M with ID2–0 = 00x).

REV. 0

–9–

ADSP-21160M

Table 2. Pin Function Descriptions (Continued)

Type

Function

BRST

I/O/T

Sequential Burst Access. BRST is asserted by ADSP-21160M or a host to indicate that

data associated with consecutive addresses is being read or written. A slave device

samples the initial address and increments an internal address counter after each

transfer. The incremented address is not pipelined on the bus. If the burst access is a

read from host to ADSP-21160M, ADSP-21160M automatically increments the

address as long as BRST is asserted. BRST is asserted after the initial access of a burst

transfer. It is asserted for every cycle after that, except for the last data request cycle

(denoted by RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s

BRST pin maintains the input at the level it was last driven (only enabled on the

ADSP-21160M with ID2–0 = 00x).

ACK

I/O/S

I/S

Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to

an external memory access. ACK is used by I/O devices, memory controllers, or other

peripherals to hold off completion of an external memory access. The ADSP-21160M

deasserts ACK as an output to add wait states to a synchronous access of its internal

memory. A keeper latch on the DSP’s ACK pin maintains the input at the level it was

last driven (only enabled on the ADSP-21160M with ID2–0 = 00x).

Suspend Bus and Three-State. External devices can assert SBTS (low) to place the

external bus address, data, selects, and strobes in a high impedance state for the

following cycle. If the ADSP-21160Mattempts to access external memory whileSBTS

is asserted, the processor will halt and the memory access will not be completed until

SBTS is deasserted. SBTS should only be used to recover from host processor and/or

ADSP-21160M deadlock or used with a DRAM controller.

SBTS

IRQ2–0

FLAG3–0

TIMEXP

HBR

I/A

I/O/A

O

Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be

either edge-triggered or level-sensitive.

Flag Pins. Each is configured via control bits as either an input or output. As an input,

it can be tested as a condition. As an output, it can be used to signal external peripherals.

Timer Expired. Asserted for four CLKIN cycles when the timer is enabled and

TCOUNT decrements to zero.

Host Bus Request. Must be asserted by a host processor to request control of the

ADSP-21160M’s external bus. WhenHBRis asserted in a multiprocessing system, the

ADSP-21160Mthat isbusmasterwill relinquishthebus andassertHBG. Torelinquish

the bus, the ADSP-21160M places the address, data, select, and strobe lines in a high

impedance state. HBR has priority over all ADSP-21160M bus requests (BR6–1) in a

multiprocessing system.

I/A

HBG

I/O

Host Bus Grant. Acknowledges anHBRbus request, indicating that the host processor

may takecontrol of theexternal bus. HBGis asserted (held low) by the ADSP-21160M

until HBR is released. In a multiprocessing system, HBG is output by the

ADSP-21160M bus master and is monitored by all others.

CS

REDY

I/A

O (O/D)

Chip Select. Asserted by host processor to select the ADSP-21160M.

Host Bus Acknowledge. The ADSP-21160M deasserts REDY (low) to add waitstates

to a host access when CS and HBR inputs are asserted.

DMAR1

DMAR2

I/A

DMARequest1(DMAChannel11).AssertedbyexternalportdevicestorequestDMA

services.

DMARequest2(DMAChannel12).AssertedbyexternalportdevicestorequestDMA

services.

ID2–0

I

MultiprocessingID.Determineswhichmultiprocessingbusrequest(BR1–BR6)isused

by ADSP-21160M. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and

so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system

configuration selection which should be hardwired or only changed at reset.

DMAG1

O/T

DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160M to indicate that the

requested DMA starts on the next cycle. Driven by bus master only.

–10–

REV. 0

ADSP-21160M

Table 2. Pin Function Descriptions (Continued)

Type

Function

DMAG2

O/T

DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160M to indicate that the

requested DMA starts on the next cycle. Driven by bus master only.

Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ms to arbitrate

for bus mastership. An ADSP-21160M only drives its own BRx line (corresponding to

the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with

less than six ADSP-21160Ms, the unused BRx pins should be pulled high; the

processor’s own BRx line must not be pulled high or low because it is an output.

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for

multiprocessor bus arbitration is selected. When RPBAis low, fixed priority is selected.

This signal is a system configuration selection which must be set to the same value on

every ADSP-21160M. If thevalueof RPBAischangedduringsystemoperation, it must

be changed in the same CLKIN cycle on every ADSP-21160M.

BR6–1

RPBA

PA

I/O/S

I/S

I/O/T

Priority Access. Asserting its PA pin allows an ADSP-21160M bus slave to interrupt

background DMA transfers and gain access to the external bus. PA is connected to all

ADSP-21160Ms in the system. If access priority is not required in a system, the PA pin

should be left unconnected.

DTx

DRx

TCLKx

O

I

I/O

Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.

Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.

Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal

pull-up resistor.

RCLKx

TFSx

RFSx

I/O

Receive Clock (Serial Ports 0, 1). Each RCLKpin has a 50 kΩ internal pull-up resistor.

Transmit Frame Sync (Serial Ports 0, 1).

Receive Frame Sync (Serial Ports 0, 1).

LxDAT7–0

Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down

resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down

resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal

pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.

EPROM Boot Select. For a description of how this pin operates, see Table 3. This

signal is a system configuration selection that should be hardwired.

Link Boot. For a description of how this pin operates, see Table 3. This signal is a

system configuration selection that should be hardwired.

LxCLK

LxACK

EBOOT

LBOOT

BMS

I/O

I

I/O/T

Boot Memory Select. Serves as an output or input as selected with the EBOOT and

LBOOT pins; see Table 3. This input is a system configuration selection that should

be hardwired.

CLKIN

I

Local Clock In. CLKIN is the ADSP-21160M clock input. The ADSP-21160M

external port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple

of the CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,

changed, or operated below the specified frequency.

CLK_CFG3–0

CLKOUT

I

Core/CLKINRatioControl. ADSP-21160Mcoreclock(instructioncycle)rateisequal

to n

؋

CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.

For clock configuration definitions, see the RESET & CLKIN section of the System

Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.

Local Clock Out. CLKOUT is driven at the CLKIN frequency by the current bus

master. This output is three-stated when the ADSP-21160M is not the bus master, or

whenthe host controls the bus (HBGasserted). Akeeper latchonthe DSP’s CLKOUT

pin maintains the output at the level it was last driven (only enabled on the

ADSP-21160M with ID2–0 = 00x).

O/T

RESET

I/A

Processor Reset. Resets the ADSP-21160M to a known state and begins execution at

the program memory location specified by the hardware reset vector address. The

RESET input must be asserted (low) at power-up.

REV. 0

–11–

ADSP-21160M

Table 2. Pin Function Descriptions (Continued)

Type

Function

TCK

TMS

I

I/S

Test Clock (JTAG). Provides a clock for JTAG boundary scan.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ

internal pull-up resistor.

TDI

I/S

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

20 kΩ internal pull-up resistor.

TDO

TRST

O

I/A

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Reset (JTAG). Resets the test state machine. TRSTmust be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21160M. TRST has a

20 kΩ internal pull-up resistor.

EMU

CIF

O (O/D)

O/T

Emulation Status. Must be connected to the ADSP-21160M emulator target board

connector only. EMU has a 50 kΩ internal pull-up resistor.

Core Instruction Fetch. Signal is active low when an external instruction fetch is

performed. Driven by bus master only. Three-state when host is bus master.

Core Power Supply. Nominally 2.5 V dc and supplies the DSP’s core processor

(40 pins).

V_DDINT

P

V_DDEXT

AV_DD

P

I/O Power Supply. Nominally 3.3 V dc (46 pins).

Analog Power Supply. Nominally 2.5 V dc and supplies the DSP’s internal PLL (clock

generator). This pin has the same specifications as V_DDINT, except that added filtering

circuitry is required. For more information, see Power Supplies on page 6.

Analog Power Supply Return.

Power Supply Return. (83 pins)

Do Not Connect. Reserved pins that must be left open and unconnected (5 pins).

AGND

GND

NC

G

Table 3. Boot Mode Selection

EBOOT LBOOT BMS

Booting Mode

1

0

1

0

1

0

1

Output

EPROM (Connect BMS to EPROM chip select.)

Host Processor

Link Port

No Booting. Processor executes from external memory.

Reserved

1 (Input)

0 (Input)

x (Input)

–12–

REV. 0

ADSP-21160M

ADSP-21160M SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Signal

K Grade Parameter¹

Min

Max

Unit

V_DDINT

AV_DD

V_DDEXT

V_IH1

V_IH2

V_IL

Internal (Core) Supply Voltage

Analog (PLL) Supply Voltage

External (I/O) Supply Voltage

2.37

3.13

2.2

2.3

–0.5

0

2.63

3.47

V_DDEXT+0.5

0.8

V

ºC

High Level Input Voltage², @ V_DDEXT=Max

High Level Input Voltage³, @ V_DDEXT=Max

Low Level Input Voltage^2,3, @ V_DDEXT=Min

Case Operating Temperature⁴

T_CASE

85

1

Specifications subject to change without notice.

²Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1,

ID2–0, RPBA, PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1,

TCLK0, TCLK1, RCLK0, RCLK1.

³Applies to input pins: CLKIN, RESET, TRST.

⁴See Environmental Conditions on page 45 for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter¹

Test Conditions

Min

Max

Unit

V_OH

V_OL

I_IH

I_IL

I_ILPU1

High Level Output Voltage²

Low Level Output Voltage²

High Level Input Current^4,5,6

Low Level Input Current⁴

Low Level Input Current

Pull-Up1⁵

@ V_DDEXT=Min, I_OH=–2.0 mA³

@ V_DDEXT=Min, I_OL=4.0 mA³

@ V_DDEXT=Max, V_IN=V_DDMax

@ V_DDEXT=Max, V_IN=0 V

2.4

V

µA

0.4

10

@ V_DDEXT=Max, V_IN=0 V

250

I_ILPU2

Low Level Input Current

@ V_DDEXT=Max, V_IN=0 V

500

µA

Pull-Up2⁶

I_OZH

I_OZL

I_OZHPD

Three-State Leakage Current^7,8,9,10@ V_DDEXT=Max, V_IN=V_DDMax

10

250

µA

Three-State Leakage Current⁷

Three-State Leakage Current

Pull-Down¹⁰

@ V_DDEXT=Max, V_IN=0 V

@ V_DDEXT=Max, V_IN=V_DDMax

I_OZLPU1

I_OZLPU2

Three-State Leakage Current

@ V_DDEXT=Max, V_IN=0 V

250

500

µA

Pull-Up1⁸

Three-State Leakage Current

Pull-Up2⁹

I_OZHA

I_OZLA

Three-State Leakage Current¹¹

Supply Current (Internal)¹²

Supply Current (Internal)¹³

Supply Current (Internal)¹⁴

Supply Current (Idle)¹⁵

Supply Current (Analog)¹⁶

Input Capacitance^17,18

@ V_DDEXT=Max, V_IN=V_DDMax

@ V_DDEXT=Max, V_IN=0 V

t_CCLK=12.5 ns, V_DDINT=Max

@AV_DD=Max

25

4

µA

mA

I_DD-INPEAK

I_DD-INHIGH

I_DD-INLOW

I_DD-IDLE

AI_DD

1400 mA

875

625

80

10

4.7

mA

pF

C_IN

f_IN=1 MHz, T_CASE=25°C, V_IN=2.5 V

1

Specifications subject to change without notice.

²Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY,

DMAG1, DMAG2, BR6–1, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK,

BMS, TDO, EMU.

³See Output Drive Currents on page 42 for typical drive current capabilities.

⁴Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, CLK_CFG3-0.

REV. 0

–13–

ADSP-21160M

⁵Applies to input pins with internal pull-ups: DR0, DR1.

⁶Applies to input pins with internal pull-ups: DMARx, TMS, TDI, TRST.

⁷Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, TDO.

⁸Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU.

⁹Applies to three-statable pins with internal pull-ups: MS3–0, RDx, WRx, DMAGx, PA, CIF.

¹⁰Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, LxACK.

¹¹Applies to ACK pulled up internally with 2 kΩ during reset or ID2–0 = 00x.

¹²The test program used to measure I_DD-INPEAKrepresents worst case processor operation and is not sustainable under normal application conditions. Actual

internal power measurements made using typical applications are less than specified. For more information, see Power Dissipation on page 42.

13

I

is a composite average based on a range of high activity code. For more information, see Power Dissipation on page 42.

is a composite average based on a range of low activity code. For more information, see Power Dissipation on page 42.

DDINHIGH

14

I

DDINLOW

¹⁵Idle denotes ADSP-21160M state during execution of IDLE instruction. For more information, see Power Dissipation on page 42.

¹⁶Characterized, but not tested.

¹⁷Applies to all signal pins.

¹⁸Guaranteed, but not tested.

ABSOLUTE MAXIMUM RATINGS

Internal (Core) Supply Voltage (V_DDINT)¹. . .–0.3 V to +3.0 V

Analog (PLL) Supply Voltage (A_VDD) . . . . .–0.3 V to +3.0 V

External (I/O) Supply Voltage (V_DDEXT) . . . .–0.3 V to +4.6 V

Input Voltage. . . . . . . . . . . . . . . . . .–0.5 V to V_DDEXT+0.5 V

Output Voltage Swing . . . . . . . . . . .–0.5 V to V_DDEXT+0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Storage Temperature Range. . . . . . . . . . . –65ºC to +150ºC

Lead Temperature (5 seconds). . . . . . . . . . . . . . . . . 185ºC

¹Stressesgreaterthanthoselistedabovemaycausepermanentdamagetothedevice.

These are stress ratings only. Functional operation of the device at these or any

other conditions greater than those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

ESD SENSITIVITY

CAUTION:

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-21160M features proprietary ESD protection

circuitry, permanent damage may occur on devices subjected to high-energy electro-

static discharges. Therefore, proper ESD precautions are recommended to avoid

performance degradation or loss of functionality.

–14–

REV. 0

ADSP-21160M

Timing Specifications

Switching Characteristics specify how the processor

The ADSP-21160M’s internal clock switches at higher fre-

quenciesthanthesysteminputclock(CLKIN).Togenerate

the internal clock, the DSP uses an internal phase-locked

loop (PLL). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the DSP’s

internal clock (the clock source for the external port logic

and I/O pads).

changes its signals. Circuitry external tothe processor must

be designed for compatibility with these signal characteris-

tics. Switching characteristics describe what the processor

will do in a given circumstance. Use switching characteris-

tics to ensure that any timing requirement of a device

connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled

by circuitry external to the processor, such as the data input

for a read operation. Timing requirements guarantee that

the processor operates correctly with other devices.

TheADSP-21160M’sinternalclock(amultipleofCLKIN)

provides the clock signal for timing internal memory,

processor core, link ports, serial ports, and external port (as

required for read/write strobes in asynchronous access

mode). During reset, program the ratio between the DSP’s

internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG3–0 pins. Even though the

internal clock is the clock source for the external port, the

external port clock always switches at the CLKIN fre-

quency. To determine switching frequencies for the serial

and link ports, divide down the internal clock, using the

programmabledivider control of each port (TDIVx/RDIVx

for the serial ports and LxCLKD1–0 for the link ports).

Note the following definitions of various clock periods that

are a function of CLKIN and the appropriate ratio control:

• t_CCLK= (t_CK) / CR

• t_LCLK= (t_CCLK)

؋

LR

• t_SCLK= (t_CCLK)

؋

SR

Where:

• LCLK = Link Port Clock

• SCLK = Serial Port Clock

• t_CK= CLKIN Clock Period

• t_CCLK= (Processor) Core Clock Period

• t_LCLK= Link Port Clock Period

• t_SCLK= Serial Port Clock Period

• CR = Core/CLKIN Ratio (2, 3, or 4:1,

determined by CLK_CFG3–0 at reset)

• LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,

determined by LxCLKD)

• SR = Serial Port/Core Clock Ratio (wide range,

determined by

؋

CLKDIV)

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of

others. While addition or subtraction would yield meaning-

ful results for an individual device, the values given in this

data sheet reflect statistical variations and worst cases. Con-

sequently, it is not meaningful to add parameters to derive

longer times.

See Figure 32 under Test Conditions for voltage reference

levels.

REV. 0

–15–

ADSP-21160M

Clock Input

Table 4. Clock Input

80 MHz

Min

Parameter

Unit

Max

Timing Requirements:

t_CK

CLKIN Period

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4V–2.0V)

25

10.5

80

40

3

ns

t_CKL

t_CKH

t_CKRF

W_&.

&/.,1

W_&.+

W_&./

Figure 10. Clock Input

Reset

Table 5. Reset

Parameter

Min

Max

Unit

Timing Requirements:

t_WRST

RESET Pulsewidth Low¹

t_SRST

RESET Setup Before CLKIN High²

4t_CK

8

ns

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 ms while RESET is

low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).

²Only required if multiple ADSP-21160Ms must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple

ADSP-21160Ms communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself

after reset.

&/.,1

W₆₅₆₇

W_:567

5(6(7

Figure 11. Reset

–16–

REV. 0

ADSP-21160M

Interrupts

Table 6. Interrupts

Parameter

Min

Max

Unit

Timing Requirements:

t_SIR

t_HIR

t_IPW

IRQ2–0 Setup Before CLKIN High¹

6

0

ns

IRQ2–0 Hold After CLKIN High¹

IRQ2–0 Pulsewidth²

2+t_CK

¹Only required for IRQx recognition in the following cycle.

²Applies only if t_SIRand t_HIRrequirements are not met.

&/.,1

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Figure 12. Interrupts

Timer

Table 7. Timer

Parameter

Min

Max

Unit

Switching Characteristic:

t_DTEX

CLKIN High to TIMEXP

1

7

ns

&/.,1

W_'7( ;

7,0(;3

Figure 13. Timer

REV. 0

–17–

ADSP-21160M

Flags

Table 8. Flags

Parameter

Min

Max

Unit

Timing Requirements:

t_SFI

t_HFI

FLAG3–0 IN Setup Before CLKIN High¹

4

1

ns

FLAG3–0 IN Hold After CLKIN High¹

FLAG3–0 IN Delay After RDx/WRx Low¹

FLAG3–0 IN Hold After RDx/WRx Deasserted¹

t_DWRFI

t_HFIWR

Switching Characteristics:

12

9

0

t_DFO

FLAG3–0 OUT Delay After CLKIN High

ns

t_HFO

t_DFOE

t_DFOD

FLAG3–0 OUT Hold After CLKIN High

CLKIN High to FLAG3–0 OUT Enable

CLKIN High to FLAG3–0 OUT Disable

1

ns

5

¹Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.

&/.,1

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Figure 14. Flags

–18–

REV. 0

ADSP-21160M

memory space in asynchronous access mode. Note that

timing for ACK, DATA, RDx, WRx, and DMAG strobe

timing parameters only applies to asynchronous access

mode.

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to

memories (and memory-mapped peripherals) without

reference to CLKIN. These specifications apply when the

ADSP-21160M is the bus master accessing external

Table 9. Memory Read—Bus Master

Parameter

Min

Max

Unit

Timing Requirements:

t_DAD

Address, CIF, Selects Delay to Data

t_CK–0.25t_CCLK–11+W

0.75t_CK–11+W

ns

Valid^1,2

t_DRLD

t_HDA

t_SDS

t_HDRH

t_DAAK

t_DSAK

t_SAKC

t_HAKC

RDx Low to Data Valid^1,3

Data Hold from Address, Selects⁴

Data Setup to RDx High¹

Data Hold from RDx High^3,4

ACK Delay from Address, Selects^2,5

ACK Delay from RDx Low^3,5

ACK Setup to CLKIN^3,5

ACK Hold After CLKIN³

ns

0

8

1

t_CK–0.5t_CCLK–12+W

t_CK–0.75t_CCLK–11+W

0.5t_CCLK+3

1

Switching Characteristics:

t_DRHA

Address, CIF, Selects Hold After RDx

0.25t_CCLK–1+H

ns

High³

t_DARL

t_RW

t_RWR

Address, CIF, Selects to RDx Low²

RDx Pulse width³

0.25t_CCLK–3

t_CK–0.5t_CCLK–1+W

ns

RDx High to WRx, RDx, DMAGx Low³0.5t_CCLK–1+HI

W = (number of wait states specified in WAIT register)

؋

t_CK.

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t_CK(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

¹Data Delay/Setup: User must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of MSx, BMS is referenced.

³Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.

⁴Data Hold: User must meet t_HDAor t_HDRHin asynchronous access mode. See Example System Hold Time Calculation on page 44 for the calculation of

hold times given capacitive and dc loads.

⁵ACK Delay/Setup: User must meet t_DAAK, t_DSAK, or t_SAKCfor deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).

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Figure 15. Memory Read—Bus Master

REV. 0

–19–

ADSP-21160M

memory space in asynchronous access mode. Note that

timing for ACK, DATA, RDx, WRx, and DMAG strobe

timing parameters only applies to asynchronous access

mode.

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to

memories (and memory-mapped peripherals) without

reference to CLKIN. These specifications apply when the

ADSP-21160M is the bus master accessing external

Table 10. Memory Write—Bus Master

Parameter

Min

Max

Unit

Timing Requirements:

t_DAAK

t_DSAK

t_SAKC

t_HAKC

ACK Delay from Address, Selects^1,2

ACK Delay from WRx Low^1,3

ACK Setup to CLKIN^1,3

t_CK–0.5t_CCLK–12+W

t_CK–0.75t_CCLK–11+W

ns

0.5t_CCLK+3

1

ACK Hold After CLKIN^1,3

Switching Characteristics:

t_DAWH

Address, CIF, Selects to WRx

t_CK–0.25t_CCLK–3+W

ns

Deasserted^2,3

t_DAWL

t_WW

Address, CIF, Selects to WRx Low²

WRx Pulse width³

0.25t_CCLK–3

ns

t_CK–0.5t_CCLK–1+W

t_CK–0.25t_CCLK–12.5+W

0.25t_CCLK–1+H

0.25t_CCLK–2+H

0.5t_CCLK–1+HI

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

t_WWR

Data Setup before WRx High³

Address Hold after WRx Deasserted³

Data Hold after WRx Deasserted³

Data Disable after WRx Deasserted^3,4

WRx High to WRx, RDx, DMAGx

Low³

0.25t_CCLK+2+H

t_DDWR

t_WDE

Data Disable before WRx or RDx Low 0.25t_CCLK–1+I

WRx Low to Data Enabled –0.25t_CCLK–1

ns

W = (number of wait states specified in WAIT register) × t_CK.

H = t_CK(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

I = t_CK(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

¹ACK Delay/Setup: User must meet t_DAAKor t_DSAKor t_SAKCfor deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).

²The falling edge of MSx, BMS is referenced.

³Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.

⁴See Example System Hold Time Calculation on page 44 for calculation of hold times given capacitive and dc loads.

–20–

REV. 0

ADSP-21160M

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Figure 16. Memory Write—Bus Master

REV. 0

–21–

ADSP-21160M

When accessing a slave ADSP-21160M, these switching

characteristics must meet the slave’s timing requirements

for synchronous read/writes (see Synchronous

Read/Write—Bus Slave on page 24). The slave

ADSP-21160M must also meet these (bus master) timing

requirements for data and acknowledge setup and hold

times.

Synchronous Read/Write—Bus Master

Use these specifications for interfacing to external memory

systems that require CLKIN—relative timing or for

accessing a slave ADSP-21160M (in multiprocessor

memory space). These synchronous switching characteris-

tics are also valid during asynchronous memory reads and

writes except where noted (see Memory Read—Bus Master

on page 19 and Memory Write—Bus Master on page 20).

Table 11. Synchronous Read/Write—Bus Master

Parameter

Min

Max

Unit

Timing Requirements:

t_SSDATI

t_HSDATI

t_SACKC

t_HACKC

Data Setup Before CLKIN¹

Data Hold After CLKIN¹

ACK Setup Before CLKIN¹

ACK Hold After CLKIN¹

5.5

1

0.5t_CCLK+3

1

ns

Switching Characteristics:

t_DADDO

t_HADDO

t_DPGO

t_DRDO

t_DWRO

t_DRWL

t_DDATO

t_HDATO

t_DACKMO

t_ACKMTR

t_DCKOO

t_CKOP

Address, MSx, BMS, BRST, CIF Delay After CLKIN

10

ns

Address, MSx, BMS, BRST, CIF Hold After CLKIN

PAGE Delay After CLKIN

RDx High Delay After CLKIN¹

WRx High Delay After CLKIN¹

RDx/WRx Low Delay After CLKIN

Data Delay After CLKIN

1.5

0.25t_CCLK–1

11

0.25t_CCLK+9

12.5

Data Hold After CLKIN

1.5

ACK Delay After CLKIN²

0.25t_CCLK+3

0.25t_CCLK–3

2

t_CK–1

t_CK/2–2

0.25t_CCLK+9

ACK Disable Before CLKIN²

CLKOUT Delay After CLKIN

CLKOUT Period

5

t_CK³+1

t_CK/2+2³

t_CKWH

t_CKWL

CLKOUT Width High

CLKOUT Width Low

t_CK/2–2

¹Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to synchronous access mode.

²Applies to broadcast write, master precharge of ACK.

³Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise, For more information, see the System Design chapter

in the ADSP-2116x SHARC DSP Hardware Reference.

–22–

REV. 0

ADSP-21160M

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Figure 17. Synchronous Read/Write—Bus Master

REV. 0

–23–

ADSP-21160M

Synchronous Read/Write—Bus Slave

Use these specifications for ADSP-21160M bus master

accesses of a slave’s IOP registers or internal memory (in

multiprocessor memory space). The bus master must meet

these (bus slave) timing requirements.

Table 12. Synchronous Read/Write—Bus Slave

Parameter

Min

Max

Unit

Timing Requirements:

t_SADDI

t_HADDI

t_SRWI

t_HRWI

t_SSDATI

t_HSDATI

Address, BRST Setup Before CLKIN

Address, BRST Hold After CLKIN

RDx/WRx Setup Before CLKIN

RDx/WRx Hold After CLKIN

Data Setup Before CLKIN

5

1

5

1

5.5

1

ns

Data Hold After CLKIN

Switching Characteristics:

t_DDATO

t_HDATO

t_DACKC

t_HACKO

Data Delay After CLKIN

12.5

10

ns

Data Hold After CLKIN

ACK Delay After CLKIN

ACK Hold After CLKIN

1.5

–24–

REV. 0

ADSP-21160M

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Figure 18. Synchronous Read/Write—Bus Slave

REV. 0

–25–

ADSP-21160M

Multiprocessor Bus Request and Host Bus Request

Use these specifications for passing of bus mastership

between multiprocessing ADSP-21160Ms (BRx) or a host

processor (HBR, HBG).

Table 13. Multiprocessor Bus Request and Host Bus Request

Parameter

Min

Max

Unit

Timing Requirements:

t_HBGRCSV

HBG Low to RDx/WRx/CS Valid

19

ns

t_SHBRI

t_HHBRI

t_SHBGI

t_HHBGI

t_SBRI

t_HBRI

t_SPAI

t_HPAI

t_SRPBAI

t_HRPBAI

HBR Setup Before CLKIN¹

6

1

6

1

9

1

9

1

6

2

ns

HBR Hold After CLKIN¹

HBG Setup Before CLK/=’]IN

HBG Hold After CLKIN High

BRx, PA Setup Before CLKIN

BRx, PA Hold After CLKIN High

PA Setup Before CLKIN

PA Hold After CLKIN High

RPBA Setup Before CLKIN

RPBA Hold After CLKIN

Switching Characteristics:

t_DHBGO

t_HHBGO

t_DBRO

HBG Delay After CLKIN

HBG Hold After CLKIN

BRx Delay After CLKIN

BRx Hold After CLKIN

PA Delay After CLKIN, Slave

PA Disable After CLKIN, Slave

PA Delay After CLKIN, Master

PA Disable Before CLKIN, Master

REDY (O/D) or (A/D) Low from CS and HBR Low²

REDY (O/D) Disable or REDY (A/D) High from HBG²

REDY (A/D) Disable from CS or HBR High²

7

ns

2

8

t_HBRO

1.5

t_DPASO

t_TRPAS

t_DPAMO

t_PATR

t_DRDYCS

t_TRDYHG

t_ARDYTR

8

1.5

0.25t_CCLK+9

0.5t_CK

0.25t_CCLK–5

t_CK+25

11

¹Only required for recognition in the current cycle.

²(O/D) = open drain, (A/D) = active drive.

–26–

REV. 0

ADSP-21160M

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Figure 19. Multiprocessor Bus Request and Host Bus Request

REV. 0

–27–

ADSP-21160M

Asynchronous Read/Write—Host to ADSP-21160M

Use these specifications (Table 14 and Table 15) for asyn-

chronous host processor accesses of an ADSP-21160M,

after the host has asserted CS and HBR (low). After HBG

is returned by the ADSP-21160M, the host can drive the

RDx and WRx pins to access the ADSP-21160M’s internal

memory or IOP registers. HBR and HBG are assumed low

for this timing

Table 14. Read Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_SADRDL

t_HADRDH

t_WRWH

t_DRDHRDY

Address Setup/CS Low Before RDx Low

Address Hold/CS Hold Low After RDx

RDx/WRx High Width

RDx High Delay After REDY (O/D) Disable

RDx High Delay After REDY (A/D) Disable

0

2

5

0

ns

Switching Characteristics:

t_SDATRDY

t_DRDYRDL

t_RDYPRD

Data Valid Before REDY Disable from Low

2

ns

REDY (O/D) or (A/D) Low Delay After RDx Low

REDY (O/D) or (A/D) Low Pulsewidth for Read

Data Disable After RDx High

10

6

t_CK

2

t_HDARWH

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Figure 20. Read Cycle (Asynchronous Read—Host to ADSP-21160M)

–28–

REV. 0

ADSP-21160M

Table 15. Write Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_SCSWRL

t_HCSWRH

t_SADWRH

t_HADWRH

t_WWRL

CS Low Setup Before WRx Low

0

6

2

7

5

0

5

4

ns

CS Low Hold After WRx High

Address Setup Before WRx High

Address Hold After WRx High

WRx Low Width

t_WRWH

RDx/WRx High Width

t_DWRHRDY

t_SDATWH

t_HDATWH

WRx High Delay After REDY (O/D) or (A/D) Disable

Data Setup Before WRx High

Data Hold After WRx High

Switching Characteristics:

t_DRDYWRLREDY (O/D) or (A/D) Low Delay After WRx/CS Low

t_RDYPWRREDY (O/D) or (A/D) Low Pulsewidth for Write

11

ns

12

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Figure 21. Write Cycle (Asynchronous Write—Host to ADSP-21160M)

REV. 0

–29–

ADSP-21160M

Three-State Timing—Bus Master and Bus Slave

These specifications show how the memory interface is

disabled (stops driving) or enabled (resumes driving)

relative to CLKIN and the SBTS pin. This timing is appli-

cable to bus master transition cycles (BTC) and host

transition cycles (HTC) as well as the SBTS pin.

Table 16. Three-State Timing—Bus Slave, HBR, SBTS

Parameter

Min

Max

Unit

Timing Requirements:

t_STSCK

SBTS Setup Before CLKIN

6

1

ns

t_HTSCK

SBTSHold After CLKIN

Switching Characteristics:

t_MIENAAddress/Select Enable After CLKIN

t_MIENS

t_MIENHG

t_MITRA

t_MITRS

t_MITRHG

t_DATEN

t_DATTR

t_ACKEN

t_ACKTR

t_CDCEN

t_CDCTR

t_MTRHBG

1.5

0.25t_CCLK–1

0.25t_CCLK–4

3.5

1.5

t_CCLK–3

t_CK–6

9

ns

Strobes Enable After CLKIN¹

HBG Enable After CLKIN

Address/Select Disable After CLKIN

Strobes Disable After CLKIN¹

HBG Disable After CLKIN

Data Enable After CLKIN²

Data Disable After CLKIN²

ACK Enable After CLKIN²

ACK Disable After CLKIN²

CLKOUT Enable After CLKIN

CLKOUT Disable After CLKIN

Memory Interface Disable Before HBG

Low³

0.25t_CCLK+4

0.25t_CCLK

8

10

5

9

5

9

t_CCLK+1

t_CK+2

t_MENHBG

Memory Interface Enable After HBG

t_CK–5

t_CK+5

ns

High³

¹Strobes = RDx, WRx, DMAGx.

²In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

³Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).

–30–

REV. 0

ADSP-21160M

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Figure 22. Three-State Timing—Bus Slave, HBR, SBTS

REV. 0

–31–

ADSP-21160M

Mastermode, thedatatransferiscontrolledbyADDR31–0,

RDx, WRx, MS3–0, and ACK (not DMAG). For Paced

Master mode, the Memory Read-Bus Master, Memory

Write-Bus Master, and Synchronous Read/Write-Bus

Master timing specifications for ADDR31–0, RDx, WRx,

MS3–0, PAGE, DATA63–0, and ACK also apply.

DMA Handshake

These specifications describe the three DMA handshake

modes. In all three modes DMAR is used to initiate trans-

fers. For handshake mode, DMAG controls the latching or

enabling of data externally. For external handshake mode,

the data transfer is controlled by the ADDR31–0, RDx,

WRx, PAGE,MS3–0, ACK, andDMAGsignals. ForPaced

Table 17. DMA Handshake

Parameter

Min

Max

Unit

Timing Requirements:

t_SDRC

t_WDR

DMARx Setup Before CLKIN¹

3

ns

DMARx Width Low (Nonsynchronous)²t_CCLK+4.5

t_SDATDGL

t_HDATIDG

t_DATDRH

t_DMARLL

t_DMARH

Data Setup After DMAGx Low³

0.75t_CK–7

Data Hold After DMAGx High

Data Valid After DMARx High³

DMARx Low Edge to Low Edge⁴

DMARx Width High²

2

t_CK+10

t_CK

t_CCLK+4.5

Switching Characteristics:

t_DDGL

t_WDGH

t_WDGL

t_HDGC

t_VDATDGH

t_DATRDGH

t_DGWRL

t_DGWRH

t_DGWRR

t_DGRDL

t_DRDGH

t_DGRDR

t_DGWR

DMAGx Low Delay After CLKIN

DMAGx High Width

DMAGx Low Width

0.25t_CCLK+1

0.5t_CCLK–1+HI

t_CK–0.5t_CCLK–1

t_CK–0.25t_CCLK+1.5

t_CK–0.25t_CCLK–8

0.25t_CCLK–3

–1.5

t_CK–0.5t_CCLK–2+W

–1.5

0.25t_CCLK+9

ns

DMAGx High Delay After CLKIN

Data Valid Before DMAGx High⁵

Data Disable After DMAGx High⁶

WRx Low Before DMAGx Low

DMAGx Low Before WRx High

WRx High Before DMAGx High⁷

RDx Low Before DMAGx Low

RDx Low Before DMAGx High

RDx High Before DMAGx High⁷

DMAGx High to WRx, RDx, DMAGx

Low

t_CK–0.25t_CCLK+9

t_CK–0.25t_CCLK+5

0.25t_CCLK+1.5

2

t_CK–0.5t_CCLK–2+W

–1.5

0.5t_CCLK–2+HI

2

t_DADGH

t_DDGHA

Address/Select Valid to DMAGx High

Address/Select Hold after DMAGx High

18

1

ns

W = (number of wait states specified in WAIT register)

؋

t_CK.

HI = t_CK(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

¹Only required for recognition in the current cycle.

²Maximum throughput using DMARx/DMAGx handshaking equals t_WDR+ t_DMARH= (t_CCLK+4.5) + (t_CCLK+4.5)=34ns (29.4 MHz). This throughput limit

applies to non-synchronous access mode only.

³t_SDATDGLis the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of

the write, the data can be driven t_DATDRHafter DMARx is brought high.

⁴Use t_DMARLLif DMARx transitions synchronous with CLKIN. Otherwise, use t_WDRand t_DMARH

.

⁵t_VDATDGHis valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then

t

_VDATDGH= t_CK– .25t_CCLK– 8 + (n × t_CK) where n equals the number of extra cycles that the access is prolonged.

⁶See Example System Hold Time Calculation on page 44 for calculation of hold times given capacitive and dc loads.

⁷This parameter applies for synchronous access mode only.

–32–

REV. 0

ADSP-21160M

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Figure 23. DMA Handshake Timing

REV. 0

–33–

ADSP-21160M

Table 18. Link Port—Maximum Data Throughput for

Transmit/Receive Pairs (Continued)

Link Ports

Calculation of link receiver data setup and hold relative to

link clock is required to determine the maximum allowable

skew that can be introduced in the transmission path

between LDATA and LCLK. Setup skew is the maximum

delay that can be introduced in LDATA relative to LCLK

(setup skew= t_LCLKTWHMin – t_DLDCH– t_SLDCL). Hold skew is the

maximumdelay that canbe introduced in LCLKrelative to

LDATA (hold skew = t_LCLKTWLMin – t_HLDCH– t_HLDCL). Calcu-

lationsmade directly fromspeed specifications will result in

unrealistically small skew times because they include

multiple tester guardbands.

Transmit

Link Port

Receive

Link Port

Maximum Operating

Frequency (MHz)

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

68.97

71.43

80

76.92

74.07

64.52

66.67

71.43

64.52

66.67

74.07

71.43

62.5

Note that thereis atwo-cycle effect latencybetweenthe link

port enable instruction and the DSP enabling the link port.

Maximum throughput varies across link port trans-

mit/receivepairs. Table 18showsmaximumthroughputfor

all transmit/receive pairs based on setup skew of 0.5 ns

(setupskew=t_LCLKTWHmin–t_DLDCH–t_SLDCL= 0.5 ns). Hold skew

results indicate 80 MHz operation across all link ports. All

hold time skews are equal to 0.5 ns or greater for all link

port transmit/receive pairs at 80 MHz. Based upon these

values, all link port transmit/receive pairs can be operated

at maximum throughput for LxCLK:CCLK ratios of 2:1,

3:1, and 4:1 at 80 MHz CCLK. To operate all link port

transmit/receive pairs at LxCLK:CCLK ratio of 1:1, the

core clock frequency must be no greater than 62.5 MHz.

66.67

64.52

71.43

Maximum data throughput values are based upon the reset

value of the LAR Link Port Assignment Register (Link

Buffer 0 assigned to Link Port 0, Link Buffer 1 assigned to

LinkPort 1, etc.). Throughputs arenot guaranteedfor LAR

settings other than the reset LAR value. For additional

details on LAR, refer to the ADSP-21160 DSP Hardware

Reference manual.

Table 18. Link Port—Maximum Data Throughput for

Transmit/Receive Pairs

Transmit

Link Port

Receive

Link Port

Maximum Operating

Frequency (MHz)

0

1

0

1

2

3

4

5

0

1

2

3

4

5

71.43

74.07

71.43

80

76.92

68.97

71.43

68.97

80

76.92

74.07

–34–

REV. 0

ADSP-21160M

Table 19. Link Ports—Receive

Parameter

Min

Max

Unit

Timing Requirements:

t_SLDCL

t_HLDCL

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

Data Setup Before LCLK Low

Data Hold After LCLK Low

LCLK Period

LCLK Width Low

LCLK Width High

2.5

t_LCLK

6.0

ns

Switching Characteristics:

t_DLALC

LACK Low Delay After LCLK High¹

12

17

ns

¹LACK goes low with t_DLALCrelative to rise of LCLK after first nibble, but doesn’t go low if the receiver’s link buffer is not about to fill.

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Figure 24. Link Ports—Receive

REV. 0

–35–

ADSP-21160M

Table 20. Link Ports—Transmit

Parameter

Min

Max

Unit

Timing Requirements:

t_SLACH

t_HLACH

Switching Characteristics:

LACK Setup Before LCLK High

LACK Hold After LCLK High

14

–2

ns

t_DLDCH

t_HLDCH

t_LCLKTWL

t_LCLKTWH

t_DLACLK

Data Delay After LCLK High

Data Hold After LCLK High

LCLK Width Low

LCLK Width High

LCLK Low Delay After LACK High

6.0

ns

–2

0.5t_LCLK–1.5

0.5t_LCLK+5

0.5t_LCLK+1.5

3t_LCLK+11

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Figure 25. Link Ports—Transmit

–36–

REV. 0

ADSP-21160M

Serial Ports

To determine whether communication is possible between

two devices at clock speed n, the following specifications

must be confirmed: 1) frame sync delay and frame sync

setup and hold, 2) data delay and data setup and hold, and

3) SCLK width.

Table 21. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements:

t_SFSE

TFS/RFS Setup Before TCLK/RCLK¹

TFS/RFS Hold After TCLK/RCLK^1,2

Receive Data Setup Before RCLK¹

Receive Data Hold After RCLK¹

TCLK/RCLK Width

3.5

4

1.5

4

14

2t_CCLK

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

TCLK/RCLK Period

¹Referenced to sample edge.

²RFSholdafterRCKwhenMCE=1, MFD=0is0nsminimumfromdriveedge. TFSholdafterTCKforlateexternalTFSis0nsminimumfromdrive edge.

Table 22. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements:

t_SFSI

TFS Setup Before TCLK¹; RFS Setup Before RCLK¹

8

1

6.5

3

ns

t_HFSI

t_SDRI

t_HDRI

TFS/RFS Hold After TCLK/RCLK^1,2

Receive Data Setup Before RCLK¹

Receive Data Hold After RCLK¹

¹Referenced to sample edge.

²RFSholdafterRCKwhenMCE=1, MFD=0is0nsminimumfromdriveedge. TFSholdafterTCKforlateexternalTFSis0nsminimumfromdrive edge.

Table 23. Serial Ports—External or Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics:

t_DFSE

t_HOFSE

RFS Delay After RCLK (Internally Generated RFS)¹

13

ns

RFS Hold After RCLK (Internally Generated RFS)¹

3

¹Referenced to drive edge.

Table 24. Serial Ports—External Clock

Parameter

Min

Max

Unit

Switching Characteristics:

t_DFSE

TFS Delay After TCLK (Internally Generated TFS)¹

13

16

ns

t_HOFSE

t_DDTE

t_HDTE

TFS Hold After TCLK (Internally Generated TFS)¹

Transmit Data Delay After TCLK¹

3

0

Transmit Data Hold After TCLK¹

¹Referenced to drive edge.

Table 25. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics:

t_DFSI

TFS Delay After TCLK (Internally Generated TFS)¹

4.5

ns

t_HOFSI

TFS Hold After TCLK (Internally Generated TFS)¹

–1.5

REV. 0

–37–

ADSP-21160M

Table 25. Serial Ports—Internal Clock (Continued)

Parameter

Min

Max

Unit

t_DDTI

t_HDTI

t_SCLKIW

Transmit Data Delay After TCLK¹

Transmit Data Hold After TCLK¹

TCLK/RCLK Width

7.5

ns

0

0.5t_SCLK–2.5

0.5t_SCLK+2

¹Referenced to drive edge.

Table 26. Serial Ports—Enable and Three-State

Parameter

Min

Max

Unit

Switching Characteristics:

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

Data Enable from External TCLK¹

Data Disable from External TCLK¹

Data Enable from Internal TCLK¹

Data Disable from Internal TCLK¹

4

0

ns

10

3

¹Referenced to drive edge.

–38–

REV. 0

ADSP-21160M

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Figure 26. Serial Ports

REV. 0

–39–

ADSP-21160M

Table 27. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics:

t_DDTLFSE

Data Delay from Late External TFS or External RFS with

13

ns

MCE = 1, MFD = 0¹

t_DDTENFS

Data Enable from late FS or MCE = 1, MFD = 0¹

1.0

¹MCE = 1, TFS enable and TFS valid follow t_DDTLFSEand t_DDTENFS

.

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Figure 27. External Late Frame Sync

–40–

REV. 0

ADSP-21160M

JTAG Test Access Port and Emulation

Table 28. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements:

t_TCK

TCK Period

t_CK

5

6

7

18

ns

t_STAP

t_HTAP

t_SSYS

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low¹

TRST Pulsewidth

t_HSYS

t_TRSTW

Switching Characteristics:

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low²

4t_CK

13

30

ns

¹System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0,

PA,BRST, DR0,DR1, TCLK0,TCLK1, RCLK0, RCLK1,TFS0,TFS1,RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS,CLKIN,

RESET.

²System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF,

FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS.

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Figure 28. IEEE 11499.1 JTAG Test Access Port

REV. 0

–41–

ADSP-21160M

Output Drive Currents

Figure 29 shows typical I–V characteristics for the output drivers of the ADSP-21160M. The curves represent the current

drive capability of the output drivers as a function of output voltage.

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Figure 29. ADSP-21160M Typical Drive Currents

Power Dissipation

Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output

drivers.

Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Using the

current specifications (I_DDINPEAK, I_DDINHIGH, I_DDINLOW, I_DDIDLE) from Electrical Characteristics on page 13 and the current-ver-

sus-operation information in Table 29, engineers can estimate the ADSP-21160M’s internal power supply (V_DDINT) input

current for a specific application, according to the following formula:

% Peak × I_DDINPEAK

% High × I_DDINHIGH

% Low × I_DDINLOW

+ % Idle × I_DDIDLE

-------------------------------------------------

I_DDINT

The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on:

• the number of output pins that switch during each cycle (O)

• the maximum frequency at which they can switch (f)

• their load capacitance (C)

• their voltage swing (VDD)

and is calculated by:

P

_EXT= O × C × V_DD²× f

–42–

REV. 0

ADSP-21160M

The load capacitance should include the processor’s

package capacitance (C_IN). The switching frequency

includes driving the load high and then back low. Address

and data pins can drive high and low at a maximum rate of

1/(2t_CK). The write strobe can switch every cycle at a

frequency of 1/t_CK. Select pins switch at 1/(2t_CK), but selects

can switch on each cycle.

Table 29. ADSP-21160M Operation Types vs. Input Current

Operation

Peak Activity¹

High Activity¹

Low Activity¹

Instruction Type

Multifunction

Cache

2 per t_CKcycle

(DM

؋

64 and PM

؋

64)

1 per 2 t_CCLKcycles

1 per external port cycle (

؋

64) 1 per external port cycle (

؋

64) None

Worst case Random N/A

Multifunction

Internal Memory

1 per t_CKcycle

(DM

؋

64)

Single Function

Internal Memory

None

Instruction Fetch

Core Memory Access²

Internal Memory DMA

External Memory DMA

Data bit pattern for core

memory access and DMA

1 per 2 t_CCLKcycles

None

¹Peak Activity=I_DDINPEAK, HighActivity=I_DDINHIGH, and Low Activity=I_DDINLOW. The state of the PEYENbit (SIMDversus SISDmode) does not influence

these calculations.

²These assume a 2:1 core clock ratio. For more information on ratios and clocks (t_CKand t_CCLK), see the timing ratio definitions on page 15.

REV. 0

–43–

ADSP-21160M

• External data memory writes occur every other cycle, a

rate of 1/(4 t_CK), with 50% of the pins switching

Example: Estimate P_EXTwith the following assumptions:

• A system with one bank of external data memory—asyn-

chronous RAM (64-bit)

• The bus cycle time is 40 MHz (t_CK= 25 ns).

The P_EXTequation is calculated for each class of pins that

can drive:

• Four 64K × 16 RAM chips are used, each with a load of

10 pF

Table 30. External Power Calculations (3.3 V Device)

Pin Type

# of Pins

% Switching

× C

× f

× VDD²

= P_EXT

Address

MS0

WRx

Data

CLKOUT

15

1

2

64

1

50

0

–

50

–

× 44.7 pF

× 14.7 pF

× 4.7 pF

× 12.5 MHz

× 25 MHz

× 12.5 MHz

× 25 MHz

× 10.9 V

= 0.046 W

= 0.000 W

= 0.024 W

= 0.064 W

= 0.001 W

P_EXT= 0.135 W

Output Enable Time

A typical power consumption can now be calculated for

these conditions by adding a typical internal power

dissipation:

Output pins are considered to be enabled when they have

madea transition froma high impedance state towhenthey

startdriving.Theoutputenabletimet_ENAistheintervalfrom

when a reference signal reaches a high or low voltage level

to when the output has reached a specified high or low trip

point, as shown in the Output Enable/Disable diagram

(Figure 30). If multiple pins (such as the data bus) are

enabled, the measurement value is that of the first pin to

start driving.

P_TOTAL= P_EXT+ P_INT+ P_PLL

Where:

• P_EXTis from Table 30

• P_INTis I_DDINT× 2.5V, using the calculation I_DDINTlisted in

Power Dissipation on page 42

• P_PLLis AI_DD× 2.5V, using the value for AI_DDlisted in

ABSOLUTE MAXIMUM RATINGS on page 14

Example System Hold Time Calculation

To determine the data output hold time in a particular

system, first calculate t_DECAYusing the equation given above.

Choose –V to be the difference between the

Note that the conditions causing a worst-case P_EXTare

different from those causing a worst-case P_INT. Maximum

P_INTcannot occur while 100% of the output pins are

ADSP-21160M’soutputvoltageandtheinputthresholdfor

thedevicerequiringtheholdtime.Atypical–Vwillbe0.4 V.

C_Lis the total bus capacitance (per data line), and I_Lis the

total leakage or three-state current (per data line). The hold

time will be t_DECAYplus the minimum disable time (i.e.,

switching from all ones to all zeros. Note also that it is not

common for an application to have 100% or even 50% of

the outputs switching simultaneously.

Test Conditions

The test conditions for timing parameters appearing in

ADSP-21160M specifications on page 13 include output

disable time, output enable time, and capacitive loading.

t_DATRWHfor the write cycle).

Output Disable Time

REFERENCE

SIGNAL

Output pins are considered to be disabled when they stop

driving, go into a high impedance state, and start to decay

from their output high or low voltage. The time for the

voltage on the bus to decay by –Vis dependent onthe capac-

itive load, C_Land the load current, I_L. This decay time can

be approximated by the following equation:

t

MEASURED

t

ENA

DIS

V

OH (MEASURED)

V

– DV

+ DV

2.0V

OH (MEASURED)

V

t

OL (MEASURED)

DECAY

1.0V

V

OL (MEASURED)

t_DECAY= (C_L∆V)/I_L

The output disable time t_DISis the difference between

t_MEASUREDand t_DECAYas shown in Figure 30. The time t_MEASURED

is the interval from when the reference signal switches to

when the output voltage decays –V from the measured

output high or output low voltage. t_DECAYis calculated with

test loads C_Land I_L, and with –V equal to 0.5 V.

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE THISVOLTAGE

TO BE APPROXIMATELY 1.5V

Figure 30. Output Enable/Disable

–44–

REV. 0

ADSP-21160M

,

2/

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5,6(ꢀ7,0(

72

287387

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,

2+

Figure 31. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

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Figure 34. Typical Output Rise Time (10%–90%,

,1387

25

V_DDEXT= Min) vs. Load Capacitance

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Figure 32. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Capacitive Loading

Output delays and holds are based on standard capacitive

loads: 50 pF on all pins (see Figure 31). The delay and hold

specifications given should be derated by a factor of

1.5 ns/50 pF for loads other than the nominal value of

50 pF. Figure 33 and Figure 34 show how output rise time

varies with capacitance. Figure 35 graphically shows how

output delays and holds vary with load capacitance. (Note

that this graph or derating does not apply to output disable

delays; see Output Disable Time on page 44.) The graphs

of Figure 33, Figure 34, and Figure 35 may not be linear

outside the ranges shown.

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Figure 35. Typical Output Delay or Hold vs. Load

Capacitance (at Max Case Temperature)

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ꢇꢍꢏꢁꢁ

Environmental Conditions

The ADSP-21160M is tested for performance over the

commercial temperature range, 0°C to 85°C.

5,6(ꢀ7,0(

ꢇꢁꢏꢁꢁ

Thermal Characteristics

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The ADSP-21160M is packaged in a 400-ball Plastic Ball

Grid Array (PBGA). The ADSP-21160M is specified for a

case temperature (T_CASE). To ensure that the T_CASEdata sheet

specification is not exceeded, a heatsink and/or an air flow

source may be used. Use the center block of ground pins

(PBGA balls: H8–13, J8–13, K8–13, L8–13, M8–13, and

N8–13) to provide thermal pathways to the printed circuit

board’s ground plane. A heatsink should be attached to the

ground plane (as close as possible to the thermal pathways)

with a thermal adhesive.

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Figure 33. Typical Output Rise Time (10%–90%,

V_DDEXT= Max) vs. Load Capacitance

REV. 0

–45–

ADSP-21160M

T_CASE= T_AMB+ (PD × θ_CA

)

• T_CASE= Case temperature (measured on top surface

of package)

• PD = Power dissipation in W (this value depends upon

the specific application; a method for calculating PD is

shown under Power Dissipation).

• θ_CA= Value from Table 31.

• θ = 6.46°C/W

JB

Table 31. Airflow Over Package Versus θ_CA

Airflow (Linear Ft./Min.)

θ_CA(°C/W)¹

0

200

400

8.7

12.13 9.86

¹θ_JC= 3.6 °C/W.

400-BALL METRIC PBGA PIN CONFIGURATIONS

Table 32 lists the pin assignments for the PBGA package,

and the pin configurations diagram on page 51 shows the

pin assignment summary.

–46–

REV. 0

ADSP-21160M

Table 32. 400-ball Metric PBGA Pin Assignments

Pin Name

PBGA Pin# Pin Name

PBGA Pin#

DATA[14]

DATA[13]

DATA[10]

DATA[8]

DATA[4]

DATA[2]

TDI

TRST

RESET

RPBA

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

E01

E02

E03

E04

E05

E06

E07

E08

E09

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

DATA[22]

DATA[16]

DATA[15]

DATA[9]

DATA[6]

DATA[3]

DATA[0]

TCK

EMU

IRQ2

FLAG3

FLAG0

V_DDEXT

NC

DT1

RCLK1

RFS0

TCLK0

L0DAT[5]

L0DAT[2]

DATA[34]

DATA[33]

DATA[27]

DATA[26]

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

L1DAT[4]

L1DAT[3]

L1DAT[0]

L2DAT[7]

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

F01

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

DATA[24]

DATA[18]

DATA[17]

DATA[11]

DATA[7]

DATA[5]

DATA[1]

TMS

TD0

IRQ1

FLAG2

V_DDEXT

NC

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

G01

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

DATA[28]

DATA[25]

DATA[20]

DATA[19]

DATA[12]

V_DDEXT

V_DDINT

V_DDEXT

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

H01

H02

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

IRQ0

V_DDEXT

V_DDINT

V_DDEXT

FLAG1

TIMEXP

V_DDEXT

NC

TFS1

RFS1

RCLK0

DT0

L0DAT[4]

DATA[30]

DATA[29]

DATA[23]

DATA[21]

V_DDEXT

V_DDINT

GND

V_DDINT

TCLK1

DR1

DR0

TFS0

L1DAT[7]

L0CLK

L0DAT[3]

L0DAT[1]

L1CLK

DATA[40]

DATA[39]

DATA[37]

DATA[36]

V_DDEXT

V_DDINT

GND

L0DAT[7]

L0DAT[6]

L0ACK

L0DAT[0]

DATA[38]

DATA[35]

DATA[32]

DATA[31]

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

V_DDINT

V_DDEXT

L1DAT[6]

L1DAT[5]

L1ACK

L1DAT[1]

GND

V_DDINT

V_DDEXT

L2DAT[5]

L2ACK

L2DAT[3]

L2DAT[1]

L1DAT[2]

L2DAT[6]

L2DAT[4]

L2CLK

REV. 0

–47–

ADSP-21160M

Table 32. 400-ball Metric PBGA Pin Assignments (Continued)

Pin Name

PBGA Pin# Pin Name

L01 AV_DD

PBGA Pin#

DATA[44]

DATA[43]

DATA[42]

DATA[41]

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

J01

CLK_CFG_0 K01

CLKIN

M01

J02

J03

J04

J05

DATA[46]

DATA[45]

DATA[47]

V_DDEXT

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

CLK_CFG_1 L02

AGND L03

CLK_CFG_2 L04

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

BR2

BR1

CLK_CFG_3 M02

CLKOUT

GND

M03

M04

M05

M06

M07

M08

M09

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

T01

T02

T03

T04

T05

T06

T07

T08

T09

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

L05

L06

L07

L08

L09

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

R01

R02

R03

R04

R05

R06

R07

R08

R09

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

PAGE

SBTS

PA

L3DAT[7]

DATA[56]

DATA[58]

DATA[59]

DATA[63]

V_DDEXT

V_DDINT

V_DDEXT

L4DAT[3]

L4ACK

L4CLK

L4DAT[4]

J06

V_DDINT

J07

GND

J08

GND

J09

GND

J10

GND

J11

GND

J12

GND

J13

GND

J14

GND

J15

V_DDINT

J16

V_DDEXT

L2DAT[2]

L2DAT[0]

HBG

HBR

NC

J17

BR6

J18

BR5

J19

BR4

ACK

J20

BR3

REDY

DATA[53]

DATA[54]

DATA[57]

DATA[60]

V_DDEXT

V_DDINT

GND

V_DDEXT

N01

N02

N03

N04

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

DATA[49]

DATA[50]

DATA[52]

DATA[55]

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

NC

DATA[48]

DATA[51]

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

L3DAT[5]

L3DAT[6]

L3DAT[4]

L3CLK

L3DAT[2]

L3DAT[1]

L3DAT[3]

L3ACK

L4DAT[5]

L4DAT[6]

L4DAT[7]

L3DAT[0]

–48–

REV. 0

ADSP-21160M

Table 32. 400-ball Metric PBGA Pin Assignments (Continued)

Pin Name

PBGA Pin# Pin Name

PBGA Pin#

DATA[61]

DATA[62]

ADDR[3]

ADDR[2]

V_DDEXT

U01

U02

U03

U04

U05

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

ADDR[4]

ADDR[6]

ADDR[7]

ADDR[10]

ADDR[14]

ADDR[18]

ADDR[22]

ADDR[25]

ADDR[28]

ID0

V01

V02

V03

V04

V05

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

ADDR[5]

ADDR[9]

ADDR[12]

ADDR[15]

ADDR[17]

ADDR[20]

ADDR[23]

ADDR[26]

ADDR[29]

ID1

ADDR[0]

BMS

MS2

CIF

RDH

W01

W02

W03

W04

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

ADDR[8]

ADDR[11]

ADDR[13]

ADDR[16]

ADDR[19]

ADDR[21]

ADDR[24]

ADDR[27]

ADDR[30]

ADDR[31]

ID2

Y01

Y02

Y03

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

ADDR[1]

MS1

CS

BRST

MS0

MS3

WRH

RDL

DMAR2

L5DAT[0]

L5DAT[2]

L5ACK

L5DAT[4]

L5DAT[6]

DMAG2

LBOOT

L5DAT[1]

L5DAT[3]

L5DAT[5]

WRL

L5DAT[7]

L4DAT[0]

L4DAT[1]

L4DAT[2]

DMAG1

DMAR1

EBOOT

L5CLK

REV. 0

–49–

ADSP-21160M

400-BALL METRIC PBGA PIN CONFIGURATIONS (BOTTOM VIEW, SUMMARY)

ꢇꢁ

ꢂꢌ

ꢂꢅ

ꢂꢄ

ꢂꢇ

ꢂꢁ

ꢌ

ꢅ

ꢄ

ꢇ

ꢂꢎ

ꢂꢋ

ꢂꢍ

ꢂꢃ

ꢂꢂ

ꢋ

ꢍ

ꢃ

ꢂ

ꢎ

$

%

&

'

(

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*

+

-

.

/

0

1

3

5

7

8

9

:

<

.(< ꢑ

9

*1'ꢐ

$9

'',17

''

$*1'

,ꢊ2ꢀ6,*1$/6

''(;7

ꢐ

86(ꢀ7+(ꢀ&(17(5ꢀ%/2&.ꢀ2)ꢀ*5281'ꢀ3,16ꢀꢀꢈ3%*$ꢀ%$//6ꢑ

+ꢌ±ꢂꢃ@ꢀ-ꢌ±ꢂꢃ@ꢀ.ꢌ±ꢂꢃ@ꢀ/ꢌ±ꢂꢃ@ꢀ0ꢌ±ꢂꢃ@ꢀꢀ$1'ꢀ1ꢌ±ꢂꢃꢉꢀ72ꢀ3529,'(

7+(50$/ꢀ3$7+: $<6ꢀ72ꢀ<285ꢀ35,17('ꢀ&,5&8,7ꢀ%2$5'¶6

*5281'ꢀ3/$1(ꢏ

–50–

REV. 0

ADSP-21160M

OUTLINE DIMENSIONS

The ADSP-21160M comes in a 27mm

؋

27mm, 400-ball Metric PBGA package with 20 rows of balls.

400-BALL METRIC PBGA (B-400)

ꢇꢋꢏꢇꢁ

ꢇꢋꢏꢁꢁ 64

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0

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7

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64

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64

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8

9

:

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%27720 ꢀ9,(:

723ꢀ9,(:

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ꢁꢏꢍꢍ

ꢁꢏꢍꢁ

'(7$,/ꢀ$

ꢁꢏꢋꢁ

ꢁꢏꢅꢁ

ꢁꢏꢍꢁ

127(6ꢑ

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3/$1(

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ꢁꢏꢋꢍ

ꢁꢏꢅꢁ

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ꢀꢀꢀꢀꢀ3,7&+ꢀ,6ꢀ,1ꢀ,1&+(6ꢏ

ꢇꢏꢀꢀ&(17(5ꢀ),* 85(6ꢀ$5(ꢀ120 ,1$/ꢀ',0 (16,216ꢏ

ꢁꢏꢇꢁꢀ0 $;

%$//ꢀ',$0 (7(5

ꢃꢏꢀꢀ7+(ꢀ$&78$/ꢀ326,7,21ꢀ2)ꢀ7+(ꢀ%$//ꢀ*5,'ꢀ,6ꢀ: ,7+,1ꢀꢁꢏꢃꢁꢀ2)ꢀ,76ꢀ,'($/

ꢀꢀꢀꢀꢀ326,7,21ꢀ5(/$7,9(ꢀ72ꢀ7+(ꢀ3$&.$* (ꢀ('* (6ꢏ

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ꢄꢏꢀꢀ7+(ꢀ$&78$/ꢀ326,7,21ꢀ2)ꢀ($&+ꢀ%$//ꢀ,6ꢀ: ,7+,1ꢀꢁꢏꢂꢁꢀ2)ꢀ,76ꢀ,'($/

ꢀꢀꢀꢀꢀ326,7,21ꢀ5(/$7,9(ꢀ72ꢀ7+(ꢀ%$//ꢀ*5,'ꢏ

REV. 0

–51–

ADSP-21160M

ORDERING GUIDE

Case Temperature

Range

On-Chip

SRAM

Part Number^{1, 2}

Instruction Rate

Operating Voltage

ADSP-21160MKB-80

0°C to 85°C

80 MHz

4 Mbit

2.5 INT/3.3 EXT V

¹B = Plastic Ball Grid Array (PBGA) package.

²See ADSP-21160N data sheet for ordering information for higher-performance derivative.

–52–

REV. 0

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.


型号：	ADSP-21160M
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 电脑
文件：	总53页 (文件大小：695K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21160M [ADI]

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