ADSP-21161NCCAZ100_技术文档

SHARC Processor

ADSP-21161N

Integrated peripherals—integrated I/O processor, 1M bit on-

chip dual-ported SRAM, SDRAM controller, glueless multi-

processing features, and I/O ports (serial, link, external

bus, SPI, and JTAG)

ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit

floating-point formats

100 MHz/110 MHz core instruction rate

Single-cycle instruction execution, including SIMD opera-

tions in both computational units

Up to 660 MFLOPs peak and 440 MFLOPs sustained

performance

SUMMARY

High performance 32-Bit DSP—applications in audio, medi-

cal, military, wireless communications, graphics, imaging,

motor-control, and telephony

Super Harvard Architecture—four independent buses for

dual data fetch, instruction fetch, and nonintrusive zero-

overhead I/O

Code compatible with all other sharc family DSPs

Single-instruction multiple-data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point computation units,

each with a multiplier, ALU, shifter, and register file

Serial ports offer I²S support via 8 programmable and simul-

taneous receive or transmit pins, which support up to 16

transmit or 16 receive channels of audio

225-ball 17 mm 17 mm CSP_BGA package

DUAL-PORTED SRAM

CORE PROCESSOR

INSTRUCTION

6

JTAG TEST

AND EMULATION

TWO INDEPENDENT

DUAL-PORTED BLOCKS

CACHE

32 u 48-BIT

TIMER

I/O PORT

PROCESSOR PORT

ADDR DATA

12

8

GPIO

FLAGS

DATA

ADDR

DATA

DAG1

8 u 4 u 32

DAG2

8 u 4 u 32

PROGRAM

SEQUENCER

SDRAM

CONTROLLER

IOD

64

IOA

18

EXTERNAL PORT

32

24

32

ADDR BUS

MUX

PM ADDRESS BUS

DM ADDRESS BUS

64

MULTIPROCESSOR

INTERFACE

BUS

CONNECT

(PX)

PM DATA BUS

DM DATA BUS

DATA BUS

MUX

DATA

REGISTER

FILE

(PEY)

16 u 40-BIT

DATA

REGISTER

FILE

(PEX)

16 u 40-BIT

HOST PORT

BARREL

SHIFTER

BARREL

SHIFTER

MULT

5

DMA

CONTROLLER

IOP

REGISTERS

(MEMORY MAPPED)

ALU

16

20

4

SERIAL PORTS (4)

CONTROL,

STATUS, &

DATA BUFFERS

LINK PORTS (2)

SPI PORTS (1)

S

I/O PROCESSOR

Figure 1. ADSP-21161N Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADSP-21161N

TABLE OF CONTENTS

Summary ............................................................... 1

General Description ................................................. 3

ADSP-21161N Family Core Architecture .................... 3

ADSP-21161N Memory and I/O Interface Features ....... 5

Development Tools ............................................... 9

Additional Information ........................................ 10

Related Signal Chains .......................................... 10

Pin Function Descriptions ....................................... 11

Boot Modes ....................................................... 16

Specifications ........................................................ 17

Operating Conditions .......................................... 17

Electrical Characteristics ....................................... 18

Package Information ........................................... 19

Absolute Maximum Ratings ................................... 19

ESD Caution ...................................................... 19

Timing Specifications ........................................... 19

Power Dissipation ............................................... 20

Output Drive Currents ......................................... 54

Test Conditions .................................................. 54

Environmental Conditions .................................... 55

225-Ball CSP_BGA Ball Configurations ....................... 56

Outline Dimensions ................................................ 58

Surface-Mount Design .......................................... 58

Ordering Guide ..................................................... 58

REVISION HISTORY

1/13—Rev. B to Rev. C

Updated Development Tools ...................................... 9

Added section, Related Signal Chains .......................... 10

Added footnote 3 to Table 16 in

Memory Read — Bus Master .................................... 27

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ADSP-21161N

GENERAL DESCRIPTION

The ADSP-21161N SHARC^®DSP is a low cost derivative of the

ADSP-21160 featuring Analog Devices Super Harvard Archi-

tecture. Easing portability, the ADSP-21161N is source code

compatible with the ADSP-21160 and with first generation

ADSP-2106x SHARC processors in SISD (Single-Instruction,

Single-Data) mode. Like other SHARC DSPs, the ADSP-

21161N is a 32-bit processor that is optimized for high perfor-

mance DSP applications. The ADSP-21161N includes a

100 MHz or 110 MHz core, a dual-ported on-chip SRAM, an

integrated I/O processor with multiprocessing support, and

multiple internal buses to eliminate I/O bottlenecks.

The block diagram of the ADSP-21161N on Page 1 illustrates

the following architectural features:

• Two processing elements, each made up of an ALU, multi-

plier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core every core proces-

sor cycle

• Interval timer

As was first offered in the ADSP-21160, the ADSP-21161N

offers a single-instruction multiple-data (SIMD) architecture.

Using two computational units (ADSP-2106x SHARC proces-

sors have one), the ADSP-21161N can double cycle

performance versus the ADSP-2106x on a range of DSP

algorithms.

• On-Chip SRAM (1M bit)

• SDRAM controller for glueless interface to SDRAMs

• External port that supports:

• Interfacing to off-chip memory peripherals

• Glueless multiprocessing support for six

ADSP-21161N SHARCs

Fabricated in a state of the art, high speed, low power CMOS

process, the ADSP-21161N has a 10 ns or 9 ns instruction cycle

time. With its SIMD computational hardware running at

110 MHz, the ADSP-21161N can perform 660 million floating-

point operations per second. Table 1 shows performance bench-

marks for the ADSP-21161N.

• Host port read/write of IOP registers

• DMA controller

• Four serial ports

These benchmarks provide single-channel extrapolations of

measured dual-channel processing performance. For more

information on benchmarking and optimizing DSP code, for

both single and dual-channel processing, see the Analog Devices

Inc. website.

• Two link ports

• SPI compatible interface

• JTAG test access port

• 12 general-purpose I/O pins

Figure 2 shows a typical single-processor system. A multipro-

cessing system appears in Figure 5 on Page 8.

Table 1. Benchmarks

100 MHz

Instruction

Rate

110 MHz

Instruction

Rate

ADSP-21161N FAMILY CORE ARCHITECTURE

The ADSP-21161N includes the following architectural features

of the ADSP-2116x family core. The ADSP-21161N is code

compatible at the assembly level with the ADSP-21160,

ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21065L.

Benchmark Algorithm

1024 Point Complex FFT

(Radix 4, with Reversal)

92 μs

83.6 μs

FIR Filter (Per Tap)

IIR Filter (Per Biquad)

Matrix Multiply (Pipelined)

[3 3]  [3 1]

[4 4]  [4 1]

Divide (y/x)

5 ns

4.5 ns

SIMD Computational Engine

20 ns

18.18 ns

The ADSP-21161N contains two computational processing ele-

ments that operate as a single-instruction multiple-data (SIMD)

engine. The processing elements are referred to as PEX and

PEY, and each contains an ALU, multiplier, shifter, and register

file. PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive DSP

algorithms.

45 ns

40.9 ns

80 ns

72.72 ns

54.54 ns

36.36 ns

880M bytes/s

60 ns

Inverse Square Root

DMA Transfers

40 ns

800M bytes/s

The ADSP-21161N continues SHARC’s industry-leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features. These

features include a 1M bit dual ported SRAM memory, host pro-

cessor interface, I/O processor that supports 14 DMA channels,

four serial ports, two link ports, SDRAM controller, SPI inter-

face, external parallel bus, and glueless multiprocessing.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the

bandwidth between memory and the processing elements.

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ADSP-21161N

When using the DAGs to transfer data in SIMD mode, two data

values are transferred with each access of memory or the regis-

ter file.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the SHARC enhanced Harvard

architecture, allow unconstrained data flow between computa-

tion units and internal memory. The registers in PEX are

referred to as R0–R15 and in PEY as S0–S15.

SIMD is supported only for internal memory accesses and is not

supported for off-chip accesses.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform single-cycle

instructions. The three units within each processing element are

arranged in parallel, maximizing computational throughput.

Single multifunction instructions execute parallel ALU and

multiplier operations. In SIMD mode, the parallel ALU and

multiplier operations occur in both processing elements. These

computation units support IEEE 32-bit single-precision float-

ing-point, 40-bit extended precision floating-point, and 32-bit

fixed-point data formats.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21161N features an enhanced Harvard architecture

in which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 2). With the ADSP-21161N’s separate program and

data memory buses and on-chip instruction cache, the proces-

sor can simultaneously fetch four operands (two over each data

bus) and an instruction (from the cache), all in a single cycle.

ADSP-21161N

CLKIN

CLOCK

XTAL

2

CLK_CFG1-0

CLKDBL

EBOOT

BMS

CS

BOOT

EPROM

(OPTIONAL)

ADDR

DATA

LBOOT

IRQ2-0

BRST

3

12

FLAG11-0

ADDR23-0

ADDR

TIMEXP

RPBA

ID2-0

MEMORY

AND

PERIPHERALS

(OPTIONAL)

DATA47-16

RD

DATA

OE

WE

LINK

DEVICES

(2 MAX)

WR

LXCLK

ACK

MS3-0

ACK

CS

LXACK

(OPTIONAL)

LXDAT7-0

RAS

CAS

RAS

CAS

SCLK0

FS0

D0A

D0B

SERIAL

DEVICE

(OPTIONAL)

SDRAM

(OPTIONAL)

DQM

SDWE

WE

SDCLK1-0

CLK

SCLK1

FS1

D1A

SERIAL

DEVICE

(OPTIONAL)

SDCKE

SDA10

CKE

A10

CS

D1B

ADDR

SCLK2

FS2

D2A

D2B

SERIAL

DEVICE

(OPTIONAL)

DATA

CLKOUT

DMAR2-1

DMA DEVICE

(OPTIONAL)

DMAG2-1

SCLK3

FS3

D3A

D3B

SERIAL

DEVICE

(OPTIONAL)

DATA

CS

HBR

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

HBG

REDY

SPICLK

SPIDS

SPI

COMPATIBLE

DEVICE

(HOST OR SLAVE)

BR6-1

ADDR

DATA

MOSI

MISO

PA

(OPTIONAL)

SBTS

RESET RSTOUT JTAG

7

Figure 2. System Diagram

Rev. C

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ADSP-21161N

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

Instruction Cache

The ADSP-21161N includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache enables full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Off-Chip Memory and Peripherals Interface

The ADSP-21161N’s external port provides the processor’s

interface to off-chip memory and peripherals. The 62.7-M word

off-chip address space (254.7-M word if all SDRAM) is included

in the ADSP-21161N’s unified address space. The separate on-

chip buses—for PM addresses, PM data, DM addresses, DM

data, I/O addresses, and I/O data—are multiplexed at the exter-

nal port to create an external system bus with a single 24-bit

address bus and a single 32-bit data bus. Every access to external

memory is based on an address that fetches a 32-bit word.

When fetching an instruction from external memory, two 32-bit

data locations are being accessed for packed instructions.

Unused link port lines can also be used as additional data lines

DATA15–DATA0, allowing single-cycle execution of instruc-

tions from external memory, at up to 110 MHz. Figure 4 shows

the alignment of various accesses to external memory.

Data Address Generators With Hardware Circular Buffers

The ADSP-21161N’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs of the ADSP-21161N con-

tain sufficient registers to allow the creation of up to 32 circular

buffers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wrap-around, reduce

overhead, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

The external port supports asynchronous, synchronous, and

synchronous burst accesses. Synchronous burst SRAM can be

interfaced gluelessly. The ADSP-21161N also can interface glue-

lessly to SDRAM. Addressing of external memory devices is

facilitated by on-chip decoding of high-order address lines to

generate memory bank select signals. The ADSP-21161N pro-

vides programmable memory wait states and external memory

acknowledge controls to allow interfacing to memory and

peripherals with variable access, hold, and disable time

requirements.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21161N can conditionally execute a multiply, an add,

and a subtract in both processing elements, while branching, all

in a single instruction.

ADSP-21161N MEMORY AND I/O INTERFACE

FEATURES

SDRAM Interface

The ADSP-21161N adds the following architectural features to

the ADSP-2116x family core.

The SDRAM interface enables the ADSP-21161N to transfer

data to and from synchronous DRAM (SDRAM) at the core

clock frequency or at one-half the core clock frequency. The

synchronous approach, coupled with the core clock frequency,

supports data transfer at a high throughput—up to 440M

bytes/s for 32-bit transfers and up to 660M bytes/s for 48-bit

transfers.

Dual-Ported On-Chip Memory

The ADSP-21161N contains one megabit of on-chip SRAM,

organized as two blocks of 0.5M bits (Figure 3). Each block can

be configured for different combinations of code and data stor-

age. Each memory block is dual-ported for single-cycle,

The SDRAM interface provides a glueless interface with stan-

dard SDRAMs—16Mb, 64Mb, 128Mb, and 256Mb— and

includes options to support additional buffers between the

ADSP-21161N and SDRAM. The SDRAM interface is

extremely flexible and provides capability for connecting

SDRAMs to any one of the ADSP-21161N’s four external mem-

ory banks, with up to all four banks mapped to SDRAM.

independent accesses by the core processor and I/O processor.

The dual-ported memory in combination with three separate

on-chip buses allow two data transfers from the core and one

from the I/O processor, in a single cycle. On the ADSP-21161N,

the memory can be configured as a maximum of 32K words of

32-bit data, 64K words of 16-bit data, 21K words of 48-bit

instructions (or 40-bit data), or combinations of different word

sizes up to one megabit. All of the memory can be accessed as

16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point

storage format is supported that effectively doubles the amount

of data that may be stored on-chip. Conversion between the

32-bit floating-point and 16-bit floating-point formats is done

in a single instruction. While each memory block can store

combinations of code and data, accesses are most efficient when

one block stores data using the DM bus for transfers, and the

other block stores instructions and data using the PM bus for

transfers. Using the DM bus and PM bus, with one dedicated to

Systems with several SDRAM devices connected in parallel may

require buffering to meet overall system timing requirements.

The ADSP-21161N supports pipelining of the address and con-

trol signals to enable such buffering between itself and multiple

SDRAM devices.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21161N

processor to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

Rev. C

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ADSP-21161N

ADDRESS

0x0020 0000

0x0000 0000 0x0001 FFFF

IOP REGISTERS

0x0002 0000 0x0002 1FFF (BLK 0)

0x0002 8000 0x0002 9FFF (BLK 1)

LONG WORD ADDRESSING

INTERNAL

MEMORY

SPACE

MS0

0x0004 0000 0x0004 3FFF (BLK 0)

0x0005 0000 0x0005 3FFF (BLK 1)

BANK 0

NORMAL WORD ADDRESSING

0x00FF FFFF (NON-SDRAM)

0x03FF FFFF (SDRAM)

0x0008 0000 0X0008 7FFF (BLK 0)

0x000A 0000 0x000A 7FFF (BLK 1)

SHORT WORD ADDRESSING

0x0400 0000

IOP REGISTERS OF ADSP-21161N

0x0010 0000

0x0012 0000

0x0014 0000

0x0011 FFFF

0x0013 FFFF

0x0015 FFFF

WITH ID = 001

IOP REGISTERS OF ADSP-21161N

MS1

WITH ID = 010

BANK 1

IOP REGISTERS OF ADSP-21161N

0x04FF FFFF (NON-SDRAM)

0x07FF FFFF (SDRAM)

WITH ID = 011

MULTIPROCESSOR

MEMORY

IOP REGISTERS OF ADSP-21161N

0x0016 0000

0x0017 FFFF

0x0019 FFFF

WITH ID = 100

0x0800 0000

SPACE

IOP REGISTERS OF ADSP-21161N

0x0018 0000

WITH ID = 101

MS2

BANK 2

IOP REGISTERS OF ADSP-21161N

0x001A 0000

0x001C 0000

0x001B FFFF

0x08FF FFFF (NON-SDRAM)

0x0BFF FFFF (SDRAM)

WITH ID = 110

RESERVED

0x0C00 0000

0x001F FFFF

MS3

BANK

3

EXTERNAL MEMORY SPACE

0x0CFF FFFF (NON-SDRAM)

0x0FFF FFFF (SDRAM)

NOTE: BANK SIZES ARE FIXED

Figure 3. Memory Map

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processor stacks. The processor’s JTAG interface ensures that

the emulator will not affect target system loading or timing.

core is simultaneously executing its program instructions. DMA

transfers can occur between the ADSP-21161N’s internal mem-

ory and external memory, external peripherals, or a host

processor. DMA transfers can also occur between the ADSP-

21161N’s internal memory and its serial ports, link ports, or the

SPI-compatible (Serial Peripheral Interface) port. External bus

packing and unpacking of 32-, 48-, or 64-bit words in internal

memory is performed during DMA transfers from either 8-,

16-, or 32-bit wide external memory. Fourteen channels of

DMA are available on the ADSP-21161N—two are shared

between the SPI interface and the link ports, eight via the serial

ports, and four via the processor’s external port (for host pro-

cessor, other ADSP-21161Ns, memory, or I/O transfers).

Programs can be downloaded to the ADSP-21161N using DMA

transfers. Asynchronous off-chip peripherals can control two

DMA channels using DMA Request/Grant lines (DMAR2–1,

DMAG2–1). Other DMA features include interrupt generation

upon completion of DMA transfers, and DMA chaining for

automatic linked DMA transfers.

For complete information on SHARC Analog Devices DSP

Tools product line of JTAG emulator operation, see the appro-

priate Emulator Hardware User’s Guide. For detailed infor-

mation on the interfacing of Analog Devices JTAG emulators

with Analog Devices DSP products with JTAG emulation ports,

please refer to Engineer to Engineer Note EE-68: Analog Devices

JTAG Emulation Technical Reference. Both of these documents

can be found on the Analog Devices website.

DMA Controller

The ADSP-21161N’s on-chip DMA controller enables zero-

overhead data transfers without processor intervention. The

DMA controller operates independently and invisibly to the

processor core, allowing DMA operations to occur while the

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ADSP-21161N

its own double-buffered input and output registers.

Clock/acknowledge handshaking controls link port transfers.

Transfers are programmable as either transmit or receive.

DATA47–16

DATA15–0

47

40 39

32 31

24 23

16 15

L1DATA7–0

DATA15-8

8

7

0

L0DATA7–0

DATA7–0

PROM

BO O T

Serial Ports

The ADSP-21161N features four synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices. Each serial port is made up of

two data lines, a clock and frame sync. The data lines can be

programmed to either transmit or receive.

8-BIT PACKED DMA DATA

8-BIT PACKED INSTRUCTION

EXECUTION

16-BIT PACKED DMA DATA

16-BIT PACKED INSTRUC-

TION EXECUTION

FLOAT OR FIXED, D31–D0,

32-BIT PACKED

32-BIT PACKED INSTRUC-

TION

The serial ports operate at up to half the clock rate of the core,

providing each with a maximum data rate of 55M bit/s. The

serial data pins are programmable as either a transmitter or

receiver, providing greater flexibility for serial communications.

Serial port data can be automatically transferred to and from

on-chip memory via a dedicated DMA. Each of the serial ports

features a Time Division Multiplex (TDM) multichannel mode,

where two serial ports are TDM transmitters and two serial

ports are TDM receivers (SPORT0 Rx paired with SPORT2 Tx,

SPORT1 Rx paired with SPORT3 Tx). Each of the serial ports

also support the I²S protocol (an industry standard interface

commonly used by audio codecs, ADCs and DACs), with two

data pins, allowing four I²S channels (using two I²S stereo

devices) per serial port, with a maximum of up to 16 I²S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For I²S mode, data-word lengths are selectable between

8 bits and 32 bits. Serial ports offer selectable synchronization

and transmit modes as well as optional μ-law or A-law com-

panding. Serial port clocks and frame syncs can be internally or

externally generated.

48-BIT INSTRUCTION FETCH

(NO PACKING)

NOTE:

EXTRA DA TA LINES DATA15–0 ARE ONLY ACCESSIBLE IF LINK PORTS

ARE DISABLED. ENABLE THESE ADDITIONAL DATA LINKS BY SELECT-

ING IPACK1–0 = 01 IN SYSCON.

Figure 4. External Data Alignment Options

Multiprocessing

The ADSP-21161N offers powerful features tailored to

multiprocessing DSP systems. The external port and link ports

provide integrated glueless multiprocessing support.

The external port supports a unified address space (see Figure 3)

that enables direct interprocessor accesses of each ADSP-

21161N’s internal memory-mapped (I/O processor) registers.

All other internal memory can be indirectly accessed via DMA

transfers initiated via the programming of the IOP DMA

parameter and control registers. Distributed bus arbitration

logic is included on-chip for simple, glueless connection of sys-

tems containing up to six ADSP-21161Ns and a host processor

(Figure 5). Master processor change over incurs only one cycle

of overhead. Bus arbitration is selectable as either fixed or rotat-

ing priority. Bus lock enables indivisible read-modify-write

sequences for semaphores. A vector interrupt is provided for

interprocessor commands. Using an instruction rate of

110 MHz, maximum throughput for interprocessor data trans-

fer is 440M bytes/s over the external port.

Serial Peripheral (Compatible) Interface

Serial Peripheral Interface (SPI) is an industry standard syn-

chronous serial link, enabling the ADSP-21161N SPI-

compatible port to communicate with other SPI-compatible

devices. SPI is a 4-wire interface consisting of two data pins, one

device select pin, and one clock pin. It is a full-duplex synchro-

nous serial interface, supporting both master and slave modes.

The SPI port can operate in a multimaster environment by

interfacing with up to four other SPI-compatible devices, either

acting as a master or slave device. The ADSP-21161N SPI-com-

patible peripheral implementation also features programmable

baud rate and clock phase/polarities. The ADSP-21161N SPI-

compatible port uses open drain drivers to support a multimas-

ter configuration and to avoid data contention.

Two link ports provide a second method of multiprocessing

communications. Each link port can support communications

to another ADSP-21161N. The ADSP-21161N, running at

110 MHz, has a maximum throughput for interprocessor com-

munications over the links of 220M bytes/s. The link ports and

cluster multiprocessing can be used concurrently or

independently.

Host Processor Interface

Link Ports

The ADSP-21161N host interface enables easy connection to

standard 8-bit, 16-bit, or 32-bit microprocessor buses with little

additional hardware required. The host interface is accessed

through the ADSP-21161N’s external port. Four channels of

DMA are available for the host interface; code and data transfers

are accomplished with low software overhead. The host proces-

sor requests the ADSP-21161N’s external bus with the host bus

request (HBR), host bus grant (HBG), and chip select (CS) sig-

nals. The host can directly read and write the internal IOP

registers of the ADSP-21161N, and can access the DMA channel

The ADSP-21161N features two 8-bit link ports that provide

additional I/O capabilities. With the capability of running at

110 MHz, each link port can support 110M bytes/s. Link port

I/O is especially useful for point-to-point interprocessor com-

munication in multiprocessing systems. The link ports can

operate independently and simultaneously, with a maximum

data throughput of 220M bytes/s. Link port data is packed into

48- or 32-bit words and can be directly read by the core proces-

sor or DMA-transferred to on-chip memory. Each link port has

Rev. C

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ADSP-21161N

CLOCK

RESET

ADSP-21161N #4

ADSP-21161N #3

ADDR23-0

CLKIN

DATA47-16

RESET

3

ID2-0

CONTROL

ADSP-21161N #2

CLKIN

ADDR23-0

DATA47-16

RESET

2

ID2-0

CONTROL

ADDR

DATA

BOOT

EPROM

(OPTIONAL)

ADSP-21161N #1

CS

BMS

ADDR23-0

ADDR

DATA

CLKIN

GLOBAL

MEMORY

AND

DATA47-16

RD

RESET

OE

PERIPHERALS

(OPTIONAL)

1

ID2-0

WR

ACK

WE

ACK

CS

MS3-0

SBTS

CS

HOST

HBR

HBG

REDY

PROCESSOR

INTERFACE

(OPTIONAL)

ADDR

DATA

BR6-2

BR1

RAS

CAS

RAS

CAS

DQM

SDWE

DQM

WE

SDCLK1-0

CLK

SDCKE

CKE

SDRAM

(OPTIONAL)

SDA10

A10

CS

ADDR

DATA

Figure 5. Shared Memory Multiprocessing System

setup and message registers. DMA setup via a host would allow

it to access any internal memory address via DMA transfers.

Vector interrupt support provides efficient execution of host

commands.

The host processor interface can be used in either multiproces-

sor or single processor SHARC systems. For multiprocessor

systems, host access to the SHARC requires address pins

ADDR17, ADDR18, ADDR19, and ADDR20 to be driven low.

It is not enough to tie these pins to ground through a resistor

Rev. C

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ADSP-21161N

(for example 10k ohm). These pins must be driven low with a

strong enough drive strength (10–50 ohms) to overcome the

SHARC keeper latches present on these pins. If the drive

strength provided is not strong enough, data access failures can

occur.

10 ⍀

0.1␮F

AV_DD

V_DDINT

0.01␮F

AGND

For single processor SHARC systems using this host access fea-

ture, address pins ADDR17, ADDR18, ADDR19, and ADDR20

may be tied low (for example through a 10k ohm resistor),

driven low by a buffer/driver, or left floating. Any of these

options is sufficient.

Figure 6. Analog Power (AV_DD) Filter Circuit

DEVELOPMENT TOOLS

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore^®Embed-

ded Studio and/or VisualDSP++^®), evaluation products,

emulators, and a wide variety of software add-ins.

General-Purpose I/O Ports

The ADSP-21161N also contains 12 programmable, general

purpose I/O pins that can function as either input or output. As

output, these pins can signal peripheral devices; as input, these

pins can provide the test for conditional branching.

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

Program Booting

The newest IDE, CrossCore Embedded Studio, is based on the

The internal memory of the ADSP-21161N can be booted at

system power-up from either an 8-bit EPROM, a host processor,

the SPI interface, or through one of the link ports. Selection of

the boot source is controlled by the Boot Memory Select (BMS),

EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins.

8-, 16-, or 32-bit host processors can also be used for booting.

TM

Eclipse framework. Supporting most Analog Devices proces-

sor families, it is the IDE of choice for future processors,

including multicore devices. CrossCore Embedded Studio

seamlessly integrates available software add-ins to support real

time operating systems, file systems, TCP/IP stacks, USB stacks,

algorithmic software modules, and evaluation hardware board

support packages. For more information visit

Phase-Locked Loop and Crystal Double Enable

www.analog.com/cces.

The ADSP-21161N uses an on-chip phase-locked loop (PLL) to

generate the internal clock for the core. The CLK_CFG1–0 pins

are used to select ratios of 2:1, 3:1, and 4:1. In addition to the

PLL ratios, the CLKDBL pin can be used for more clock ratio

options. The (1/2 CLKIN) rate set by the CLKDBL

pin determines the rate of the PLL input clock and the rate at

which the external port operates. With the combination of

CLK_CFG1–0 and CLKDBL, ratios of 2:1, 3:1, 4:1, 6:1, and 8:1

between the core and CLKIN are supported. See also Figure 8

on Page 20.

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite^®evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders^®, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

Power Supplies

The ADSP-21161N has separate power supply connections for

the analog (AV_DD/AGND), internal (V_DDINT), and external

(V_DDEXT) power supplies. The internal and analog supplies must

meet the 1.8 V requirement. The external supply must meet the

3.3 V requirement. All external supply pins must be connected

to the same supply.

Note that the analog supply (AV_DD) powers the ADSP-21161N’s

clock generator PLL. To produce a stable clock, provide an

external circuit to filter the power input to the AV_DDpin. Place

the filter as close as possible to the pin. The AV_DDfilter circuit

shown in Figure 6 must be added for each ADSP-21161N in the

multiprocessor system. To prevent noise coupling, use a wide

trace for the analog ground (AGND) signal and install a decou-

pling capacitor as close as possible to the pin.

EZ-KIT Lite Evaluation Kits

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Rev. C

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ADSP-21161N

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the

ADSP-21161N architecture and functionality. For detailed

information on the ADSP-2116x Family core architecture and

instruction set, refer to the ADSP-21161 SHARC DSP Hardware

Reference and the ADSP-21160 SHARC DSP Instruction Set

Reference.

Board Support Packages for Evaluation Hardware

RELATED SIGNAL CHAINS

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in

Wikipedia or the Glossary of EE Terms on the Analog Devices

website.

Middleware Packages

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

• www.analog.com/ucos3

• www.analog.com/ucfs

• www.analog.com/ucusbd

• www.analog.com/lwip

The Application Signal Chains page in the Circuits from the

TM

Lab site (http://www.analog.com/signal chains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com and

search on “Blackfin software modules” or “SHARC software

modules”.

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

Rev. C

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ADSP-21161N

PIN FUNCTION DESCRIPTIONS

ADSP-21161N pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-

tified as asynchronous (A) can be asserted asynchronously to

CLKIN (or to TCK for TRST). Tie or pull unused inputs to

The following symbols appear in the Type column of Table 2:

A = Asynchronous, G = Ground, I = Input, O = Output,

P = Power Supply, S = Synchronous, (A/D) = Active Drive,

(O/D) = Open Drain, and T = Three-State (when SBTS is

asserted or when the ADSP-21161N is a bus slave).

V_DDEXTor GND, except for the following:

Unlike previous SHARC processors, the ADSP-21161N con-

tains internal series resistance equivalent to 50  on all

input/output drivers except the CLKIN and XTAL pins.

Therefore, for traces longer than six inches, external series resis-

tors on control, data, clock, or frame sync pins are not required

to dampen reflections from transmission line effects for point-

to-point connections. However, for more complex networks

such as a star configuration, series termination is still

recommended.

• ADDR23–0, DATA47–0, BRST, CLKOUT (Note: These

pins have a logic-level hold circuit enabled on the

ADSP-21161N DSP with ID2–0 = 00x.)

• PA, ACK, RD, WR, DMARx, DMAGx, (ID2–0 = 00x)

(Note: These pins have a pull-up enabled on the

ADSP-21161N DSP with ID2–0 = 00x.)

• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note: See

Link Port Buffer Control Register Bit definitions in the

ADSP-21161N SHARC DSP Hardware Reference.)

• DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU,

TMS,TRST, TDI (Note: These pins have a pull-up.)

Table 2. Pin Function Descriptions

Type

Function

ADDR23–0

I/O/T

External Bus Address. The ADSP-21161N outputs addresses for external memory and peripherals on these

pins. In a multiprocessor system the bus master outputs addresses for read/writes of the IOP registers of other

ADSP-21161Ns while all other internal memory resources can be accessed indirectly via DMA control (that

is, accessing IOP DMA parameter registers). The ADSP-21161N inputs addresses when a host processor or

multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the DSP’s ADDR23-0 pins

maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with

ID2–0=00x.

DATA47–16

I/O/T

External Bus Data. The ADSP-21161N inputs and outputs data and instructions on these pins. Pull-up

resistors on unused data pins are not necessary. A keeper latch on the DSP’s DATA47–16 pins maintains the

input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2–0=00x.

Note: DATA15–8 pins (multiplexed with L1DAT7–0) can also be used to extend the data bus if the link ports are

disabled and will not be used. In addition, DATA7–0 pins (multiplexed with L0DAT7–0) can also be used to extend

the data bus if the link ports are not used. This enables execution of 48-bit instructions from external SBSRAM

(system clock speed-external port), SRAM (system clock speed-external port) and SDRAM (core clock or one-half

the core clock speed). The IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1–0=0x1)

to enable this full instruction Width/No-packing Mode of operation.

MS3–0

I/O/T

Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of

external memory. Memory bank sizes are fixed to 16 M words for non-SDRAM and 64M words for SDRAM.

The MS3–0 outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs

transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert with the

other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted. In a

multiprocessor system, the MSx signals are tracked by slave SHARCs.

RD

I/O/T

Memory Read Strobe. RD is asserted whenever ADSP-21161N reads a word from external memory or from

the IOP registers of other ADSP-21161Ns. External devices, including other ADSP-21161Ns, must assert RD

for reading from a word of the ADSP-21161N IOP register memory. In a multiprocessing system, RD is driven

by the bus master. RD has a 20 k internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

Memory Write Low Strobe. WR is asserted when ADSP-21161N writes a word to external memory or IOP

registers of other ADSP-21161Ns. External devices must assert WR for writing to ADSP-21161N IOP registers.

In a multiprocessing system, the bus master drives WR. WRhas a 20 kinternal pull-up resistor that is enabled

for DSPs with ID2–0=00x.

WR

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ADSP-21161N

Table 2. Pin Function Descriptions (Continued)

Type

Function

BRST

I/O/T

SequentialBurstAccess. BRSTisassertedbyADSP-21161Ntoindicatethatdataassociatedwithconsecutive

addresses is being read or written. A slave device samples the initial address and increments an internal

address counter after each transfer. The incremented address is not pipelined on the bus. A master ADSP-

21161N in a multiprocessor environment can read slave external port buffers (EPBx) using the burst protocol.

BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for

the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch on the DSP’s

BRST pin maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N

with ID2–0=00x.

ACK

I/O/S

I/S

Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to an external memory

access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an

external memory access. The ADSP-21161N deasserts ACK as an output to add wait states to a synchronous

access of its IOP registers. ACK has a 20 k internal pull-up resistor that is enabled during reset or on DSPs

with ID2–0=00x.

SBTS

Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus address,

data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21161N attempts to

access external memory while SBTS is asserted, the processor will halt and the memory access will not be

completed until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21161N

deadlock.

CAS

I/O/T

O/T

SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10,

defines the operation for the SDRAM to perform.

RAS

SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines

the operation for the SDRAM to perform.

SDWE

DQM

SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes SDA10, defines the

operation for the SDRAM to perform.

SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a precharge command

and during SDRAM power-up initialization.

SDCLK0

SDCLK1

I/O/S/T

O/S/T

SDRAM Clock Output 0. Clock for SDRAM devices.

SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices,

handles the increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or

both SDCLKx pins can be three-stated.

SDCKE

SDA10

IRQ2–0

FLAG11–0

TIMEXP

HBR

I/O/T

O/T

I/A

SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet supplied with the

SDRAM device.

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-SDRAM accesses or host

accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edge-triggered

or level-sensitive.

I/O/A

O

Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested as a

condition. As an output, it can be used to signal external peripherals.

Timer Expired. Asserted for four core clock cycles when the timer is enabled and TCOUNT decrements to

zero.

I/A

Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21161N’s external

bus. When HBR is asserted in a multiprocessing system, the ADSP-21161N that is bus master will relinquish

the bus and assert HBG. To relinquish the bus, the ADSP-21161N places the address, data, select, and strobe

lines in a high impedance state. HBR has priority over all ADSP-21161N bus requests (BR6–1) in a multipro-

cessing system.

HBG

CS

I/O

I/A

Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of

the external bus. HBG is asserted (held low) by the ADSP-21161N until HBR is released. In a multiprocessing

system, HBG is output by the ADSP-21161N bus master and is monitored by all others.

After HBR is asserted, and before HBG is given, HBG will float for 1 t_CK(1 CLKIN cycle). To avoid erroneous

grants, HBG should be pulled up with a 20 k to 50 k external resistor.

Chip Select. Asserted by host processor to select the ADSP-21161N.

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ADSP-21161N

Table 2. Pin Function Descriptions (Continued)

Type

Function

REDY

O (O/D)

Host Bus Acknowledge. The ADSP-21161N deasserts REDY (low) to add wait states to a host access of its

IOP registers when CS and HBR inputs are asserted.

DMAR1

DMAR2

DMAG1

I/A

O/T

DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has

a 20 k internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has

a 20 k internal pull-up resistor that is enabled for DSPs with ID2–0=00x.

DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21161N to indicate that the requested DMA starts on the

next cycle. Driven by bus master only. DMAG1 has a 20 k internal pull-up resistor that is enabled for DSPs

with ID2–0=00x.

DMAG2

BR6–1

O/T

DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21161N to indicate that the requested DMA starts on the

next cycle. Driven by bus master only. DMAG2 has a 20 k internal pull-up resistor that is enabled for DSPs

with ID2–0=00x.

I/O/S

Multiprocessing Bus Requests. Used by multiprocessing ADSP-21161Ns to arbitrate for bus mastership. An

ADSP-21161N only drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all

others. In a multiprocessor system with less than six ADSP-21161Ns, the unused BRx pins should be pulled

high; the processor's own BRx line must not be pulled high or low because it is an output.

BMSTR

ID2–0

O

I

Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21161N is current bus master

of the shared external bus. The ADSP-21161N drives BMSTR high only while it is the bus master. In a single-

processor system (ID=000), the processor drives this pin high. This pin is used for debugging purposes.

Multiprocessing ID. Determines which multiprocessing bus request (BR6–BR1) is used by ADSP-21161N.

ID=001 corresponds to BR1, ID=010 corresponds to BR2, and so on. Use ID=000 or ID=001 in single-

processorsystems. Theselinesareasystemconfigurationselectionthatshouldbehardwiredoronlychanged

at reset.

RPBA

PA

I/S

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus

arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration

selection that must be set to the same value on every ADSP-21161N. If the value of RPBA is changed during

system operation, it must be changed in the same CLKIN cycle on every ADSP-21161N.

I/O/T

Priority Access. Asserting its PA pin enables an ADSP-21161N bus slave to interrupt background DMA

transfers and gain access to the external bus. PA is connected to all ADSP-21161Ns in the system. If access

priority is not required in a system, the PA pin should be left unconnected. PA has a 20 k internal pull-up

resistor that is enabled for DSPs with ID2–0=00x.

DxA

DxB

I/O

Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an internal pull-up resistor.

Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to

receive serial data.

Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an internal pull-up resistor.

Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to

receive serial data.

SCLKx

FSx

I/O

Transmit/Receive Serial Clock (Serial Ports 0, 1, 2, 3). Each SCLK pin has an internal pull-up resistor. This

signal can be either internally or externally generated.

Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates shifting of serial data.

This signal is either generated internally or externally. It can be active high or low or an early or a late frame

sync, in reference to the shifting of serial data.

SPICLK

I/O

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is

transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit trans-

mitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word.

Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift

out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge

of the clock and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data

are programmable into the SPICTL control register and define the transfer format. SPICLK has a 50 kinternal

pull-up resistor.

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ADSP-21161N

Table 2. Pin Function Descriptions (Continued)

Type

Function

SPIDS

I

SerialPeripheral InterfaceSlaveDeviceSelect. Anactivelowsignalusedto enableslavedevices. Thisinput

signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster

mode SPIDS signal can be asserted to a master device to signal that an error has occurred, as some other

deviceisalsotrying to bethe masterdevice. If assertedlow when thedeviceisin mastermode, it isconsidered

a multimaster error. For a single-master, multiple-slave configuration where FLAG3–0 are used, this pin must

be tied or pulled high to V_DDEXTon the master device. For ADSP-21161N to ADSP-21161N SPI interaction, any

of the master ADSP-21161N’s FLAG3–0 pins can be used to drive the SPIDS signal on the ADSP-21161N SPI

slave device.

MOSI

MISO

I/O (o/d)

SPI Master Out Slave. If the ADSP-21161N is configured as a master, the MOSI pin becomes a data transmit

(output) pin, transmitting output data. If the ADSP-21161N is configured as a slave, the MOSI pin becomes a

data receive (input) pin, receiving input data. In an ADSP-21161N SPI interconnection, the data is shifted out

from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal

pull-up resistor.

SPI Master In Slave Out. If the ADSP-21161N is configured as a master, the MISO pin becomes a data receive

(input) pin, receiving input data. If the ADSP-21161N is configured as a slave, the MISO pin becomes a data

transmit (output) pin, transmitting output data. In an ADSP-21161N SPI interconnection, the data is shifted

out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has an

internal pull-up resistor. MISO can be configured as o/d by setting the OPD bit in the SPICTL register.

Note: Only one slave is allowed to transmit data at any given time.

LxDAT7–0

I/O

Link Port Data (Link Ports 0–1).

[DATA15–0]

[I/O/T]

For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when used as a data

pin; or a 20 k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.

For silicon revisions 0.3, 1.0, and 1.1 each LxDAT pin has a 50 k internal pull-down resistor that is enabled

or disabled by the LxPDRDE bit of the LCTL register.

Note: L1DAT7–0 are multiplexed with the DATA15–8 pins L0DAT7–0 are multiplexed with the DATA7–0 pins. If link

ports are disabled and are not used, these pins can be used as additional data lines for executing instructions at

up to the full clock rate from external memory. See DATA47–16 for more information.

LxCLK

LxACK

EBOOT

LBOOT

BMS

I/O

Link Port Clock (Link Ports 0–1). Each LxCLK pin has an internal pull-down 50 k resistor that is enabled or

disabled by the LxPDRDE bit of the LCTL register.

I/O

Link Port Acknowledge (Link Ports 0–1). Each LxACK pin has an internal pull-down 50 k resistor that is

enabled or disabled by the LxPDRDE bit of the LCTL register.

I

EPROM Boot Select. For a description of how this pin operates, see the table in the BMS pin description. This

signal is a system configuration selection that should be hardwired.

I

Link Boot. For a description of how this pin operates, see the table in the BMS pin description. This signal is

a system configuration selection that should be hardwired.

I/O/T

Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins (see Table 4).

This input is a system configuration selection that should be hardwired. For Host and PROM boot, DMA

channel 10 (EPB0) is used. For Link boot and SPI boot, DMA channel 8 is used.

Three-state only in EPROM boot mode (when BMS is an output).

CLKIN

I

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161N clock input. It configures the ADSP-

21161N to use either its internal clock generator or an external clock source. Connecting the necessary

components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN

while leaving XTAL unconnected configures the ADSP-21161N to use the external clock source such as an

external clock oscillator.The ADSP-21161N external port cycles at the frequency of CLKIN. The instruction

cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up via the CLK_CFG1–0 pins.

CLKIN may not be halted, changed, or operated below the specified frequency.

XTAL

O

I

Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP-21161N’s internal clock

oscillator or to disable it to use an external clock source. See CLKIN.

CLK_CFG1-0

Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate is equal to n  PLLICLK where

n is user selectable to 2, 3, or 4, using the CLK_CFG1–0 inputs. These pins can also be used in combination

with the CLKDBL pin to generate additional core clock rates of 6  CLKIN and 8  CLKIN (see the Clock Rate

Ratios table in the CLKDBL description).

Rev. C

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January 2013

ADSP-21161N

Table 2. Pin Function Descriptions (Continued)

Type

Function

CLKDBL

I

Crystal Double Mode Enable. This pin is used to enable the 2 clock double circuitry, where CLKOUT can

be configured as either 1 or 2 the rate of CLKIN. This CLKIN double circuit is primarily intended to be used

for an external crystal in conjunction with the internal clock generator and the XTAL pin. The internal clock

generator when used in conjunction with the XTAL pin and an external crystal is designed to support up to

a maximum of 27.5 MHz external crystal frequency. CLKDBL can be used in XTAL mode to generate a 55 MHz

input into the PLL. The 2 clock mode is enabled (during RESET low) by tying CLKDBL to GND, otherwise it is

connected to V_DDEXTfor 1 clock mode. For example, this enables the use of a 27.5 MHz crystal to enable 110

MHz core clock rates and a 55 MHz CLKOUT operation when CLK_CFG0=0, CLK_CFG1=0 and CLKDBL=0.

This pin can also be used to generate different clock rate ratios for external clock oscillators as well. The

possible clock rate ratio options (up to 110 MHz) for either CLKIN (external clock oscillator) or XTAL (crystal

input) are shown in Table 3 on Page 16. An 8:1 ratio enables the use of a 12.5 MHz crystal to generate a 100

MHzcore(instructionclock)rateanda25MHzCLKOUT(externalport)clockrate. Seealso Figure 8onPage 20.

Note: When using an external crystal, the maximum crystal frequency cannot exceed 27.5 MHz. For all other

external clock sources, the maximum CLKIN frequency is 55 MHz.

CLKOUT

O/T

Local Clock Out. CLKOUT is 1 or 2 and is driven at either 1 or 2 the frequency of CLKIN frequency by the

current bus master. The frequency is determined by the CLKDBL pin. This output is three-stated when the

ADSP-21161N is not the bus master or when the host controls the bus (HBG asserted). A keeper latch on the

DSP’s CLKOUT pin maintains the output at the level it was last driven. This latch is only enabled on the ADSP-

21161N with ID2–0=00x.

If CLKDBL enabled, CLKOUT=2 CLKIN

If CLKDBL disabled, CLKOUT=1 CLKIN

Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1 CLKIN or 2  CLKIN.

Do not use CLKOUT in multiprocessing systems. Use CLKIN instead.

RESET

I/A

O

Processor Reset. Resets the ADSP-21161N to a known state and begins execution at the program memory

location specified by the hardware reset vector address. The RESET input must be asserted (low) at power-up.

RSTOUT¹

Reset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in reset. It is deasserted

4080 cycles after RESET is deasserted indicating that the PLL is stable and locked.

TCK

TMS

TDI

I

Test Clock (JTAG). Provides a clock for JTAG boundary scan.

I/S

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up

resistor.

TDO

TRST

O

Test Data Output (JTAG). Serial scan output of the boundary scan path.

I/A

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held

low for proper operation of the ADSP-21161N. TRST has a 20 k internal pull-up resistor.

EMU

O (O/D)

Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools product line of JTAG

emulators target board connector only. EMU has a 50 k internal pull-up resistor.

V_DDINT

V_DDEXT

AVDD

P

Core Power Supply. Nominally +1.8 V dc and supplies the DSP’s core processor (14 pins).

I/O Power Supply. Nominally +3.3 V dc. (13 pins).

Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock generator). This pin

has the same specifications as V_DDINT, except that added filtering circuitry is required. For more information,

see Power Supplies on Page 9.

AGND

GND

NC

G

Analog Power Supply Return.

Power Supply Return. (26 pins).

Do Not Connect. Reserved pins that must be left open and unconnected. (4 pins)

¹RSTOUT exists only for silicon revisions 1.2 and greater.

Rev. C

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ADSP-21161N

Table 3. Clock Rate Ratios

CLKDBL

CLK_CFG1

CLK_CFG0

Core:CLKIN

CLKIN:CLKOUT

1

0

1

0

1

0

1

0

1

0

2:1

3:1

4:1

6:1

8:1

1:1

1

1:2

BOOT MODES

Table 4. Boot Mode Selection

EBOOT

LBOOT

BMS

Booting Mode

1

0

1

0

1

0

1

Output

1 (Input)

0 (Input)

1 (Input)

0 (Input)

x (Input)

EPROM (Connect BMS to EPROM chip select.)

Host Processor

Serial Boot via SPI

Link Port

No Booting. Processor executes from external memory.

Reserved

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January 2013

ADSP-21161N

SPECIFICATIONS

OPERATING CONDITIONS

100 MHz

Max

110 MHz

Parameter¹Description

Test Conditions

Min

Max

Unit

V_DDINT

AV_DD

V_DDEXT

V_IH

Internal (Core) Supply Voltage

1.71

3.13

2.0

1.89

3.47

1.71

3.13

2.0

1.89

V

Analog (PLL) Supply Voltage

External (I/O) Supply Voltage

High Level Input Voltage²

Low Level Input Voltage²

1.89

V

3.47

V

@ V_DDEXT= Max

@ V_DDEXT= Min

V_DDEXT+0.5

+0.8

V

V_IL

–0.5

–40

+0.8

–0.5

–40

V

T_CASE

Case Operating Temperature³

+105

+125

C

¹Specifications subject to change without notice.

²Applies to input and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, DMAR1, DMAR2, BR6–1, ID2–0,

RPBA, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE,

CLK_CFGx, CLKDBL, CLKIN, RESET, TRST, TCK, TMS, TDI.

³See Thermal Characteristics on Page 55 for information on thermal specifications.

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January 2013

ADSP-21161N

ELECTRICAL CHARACTERISTICS

Parameter Description

Test Conditions

Min

Max

Unit

V_OH

V_OL

I_IH

I_IL

I_IHC

I_ILC

I_IKH

I_IKL

I_IKH-OD

I_IKL-OD

I_ILPU

I_OZH

I_OZL

I_OZLPU1

I_OZLPU2

I_OZHPD1

I_OZHPD2

I_DD-INPEAK

High Level Output Voltage¹

@ V_DDEXT= Min, I_OH= –2.0 mA²

@ V_DDEXT= Min, I_OL= 4.0 mA²

@ V_DDEXT= Max, V_IN= V_DDEXTMax

@ V_DDEXT= Max, V_IN= 0 V

@ V_DDEXT= Max, V_IN= V_DDEXTMax

@ V_DDEXT= Max, V_IN= 0 V

@ V_DDEXT= Max, V_IN= 2.0 V

@ V_DDEXT= Max, V_IN= 0.8 V

@ V_DDEXT= Max

2.4

V

Low Level Output Voltage¹

0.4

10

35

High Level Input Current^{3, 4}

Low Level Input Current³

μA

mA

CLKIN High Level Input Current⁵

CLKIN Low Level Input Current⁵

Keeper High Load Current⁶

–250

50

–300

300

–100

200

Keeper Low Load Current⁶

Keeper High Overdrive Current^{6, 7, 8}

Keeper Low Overdrive Current^{6, 7, 8}

Low Level Input Current Pull-Up⁴

Three-State Leakage Current^{9, 10, 11}

Three-State Leakage Current^{9, 12, 13}

Three-State Leakage Current Pull-Up1¹⁰

Three-State Leakage Current Pull-Up2¹¹

Three-State Leakage Current Pull-Down1¹²

Three-State Leakage Current Pull-Down2¹³

Supply Current (Internal)^{14, 15}

@ V_DDEXT= Max

@ V_DDEXT= Max, V_IN= 0 V

@ V_DDEXT= Max, V_IN= V_DDEXTMax

@ V_DDEXT= Max, V_IN= 0 V

@ V_DDEXT= Max, V_IN= V_DDEXTMax

t_CCLK= 9.0 ns, V_DDINT= Max

350

10

500

350

500

965

900

t

_CCLK= 10.0 ns, V_DDINT= Max

t_CCLK= 9.0 ns, V_DDINT= Max

_CCLK= 10.0 ns, V_DDINT= Max

t_CCLK= 9.0 ns, V_DDINT= Max

_CCLK= 10.0 ns, V_DDINT= Max

t_CCLK= 9.0 ns, V_DDINT= Max

_CCLK= 10.0 ns, V_DDINT= Max

I_DD-INHIGH

I_DD-INLOW

I_DD-IDLE

Supply Current (Internal)^{15, 16}

Supply Current (Internal)^{15, 17}

Supply Current (Idle)^{15, 18}

700

650

mA

t

535

500

t

425

400

t

AI_DD

C_IN

Supply Current (Analog)¹⁹

Input Capacitance^{20, 21}

@ AV_DD= Max

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 1.8 V

10

4.7

mA

pF

1

Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,

BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL,

TDO, CLKOUT, TIMEXP, RSTOUT.

²See Output Drive Currents on Page 54 for typical drive current capabilities.

³Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE,

SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN.

⁴Applies to input pins with 20 k internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.

⁵Applies to CLKIN only.

⁶Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.

⁷Current required to switch from kept high to low or from kept low to high.

⁸Characterized, but not tested.

⁹Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10,

BRST.

¹⁰Applies to three-statable pins with 20 kpull-ups: RD, WR, DMAG1, DMAG2, PA.

¹¹Applies to three-statable pins with 50 k internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI.

¹²Applies to three-statable pins with 50 k internal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use I_OZHPD2for Rev. 1.2 and higher.

¹³Applies to three-statable pins with 20 k internal pull-downs: LxDAT7-0 (Revision 1.2 and higher).

¹⁴The test program used to measure I_DDINPEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power

measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 20.

¹⁵Current numbers are for V_DDINTand AVDD supplies combined.

16

I

is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 20.

is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 20.

DDINHIGH

17

DDINLOW

¹⁸Idle denotes ADSP-21161N state during execution of IDLE instruction. For more information, see Power Dissipation on Page 20.

¹⁹Characterized, but not tested.

²⁰Applies to all signal pins.

²¹Guaranteed, but not tested.

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January 2013

ADSP-21161N

PACKAGE INFORMATION

ESD CAUTION

The information presented in Figure 7 provides details about

how to read the package brand and relate it to specific product

features.

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

a

ADSP-21161N

tppZ-cc

vvvvvv.x n.n

TIMING SPECIFICATIONS

#yyww country_of_origin

The ADSP-21161N’s internal clock switches at higher frequen-

cies than the system input clock (CLKIN). To generate the

internal clock, the DSP uses an internal phase-locked loop

(PLL). This PLL-based clocking minimizes the skew between

the system clock (CLKIN) signal and the DSP’s internal clock

(the clock source for the external port logic and I/O pads).

S

Figure 7. Typical Package Brand

Table 5. Package Brand Information

The ADSP-21161N’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, link ports, serial ports, and external port (as required for

read/write strobes in asynchronous access mode). During reset,

program the ratio between the DSP’s internal clock frequency

and external (CLKIN) clock frequency with the CLK_CFG1–0

and CLKDBL pins. Even though the internal clock is the clock

source for the external port, it behaves as described in the Clock

Rate Ratio chart in Table 3 on Page 16. To determine switching

frequencies for the serial and link ports, divide down the inter-

nal clock, using the programmable divider control of each port

(DIVx for the serial ports and LxCLKD for the link ports).

Brand Key

Field Description

Model Number

ADSP-21161N

t

Temperature Range

Package Type

pp

z

RoHS Compliance Option

Assembly Lot Code

Silicon Revision

vvvvv.x

n.n

#

RoHS Compliance Designation

Date Code

yyww

Note the following definitions of various clock periods that are a

function of CLKIN and the appropriate ratio control (Table 7).

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 6 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Figure 8 enables Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1, and

8:1 with external oscillator or crystal. It also shows support for

CLKOUT-to-CLKIN ratios of 1:1 and 2:1.

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times.

Table 6. Absolute Maximum Ratings

Parameter

Rating

See Figure 37 on Page 54 under Test Conditions for voltage ref-

erence levels.

Internal (Core) Supply Voltage (V_DDINT

)

–0.3 V to +2.2 V

–0.3 V to +4.6 V

–0.5 V to V_DDEXT+ 0.5 V

200 pF

Analog (PLL) Supply Voltage (A_VDD

)

Switching characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given circum-

stance. Use switching characteristics to ensure that any timing

requirement of a device connected to the processor (such as

memory) is satisfied.

External (I/O) Supply Voltage (V_DDEXT

)

Input Voltage

Output Voltage Swing

Load Capacitance

Storage Temperature Range

–65C to +150C

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Rev. C

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January 2013

ADSP-21161N

CORE

I/O PROCESSOR

SYNCHRONOUS EP

ASYNCHRONOUS EP

HARDWARE

INTERRUPT

I/O FLAG

MULTIPROCESSING

SBSRAM

HOST

SRAM

TIMER

LINK PORTS

x1, x1/2, x1/3, x1/4

SDRAM

x1, x1/2

CLKIN

(CRYSTAL OSCILLATOR

4.2–55 MHz)

SERIAL PORTS

x1/2 MAX

CLOCK DOUBLER

RATIOS

x2, x3, x4

x1, x2

XTAL

(QUARTZ CRYSTAL

27.5 MHz MAX)

PLL

SPI

x1/8 MAX

CLKOUT

CLK_CFG1–0

CLKDBL

Figure 8. Core Clock and System Clock Relationship to CLKIN

Table 7. CLKOUT and CCLK Clock Generation Operation

Timing Requirements

Description¹

Calculation

CLKIN

CLKOUT

PLLICLK

CCLK

t_CK

Input Clock

1/t_CK

External Port System Clock

PLL Input Clock

1/t_CKOP

1/t_PLLIN

Core Clock

1/t_CCLK

CLKIN Clock Period

(Processor) Core Clock Period

Link Port Clock Period

Serial Port Clock Period

SDRAM Clock Period

SPI Clock Period

1/CLKIN

1/CCLK

t_CCLK

t_LCLK

(t_CCLK) LR

(t_CCLK)  SR

(t_CCLK)  SDCKR

(t_CCLK)  SPIR

t_SCLK

t_SDK

t_SPICLK

¹where:

LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD)

SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)

SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register)

LCLK = Link Port Clock

SCLK = Serial Port Clock

SDK = SDRAM Clock

SPICLK = SPI Clock

POWER DISSIPATION

Total power dissipation has two components: one due to inter-

nal circuitry and one due to the switching of external output

drivers.

Internal power dissipation depends on the instruction execution

sequence and the data operands involved. Using the current

specifications (I_DDINPEAK, I_DDINHIGH, I_DDINLOW, I_DDIDLE) from the

Electrical Characteristics on Page 18 and the current-versus-

operation information in Table 8, the programmer can estimate

the ADSP-21161N’s internal power supply (V_DDINT) input cur-

rent for a specific application, according to the following

formula:

% Peak  I_DD

-

INPEAK

% High  I_DD

-

INHIGH

% Low  I_DD

-

INLOW

+ % Peak  I_DD

-

IDLE

= I_DDINT

Rev. C

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January 2013

ADSP-21161N

Table 8. Operation Types Versus Input Current

Operation

Peak Activity¹(I_DDINPEAK

Multifunction

Cache

)

High Activity¹(I_DDINHIGH

Multifunction

)

Low Activity¹(I_DDINLOW

)

Instruction Type

Single Function

Instruction Fetch

Core Memory Access²

Internal Memory DMA

External Memory DMA

Internal Memory

2 per t_CKcycle (DM64 and PM64)

1 per 2 t_CCLKcycles

1 per t_CKcycle (DM64)

1 per 2 t_CCLKcycles

None

N/A

1 per external port cycle (32)

Worst case

1 per external port cycle (32)

Random

N/A

Data bit pattern for core

memory access and DMA

N/A

¹The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.

²These assume a 2:1 core clock ratio. For more information on ratios and clocks (t_CKand t_CCLK), see the timing ratio definitions on Page 19.

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• The bus cycle time is 55 MHz

• The external SDRAM clock rate is 110 MHz

• Ignoring SDRAM refresh cycles

• The number of output pins that switch during each cycle

(O)

• Addresses are incremental and on the same page

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

The P_EXTequation is calculated for each class of pins that can

drive, as shown in Table 9.

• Their voltage swing (V_DD

)

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

and is calculated by:

2

P

= O  C  V

 f

P

= P

+ P

EXT

DD

TOTAL

EXT

INT

PLL

The load capacitance should include the processor package

capacitance (C_IN). The switching frequency includes driving the

Where:

P

_EXTis from Table 9.

_INTis I_DDINT× 1.8 V, using the calculation I_DDINTlisted in Power

load high and then back low. At a maximum rate of 1/t_CK

,

address and data pins can drive high and low, while writing to a

SDRAM memory.

Dissipation on Page 20.

P

_PLLis AI_DD× 1.8 V, using the value for AI_DDlisted in the Electri-

Example: Estimate P_EXTwith the following assumptions:

cal Characteristics on Page 18.

• A system with one bank of external memory (32 bit)

Note that the conditions causing a worst-case P_EXTare different

from those causing a worst-case P_INT. Maximum P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching

simultaneously.

• Two 1M

؋

16 SDRAM chips are used, each with a load of

10 pF (ignoring trace capacitance)

• External Data Memory writes can occur every cycle at a

rate of 1/t_CKwith 50% of the pins switching

Table 9. External Power Calculations—110 MHz Instruction Rate

2

Pin Type

Address

MSx

Number of Pins

% Switching

؋

C

؋

f

؋

V_DD

10.9 V

= P_EXT

11

4

20

0

24.7 pF

14.7 pF

24.7 pF

55 MHz

N/A

= 0.033 W

= 0.000 W

= 0.141 W

= 0.030 W

_EXT= 0.204 W

SDWE

1

0

N/A

Data

32

1

50

100

55 MHz

110 MHz

SDCLK0

P

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January 2013

ADSP-21161N

protection circuitry. With this technique, if the 1.8 V rail rises

ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail

along with the 1.8 V rail.

Power-Up Sequencing — Silicon Revision 1.2 and Greater

The timing requirements for DSP startup are given in Table 10.

During the power-up sequence of the DSP, differences in the

ramp-up rates and activation time between the two supplies can

cause current to flow in the I/O ESD protection circuitry. To

prevent damage to the ESD diode protection circuitry, Analog

Devices recommends including a bootstrap Schottky diode.

DC INPUT

SOURCE

3.3V I/O

VOLTAGE

V_DDEXT

REGULATOR

ADSP-21161N

The bootstrap Schottky diode is connected between the 1.8 V

and 3.3 V power supplies as shown in Figure 9. It protects the

ADSP-21161N from partially powering the 3.3 V supply.

Including a Schottky diode will shorten the delay between

the supply ramps and thus prevent damage to the ESD diode

1.8V CORE

VOLTAGE

REGULATOR

V_DDINT

Figure 9. Dual Voltage Schottky Diode

Table 10. Power-Up Sequencing Silicon Revision 1.2 and Greater (DSP Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

t_IVDDEVDD

t_CLKVDD

t_CLKRST

t_PLLRST

t_WRST

RESET Low Before V_DDINT/V_DDEXTon

V_DDINTon Before V_DDEXT

CLKIN Valid After V_DDINT/V_DDEXTValid¹

CLKIN Valid Before RESET Deasserted²

PLL Control Setup Before RESET Deasserted³

Subsequent RESET Low Pulsewidth⁴

0

ns

ms

μs

ns

–50

0

+200

200

10

20

4t_CK

Switching Requirements

3, 5

t_CORERSTDSP core reset deasserted after RESET deasserted

4080t_CK

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles.

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4080 cycle count depends on t_SRSTspecification in Table 12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in

4081 cycles maximum.

RESET

t_RSTVDD

VDDINT

t_IVDDEVDD

VDDEXT

t_CLKRST

t_CLKVDD

CLKIN

CLKDBL

CLK_CFG1-0

t_PLLRST

t_CORERST

RSTOUT

Figure 10. Power-Up Sequencing for Silicon Revision 1.2 and Greater (DSP Startup)

Rev. C

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January 2013

ADSP-21161N

Clock Input

In systems that use multiprocessing or SBSRAM, CLKDBL can-

not be enabled nor can the systems use an external crystal as the

CLKIN source.

Do not use CLKOUT as the clock source for the SBSRAM

device. Using an external crystal in conjunction with CLKDBL

to generate a CLKOUT frequency is not supported. Negative

hold times can result from the potential skew between CLKIN

and CLKOUT.

Table 11. Clock Input

100 MHz

110 MHz

Unit

Parameter

Min

Max

Min

Max

Timing Requirements

t_CK

CLKIN Period¹

20

238

119

3

18

7

238

119

3

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low¹

CLKIN Width High¹

CLKIN Rise/Fall (0.4 V–2.0 V)

CCLK Period

7.5

7

10

30

9

30

Switching Characteristics

t_DCKOOCLKOUT Delay After CLKIN

0

2

0

2

ns

t_CKOP

CLKOUT Period

t_CK–1

t_CK+1

t_CK–1

t_CK+1

t_CKWHCLKOUT Width High

t_CKWLCLKOUT Width Low

t_CKOP/2–2

t_CKOP/2+2

t_CKOP/2–2

t_CKOP/2+2

¹CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired t_CCLK

.

t_CK

CLKIN

t_CKH

t_CKL

1

t_CKOP

t_DCKOO

1

t_CKWH

t_CKWL

CLKOUT

2

t_DCKOO

2

t_CKOP

t_DCKOO

2

t_CKWL

t_CKWH

CLKOUT

NOTES:

1. WHEN CLKDBL IS DISABLED, ANY SPECIFICATION TO CLKIN

APPLIES TO THE RISING EDGE, ONLY.

2. WHEN CLKDBL IS ENABLED, ANY SPECIFICATION TO CLKIN

APPLIES TO THE RISING OR FALLING EDGE.

Figure 11. Clock Input

Rev. C

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January 2013

ADSP-21161N

Clock Signals

The ADSP-21161N can use an external clock or a crystal. See

CLKIN pin description. The programmer can configure the

ADSP-21161N to use its internal clock generator by connecting

the necessary components to CLKIN and XTAL. Figure 12

shows the component connections used for a crystal operating

in fundamental mode.

CLKIN

XTAL

X1

C2

27pF

C1

27pF

SUGGESTED COMPONENTS FOR 100MHz OPERATION:

ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE)

ECLIPTEK EC-25.000M (THROUGH-HOLE PACKAGE)

C1 = 27pF

C2 = 27pF

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. THIS 25MHz

CRYSTAL GENERATES A 100MHz CCLK AND A 50MHz EP CLOCK

WITH CLKDBL ENABLED AND A 2:1 PLL MULTIPLY RATIO.

Figure 12. 100 MHz Operation (Fundamental Mode Crystal)

Reset

Table 12. Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRST

t_SRST

RESET Pulsewidth Low¹

RESET Setup Before CLKIN High²

4t_CK

8.5

ns

¹Applies after the power-up sequence is complete.

²Only required if multiple ADSP-21161Ns mustcome out of reset synchronousto CLKIN with program counters (PC) equal. Not required for multipleADSP-21161Ns

communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.

CLKIN

t_SRST

t_WRST

RESET

Figure 13. Reset

Rev. C

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January 2013

ADSP-21161N

Interrupts

Table 13. Interrupts

Parameter

Min

Max

Unit

Timing Requirements

t_SIR

t_HIR

t_IPW

IRQ2–0 Setup Before CLKIN¹

IRQ2–0 Hold After CLKIN¹

IRQ2–0 Pulsewidth²

6

ns

0

t_CKOP+ 2

¹Only required for IRQx recognition in the following cycle.

²Applies only if t_SIRand t_HIRrequirements are not met.

CLKIN

t_HIR

t_SIR

IRQ2–0

t_IPW

Figure 14. Interrupts

Timer

Table 14. Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_DTEX

CCLK to TIMEXP

1

7

ns

CCLK

t_DTEX

TIMEXP

Figure 15. Timer

Rev. C

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January 2013

ADSP-21161N

Flags

Table 15. Flags

100 MHz

Max

110 MHz

Max

Parameter

Min

Unit

Timing Requirement

t_SFI

FLAG11–0_INSetup Before CLKIN¹

FLAG11–0_INHold After CLKIN¹

FLAG11–0_INDelay After RD/WR Low¹

FLAG11–0_INHold After RD/WR Deasserted¹

4

1

4

1

ns

t_HFI

t_DWRFI

t_HFIWR

12

9

5

0

Switching Characteristics

t_DFO

FLAG11–0_OUTDelay After CLKIN

ns

t_HFO

FLAG11–0_OUTHold After CLKIN

CLKIN to FLAG11–0_OUTEnable

CLKIN to FLAG11–0_OUTDisable

1

t_DFOE

t_DFOD

5

¹Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.

CLKIN

t_DFO

t_DFOD

t_DFOE

t_HFO

FLAG11–0

CLKIN

OUT

FLAG OUTPUT

t_SFI

t_HFI

FLAG11–0

IN

t_DWRFI

t_HFIWR

⑁ ⌹

⌹⌬,

FLAG INPUT

Figure 16. Flags

Rev. C

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January 2013

ADSP-21161N

Table 16. These specifications apply when the ADSP-21161N is

the bus master accessing external memory space in asynchro-

nous access mode.

Memory Read — Bus Master

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN except for ACK pin requirements listed in footnote 4 of

Table 16. Memory Read — Bus Master

100 MHz

110 MHz

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_DAD

Address, Selects Delay to

t_CKOP–0.25t_CCLK–8.5+W

0.75t_CKOP–11+W

t_CKOP–0.25t_CCLK–6.75+W ns

Data Valid^{1, 2, 3}

t_DRLD

t_HDA

RD Low to Data Valid^1,3

0.75t_CKOP–11+W

ns

Data Hold from Address, 0

Selects⁴

0

t_SDS

Data Setup to RD High

Data Hold from RD High⁴

8

1

8

1

ns

t_HDRH

t_DAAK

ACK Delay from Address,

Selects^{2, 5}

ACK Delay from RD Low⁵

ACK Setup to CLKIN⁵

ACK Hold After CLKIN

t_CKOP–0.5t_CCLK–12+W

t_CKOP–0.75t_CCLK–11+W

t_CKOP–0.5t_CCLK–12+W

t_DSAK

t_SAKC

t_HAKC

t_CKOP–0.75t_CCLK–11+W ns

0.5t_CCLK+3

1

0.5t_CCLK+3

1

ns

Switching Characteristics

t_DRHAAddress Selects Hold

0.25t_CCLK–1+H

0.25t_CCLK–3

0.25t_CCLK–1+H

0.25t_CCLK–3

ns

After RD High

t_DARL

Address Selects to RD

Low²

t_RW

RD Pulsewidth

t_CKOP–0.5t_CCLK–1+W

0.5t_CCLK–1+HI

t_CKOP–0.5t_CCLK–1+W

0.5t_CCLK–1+HI

ns

t_RWR

RD High to WR, RD,

DMAGx Low

W = (number of wait states specified in WAIT register) × t_CKOP

.

HI = t_CKOP(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t_CKOP(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

¹Data Delay/Setup: User must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of MSx, BMS is referenced.

³The maximum limits of timing requirement values for t_DADand t_DRLDparameters are applicable for the case where ACK is always high.

⁴Data Hold: User must meet t_HDAor t_HDRHin asynchronous access mode. See Example System Hold Time Calculation on Page 54 for the calculation of hold times given capacitive

and dc loads.

⁵For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,

ACK must be driven low (deasserted) by t_DAAK, t_DSAK, or t_SAKC. For the second and subsequent cycles of an asynchronous external memory access, the t_SAKCand t_HAKCmust be

met for both assertion and deassertion of ACK signal.

Rev. C

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January 2013

ADSP-21161N

t_HDA

ADDRESS

MSx, BMS

t_DRHA

t_DARL

t_RW

RD

t_SDS

t_DRLD

t_DAD

t_HDRH

DATA

t_DSAK

t_DAAK

t_RWR

ACK

t_HAKC

t_SAKC

CLKIN

WR, DMAG

Figure 17. Memory Read — Bus Master

Rev. C

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January 2013

ADSP-21161N

Table 17. These specifications apply when the ADSP-21161N is

the bus master accessing external memory space in asynchro-

nous access mode.

Memory Write — Bus Master

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN except for ACK pin requirements listed in footnote 1 of

Table 17. Memory Write — Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_DAAK

t_DSAK

t_SAKC

t_HAKC

ACK Delay from Address, Selects^{1, 2}

ACK Delay from WR Low¹

ACK Setup to CLKIN¹

t_CKOP–0.5t_CCLK–12+W

t_CKOP–0.75t_CCLK–11+W

ns

0.5t_CCLK+3

1

ACK Hold After CLKIN¹

Switching Characteristics

t_DAWH

t_DAWL

t_WW

Address, Selects to WR Deasserted²

Address, Selects to WR Low²

t_CKOP– 0.25t_CCLK– 3+W

0.25t_CCLK– 3

ns

WR Pulsewidth

t_CKOP– 0.5t_CCLK– 1+W

t_CKOP–0.25t_CCLK– 13.5+W

0.25t_CCLK– 1+H

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

t_WWR

Data Setup Before WR High

Address Hold After WR Deasserted

Data Hold After WR Deasserted

Data Disable After WR Deasserted³

WR High to WR, RD, DMAGx Low

Data Disable Before WR or RD Low

WR Low to Data Enabled

0.25t_CCLK– 1+H

0.25t_CCLK– 2+H

0.25t_CCLK+2.5+H

0.5t_CCLK– 1.25+HI

0.25t_CCLK– 3+I

t_DDWR

t_WDE

–0.25t_CCLK– 1

W = (number of wait states specified in WAIT register) × t_CKOP

.

H = t_CKOP(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

HI = t_CKOP(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

I = t_CKOP(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

¹For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,

ACK must be driven low (deasserted) by t_DAAK, t_DSAK, or t_SAKC. For the second and subsequent cycles of an asynchronous external memory access, the t_SAKCand t_HAKCmust be

met for both assertion and deassertion of ACK signal.

²The falling edge of MSx, BMS is referenced.

³See Example System Hold Time Calculation on Page 54 for calculation of hold times given capacitive and dc loads.

Rev. C

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Page 29 of 60

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January 2013

ADSP-21161N

ADDRESS

MSx, BMS

t_DAWH

t_DWHA

t_DAWL

t_WW

WR

t_WWR

t_DATRWH

t_WDE

t_DDWH

t_DDWR

DATA

ACK

t_DSAK

t_DWHD

t_DAAK

t_HAKC

t_SAKC

CLKIN

RD, DMAG

Figure 18. Memory Write — Bus Master

Rev. C

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Page 30 of 60

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January 2013

ADSP-21161N

must meet the slave's timing requirements for synchronous

read/writes (see Synchronous Read/Write — Bus Slave on

Page 32). The slave ADSP-21161N must also meet these (bus

master) timing requirements for data and acknowledge setup

and hold times.

Synchronous Read/Write — Bus Master

Use these specifications for interfacing to external memory sys-

tems that require CLKIN, relative to timing or for accessing a

slave ADSP-21161N (in multiprocessor memory space). When

accessing a slave ADSP-21161N, these switching characteristics

Table 18. Synchronous Read/Write — Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_SSDATI

t_HSDATI

t_SACKC

t_HACKC

Data Setup Before CLKIN

Data Hold After CLKIN

ACK Setup Before CLKIN

ACK Hold After CLKIN

5.5

ns

1

0.5t_CCLK+3

1

Switching Characteristics

t_DADDO

t_HADDO

t_DRDO

Address, MSx, BMS, BRST, Delay After CLKIN

10

ns

Address, MSx, BMS, BRST, Hold After CLKIN

RD High Delay After CLKIN

WR High Delay After CLKIN

RD/WR Low Delay After CLKIN

Data Delay After CLKIN

1.5

0.25t_CCLK–1

0.25t_CCLK+9

12.5

t_DWRO

t_DRWL

t_DDATO

t_HDATO

Data Hold After CLKIN

1.5

CLKIN

t_HADDO

t_DADDO

ADDRESS

MSx, BRST

t_SACKC

t_HACKC

ACK

(IN)

READ CYCLE

t_DRWL

t_DRDO

RD

t_SSDATI

t_HSDATI

DATA

(IN)

WRITE CYCLE

t_DRWL

t_DWRO

WR

t_DDATO

t_HDATO

DATA (OUT)

Figure 19. Synchronous Read/Write — Bus Master

Rev. C

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Page 31 of 60

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January 2013

ADSP-21161N

Synchronous Read/Write — Bus Slave

Use these specifications for ADSP-21161N bus master accesses

of a slave’s IOP registers in multiprocessor memory space. The

bus master must meet these (bus slave) timing requirements.

Table 19. Synchronous Read/Write — Bus Slave

Parameter

Min

Max

Unit

Timing Requirements

t_SADDI

t_HADDI

t_SRWI

Address, BRST Setup Before CLKIN

Address, BRST Hold After CLKIN

RD/WR Setup Before CLKIN

RD/WR Hold After CLKIN

5

ns

1

5

t_HRWI

1

t_SSDATI

t_HSDATI

Data Setup Before CLKIN

5.5

1

Data Hold After CLKIN

Switching Characteristics

t_DDATO

t_HDATO

t_DACKC

t_HACKO

Data Delay After CLKIN

12.5

10

ns

Data Hold After CLKIN

ACK Delay After CLKIN

ACK Hold After CLKIN

1.5

CLKIN

t_SADDI

t_HADDI

ADDRESS

t_HACKO

t_DACKC

ACK

READ ACCESS

t_SRWI

t_HRWI

RD

t_DDATO

t_HDATO

DATA

(OUT)

WRITE ACCESS

t_HRWI

t_SRWI

WR

t_SSDATI

t_HSDATI

DATA

(IN)

Figure 20. Synchronous Read/Write — Bus Slave

Rev. C

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Page 32 of 60

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January 2013

ADSP-21161N

Host Bus Request

Use these specifications for asynchronous host bus requests of

an ADSP-21161N (HBR, HBG).

Table 20. Host Bus Request

100 MHz

Max

110 MHz

Parameter

Min

Max

Unit

Timing Requirements

t_HBGRCSV

t_SHBRI

HBG Low to RD/WR/CS Valid

HBR Setup Before CLKIN¹

HBR Hold After CLKIN¹

HBG Setup Before CLKIN

HBG Hold After CLKIN

19

ns

6

1

6

1

6

1

6

1

t_HHBRI

t_SHBGI

t_HHBGI

Switching Characteristics

t_DHBGO

t_HHBGO

t_DRDYCS

t_TRDYHG

t_ARDYTR

HBG Delay After CLKIN

7

ns

HBG Hold After CLKIN

1.5

REDY (O/D) or (A/D) Low from CS and HBR Low²

REDY (O/D) Disable or REDY (A/D) High from HBG²

REDY (A/D) Disable from CS or HBR High²

10

11

10

11

t_CKOP+ 14

t_CKOP+ 12

¹Only required for recognition in the current cycle.

²(O/D) = open drain, (A/D) = active drive.

Rev. C

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Page 33 of 60

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January 2013

ADSP-21161N

CLKIN

t_SHBRI

t_HHBRI

HBR

t_{DHBG O}

t_HHBGO

HBG (OUT)

t_SHBGI

t_HHBGI

HBG

(IN)

HBR

CS

t_{DRDY CS}

t_TRDYHG

RE DY

(O/D)

t_ARDYTR

RE DY

(A/D)

t_{HBGRCS V}

HBG (OUT)

RD

WR

CS

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 21. Host Bus Request

Rev. C

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January 2013

ADSP-21161N

Multiprocessor Bus Request

Use these specifications for passing of bus mastership between

multiprocessing ADSP-21161Ns (BRx).

Table 21. Multiprocessor Bus Request

Parameter

Min

Max

Unit

Timing Requirements

t_SBRI

BRx Setup Before CLKIN High

BRx Hold After CLKIN High

PA Setup Before CLKIN High

PA Hold After CLKIN High

9

ns

t_HBRI

0.5

9

t_SPAI

t_HPAI

1

t_SRPBAI

t_HRPBAI

RPBA Setup Before CLKIN High

RPBA Hold After CLKIN High

6

2

Switching Characteristics

t_DBRO

t_HBRO

t_DPASO

t_TRPAS

t_DPAMO

t_PATR

BRx Delay After CLKIN High

8

ns

BRx Hold After CLKIN High

1.0

PA Delay After CLKIN High, Slave

PA Disable After CLKIN High, Slave

PA Delay After CLKIN High, Master

PA Disable Before CLKIN High, Master

1.5

0.25t_CCLK+9

ns

0.25t_CCLK–5

CLKIN

t_DBRO

t_HBRO

BRx (OUT)

t_{DP A SO}

t_TRPAS

PA (OUT)

(SLAV E)

t_DPAMO

t_{PAT R}

PA (OUT)

(MASTER)

t_SBRI

t_HBRI

BRx (IN)

t_{S PAI}

t_HPAI

PA (IN)

(O/D)

t_{S RPBAI}

t_{HR P BAI}

RP BA

O/D = OPEN DRAIN

Figure 22. Multiprocessor Bus Request

Rev. C

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Page 35 of 60

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January 2013

ADSP-21161N

for this timing. Although the DSP will recognize HBR asserted

before reset, a HBG will not be returned by the DSP until after

reset is deasserted and the DSP completes bus synchronization.

Note: Host internal memory access is not supported.

Asynchronous Read/Write — Host to ADSP-21161N

Use these specifications for asynchronous host processor

accesses of an ADSP-21161N, after the host has asserted CS and

HBR (low). After HBG is returned by the ADSP-21161N, the

host can drive the RD and WR pins to access the

ADSP-21161N’s IOP registers. HBR and HBG are assumed low

Table 22. Read Cycle

Parameter

Min

Max

Unit

Timing Requirements

t_SADRDL

t_HADRDH

t_WRWH

Address Setup and CS Low Before RD Low

Address Hold and CS Hold Low After RD

RD/WR High Width

0

ns

2

3.5

0

t_DRDHRDY

RD High Delay After REDY (O/D) Disable

RD High Delay After REDY (A/D) Disable

0

Switching Characteristics

t_SDATRDY

t_DRDYRDL

t_RDYPRD

t_HDARWH

Data Valid Before REDY Disable from Low

2

ns

REDY (O/D) or (A/D) Low Delay After RD Low

REDY (O/D) or (A/D) Low Pulsewidth for Read

Data Disable After RD High

10

6

1.5t_CCLK

2

Table 23. Write Cycle

Parameter

Min

Max

Unit

Timing Requirements

t_SCSWRL

t_HCSWRH

t_SADWRH

t_HADWRH

t_WWRL

CS Low Setup Before WR Low

0

ns

CS Low Hold After WR High

Address Setup Before WR High

Address Hold After WR High

WR Low Width

0

6

2

t_CCLK

3.5

0

t_WRWH

RD/WR High Width

t_DWRHRDY

t_SDATWH

t_HDATWH

WR High Delay After REDY (O/D) or (A/D) Disable

Data Setup Before WR High

Data Hold After WR High

5

4

Switching Characteristics

t_DRDYWRL

REDY (O/D) or (A/D) Low Delay After WR/CS Low¹

t_RDYPWR

REDY (O/D) or (A/D) Low Pulsewidth for Write¹

11

ns

12

¹Only when slave write FIFO is full.

Rev. C

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January 2013

ADSP-21161N

READ CYCLE

ADDRESS/CS

t_SADRDL

t_HADRDH

t_WRWH

RD

t_{HDARW H}

DATA (OUT)

t_{SDAT RDY}

t_DRDYRDL

t_DRDHRDY

t_RDYPRD

REDY (O/D)

REDY (A/D)

WRITE CYCLE

ADDRESS

t_{SADW RH}

t_{HADW RH}

t_SCSWRL

t_HCSWRH

CS

t_WWRL

t_{W RW H}

WR

t_SDATWH

t_HDATWH

DATA (IN)

t_DRDYWRL

t_{RDYPW R}

t_DWRHRDY

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 23. Asynchronous Read/Write — Host to ADSP-21161N

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ADSP-21161N

During reset, the DSP will not respond to SBTS, HBR, and MMS

accesses. Although the DSP will recognize HBR asserted before

reset, a HBG will not be returned by the DSP until after reset is

deasserted and the DSP completes bus synchronization.

Three-State Timing — Bus Master, Bus Slave

These specifications show how the memory interface is disabled

(stops driving) or enabled (resumes driving) relative to CLKIN

and the SBTS pin. This timing is applicable to bus master transi-

tion cycles (BTC) and host transition cycles (HTC) as well as the

SBTS pin.

Table 24. Three-State Timing — Bus Master, Bus Slave

Parameter

Min

Max

Unit

Timing Requirements

t_STSCK

t_HTSCK

SBTS Setup Before CLKIN

SBTS Hold After CLKIN

6

2

ns

Switching Characteristics

t_MIENAAddress/Select Enable After CLKIN High

t_MIENS

t_MIENHG

t_MITRA

1.5

9

ns

Strobes Enable After CLKIN High¹

HBG Enable After CLKIN

–1.5

+9

1.5

9

Address/Select Disable After CLKIN High

Strobes Disable After CLKIN High

HBG Disable After CLKIN²

0.5t_CKOP–20

t_CKOP–0.25t_CCLK–17

0.5t_CKOP+Nt_CCLK–20

1.5

0.5t_CKOP–15

t_MITRS

t_CKOP–0.25t_CCLK–12.5

0.5t_CKOP+Nt_CCLK–15

10

t_MITRHG

t_DATEN

t_DATTR

t_ACKEN

t_ACKTR

t_CDCEN

t_CDCTR

t_ATRHBG

t_STRHBG

t_BTRHBG

t_MENHBG

Data Enable After CLKIN³

Data Disable After CLKIN³

1.5

6

ACK Enable After CLKIN High

ACK Disable After CLKIN High

CLKOUT Enable After CLKIN²

1.5

9

0.2

5

0.5t_CKOP+Nt_CCLK

t_CKOP–5

0.5t_CKOP+Nt_CCLK+5

t_CKOP

CLKOUT Disable After CLKIN

Address/Select Disable Before HBG Low⁴

RD/WR/DMAGx Disable Before HBG Low⁴

BMS Disable Before HBG Low⁴

Memory Interface Enable After HBG High⁴

1.5t_CKOP–6

t_CKOP+0.25t_CCLK–4

0.5t_CKOP–4

t_CKOP–5

1.5t_CKOP+2

t_CKOP+0.25t_CCLK+3

0.5t_CKOP+2

t_CKOP+5

¹Strobes = RD, WR, DMAGx.

²Where N = 0.5, 1.0, 1.5 for 1:2, 1:3, and 1:4, respectively.

³In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

⁴Memory Interface = Address, RD, WR, MSx, DMAGx, and BMS (in EPROM boot mode). BMS is only an output in EPROM boot mode.

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ADSP-21161N

CLKIN

t_STSCK

t_HTSCK

SBTS

t_MIENA,t_MIENS,t_MIENHG

t_MITRA,t_MITRS,t_MITRHG

MEMORY

INTERFACE

t_DATEN

t_DATTR

DATA

ACK

t_ACKEN

t_ACKTR

CLKIN

t_CDCEN

t_CDCTR

CLKOUT

HBG

t_MENHBG

t_ATRHBG,t_STRHBG,t_BTRHBG

MEMORY

INTERFACE

MEMORY INTERFACE = ADDRESS, RD, WR, MSx, DMAGx, BMS (IN EPROM MODE)

Figure 24. Three-State Timing — Bus Master, Bus Slave

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ADSP-21161N

DMAG signals. For Paced Master mode, the data transfer is

controlled by ADDR23–0, RD, WR, MS3–0, and ACK (not

DMAG). For Paced Master mode, the Memory Read-Bus Mas-

ter, Memory Write-Bus Master, and Synchronous Read/Write-

Bus Master timing specifications for ADDR23–0, RD, WR,

MS3–0, DATA47–16, and ACK also apply.

DMA Handshake

These specifications describe the three DMA handshake modes.

In all three modes DMAR is used to initiate transfers. For hand-

shake mode, DMAG controls the latching or enabling of data

externally. For external handshake mode, the data transfer is

controlled by the ADDR23–0, RD, WR, MS3–0, ACK, and

Table 25. DMA Handshake

100 MHz

Max

110 MHz

Parameter

Min

Max

Unit

Timing Requirements

t_SDRC

t_WDR

DMARx Setup Before CLKIN¹

3.5

ns

DMARx Width Low

(Nonsynchronous)²

t_CCLK+4.5

t_SDATDGL

t_HDATIDG

t_DATDRH

t_DMARLL

t_DMARH

Data Setup After DMAGx Low³

Data Hold After DMAGx High

Data Valid After DMARx High³

DMARx Low Edge to Low Edge⁴

DMARx Width High²

t_CKOP– 0.5t_CCLK–7

t_CKOP+3

t_CKOP– 0.5t_CCLK–7 ns

ns

2

t_CKOP+3

ns

t_CKOP

t_CCLK+4.5

Switching Characteristics

t_DDGL

t_WDGH

t_WDGL

t_HDGC

DMAGx Low Delay After CLKIN

0.25t_CCLK+1

0.25t_CCLK+9

0.25t_CCLK+1

0.25t_CCLK+9

ns

DMAGx High Width

0.5t_CCLK– 1+HI

t_CKOP– 0.5t_CCLK– 1

0.5t_CCLK– 1+HI

t_CKOP– 0.5t_CCLK– 1

DMAGx Low Width

DMAGx High Delay After CLKIN

t_CKOP– 0.25t_CCLK+1.0 t_CKOP– 0.25t_CCLK+9 t_CKOP– 0.25t_CCLK+1.0 t_CKOP– 0.25t_CCLK+9 ns

t_VDATDGHData Valid Before DMAGx High⁵

t_DATRDGHData Disable After DMAGx High⁶

t_CKOP– 0.25t_CCLK– 8

0.25t_CCLK– 3

–1.5

t_CKOP– 0.25t_CCLK+5 t_CKOP– 0.25t_CCLK– 8

t_CKOP– 0.25t_CCLK+5 ns

0.25t_CCLK+4

+2

0.25t_CCLK– 3

0.25t_CCLK+4

+2

ns

t_DGWRL

t_DGWRH

t_DGWRR

t_DGRDL

t_DRDGH

t_DGRDR

t_DGWR

WRx Low Before DMAGx Low

DMAGx Low Before WRx High

WRx High Before DMAGx High⁷

RDx Low Before DMAGx Low

RDx Low Before DMAGx High

RDx High Before DMAGx High⁷

DMAGx High to WRx, RDx Low

–1.5

t_CKOP– 0.5t_CCLK– 2 +W

–1.5

t_CKOP– 0.5t_CCLK– 2 +W

+2

–1.5

+2

–1.5

t_CKOP– 0.5t_CCLK–2+W

–1.5

t_CKOP– 0.5t_CCLK–2+W

+2

–1.5

+2

0.5t_CCLK– 2+HI

t_DADGH

t_DDGHA

Address/Select Valid to DMAGx High 15

13

1

Address/Select Hold After DMAGx

High

1

W = (number of wait states specified in WAIT register)  t_CKOP

.

HI = t_CKOP(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

¹Only required for recognition in the current cycle.

²Maximum throughput (@ 110 MHz) using DMARx/DMAGx handshaking equals t_WDR+ t_DMARH= (t_CCLK+4.5) + (t_CCLK+4.5)=27 ns (37 MHz). This throughput limit applies

to non-synchronous access mode only.

³t_SDATDGLis the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can

be driven t_DATDRHafter DMARx is brought high.

⁴Use t_DMARLLif DMARx transitions synchronous with CLKIN. Otherwise, use t_WDRand t_DMARH

.

⁵t_VDATDGHis valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t_VDATDGH= t_CKOP– 0.25t_CCLK– 8 + (n × t_CKOP) where

n equals the number of extra cycles that the access is prolonged.

⁶See Example System Hold Time Calculation on Page 54 for calculation of hold times given capacitive and dc loads.

⁷This parameter applies for synchronous access mode only.

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ADSP-21161N

CLKIN

t_DMARLL

t_SDRC

t_DMARH

t_WDR

DMARx

DMAGx

t_HDGC

t_DDGL

t_WDGL

t_WDGH

TRANSFERS BETWEEN ADSP-21161N

INTERNAL MEMORY AND EXTERNAL DEVICE

t_DATRDGH

t_VDATDGH

DATA

(FROM ADSP-2116x TO EXTERNAL DRIVE)

t_DATDRH

t_HDATIDG

t_SDATDGL

DATA

(FROM EXTERNAL DRIVE TO ADSP-21161N)

TRANSFERS BETWEEN EXTERNAL DEVICE AND

EXTERNAL MEMORY¹(EXTERNAL HANDSHAKE MODE)

t_DGWRL

t_DGWRH

t_DGWR

t_DGWRR

(EXTERNAL DEVICE TO EXTERNAL MEMORY)

WR

RD

t_DGRDR

t_DGRDL

(EXTERNAL MEMORY TO EXTERNAL DEVICE)

t_DRDGH

t_DDGHA

t_DADGH

ADDRESS

MSx

¹MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER

TIMING SPECIFICATIONS FOR ADDR23–0, RD, WR, MS3-0 AND ACK ALSO APPLY HERE.

Figure 25. DMA Handshake

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ADSP-21161N

SDRAM Interface — Bus Master

Use these specifications for ADSP-21161N bus master accesses

of SDRAM:

Table 26. SDRAM Interface — Bus Master

100 MHz

Max

110 MHz

Max

Parameter

Min

Unit

Timing Requirements

t_SDSDK

t_HDSDK

Switching Characteristics

t_DSDK1

First SDCLK Rise Delay After CLKIN^{1, 2}

t_SDK

Data Setup Before SDCLK

2.0

2.3

2.0

2.3

ns

Data Hold After SDCLK

0.75t_CCLK+ 1.5

0.75t_CCLK+ 8.0

0.75t_CCLK+ 1.5

0.75t_CCLK+ 8.0

ns

SDCLK Period

t_CCLK

4

2  t_CCLK

t_CCLK

3

2  t_CCLK

t_SDKH

SDCLK Width High

t_SDKL

SDCLK Width Low

4

3

t_DCADSDK

t_HCADSDK

t_SDTRSDK

t_SDENSDK

t_SDCTR

Command, Address, Data, Delay After SDCLK³

Command, Address, Data, Hold After SDCLK³

Data Three-State After SDCLK⁴

Data Enable After SDCLK⁵

0.25t_CCLK+2.5

0.5t_CCLK+ 2.0

0.25t_CCLK+2.5

0.5t_CCLK+ 2.0

2.0

0.75t_CCLK

Command Three-State After CLKIN

Command Enable After CLKIN

SDCLK Three-State After CLKIN

SDCLK Enable After CLKIN

0.5t_CCLK–1.5

0.5t_CCLK+ 6.0

0.5t_CCLK–1.5

0.5t_CCLK+ 6.0

t_SDCEN

t_SDSDKTR

t_SDSDKEN

t_SDATR

2

5

2

5

0

3

0

3

1

4

1

4

Address Three-State After CLKIN

0.25 t_CCLK5

0.4

0.25t_CCLK

+7.2

0.25 t_CCLK5

0.4

0.25t_CCLK

+7.2

t_SDAEN

Address Enable After CLKIN

¹For the second, third, and fourth rising edges of SDCLK delay from CLKIN, add appropriate number of SDCLK period to the t_DSDK1and t_SSDKC1values, depending upon the SDCKR

value and the core clock to CLKIN ratio.

²Subtract t_CCLKfrom result if value is greater than or equal to t_CCLK

.

³Command = SDCKE, MSx, DQM, RAS, CAS, SDA10, and SDWE.

⁴SDRAM Controller adds one SDRAM CLK three-stated cycle delay on a read, followed by a write.

⁵Valid when DSP transitions to SDRAM master from SDRAM slave.

SDRAM Interface — Bus Slave

These timing requirements allow a bus slave to sample the bus

master’s SDRAM command and detect when a refresh occurs:

Table 27. SDRAM Interface — Bus Slave

Parameter

Min

Max

Unit

Timing Requirements

t_SSDKC1

t_SCSDK

t_HCSDK

First SDCLK Rise after CLKOUT^{1, 2, 3}

Command Setup before SDCLK⁴

Command Hold after SDCLK⁴

SDCK  t_CCLK0.5t_CCLK 0.5

2

SDCKR  t_CCLK0.25t_CCLK+ 2.0

ns

1

¹For the second, third, and fourth rising edges of SDCLK delay from CLKOUT, add appropriate number of SDCLK period to the t_DSDK1and t_SSDKC1values, depending upon the

SDCKR value and the Core clock to CLKOUT ratio.

²SDCKR = 1 for SDCLK equal to core clock frequency and SDCKR = 2 for SDCLK equal to half core clock frequency.

³Subtract t_CCLKfrom result if value is greater than or equal to t_CCLK

⁴Command = SDCKE, RAS, CAS, and SDWE.

.

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ADSP-21161N

CLKIN

t_DSDK1

t_SDKH

t_SDK

SDCLK

t_SDSDK

t_SDKL

t_HDSDK

DATA(IN)

t_SDTRSDK

t_HCADSDK

t_DCADSDK

t_SDENSDK

DATA(OUT)

t_DCADSDK

1

CMND ADDR

(OUT)

t_HCADSDK

t_SDCEN

t_SDCTR

1

CMND (OUT)

ADDR

(OUT)

t_SDAEN

t_SDATR

CLKIN

t_SDSDKTR

t_SDSDKEN

SDCLK

CLKOUT

t_SSDKC1

SDCLK (IN)

t_SCSDK

2

CMND (IN)

t_HCSDK

1

COMMAND = SDCKE, MSx, RAS, CAS, SDWE, DQM, AND SDA10.

COMMAND = SDCKE, RAS, CAS, AND SDWE.

2

Figure 26. SDRAM Interface

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ADSP-21161N

tions made directly from speed specifications will result in

unrealistically small skew times because they include multiple

tester guardbands. The setup and hold skew times shown below

are calculated to include only one tester guardband.

Link Ports

Calculation of link receiver data setup and hold relative to link

clock is required to determine the maximum allowable skew

that can be introduced in the transmission path between

LDATA and LCLK. Setup skew is the maximum delay that can

be introduced in LDATA relative to LCLK,

(setup skew = t_LCLKTWHmin – t_DLDCH– t_SLDCL). Hold skew is the

maximum delay that can be introduced in LCLK relative to

LDATA, (hold skew = t_LCLKTWLmin – t_HLDCH– t_HLDCL). Calcula-

ADSP-21161N Setup Skew = 1.5 ns max

ADSP-21161N Hold Skew = 1.5 ns max

Note that there is a two-cycle effect latency between the link

port enable instruction and the DSP enabling the link port.

Table 28. Link Ports — Receive

Parameter

Min

Max

Unit

Timing Requirements

t_SLDCL

Data Setup Before LCLK Low

Data Hold After LCLK Low

LCLK Period

1

ns

t_HLDCL

3.5

t_LCLK

4.0

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

LCLK Width Low

LCLK Width High

Switching Characteristics

t_DLALC

LACK Low Delay After LCLK High¹

8

12

ns

¹LACK goes low with t_DLALCrelative to rise of LCLK after first nibble, but does not go low if the receiver's link buffer is not about to fill.

RECEIVE

t_LCLKIW

t_LCLKRWH

t_LCLKRWL

LCLK

t_HLDCL

t_SLDCL

IN

LDAT7-0

t_DLALC

LACK (OUT)

Figure 27. Link Ports—Receive

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ADSP-21161N

Table 29. Link Ports — Transmit

Parameter

Min

Max

Unit

Timing Requirements

t_SLACH

t_HLACH

Switching Characteristics

LACK Setup Before LCLK High

8

ns

LACK Hold After LCLK High

–2

t_DLDCH

Data Delay After LCLK High

3

ns

t_HLDCH

Data Hold After LCLK High

LCLK Width Low

0

t_LCLKTWL

t_LCLKTWH

t_DLACLK

0.5t_LCLK–1.0

0.5t_LCLK+3

0.5t_LCLK+1.0

3t_LCLK+11

ns

LCLK Width High

LCLK Low Delay After LACK High

TRANSMIT

LCLK INACTIVE

(HIGH)

LAST NIBBLE/BYTE

TRANSMITTED

FIRST NIBBLE/BYTE

TRANSMITTED

t_LCLKTWH

t_LCLKTWL

LCLK

t_DLDCH

t_HLDCH

LDAT7-0

OUT

t_DLACLK

t_SLACH

t_HLACH

LACK (IN)

THE t_SLACHREQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

Figure 28. Link Ports—Transmit

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ADSP-21161N

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 30. Serial Ports — External Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSE

Transmit/Receive FS Setup Before Transmit/Receive SCLK¹

Transmit/Receive FS Hold After Transmit/Receive SCLK¹

Receive Data Setup Before Receive SCLK¹

Receive Data Hold After Receive SCLK¹

SCLKx Width

3.5

2

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

1.5

4

7

SCLKx Period

2t_CCLK

¹Referenced to sample edge.

Table 31. Serial Ports — Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSI

t_HFSI

t_SDRI

t_HDRI

FS Setup Time Before SCLK (Transmit/Receive Mode)¹

FS Hold After SCLK (Transmit/Receive Mode)¹

Receive Data Setup Before SCLK¹

8

ns

0.5t_CCLK+1

4

3

Receive Data Hold After SCLK¹

¹Referenced to sample edge.

Table 32. Serial Ports — External Clock

100 MHz

Max

110 MHz

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSE

t_HOFSE

t_DDTE

t_HDTE

FS Delay After SCLK (Internally Generated FS) ^{1, 2, 3}

FS Hold After SCLK (Internally Generated FS)^{1, 2 , 3}

Transmit Data Delay After SCLK ^{1, 2}

13

16

13

ns

3

0

2.75

0

16

Transmit Data Hold After SCLK ^{1, 2}

¹Referenced to drive edge.

²SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.

³SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.

Table 33. Serial Ports — Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

FS Delay After SCLK (Internally Generated FS)^{1, 2, 3}

FS Hold After SCLK (Internally Generated FS)^{1, 2, 3}

Transmit Data Delay After SCLK^{1, 2}

Transmit Data Hold After SCLK^{1, 2}

SCLK Width²

4.5

7.5

ns

t_HOFSI

t_DDTI

–1.5

t_HDTI

0

t_SCLKIW

0.5t_SCLK–2.5

0.5t_SCLK+2

¹Referenced to drive edge.

²SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.

³SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.

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ADSP-21161N

Table 34. Serial Ports —– Enable and Three-State

Parameter

Min

4

Max

Unit

Switching Characteristics

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

Data Enable from External Transmit SCLK^{1, 2}

Data Disable from External Transmit SCLK¹

Data Enable from Internal Transmit SCLK¹

Data Disable from Internal Transmit SCLK¹

ns

10

3

0

¹Referenced to drive edge.

²SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.

Table 35. Serial Ports — External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

t_DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS with

MCE = 1, MFD = 0¹

Data Enable from Late FS or MCE = 1, MFD = 0¹

13

ns

t_DDTENFS

0.5

¹MCE = 1, Transmit FS enable and Transmit FS valid follow t_DDTLFSEand t_DDTENFS

.

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ADSP-21161N

DATA RECEIVE— INTERNAL CLOCK

DATA RECEIVE— EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

SCLK

t_DFSI

t_DFSE

t_SFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_HFSE

FS

t_HDRE

t_SDRI

t_HDRI

t_SDRE

D_XA/D_XB

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT — INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT — EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

t_SCLKW

SCLK

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

FS

t_DDTE

t_DDTI

t_HDTE

t_HDTI

D_XA/D_XB

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

SCLK

SCLK (EXT)

t_DDTEN

t_DDTTE

D_XA/D_XB

DRIVE EDGE

SCLK (INT)

SCLK

t_DDTIN

t_DDTTI

D_XA/D_XB

Figure 29. Serial Ports

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ADSP-21161N

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

SAMPLE DRIVE

DRIVE

SCLK

FS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_DDTENFS

t_HDTE/I

D A/D B

1ST BIT

2ND BIT

X

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE

SAMPLE

DRIVE

SCLK

FS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_DDTENFS

t_HDTE/I

D A/D B

1ST BIT

2ND BIT

X

t_DDTLFSE

Figure 30. Serial Ports — External Late Frame Sync

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ADSP-21161N

SPI Interface Specifications

Table 36. SPI Interface Protocol — Master Switching and Timing

100 MHz

Max

110 MHz

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

t_SPICLKMSerial Clock Cycle

t_SPICHM

Data Input Valid to SPICLK Edge (Data Input Set-up Time) 0.5t_CCLK+10

0.5t_CCLK+10

0.5t_CCLK+1

ns

SPICLK Last Sampling Edge to Data Input Not Valid

0.5t_CCLK+1

8t_CCLK

8t_CCLK–4

4t_CCLK–4

ns

Serial Clock High Period

4t_CCLK–4

t_SPICLM

Serial Clock Low Period

t_DDSPIDM

t_HDSPIDM

t_{SDSCIM_0}

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

3

0

FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for 5t_CCLK

CPHASE = 0

5t_CCLK

t_{SDSCIM_1}

FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for 3t_CCLK

CPHASE = 1

3t_CCLK

ns

t_HDSM

Last SPICLK Edge to FLAG3–0 High

Sequential Transfer Delay

t_CCLK–3

2t_CCLK

t_CCLK–3

2t_CCLK

ns

t_SPITDM

FLAG3-0

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICHM

t_{D DSPIDM}

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0)

(OUTPUT)

t_SPICLM

SPICLK

(CP = 1)

(OUTPUT)

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

MSB

LSB

(INPUT)

VALID

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

t_HSPIDM

CPHASE = 0

MSB

VALID

LSB

VALID

MISO

(INPUT)

Figure 31. SPI Interface Protocol — Master Switching and Timing

Rev. C

|

Page 50 of 60

|

January 2013

ADSP-21161N

Table 37. SPI Interface Protocol — Slave Switching and Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial Clock Cycle

8t_CCLK

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

4t_CCLK–4

3.5t_CCLK+8

1.5t_CCLK+8

ns

CPHASE = 1

t_HDS

Last SPICLK Edge to SPIDS Not Asserted

CPHASE = 0

0

ns

t_SSPIDS

t_HSPIDS

t_SDPPW

Data Input Valid to SPICLK Edge (Data Input Set-up Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulsewidth (CPHASE = 0)

0

t_CCLK+1

t_CCLK

Switching Characteristics

t_DSOE

SPIDS Assertion to Data Out Active

2

0.5t_CCLK+5.5

0.75t_CCLK+3

ns

t_DSDHI

SPIDS Deassertion to Data High Impedance

1.5

t_DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

1

t_HDSPIDS

0.25t_CCLK+3

1

t_HDLSBS

SPICLK Edge to Last Bit Out Not Valid

(Data Out Hold Time) for LSB

0.5t_SPICLK+4.5t_CCLK

ns

2

t_DSOV

SPIDS Assertion to Data Out Valid (CPHASE = 0)

1.5t_CCLK+7

¹When CPHASE = 0 and baud rate is greater than 1, t_HDLSBSaffects the length of the last bit transmitted.

²Applies to the first deassertion of SPIDS only.

Rev. C

|

Page 51 of 60

|

January 2013

ADSP-21161N

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0)

(INPUT)

t_SPICLS

t_{SDSC O}

t_SPICHS

SPICLK

(CP = 1)

(INPUT)

t_DSDHI

t_HDSPIDS

t_DDSPIDS

t_DSOE

t_DDSPIDS

MISO

(OUTPUT)

MSB

LSB

t_HSPIDS

CPHASE = 1

t_SSPIDS

MOSI

(INPUT)

MSB VALID

LSB VALID

t_DSOV

t_DSOE

t_HDLSBS

t_HDSPIDS

t_DDSPIDS

t_DSDHI

MISO

(OUTPUT)

LSB

MSB

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

MSB VALID

LSB VALID

(INPUT)

Figure 32. SPI Interface Protocol — Slave Switching and Timing

Rev. C

|

Page 52 of 60

|

January 2013

ADSP-21161N

JTAG Test Access Port and Emulation

Table 38. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

t_CK

5

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low¹

TRST Pulsewidth

6

2

15

4t_CK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low²

13

30

ns

¹System Inputs = DATA47–16, ADDR23–0, RD, WR, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2–1, CLK_CFG1–0, CLKDBL, CS, HBR, SBTS, ID2–0, IRQ2–0, RESET,

BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, SDWE, HBG, RAS, CAS, SDCLK0, SDCKE, BRST, BR6–1, PA, MS3–0, FLAG11–0.

²System Outputs = BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, DATA47–16, SDWE, ACK, HBG, RAS, CAS, SDCLK1–0, SDCKE,

BRST, RD, WR, BR6–1, PA, MS3–0, ADDR23–0, FLAG11–0, DMAG2–1, DQM, REDY, CLKOUT, SDA10, TIMEXP, EMU, BMSTR, RSTOUT.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 33. JTAG Test Access Port and Emulation

Rev. C

|

Page 53 of 60

|

January 2013

ADSP-21161N

OUTPUT DRIVE CURRENTS

REFERENCE

SIGNAL

Figure 34 shows typical I-V characteristics for the output driv-

ers of the ADSP-21161N. The curves represent the current drive

capability of the output drivers as a function of output voltage.

t_MEASURED

t_DIS

V_OH

(MEASURED)

t_ENA

80

V_OH

(MEASURED)

V

_OH(MEASURED) – ⌬V

2.0V

1.0V

60

V_OL(MEASURED) + ⌬V

V_DDEXT= 3.47V, –40°C

V_OL

(MEASURED)

V_OL

(MEASURED)

50

V_DDEXT= 3.3V, +25°C

t_DECAY

40

30

V_DDEXT= 3.13V, +105°C

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

20

10

0

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

VOLTAGE TO BE APPROXIMATELY 1.5V.

–10

–20

–30

Figure 35. Output Enable/Disable

V_DDEXT= 3.47V, –40°C

Example System Hold Time Calculation

–40

V_DDEXT= 3.3V, +25°C

–50

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose V

to be the difference between the ADSP-21161N’s output voltage

and the input threshold for the device requiring the hold time. A

typical V will be 0.4 V. C_Lis the total bus capacitance (per data

line), and I_Lis the total leakage or three-state current (per data

line). The hold time will be t_DECAYplus the minimum disable

time (i.e., t_DATRWHfor the write cycle).

–60

V_DDEXT= 3.13V, +105°C

–80

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SWEEP (V_DDEXT) VOLTAGE – V

Figure 34. Typical Drive Currents

TEST CONDITIONS

The DSP is tested for output enable, disable, and hold time.

50⍀

TO

Output Enable Time

1.5V

OUTPUT

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving. The output enable time t_ENAis the interval from

the point when a reference signal reaches a high or low voltage

level to the point when the output has reached a specified high

or low trip point, as shown in the Output Enable/Disable dia-

gram (Figure 35). If multiple pins (such as the data bus) are

enabled, the measurement value is that of the first pin to start

driving.

30pF

Figure 36. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

INPUT

OR

OUTPUT

Output Disable Time

1.5V

Output pins are considered to be disabled when they stop driv-

ing, go into a high-impedance state, and start to decay from

their output high or low voltage. The time for the voltage on the

bus to decay by V is dependent on the capacitive load, C_Land

the load current, I_L. This decay time can be approximated by the

following equation:

Figure 37. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

t_DECAY= (C_LV)/I_L

The output disable time t_DISis the difference between t_MEASURED

and t_DECAYas shown in Figure 35. The time t_MEASUREDis the inter-

val from when the reference signal switches to when the output

voltage decays V from the measured output high or output low

voltage. t_DECAYis calculated with test loads C_Land I_L, and with

V equal to 0.5 V.

Rev. C

|

Page 54 of 60

|

January 2013

ADSP-21161N

Capacitive Loading

25

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 36 on Page 54). Figure 38 shows

graphically how output delays and holds vary with load capaci-

tance. (Note that this graph or derating does not apply to output

disable delays; see Output Disable Time on Page 54.) The graphs

of Figure 38, Figure 39, and Figure 40 may not be linear outside

the ranges shown for Typical Output Delay vs. Load Capaci-

tance and Typical Output Rise Time (20% – 80%, V = Min) vs.

Load Capacitance.

20

15

10

5

Y = 0.0835X - 2.42

NOMINAL

ENVIRONMENTAL CONDITIONS

The thermal characteristics in which the DSP is operating influ-

ence performance.

–5

0

30

60

90

120

150

180

210

LOAD CAPACITANCE – pF

Thermal Characteristics

Figure 38. Typical Output Delay or Hold vs. Load Capacitance (at Max Case

Temperature)

The ADSP-21161N is packaged in a 225-ball chip scale package

ball grid array (CSP_BGA). The ADSP-21161N is specified for a

case temperature (T_CASE). To ensure that the T_CASEdata sheet

specification is not exceeded, a heatsink and/or an air flow

source may be used. Use the center block of ground pins

(CSP_BGA balls: F6-10, G6-10, H6-10, J6-10, K6-10) to provide

thermal pathways to the printed circuit board’s ground plane. A

heatsink should be attached to the ground plane (as close as pos-

sible to the thermal pathways) with a thermal adhesive.

16.0

14.0

Y = 0.0743X + 1.5613

12.0

RISE TIME

10.0

8.0

FALL TIME

6.0

Y = 0.0414X + 2.0128

T

= T

+ PD  



CASE

AMB

CA

4.0

where:

2.0

0

• T_CASE= Case temperature (measured on top surface

of package)

0

20

40

60

80

100 120 140 160 180 200

LOAD CAPACITANCE – pF

• T_AMB= Ambient temperature °C

Figure 39. Typical Output Rise/Fall Time (20% – 80%, V_DDEXT= Max)

• PD = Power dissipation in W (this value depends upon the

specific application; a method for calculating PD is shown

under Power Dissipation).

16.0

14.0

• _CA= Value from Table 39.

Y = 0.0773X + 1.4399

12.0

Table 39. Airflow Over Package Versus _CA

RISE TIME

10.0

Airflow (Linear Ft./Min.)

0

200

400

1



_CA(°C/W)_JC

17.9

15.2

13.7

8.0

1

= 6.8°C/W.

FALL TIME

6.0

Y = 0.0417X + 1.8674

4.0

2.0

0

20

40

60

80

100 120 140 160 180 200

LOAD CAPACITANCE – pF

Figure 40. Typical Output Rise/Fall Time (20% – 80%, V_DDEXT= Min)

Rev. C

|

Page 55 of 60

|

January 2013

ADSP-21161N

225-BALL CSP_BGA BALL CONFIGURATIONS

Table 40. 225-Ball CSP_BGA Ball Assignments

Ball Name

NC

Ball Number

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

E01

E02

E03

E04

E05

E06

E07

E08

E09

E10

E11

E12

E13

E14

E15

J01

Ball Name

TRST

Ball Number

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

F01

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

F13

F14

F15

K01

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

K12

K13

K14

K15

Ball Name

TMS

Ball Number

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

C15

G01

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

L01

Ball Name

TDO

Ball Number

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

H01

H02

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

M01

M02

M03

M04

M05

M06

M07

M08

M09

M10

M11

M12

M13

M14

M15

BMSTR

BMS

TDI

EMU

TCK

RPBA

GND

FLAG11

MISO

SPIDS

EBOOT

LBOOT

SCLK2

D3B

MOSI

SPICLK

D0B

FS0

SCLK0

D1B

SCLK1

D2B

D1A

D2A

FS1

D3A

FS2

V_DDINT

L0DAT4

L0ACK

L0DAT2

L1DAT6

L1CLK

L1DAT2

NC

L0DAT7

L0CLK

L0DAT1

L1DAT4

L1ACK

L1DAT0

RSTOUT¹

FLAG5

FLAG7

FLAG9

FLAG6

V_DDINT

FS3

SCLK3

L0DAT5

L0DAT3

L1DAT5

DATA42

DATA46

DATA44

FLAG0

IRQ0

L0DAT6

L1DAT7

L1DAT3

L1DAT1

DATA45

DATA47

FLAG1

FLAG2

FLAG4

FLAG3

V_DDEXT

FLAG10

RESET

FLAG8

D0A

V_DDINT

IRQ1

V_DDEXT

V_DDINT

GND

V_DDEXT

V_DDINT

GND

V_DDEXT

V_DDINT

GND

V_DDEXT

L0DAT0

DATA39

DATA43

DATA41

IRQ2

V_DDINT

V_DDEXT

V_DDINT

DATA37

DATA40

DATA38

DATA36

TIMEXP

ADDR22

ADDR20

ADDR23

V_DDINT

DATA34

DATA35

DATA33

DATA32

ADDR19

ADDR17

ADDR21

ADDR2

V_DDEXT

DATA29

DATA28

DATA30

DATA31

ADDR16

ADDR12

ADDR18

ADDR6

ADDR0

MS1

ID1

J02

L02

ID2

J03

L03

ID0

J04

L04

V_DDEXT

GND

J05

L05

J06

GND

V_DDINT

L06

GND

J07

GND

V_DDEXT

L07

BR6

GND

J08

GND

V_DDINT

L08

V_DDEXT

WR

GND

J09

GND

V_DDEXT

L09

GND

J10

GND

V_DDINT

L10

SDA10

RAS

V_DDEXT

DATA26

DATA24

DATA25

DATA27

J11

V_DDINT

V_DDEXT

L11

J12

DATA22

DATA19

DATA21

DATA23

CAS

L12

ACK

J13

DATA20

DATA16

DATA18

L13

DATA17

DMAG2

DMAG1

J14

L14

J15

L15

Rev. C

|

Page 56 of 60

|

January 2013

ADSP-21161N

Table 40. 225-Ball CSP_BGA Ball Assignments (Continued)

Ball Name

ADDR14

ADDR15

ADDR10

ADDR5

ADDR1

MS0

Ball Number

N01

Ball Name

ADDR13

ADDR9

ADDR8

ADDR4

MS2

Ball Number

P01

Ball Name

NC

Ball Number

R01

Ball Name

Ball Number

N02

P02

ADDR11

ADDR7

ADDR3

MS3

R02

N03

P03

R03

N04

P04

R04

N05

P05

R05

N06

SBTS

P06

PA

R06

BR5

N07

BR4

P07

BR3

R07

BR2

N08

BR1

P08

RD

R08

BRST

N09

SDCLK1

SDCLK0

REDY

P09

CLKOUT

HBR

R09

SDCKE

CS

N10

P10

R10

N11

P11

HBG

R11

CLK_CFG1

CLK_CFG0

AVDD

N12

CLKIN

DQM

P12

CLKDBL

XTAL

R12

N13

P13

R13

N14

AGND

P14

SDWE

R14

DMAR1

N15

DMAR2

P15

NC

R15

¹RSTOUT exists only for silicon revisions 1.2 and greater. Leave this ball unconnected for silicon revisions 0.3, 1.0, and 1.1.

14

12

10

8

6

4

2

15

13

11

9

7

5

3

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

KEY:

*

GND

VDDINT

VDDEXT

AVDD

AGND

SIGNAL

*

USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL

PATHWAYS TO YOUR PRINTED CIRCUIT BOARD GROUND PLANE

Figure 41. 225-Ball CSP_BGA Ball Assignments (Bottom View, Summary)

Rev. C

|

Page 57 of 60

|

January 2013

ADSP-21161N

OUTLINE DIMENSIONS

The ADSP-21161N comes in a 17 mm  17 mm, 225-ball

CSP_BGA package with 15 rows of balls.

17.20

17.00 SQ

16.80

A1 BALL

CORNER

A1 BALL

CORNER

14 12 10

15 13 11

8

6

4

2

3 1

9

7

5

A

B

D

F

C

E

G

J

14.00

BSC SQ

H

K

M

P

1.00

BSC

L

N

R

TOP VIEW

0.50

BOTTOM VIEW

DETAIL A

REF

*

1.31

1.21

1.10

DETAIL A

*

0.54

0.50

0.30

1.85

1.71

1.40

0.70

0.60

0.50

COPLANARITY

0.20

SEATING

PLANE

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-192-AAF-2

WITH THE EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.

Figure 42. 225-Ball CSP_BGA (BC-225-1)

SURFACE-MOUNT DESIGN

Table 41 is provided as an aid to PCB design. For industry stan-

dard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern

Standard.

Table 41. BGA Data for Use with Surface-Mount Design

Package

Ball Attach Type

Solder Mask Opening

Ball Pad Size

225-Ball CSP_BGA (BC-225-1)

Solder Mask Defined

0.40 mm diameter

0.53 mm diameter

ORDERING GUIDE

On-Chip

Package

Description

Package

Option

Model¹

Temperature Range²

0C to 85C

–40C to +105C

0C to 85C

–40C to +105C

–40C to +125C

Instruction Rate

SRAM

1M bit

ADSP-21161NKCA-100

ADSP-21161NCCA-100

ADSP-21161NKCAZ100

ADSP-21161NCCAZ100

ADSP-21161NYCAZ110

100 MHz

110 MHz

225-Ball CSP_BGA BC-225-1

¹Z = RoHS Compliant Part.

²Referenced temperature is case temperature.

Rev. C

|

Page 58 of 60

|

January 2013

ADSP-21161N

Rev. C

|

Page 59 of 60

|

January 2013

ADSP-21161N

©

registered trademarks are the property of their respective owners.

D02935-0-1/13 (C)

Rev. C

|

Page 60 of 60

|

January 2013


型号：	ADSP-21161NCCAZ100
厂家：	ADI
描述：	SHARC Processor SHARC处理器微控制器和处理器外围集成电路数字信号处理器时钟
文件：	总60页 (文件大小：789K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21161NCCAZ100 [ADI]

相关型号：

ADSP-21161NKCA-100

ADSP-21161NKCA-100

ADSP-21161NKCAZ-100

ADSP-21161NKCAZ100

ADSP-21161NKCAZ100

ADSP-21161NYCAZ110

ADSP-21261

ADSP-21261SKBC-150

ADSP-21261SKBCZ-X

ADSP-21261SKBCZ150

ADSP-21261SKSTZ-X

ADSP-21261SKSTZ150