ADSP-21262SKBC-200X_技术文档

PRELIMINARY TECHNICAL DATA

S

a

High Performance Floating-Point Processor

ADSP-21262

DAI incorporates a precision clock generator (PCG), and

Input Data Port (IDP) which includes the parallel data

acquisition port (PDAP), all under software control

through the Signal Routing Unit (SRU)

Preliminary Technical Data

SUMMARY

High performance 32-bit floating-point processor

optimized for high precision signal processing

applications

Single-Instruction Multiple-Data (SIMD) computational

architecture—two 32-bit IEEE floating-point/32-bit

fixed point/40-bit extended precision floating point

computational units, each with a multiplier, ALU,

shifter, and register file

On-chip memory — 2 Mbits of on-chip SRAM and a

dedicated 4 Mbits of on-chip mask-programmable

ROM

Six independent synchronous serial ports provide a

variety of serial communication protocols

The ADSP-21262 is available with a 200MHz core

instruction rate. For complete ordering information,

see Ordering Guide on page 43

High bandwidth I/O — A Parallel port, SPI port, Serial

ports, Digital Applications Interface (DAI), and JTAG.

FUNCTIONAL BLOCK DIAGRAM

CORE PROCESSOR

DUAL-PORTED SRAM

DUAL-PORTED ROM

TWO INDEPENDENT

INSTRUCTION

CACHE

32 X 48-BIT

TWO INDEPENDENT

BLOCKS

TIMER

ADDR

DATA

ADDR

DATA

ADDR

DATA

ADDR

DATA

DAG1

8X4X32

DAG2

8X4X32

PROGRAM

SEQUENCER

IOD

32

IOA

18

32

PM ADDRESS BUS

32

64

DM ADDRESS BUS

PM DATA BUS

PX REGISTER

64

DM DATA BUS

6

4

JTAG TEST & EMULATION

GPIO FLAGS/IRQ/TIMEXP

DMA CONTROLLER

22 CHANNELS

PARAL LEL PORT

DATA

REGISTER

FI LE

(PEX)

DATA

REGISTER

FILE

(PEY)

IOP

RE GIS TE RS

(MEMORY MAPPED)

16

3

ADDRES S/DATA BUS / GP IO

CONT RO L/GPIO

BARREL

SHIFTER

BARREL

SHIFTER

16 X 40-BIT

CONTROL,

STATUS, &

4

MULT

SPI PORT (1)

DATA BUFFERS

SERIAL PORTS (6)

SIGNAL

ROUTING

UNIT

ALU

INPUT

DATA PO RT (8)

20

PRECISION CLOCK

GENERATOR (1)

DAI

3

TIMERS (3)

I/O PROCESSOR

REV. PrB

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PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

ADSP-21262

August 2003

KEY FEATURES

Left-justified Sample Pair and I²S Support,

At 200 MHz (5 ns) core instruction rate, the ADSP-21262

performs 1200 MFLOPS/800 MMACS

Super Harvard Architecture—three independent buses for

dual data fetch, instruction fetch, and nonintrusive,

zero-overhead I/O

2 Mbits on-chip dual-ported SRAM (1Mbit block 0, 1Mbit

block 1) for simultaneous access by core processor and

DMA

programmable direction for up to 24 simultaneous

receive or transmit channels using two I²S

compatible stereo devices per serial port

TDM support for telecommunications interfaces

including 128 TDM channel support for newer

telephony interfaces such as H.100/H.110

Up to 12 TDM stream support, each with 128 channels

per frame

4 Mbits on-chip dual-ported mask-programmable ROM (2

Mbits in block 0 and 2 Mbits in block 1)

Companding selection on a per channel basis in TDM

mode

Dual Data Address Generators (DAGs) with modulo and

bit-reverse addressing

Zero-overhead looping with single-cycle loop setup,

providing efficient program sequencing

Input Data Port provides an additional input path to the

DSP core configurable as 8 channels of serial data or 7

channels of serial data and a single channel of up to a

20-bit wide parallel data

Single Instruction Multiple Data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution— Each processing element

executes the same instruction, but operates on

different data

Code compatibility— At assembly level, uses the same

instruction set as other SHARC DSPs

Parallelism in busses and computational units allows:

Single cycle executions (with or without SIMD) of: a

multiply operation, an ALU operation, a dual memory

read or write, and an instruction fetch

Signal Routing Unit provides configurable and flexible

connections between all DAI components, 6 serial

ports, 3 timers, 10 interrupts, 6 flag inputs, 6 flag

outputs, and 20 SRU I/O pins (DAI_Px)

Serial Peripheral Interface (SPI)

Master or slave serial boot through SPI

Full-duplex operation

Master-Slave mode multi-master support

Open drain outputs

Programmable baud rates, clock polarities and phases

3 Muxed Flag/IRQ lines

1 Muxed Flag/Timer expired line

Transfers between memory and core at up to four 32-bit

floating- or fixed-point words per cycle, sustained 2.4

Gbytes/s bandwidth at 200 MHz core instruction rate

Accelerated FFT butterfly computation through a

multiply with add and subtract instruction

DMA Controller supports:

ROM Based Security features:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware

multiplier/divider ratios

22 zero-overhead DMA channels for transfers between

ADSP-21262 internal memory and serial ports (12),

the input data port (IDP) (8), SPI-compatible port (1),

and the parallel port (1)

JTAG background telemetry for enhanced emulation

features

IEEE 1149.1 JTAG standard test access port and on-chip

emulation

32-bit background DMA transfers at core clock speed, in

parallel with full-speed processor execution

Asynchronous parallel/external port provides:

Access to asynchronous external memory

16 multiplexed address/data lines support 24-bit

address external address range with 8-bit data or

16-bit address external address range with 16-bit

data

Dual voltage: 3.3 V I/O, 1.2 V core

Available in 136-ball BGA and 144-lead LQFP packages

66 Mbyte per sec transfer rate for 200 MHz core rate

256 word page boundaries

External memory access in a dedicated DMA channel

8- to 32- bit and 16- to 32-bit word packing options

Programmable wait state options: 2 to 31 CCLK

Digital Applications Interface (DAI) includes 6 serial ports,

a Precision Clock generator, an Input Data Port, 3 timers

and a Signal Routing Unit

Serial Ports provide:

Six dual data line serial ports that operate at up to 50

Mbits/s for a 200 MHz core on each data line — each

has a clock, frame sync and two data lines that can be

configured as either a receiver or transmitter pair

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

2

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PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

August 2003

ADSP-21262

GENERAL DESCRIPTION

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core

processor cycle

The ADSP-21262 SHARC DSP is a member of the SIMD

SHARC family of DSPs featuring Analog Devices' Super

Harvard Architecture. The ADSP-21262 is source code compat-

ible with the ADSP-21160 and ADSP-21161 DSPs as well as

with first generation ADSP-2106x SHARC processors in SISD

(Single-Instruction, Single-Data) mode. Like other SHARC

DSPs, the ADSP-21262 is a 32-bit processor optimized for high

precision signal processing applications. The ADSP-21262 is

available in a 200 MHz core, dual-ported on-chip SRAM and

mask-programmable ROM, multiple internal buses to eliminate

I/O bottlenecks, and an innovative Digital Applications Interface

(DAI).

• Three Programmable Interval Timers with PWM Gener-

ation, PWM Capture/Pulse width Measurement, and

External Event Counter Capabilities

• On-Chip SRAM (2 Mbits)

• On-Chip dual-ported mask-programmable ROM (4

Mbits)

• 8- or 16-bit Parallel port that supports interfaces to

off-chip memory peripherals

• DMA controller

The ADSP-21262 offers a Single-Instruction Multiple-Data

(SIMD) architecture, which was first introduced with the

ADSP- 21160 and ADSP-21161. As shown in the functional

block diagram on page 1, the ADSP-21262 uses two computa-

tional units to deliver a 5 to 10 times performance increase over

the ADSP-2106x on a range of DSP algorithms. Fabricated in a

state-of-the-art, high speed, low power CMOS process, the

ADSP-21262 DSP achieves an instruction cycle time of 5 ns at

200 MHz. With its SIMD computational hardware, the

ADSP-21262 can perform1200MFLOPS runningat200 MHz.

• Six full duplex serial ports

• SPI-compatible interface

• Digital Applications Interface that includes a precision

clock generator (PCG), an input data port (IDP), 6 serial

ports, 8 serial interfaces, a 20-bit parallel input port, 10

interrupts, 6 flag outputs, 6 flag inputs, 3 timers, and a

flexible signal routing unit (SRU)

• JTAG test access port

Figure 1 on page 4 shows one sample configuration of a SPORT

2

Table 1 shows performance benchmarks for the ADSP-21262.

using the precision clock generator to interface with an I S ADC

2

and an I S DAC with a much lower jitter clock than the serial

Table 1. ADSP-21262 Benchmarks (at 200 MHz)

Speed

port would generate itself. Many other SRU configurations are

possible.

Benchmark Algorithm

(at 200 MHz)

ADSP-21262 Family Core Architecture

The ADSP-21262 is code compatible at the assembly level with

theADSP-21160andADSP-21161,andwiththefirstgeneration

ADSP-2106x SHARC DSPs. The ADSP-21262 shares architec-

tural features with the ADSP-2126x and ADSP-2116x SIMD

SHARC family of DSPs, as detailed in the following sections.

1024 Point Complex FFT (Radix 4,

with reversal)

46 µs

FIR Filter (per tap)¹

IIR Filter (per biquad)¹

Matrix Multiply (pipelined)

[3x3] x [3x1]

2.5 ns

10 ns

22.5 ns

40 ns

SIMD Computational Engine

[4x4] x [4x1]

The ADSP-21262 contains two computational processing

elements that operate as a Single-Instruction Multiple-Data

(SIMD) engine. The processing elements are referred to as PEX

and PEY and each contains an ALU, multiplier, shifter and

register file. PEX is always active, and PEY may be enabled by

setting the PEYEN mode bit in the MODE1 register. When this

mode is enabled, the same instruction is executed in both pro-

cessing elements, but each processing element operates on

different data. This architecture is efficient at executing math

intensive DSP algorithms.

Divide (y/x)

Inverse Square Root

15 ns

22.5 ns

1

Assumes two files in multichannel SIMD mode

The ADSP-21262 continues SHARC’s industry leading

standardsofintegrationforDSPs,combiningahighperformance

32-bit DSP core with integrated, on-chip system features. These

features include 2 Mbits dual-ported SRAM memory, 4 Mbits

dual-ported ROM, an I/O processor that supports 22 DMA

channels, six serial ports, an SPI interface, external parallel bus,

and Digital Applications Interface (DAI).

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the

bandwidth between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

The block diagram of the ADSP-21262 on page 1, illustrates the

following architectural features:

• Two processing elements, each of which comprises an

ALU, Multiplier, Shifter and Data Register File

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

PrB

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PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

ADSP-21262

August 2003

ADSP-21262

CLKOUT

CLKIN

CLOCK

ALE

XTAL

2

LATCH

AD15-0

ADDR

CLK_CFG1-0

PARALLEL

PORT

RAM ROM

BOOT ROM

I/O DEVICE

2

3

BOOTCFG1-0

FLAG3-1

DATA

OE

RD

WR

WE

CS

FLAG0

ADC

(OPTIONAL)

CLK

FS

DAI_P1

DAI_P2

DAI_P3

SDAT

SCLK0

SFS0

SRU

SD0A

SD0B

DAC

(OPTIONAL)

CLK

DAI_ P18

DAI_P19

DAI_ P20

SPORT0

SPORT 1

SPORT2

SPORT3

SPORT4

FS

SDAT

SPORT5

CLK

FS

PCGA

PCGB

DAI

RESET

JTAG

6

Figure 1. ADSP-21262 System Sample Configuration

Independent, Parallel Computation Units

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21262 features an enhanced Harvard architecture in

whichthedatamemory(DM)bustransfersdataandtheprogram

memory (PM) bus transfers both instructions and data (see the

Figure on page 1). With the ADSP-21262’s separate program

and data memory buses and on-chip instruction cache, the

processor can simultaneously fetch four operands (two over each

data bus) and one instruction (from the cache), all in a single

cycle.

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier and shifter. Theseunitsperform alloperations

in a single cycle. The three units within each processing element

are arranged in parallel, maximizing computational throughput.

Single multi-function instructions execute parallel ALU and

multiplier operations. InSIMD mode, the parallelALU and mul-

tiplier operations occur in both processing elements. These

computation units support IEEE 32-bit single-precision float-

ing-point, 40-bit extended precision floating-point, and 32-bit

fixed-point data formats.

Instruction Cache

The ADSP-21262 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective — only the instructions whose

fetchesconflictwithPMbusdataaccessesarecached. Thiscache

allows full-speed execution of core, looped operations such as

digital filter multiply-accumulates and FFT butterfly processing.

Data Register File

A general purpose data register file is contained in each process-

ing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

registerfiles,combinedwiththeADSP-2126xenhancedHarvard

architecture, allow unconstrained data flow between computa-

tionunitsandinternalmemory. TheregistersinPEXarereferred

to as R0-R15 and in PEY as S0-S15.

Data Address Generators With Zero-Overhead

Hardware Circular Buffer Support

The ADSP-21262’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffersinhardware.Circularbuffersallowefficientprogramming

of delay lines and other data structures required in digital signal

processing, and are commonly used in digital filters and Fourier

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

4

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PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

August 2003

ADSP-21262

transforms. The two DAGs of the ADSP-21262 contain suffi-

cient registers to allow the creation of up to 32 circular buffers

(16 primary register sets, 16 secondary). The DAGs automati-

cally handle address pointer wrap-around, reduce overhead,

increase performance, and simplify implementation. Circular

buffers can start and end at any memory location.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User's Guide”.

DMA Controller

The ADSP-21262’s on-chip DMA controller allows zero-over-

head data transfers without processor intervention. The DMA

controller operates independently and invisibly to the processor

core, allowing DMA operations to occur while the core is simul-

taneously executing its program instructions. DMA transfers can

occur between the ADSP-21262’s internal memory and its serial

ports, the SPI-compatible (Serial Peripheral Interface) port, the

IDP(InputData Port), ortheparallelport. Twenty-twochannels

of DMA are available on the ADSP-21262 — one for the SPI

interface, twelve via the serial ports, eight via the Input Data Port

and one via the processor’s parallel port. Programs can be down-

loaded to the ADSP-21262 using DMA transfers. Other DMA

features include interrupt generation upon completion of DMA

transfers, and DMA chaining for automatic linked DMA

transfers.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21262 can conditionally execute a multiply, an add, and

a subtract in both processing elements while branching, and

fetching up to four 32-bit values from memory — all in a single

instruction.

ADSP-21262 Memory and I/O Interface Features

TheADSP-21262addsthefollowingarchitecturalfeaturestothe

SIMD SHARC family core:

Dual-Ported On-Chip Memory

The ADSP-21262 contains two megabits of internal SRAM and

four megabits of internal mask-programmable ROM. Each block

can be configured for different combinations of code and data

storage (see ADSP-21262 Memory Map on page 6). Each

memory block is dual-ported for single-cycle, independent

accesses by the core processor and I/O processor. The

dual-portedmemory,incombinationwiththreeseparateon-chip

buses, allow two data transfers from the core and one from the

I/O processor, in a single cycle.

Digital Applications Interface (DAI)

The Digital Applications Interface (DAI) provides the ability to

connect various peripherals to any of the DSPs DAI pins

(DAI_P[20:1]).

You make these connections using the Signal Routing Unit

(SRU).

The SRU is a matrix routing unit (or group of multiplexers) that

enablestheperipherals providedby theDAItobeinterconnected

under software control. This lets you use the DAI associated

peripherals for a much wider variety of applications by using a

larger set of algorithms than is possible with non-configurable

signal paths.

On the ADSP-21262, the SRAM can be configured as a

maximum of 64K words of 32-bit data, 128K words of 16-bit

data, 42.67K words of 48-bit instructions (or 40-bit data), or

combinations of different word sizes up to two megabits. All of

the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit

words. A 16-bit floating-point storage format is supported that

effectivelydoublestheamountofdatathatmaybestoredon-chip.

Conversion between the 32-bit floating-point and 16-bit float-

ing-pointformatsisperformedinasingleinstruction. Whileeach

memory block can store combinations of code and data, accesses

are most efficient when one block stores data using the DM bus

for transfers, and the other block stores instructions and data

using the PM bus for transfers.

The DAI also includes 6 serial ports, a precision clock generator

(PCG), aninputdataport(IDP), 6flagoutputsand6flaginputs,

and 3 timers. The IDP provides an additional input path to the

DSP core, which can be configured for up to eight channels of

2

input serial data (including I S format). Each data channel has

its own DMA channel that is independent from the

ADSP-21262's serial ports.

ForcompleteinformationonusingtheDAI, seetheADSP-2126x

Using the DM bus and PM buses, with one dedicated to each

memory block assures single-cycle execution with two data trans-

fers. In this case, the instruction must be available in the cache.

SHARC DSP Hardware Reference

.

Serial Ports

The ADSP-21262 features six synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices. The serial ports are made up of

two data lines, a clock and frame sync. The data lines can be

programmed to either transmit or receive.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21262

processor to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processorstacks. Theprocessor'sJTAGinterfaceensuresthatthe

emulator will not affect target system loading or timing.

Serial ports are enabled via 12 programmable and simultaneous

receive or transmit pins that support up to 24 transmit or 24

receive channels of serial data when all six SPORTS are enabled,

or six full duplex TDM streams of 128 channels per frame.

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

PrB

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PRELIMINARY TECHNICAL DATA

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August 2003

ADSP-21262

ADDRESS

IOP REGISTERS

0x0000 0000 - 0x0003 FFFF

0x0004 0000

BLOCK 0 SRAM (1Mbit)

0x0004 3FFF

RESERVED

0x0004 4000 - 0x0005 7FFF

0x0005 8000

BLOCK 0 ROM (2 Mbit)

LONG WORD

ADDRESS

SPACE

ADDRESS

0x0005 FFFF

0x0006 0000

0x0020 0000

RESERVED

0x00FF FFFF

0x0100 0000

BLOCK 1 SRAM (1 Mbit)

0x0006 3FFF

RESERVED

0x0006 4000 - 0x0007 7FFF

0x0007 8000

BLOCK 1 ROM (2 Mbit)

EXTERNAL DMA

ADDRESS SPACE

1

0x0007 FFFF

0x0008 0000

0x02FF FFFF

0x0300 0000

BLOCK 0 SRAM (1 Mbit)

RESERVED

0x0008 7FFF

0x3FFF FFFF

0x0008 8000 - 0x000A FFFF

0x000B 0000

NORMAL WORD

ADDRESS

2

EXTERNAL MEMORY

SPACE

BLOCK 0 ROM (2 Mbit)

0x000B FFFF

0x000C 0000

SPACE

BLOCK 1 SRAM (1 Mbit)

RESERVED

0x000C 7FFF

0x000C 8000 - 0x000E FFFF

0x000F 0000

3

1

BLOCK 1 ROM (2 Mbit)

EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE BY THE

CORE. DMA MUST BE USED TO READ OR WRITE TO THIS

MEMORY USING THE SPI OR PARALLEL PORT.

0x000F FFFF

0x0010 0000

2

3

BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE

(0x000A 0000 - 0x000A AAAA).

BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE

BLOCK 0 SRAM (1 Mbit)

(0x000E 0000 - 0x000E AAA).

0x0010 FFFF

0x0011 0000 - 0x0015 FFFF

RESERVED

0x0016 0000

BLOCK 0 ROM (2 Mbit)

0x0017 FFFF

0x0018 0000

SHORT WORD

ADDRESS

SPACE

BLOCK 1 SRAM (1 Mbit)

0x0018 FFFF

0x0019 0000 - 0x001D FFFF

0x001E 0000

RESERVED

BLOCK 1 ROM (2 Mbit)

0x001F FFFF

INTERNAL MEMORY

SPACE

Figure 2. ADSP-21262 Memory Map

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-21262

The serial ports operate at up to one-quarter of the DSP core

clockrate,providingeachwithamaximumdatarateof50Mbits/s

for a 200 MHz core. Serial port data can be automatically trans-

ferred to and from on-chip memory via dedicated DMA

channels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. One SPORT

provides two transmit signals while the other SPORT provides

the two receive signals. The frame sync and clock are shared.

DMA transfers are used to move data to and from internal

memory. Access to the core is also facilitated through the parallel

port register read/write functions. The RD, WR, and ALE

(Address Latch Enable) pins are the control pins for the parallel

port.

Timers

The ADSP-21262 has a total of four timers: a core timer able to

generate periodic interrupts and three general purpose timers

that can that can generate periodic interrupts and be indepen-

dently set to operate in one of three modes:

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I²S mode

• Pulse Waveform Generation mode

• Pulse Width Count /Capture mode

• External Event Watchdog mode

• Left-justified sample pair mode

Left-justified Sample Pair Mode is a mode in which each Frame

Sync cycle two samples of data are transmitted/received — one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. The user has control over various

attributes of this mode.

The core timer can be configured to use FLAG3 as a Timer

Expired signal, and each general purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bitperiodregister, anda 32-bitpulsewidthregister. Asingle

control and status register enables or disables all three general

purpose timers independently.

Each of the serial ports supports the Left-justified Sample Pair

2

and I S protocols (I S is an industry standard interface

commonly used by audio codecs, ADCs and DACs), with two

datapins,allowingfourLeft-justifiedSamplePairorI Schannels

ROM Based Security

2

The ADSP-21262 has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

Whenusingthisfeature, theDSPdoesnotboot-loadanyexternal

code, executing exclusively from internal SRAM/ROM. Addi-

tionally, the DSP is not freely accessible via the JTAG port.

Instead, a unique 64-bit key, which must be scanned in through

the JTAG or Test Access Port will be assigned to each customer.

The device will ignore a wrong key. Emulation features and

external boot modes are only available after the correct key is

scanned.

(using two stereo devices) per serial port, with a maximum of up

to 24 I S channels. The serial ports permit little-endian or

2

big-endian transmission formats and word lengths selectable

from 3 bits to 32 bits. For the Left-justified Sample Pair and I S

2

modes, data-word lengths are selectable between 8 bits and 32

bits. Serial ports offer selectable synchronization and transmit

modes as well as optional µ-law or A-law companding selection

on a per channel basis. Serial port clocks and frame syncs can be

internally or externally generated.

Serial Peripheral (Compatible) Interface

Serial Peripheral Interface (SPI) is an industry standard synchro-

nous serial link, enabling the ADSP-21262 SPI-compatible port

to communicate with other SPI-compatible devices. SPI is an

interface consisting of two data pins, one device select pin, and

one clock pin. It is a full-duplex synchronous serial interface,

supporting both master and slave modes. The SPI port can

operate in a multi-master environment by interfacing with up to

four other SPI-compatible devices, either acting as a master or

slave device. The ADSP-21262 SPI-compatible peripheral

implementation also features programmable baud rate and clock

phase and polarities. The ADSP-21262 SPI-compatible port

uses open drain drivers to support a multi-master configuration

and to avoid data contention.

Program Booting

The internal memory of the ADSP-21262 boots at system

power-up from an 8-bit EPROM via the parallel port, an SPI

master, an SPI slave or an internal boot. Booting is determined

by the Boot Configuration (BOOTCFG1-0) pins. Selection of

the boot source is controlled via SPI as either a master or slave

device, or it can immediately begin executing from ROM.

Phased Locked Loop

The ADSP-21262 uses an on-chip Phase Locked Loop (PLL) to

generate the internal clock for the core. On power up, the

CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1.

After booting, numerous other ratios can be selected via software

control.

Parallel Port

Theratiosaremadeupofsoftwareconfigurablenumeratorvalues

from 1 to 32 and software configurable divisor values of 1, 2, 4,

8, and 16.

The Parallel Port provides interfaces to SRAM and peripheral

devices. The multiplexed address and data pins (AD15-0) can

access8-bitdeviceswithupto24bits of address, or 16-bit devices

with up to 16 bits of address. In either mode, 8- or 16-bit, the

maximum data transfer rate is one-third the core clock speed. As

an example, for a clock rate of 200 MHz, this is equivalent to 66

Mbytes/sec.

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-21262

Power Supplies

real-time characteristics of the program. Essentially, the

The ADSP-21262 has separate power supply connections for the

internal (V_DDINT), external (V_DDEXT), and analog (A_VDD/A_VSS

power supplies. The internal and analog supplies must meet the

1.2V requirement. The external supply must meet the 3.3V

requirement. All external supply pins must be connected to the

same power supply.

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on those

areasintheprogramthatimpactperformanceandtakecorrective

action.

)

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

Note that the analog supply (A_VDD) powers the ADSP-21262’s

clock generator PLL. To produce a stable clock, you should

provide an external circuit to filter the power input to the A_VDD

pin. Place the filter as close as possible to the pin. For an example

circuit, see Figure 3. To prevent noise coupling, use a wide trace

for the analog ground (A_VSS) signal and install a decoupling

capacitor as close as possible to the pin. Note that the A_VSSand

A_VDDpins specified in Figure 3 are inputs to the DSP and not the

analog ground plane on the board.

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program

execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

¹⁰⍀

V

A

VDD

DDINT

• Create custom debugger windows

0.1␮F

0.01␮F

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the ADSP-21xxx

development tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

A

VSS

Figure 3. Analog Power (A_VDD) Filter Circuit

• Control how the development tools process inputs and

generate outputs

Development Tools

The ADSP-21262 is supported with a complete set of

• Maintain a one-to-one correspondence with the tool’s

command line switches

CROSSCORE™ software and hardware development tools,

including Analog Devices emulators and VisualDSP++™ devel-

opment environment. The same emulator hardware that

supports other ADSP-21xxx processors also fully emulates the

ADSP-21262.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resourcemanagementtailoredspecificallytoaddressthememory

and timing constraints of DSP programming. These capabilities

enableengineerstodevelopcodemoreeffectively,eliminatingthe

need to start from the very beginning, when developing new

application code. The VDK features include Threads, Critical

andUnscheduledregions,Semaphores,Events,andDeviceflags.

The VDK also supports Priority-based, Preemptive, Coopera-

tive, and Time-Sliced scheduling approaches. In addition, the

VDK was designed to be scalable. If the application does not use

a specific feature, the support code for that feature is excluded

from the target system.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an algebraic

syntax), an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ runtime library that includes DSP and mathemat-

ical functions. A key point for these tools is C/C++ code

efficiency. The compiler has been developed for efficient transla-

tion of C/C++ code to DSP assembly. The DSP has architectural

features that improve the efficiency of compiled C/C++ code.

Because the VDK is a library, a developer can decide whether to

use it or not. TheVDKis integrated intothe VisualDSP++ devel-

opment environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gener-

ation of various VDK based objects, and visualizing the system

state, when debugging an application that uses the VDK.

TheVisualDSP++debuggerhasanumberofimportantfeatures.

Data visualization is enhanced by a plotting package that offers

a significant level of flexibility. This graphical representation of

user data enables the programmer to quickly determine the per-

formance of an algorithm. As algorithms grow in complexity, this

capability can have increasing significance on the designer’s

development schedule, increasing productivity. Statistical

profiling enables the programmer to non intrusively poll the

processor as it is running the program. This feature, unique to

VisualDSP++, enables the software developer to passively gather

important code execution metrics without interrupting the

VisualDSP++ Component Software Engineering (VCSE) is

Analog Devices technology for creating, using, and reusing

software components (independent modules of substantial func-

tionality) to quickly and reliably assemble software applications.

Download components from the Web and drop them into the

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-21262

application. Publish component archives from within Visu-

alDSP++. VCSE supports component implementation in

C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of

codeanddataontheembeddedsystem. Viewmemoryutilization

in a color-coded graphical form, easily move code and data to

different areas of the DSP or external memory with the drag of

the mouse, examine run time stack and heap usage. The Expert

Linker is fully compatible with existing Linker Definition File

(LDF), allowing the developer to move between the graphical

and textual environments.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide range

of tools supporting the ADSP-21xxx processor family. Hardware

tools include ADSP-21xxx processor PC plug-in cards. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

Designing an Emulator-Compatible DSP

Board (Target)

The Analog Devices family of emulators are tools that every DSP

developer needs to test and debug hardware and software

systems.AnalogDeviceshassuppliedanIEEE1149.1JTAGTest

Access Port (TAP) on each JTAG DSP. Nonintrusive in-circuit

emulation is assured by the use of the processor’s JTAG

interface—the emulator does not affect target system loading or

timing. The emulator usestheTAP toaccess the internalfeatures

of the DSP, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers. The

DSP must be halted to send data and commands, but once an

operation has been completed by the emulator, the DSP system

is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, singleprocessorconnections, multiprocessorscanchains,

signal buffering, signal termination, and emulator pod logic, see

the EE-68: Analog Devices JTAG Emulation Technical Reference on

the Analog Devices website (www.analog.com)—use site search

on “EE-68.” This document is updated regularly to keep pace

with improvements to emulator support.

Additional Information

This data sheet provides a general overview of the ADSP-21262

architecture and functionality. For detailed information on the

ADSP-2126x Family core architecture and instruction set, refer

to the ADSP-2126x DSP Hardware Reference and the

ADSP-21160 SHARC DSP Instruction Set Reference.

This information applies to a product under development. Its characteristics and specifications are subject to change without

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ADSP-21262

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 2: A

=Asynchronous, G=Ground, I = Input, O=Output, P=Power

Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open

Drain, and T = Three-State.

ADSP-21262 pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS, TDI). Inputs

identified as asynchronous (A) can be asserted asynchronously

to CLKIN (or to TCK for TRST).Tie or pull unused inputs to

Unlike previous SHARC processors, the ADSP-21262 contains

internal series resistance equivalent to 360

Ω on the input paths

V

_DDEXTor GND, except for the following:

of all pins. Therefore, for traces longer than six inches, external

series resisters on control, data, clock or frame sync pins are not

required to dampen reflections from transmission line effects for

point-to-point connections. However, for more complex

networks such as a star configuration, series termination is still

recommended.

• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST,

TDI and AD15-0 (NOTE: These pins have pull-up

resistors.)

Table 2. Pin Descriptions

State During &

Type

After Reset

Function

AD15-0

I/O/T

Three-state with Parallel Port Address/Data. The ADSP-21262 parallel port and

pull-up enabled

its corresponding DMA unit output addresses and data for periph-

erals on these multiplexed pins. The multiplex state is determined

by the ALE pin. The parallel port can operate in either 8-bit or 16-bit

mode. Each AD pin has a 22.5 KΩ internal pull-up resistor. See

Address Data Modes on page 14 for details of the AD pin operation:

For 8-bit mode: ALE is automatically asserted whenever a change

occurs in the upper 16 external address bits, A23-8; ALE is used in

conjunction with an external latch to retain the values of the A23-8.

For 16-bit mode: ALE is automatically asserted whenever a change

occurs in the address bits, A15-0; ALE is used in conjunction with

an external latch to retain the values of the A15-0.

To use these pins as flags (FLAGS15-0) set (=1) bit 20 of the

SYSCTL register and disable the parallel port. When used as an

input, the IDP Channel0 can use these pins for parallel input data.

Parallel Port Read Enable. RD is asserted low whenever the DSP

reads 8-bit or 16-bit data from an external memory device. When

AD15-0 are flags, this pin remains deasserted.

Parallel Port Write Enable. WR isasserted lowwhenever theDSP

writes 8-bit or 16-bit data to an external memory device. When

AD15-0 are flags, this pin remains deasserted.

Parallel Port Address Latch enable. ALE is asserted whenever

the DSP drives a new address on the parallel port address pins. On

reset, ALE is active high. However, it can be reconfigured using

software to be active low. When AD15-0 are flags, this pin remains

deasserted.

RD

O

Output only,

driven high¹

WR

ALE

Output only,

driven high¹

Output only,

driven low¹

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Table 2. Pin Descriptions (Continued)

State During &

Type

After Reset

Function

FLAG3-0

I/O/A

Flag Pins. Each FLAG pin is configured via control bits as either

an input or output. As an input, it can be tested as a condition. As

an output, it can be used to signal external peripherals.These pins

can be used as an SPI interface slave select output during SPI

mastering. These pins are also multiplexed with the IRQx and the

TIMEXP signals.

Three-state

In SPI master boot mode, FLAG0 is the slave select pin that must

be connected to an SPI EPROM. FLAG0 is configured as a slave

select during SPI master boot. When bit 16 is set (=1) in the

SYSCTL register, FLAG0 is configured as IRQ0.

When bit 17 is set (=1) in the SYSCTL register, FLAG1 is

configured as IRQ1.

When bit 18 is set (=1) in the SYSCTL register, FLAG2 is

configured as IRQ2.

When bit 19 is set (=1) in the SYSCTL register, FLAG3 is

configured as TIMEXP which indicates that the system timer has

expired.

DAI_P20-1

I/O/T

Digital Applications Interface Pins.These pins provide the

physical interface to the SRU. The SRU configuration registers

define the combination of on-chip peripheral inputs or outputs

connected to the pin and to the pin’s output enable. The configu-

ration registers of these peripherals then determines the exact

behavior of the pin. Any input or output signal present in the SRU

may berouted to any of these pins. The SRU providesthe connection

from the Serial ports, Input data port, precision clock generator and

timer to the DAI_P20-1 pins These pins have internal 22.5 KΩ

pull-up resistors which are enabled on reset. These pull-ups can be

disabled in the DAI_PIN_PULLUP register.

Three-state with

programmable

pull-up

SPICLK

I/O

Serial Peripheral Interface Clock Signal. Driven by the master,

this signal controls the rate at which data is transferred. The master

may transmit data at a variety of baud rates. SPICLK cycles once for

each bit transmitted. SPICLK is a gated clock that is active during

data transfers, only for the length of the transferred word. Slave

devices ignore the serial clock if the slave select input is driven

inactive (HIGH). SPICLK is used to shift out and shift in the data

driven on the MISO and MOSI lines. The data is always shifted out

on one clock edge and sampled on the opposite edge of the clock.

Clock polarity and clock phase relative to data are programmable

into the SPICTL control register and define the transfer format.

SPICLK has a 22.5 KΩ internal pull-up resistor.

Three-state with

pull-up enabled

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Table 2. Pin Descriptions (Continued)

State During &

Type

After Reset

Function

SPIDS

I

Serial Peripheral Interface Slave Device Select. An active low

signal used to select the DSP as an SPI slave device. This input signal

behaves like a chip select, and is provided by the master device for

the slave devices. In multi-master mode the DSPs SPIDS signal can

be driven by a slave device to signal to the DSP (as SPI master) that

an error has occurred, as some other device is also trying to be the

master device. If asserted low when the device is in master mode, it

is considered a multi-master error. For a single-master,

multiple-slave configuration where FLAG pins are used, this pin

must be tied or pulled high to V_DDEXTon the master device. For

ADSP-21262 to ADSP-21262 SPI interaction, any of the master

ADSP-21262's FLAG pins can be used to drive the SPIDS signal on

the ADSP-21262 SPI slave device.

Input only

MOSI

MISO

I/O (O/D)

SPI Master Out Slave In. If the ADSP-21262 is configured as a

master, the MOSI pin becomes a data transmit (output) pin, trans-

mitting output data. If the ADSP-21262 is configured as a slave, the

MOSI pin becomes a data receive (input) pin, receiving input data.

In an ADSP-21262 SPI interconnection, the data is shifted out from

the MOSI output pin of the master and shifted into the MOSI

input(s) of the slave(s). MOSI has a 22.5 KΩ internal pull-up

resistor.

SPI Master In Slave Out. If the ADSP-21262 is configured as a

master, the MISO pin becomes a data receive (input) pin, receiving

input data. If the ADSP-21262 is configured as a slave, the MISO

pin becomes a data transmit (output) pin, transmitting output data.

In an ADSP-21262 SPI interconnection, the data is shifted out from

the MISO output pin of the slave and shifted into the MISO input

pin of the master. MISO has a 22.5 KΩ internal pull-up resistor.

MISO can be configured as O/D by setting the OPD bit in the

SPICTL register.

Three-state with

pull-up enabled

I/O (O/D)

Three-state with

pull-up enabled

Note: Only one slave is allowed to transmit data at any given time.To

enable broadcast transmission to multiple SPI-slaves, the DSP's

MISO pin may be disabled by setting (=1) bit 5 (DMISO) of the

SPICTL register.

BOOTCFG1-0

CLKIN

I

Input only

Boot Configuration Select. This pin is used to select the boot

mode for the DSP. The BOOTCFG pins must be valid before reset

is asserted. See Table 3 for a description of the boot modes.

Local Clock In. Used in conjunction with XTAL. CLKIN is the

ADSP-21262 clock input. It configures the ADSP-21262 to use

either its internal clock generator or an external clock source.

Connecting the necessary components to CLKIN and XTAL

enables the internal clock generator. Connecting the external clock

to CLKIN while leaving XTAL unconnected configures the

ADSP-21262 to use the external clock source such as an external

clock oscillator.The core is clocked either by the PLL output or this

clock input depending on the CLKCFG1-0 pin settings. CLKIN

may not be halted, changed, or operated below the specified

frequency.

XTAL

O

Output only²

Crystal Oscillator Terminal. Used in conjunction with CLKIN

to drive an external crystal.

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Table 2. Pin Descriptions (Continued)

State During &

Type

After Reset

Function

CLKCFG1-0

I

Input only

Core/CLKIN Ratio Control. These pins set the start up clock

frequency. See Table 4 for a description of the clock configuration

modes.

Note that the operating frequency can be changed by programming

the PLL multiplier and divider in the PMCTL register at any time

after the core comes out of reset.

CLKOUT

RESET

TCK

O

I/A

I

Output only

Input only

Input only³

Local Clock Out/ Reset Out. Drives out the core reset signal to an

external device. CLKOUT can also be configured as a reset out

pin.The functionality can be switched between the PLL output clock

andresetoutbysettingbit12ofthePMCTREGregister. Thedefault

is reset out.

Processor Reset. Resets the ADSP-21262 to a known state. Upon

deassertion, thereis a4096CLKIN cycle latencyforthe PLLtolock.

Afterthistime, thecorebeginsprogramexecutionfromthehardware

reset vector address. The RESET input must be asserted (low) at

power-up.

Test Clock (JTAG).ProvidesaclockforJTAGboundaryscan.TCK

must be asserted (pulsed low) after power-up or held low for proper

operation of the ADSP-21262.

TMS

TDI

I/S

O

Three-state with Test Mode Select (JTAG). Used to control the test state machine.

pull-up enabled TMS has a 22.5 KΩ internal pull-up resistor.

Three-state with Test Data Input (JTAG). Provides serial data for theboundaryscan

pull-up enabled

logic. TDI has a 22.5 KΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan

path.

TDO

TRST

Three-state⁴

I/A

Three-state with Test Reset (JTAG). Resets the test state machine. TRST must be

pull-up enabled

asserted (pulsed low) afterpower-up or held lowforproper operation

of the ADSP-21262. TRST has a 22.5 KΩ internal pull-up resistor.

EMU

O (O/D)

P

Three-state with Emulation Status. Must be connected to the ADSP-21262 Analog

pull-up enabled

Devices DSP Tools product line of JTAG emulators target board

connector only. EMU has a 22.5 KΩ internal pullup resistor.

Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s

core processor (13 pins on the BGA package, 32 pins on the LQFP

package).

V_DDINT

V_DDEXT

A_VDD

P

I/O Power Supply. Nominally +3.3 V dc. (6 pins on the BGA

package, 10 pins on the LQFP package).

Analog Power Supply. Nominally +1.2 V dc and supplies the

DSP’s internal PLL (clock generator). This pin has the same speci-

fications as

V_DDINT, except that added filtering circuitry is required. see Power

Supplies on page 8.

A_VSS

GND

G

Analog Power Supply Return.

Power Supply Return. (54 pins on the BGA package, 39 pins on

the LQFP package).

1

RD, WR, and ALE are continuously driven by the DSP and won’t be three-stated.

Output only is a three-state driver with its output path always enabled.

Input only is three-state driver with both output path.

2

3

4

Three-state is three-state driver.

This information applies to a product under development. Its characteristics and specifications are subject to change without

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Boot Modes

Table 3. Boot Mode Selection

BOOTCFG1-0

Booting Mode

00

01

10

11

SPI Slave Boot

SPI Master Boot

Parallel Port boot via EPROM

Internal Boot Mode (ROM code

only)

Core Instruction Rate to CLKIN Ratio Modes

Table 4. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1-0

Core to CLKIN Ratio

00

01

10

3:1

16:1

8:1

Address Data Modes

The following table shows the functionality of the AD pins for

8-bit and 16-bit transfers to the parallel port. For 8-bit data trans-

fers, ALE latches address bits A23-A8 when asserted, followed

by address bits A7-A0 and data bits D7-D0 when deasserted. For

16-bit data transfers, ALE latches address bits A15-A0 when

asserted, followed by data bits D15-D0 when deasserted.

Table 5. Address/ Data Mode Selection

EP Data

Mode

AD7-0

Function

AD15-8

Function

ALE

8-bit

16-bit

Asserted

Deasserted

Asserted

A15-8

D7-0

A7-0

D7-0

A23-16

A7-0

A15-8

D15-8

Deasserted

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ADSP-21262

ADSP-21262 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

Min

Signal

Parameter¹

Max

Unit

V_DDINT

A_VDD

V_DDEXT

V_IH

Internal (Core) Supply Voltage

1.14

3.13

2.0

1.26

V

Analog (PLL) Supply Voltage

1.26

External (I/O) Supply Voltage

3.47

V

High Level Input Voltage², @ V_DDEXT= max

Low Level Input Voltage²@ V_DDEXT= min

Case Operating Temperature³

V_DDEXT+0.5

0.8

V

V_IL

-0.5

0

V

T_CASE

+85

°C

1

2

Specifications subject to change without notice.

Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKIN, CLKCFGx, RESET, TCK,

TMS, TDI, TRST.

3

See Thermal Characteristics on page 36 for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter¹

Test Conditions

Min

Max

Unit

V_OH

V_OL

I_IH

High Level Output Voltage²

Low Level Output Voltage²

High Level Input Current^4,5

Low Level Input Current⁴

@ V_DDEXT= min, I_OH= -1.0 mA³

@ V_DDEXT= min, I_OL= 1.0 mA³

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

2.4

V

µA

0.4

10

I_IL

I_ILPU

I_OZH

I_OZL

I_OZLPU

Low Level Input Current Pull-Up⁵@ V_DDEXT= max, V_IN= 0 V

TBD µA

Three-State Leakage Current ^6,7

Three-State Leakage Current⁶

Three-State Leakage Current

Pull-Up1⁷

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

10

250

µA

I_DD-INTYP

AI_DD

C_IN

Supply Current (Internal)^8,9

Supply Current (Analog)¹⁰

Input Capacitance^11,12

t_CCLK= 5.0 ns, V_DDINT= max

A_VDD= max

f_IN=1 MHz, T_CASE=25°C, V_IN=1.2V

500

10

4.7

mA

pF

1

Specifications subject to change without notice.

Applies to output and bidirectional pins: AD15-0, RD, WR, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

See Output Drive Currents on page 35 for typical drive current capabilities.

2

3

4

Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

5

Applies to input pins with 22.5 KΩ internal pull-ups: TRST, TMS, TDI.

Applies to three-statable pins: AD15-0, FLAG3-0.

Applies to three-statable pins with 22.5 KΩ pull-ups: DAI_Px, SPICLK, EMU, MISO, MOSI.

Typical internal current data reflects nominal operating conditions.

See Engineering-to-Engineering Note (No. TBD) for further information.

Characterized, but not tested.

Applies to all signal pins.

6

7

8

9

10

11

12

Guaranteed, but not tested.

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ADSP-21262

ABSOLUTE MAXIMUM RATINGS

1

Internal (Core) Supply Voltage (V_DDINT

)

0.3 V to +1.5 V

1

Analog (PLL) Supply Voltage (A_VDD

)

-0.3 V to +1.5 V

-0.3 V to +4.6 V

-0.5 V to V_DDEXT¹+ 0.5 V

200 pF

1

External (I/O) Supply Voltage (V_DDEXT

Input Voltage

)

Output Voltage Swing

Load Capacitance¹

Storage Temperature Range¹

-65°C to +150°C

1

Stresses greater than those listed above may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions greater

than those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-21262 features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high-energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid perfor-

mance degradation or loss of functionality.

TIMING SPECIFICATIONS

The ADSP-21262’s internal clock (a multiple of CLKIN)

provides the clock signal for timing internal memory, processor

core, serial ports, and parallel port (as required for read/write

strobesinasynchronousaccessmode).Duringreset,programthe

ratio between the DSP’s internal clock frequency and external

(CLKIN) clock frequency with the CLKCFG1-0 pins. To

determine switching frequencies for the serial ports, divide down

the internal clock, using the programmable divider control of

each port (DIVx for the serial ports).

The ADSP-21262’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the DSP uses an internal phase-locked loop (PLL). This

PLL-based clocking minimizes the skew between the system

clock (CLKIN) signal and the DSP’s internal clock (the clock

source for the parallel port logic and I/O pads).

Note the definitions of various clock periods that are a function

of CLKIN and the appropriate ratio control (Table 6).

Table 6. ADSP-21262 CLKOUT and CCLK Clock Generation Operation

Timing Requirements

Description

Calculation

CLKIN

CCLK

Input Clock

Core Clock

1/t_CK

1/t_CCLK

Timing Requirements

Description¹

t_CK

CLKIN Clock Period

t_CCLK

t_SCLK

t_SPICLK

(Processor) Core Clock Period

Serial Port Clock Period = (t_CCLK) x SR

SPI Clock Period = (t_CCLK) x SPIR

1

where:

SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)

DAI_Px = Serial Port Clock

SPICLK = SPI Clock

This information applies to a product under development. Its characteristics and specifications are subject to change without

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Figure 4 shows Core to CLKIN ratios of 3:1, 8:1 and 16:1 with

external oscillator or crystal.

CLKOUT

CLKIN

XTAL

OSC

PLL

3:1, 8:1,

16:1

CCLK

(CORE CLOCK)

PLLILCLK

XTAL

CLK-CFG [1:0]

Figure 4. Core Clock and System Clock Relationship to CLKIN

Use the exact timing information given. Do not attempt to derive

parameters from the addition or subtraction of others. While

addition or subtraction would yield meaningful results for an

individual device, the values given in this data sheet reflect sta-

tistical variations and worst cases. Consequently, it is not

meaningful to add parameters to derive longer times.

See Figure 29 on page 35 under Test Conditions for voltage

reference levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching charac-

teristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. Timing requirements guarantee that the

processor operates correctly with other devices.

The ADSP-21262’s internal clock (a multiple of CLKIN)

provides the clock signal for timing internal memory, processor

core, serial ports, and parallel port (as required for read/write

strobesinasynchronousaccessmode).Duringreset,programthe

ratio between the DSP’s internal clock frequency and external

(CLKIN) clock frequency with the CLKCFG1-0 pins. To

determine switching frequencies for the serial ports, divide down

the internal clock, using the programmable divider control of

each port (DIVx for the serial ports).

The ADSP-21262’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the DSP uses an internal phase-locked loop (PLL). This

PLL-based clocking minimizes the skew between the system

clock (CLKIN) signal and the DSP’s internal clock (the clock

source for the parallel port logic and I/O pads).

Note the following definitions of various clock periods that are a

function of CLKIN and the appropriate ratio control.

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Power up Sequencing

The timing requirements for DSP startup are given in Table 7.

Table 7. Power Up Sequencing Timing Requirements (DSP Startup)

Name

Parameter

Min

Max

Units

Timing Requirements

t_RSTVDD

t_IVDDEVDD

t_CLKVDD

t_CLKRST

t_PLLRST

RESET low before V_DDINT/V_DDEXTon

V_DDINTon before V_DDEXT

0

ns

ms

µs

ns

-50

0

200

CLKIN valid after V_DDINT/V_DDEXTvalid¹

CLKIN valid before RESET de-asserted

PLL control setup before RESET de-asserted

Subsequent RESET low pulse width⁴

10²

20³

4t_CK

t_WRST

Switching Characteristics

t_CORERSTDSP core reset de-asserted after RESET de-asserted

4, 5

4096t_CK+512 t_CCLK

1

Valid V

/V

assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds

DDINT DDEXT

of milliseconds depending on the design of the power supply subsystem.

2

Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for

startup time. Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Based on CLKIN cycles

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly

initialize and propagate default states at all I/O pins.

3

4

5

The 4096 cycle count depends on t

specification in Table 9. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time,

SRST

resulting in 4097 cycles maximum.

RESET

t_RSTVDD

V

DDINT

t_IVDDEVDD

V

t_CLKVDD

DDEXT

CLKIN

t_CLKRST

CLK_CFG1-0

t_CORERST

t_PLLRST

RSTOUT

Figure 5. Power Up Sequencing

DuringthepowerupsequenceoftheDSP,differencesintheramp

up rates and activation time between the two supplies can cause

current to flow in the I/O ESD protection circuitry. To prevent

this damage to the ESD diode protection circuitry, Analog

Devices recommends including a bootstrap Schottky diode.

ThebootstrapSchottkydiodeisconnectedbetweenthe1.2Vand

3.3V power supplies as shown in Figure 6 on page 19. It protects

the ADSP-21262 from partially powering the 3.3V supply.

Including a Schottky diode will shorten the delay between the

supply ramps and prevent damage to the ESD diode protection

circuitry. With this technique, if the 1.2V rail rises ahead of the

3.3V rail, the Schottky diode pulls the 3.3V rail along with the

1.2V rail.

This information applies to a product under development. Its characteristics and specifications are subject to change without

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DC INPUT

SOURCE

V_DDEXT

3.3V I/O

VOLTAGE

REGULATOR

ADSP-21262

1.2V CORE

VOLTAGE

V_DDINT

REGULATOR

Figure 6. Schottky Diode

Clock Input

Table 8. Clock Input

200 MHz

Min

Parameter

Max

Units

Timing Requirements

t_CK

CLKIN Period

CLKIN Width Low

15¹

6¹

160²

80²

3

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width High

CLKIN Rise/Fall (0.4V-2.0V)

CCLK Period³

6¹

5

10

1

Applies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL.

Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL.

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

2

3

.

CCLK

CLKIN

XTAL

1M⍀

t_CK

CLKIN

t_CKH

t_CKL

C1

C2

X1

Figure 7. Clock Input

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL

SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

Clock Signals

The ADSP-21262 can use an external clock or a crystal. See

CLKIN pin description. The programmer can configure the

ADSP-21262 to use its internal clock generator by connecting

thenecessarycomponentstoCLKINandXTAL.Figure 8shows

the component connections used for a crystal operating in fun-

damental mode.

Figure 8. 200 MHz Operation (Fundamental Mode Crystal)

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Reset

ADSP-21262

Table 9. Reset

Parameter

Min

Max

Units

Timing Requirements

t_WRST

t_SRST

RESET Pulse Width Low¹

RESET Setup Before CLKIN High

4t_CK

8

ns

1

Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET

is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_SRST

t_WRST

RESET

Figure 9. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0

IRQ1, and IRQ2 interrupts.

,

Table 10. Interrupts

Parameter

Min

2 x t_CCLK+2

Max

Units

Timing Requirements

t_IPW

IRQx Pulse Width

ns

FLAG2-0

(IRQ2-0)

t_IPW

Figure 10. Interrupts

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Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Table 11. Core Timer

Parameter

Min

Max

Units

Switching Characteristic

t_WCTIM

CTIMER Pulse width

4 x t_CCLK

ns

t_WCTIM

FLAG3

(CTIMER)

Figure 11. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer[2:0] in

PWM_OUT (pulse width modulation) mode. Timer signals are

routed to the DAI_P[20:1] pins through the SRU. Therefore, the

timingspecificationsprovidedbelowarevalidattheDAI_P[20:1]

pins.

Table 12. Timer[2:0] PWM_OUT Timing

Parameter

Min

2 t_CCLK

Max

2(2³¹-1) t_CCLK

Units

Switching Characteristic

t_PWMO

Timer[2:0] Pulse width Output

ns

t_PWMO

DAI_P[20:1]

(TIMER[2:0])

Figure 12. Timer[2:0] PWM_OUT Timing

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Timer WDTH_CAP Timing

The following timing specification applies to Timer[2:0] in

WDTH_CAP (pulse width count and capture) mode. Timer

signals are routed to the DAI_P[20:1] pins through the SRU.

Therefore, the timing specifications provided below are valid at

the DAI_P[20:1] pins.

Table 13. Timer[2:0] Width Capture Timing

Parameter

Min

2 t_CCLK

Max

Units

Timing Requirement

t_PWI

Timer[2:0] Pulse width

2(2³¹-1) t_CCLK

ns

t_PWI

DAI_P[20:1]

(TIMER[2:0])

Figure 13. Timer[2:0] Width Capture Timing

Flags

The timing specifications provided below apply to the

FLAG[3:0]andDAI_P[20:1]pins,theparallelportandtheserial

peripheral interface (SPI). See Table 2, “Pin Descriptions,” on

page 10 for more information on FLAG use.

Table 14. Flags

Parameter

Min

Max

N x t_CCLK+9

Units

Timing Requirement

t_FIPW

Switching Characteristic

t_FOPWFLAG[3:0] OUT Pulse Width

FLAG[3:0] IN Pulse Width¹

2 x t_CCLK+3

2 x t_CCLK

ns

1

Where N = 0-2 (CLKCFG1-0 = 00), 0-15 (CLKCFG1-0 = 01) or 0-7(CLKCFG1-0 = 10)

DAI_P[20:1]

(FLAG3-0 )

IN

(AD[15:0]

t_FIPW

DAI_P[20:1]

(FLAG3-0_OUT

)

(AD[15:0]

t_FOPW

Figure 14. Flags

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Memory Read–Parallel Port

Use these specifications for asynchronous interfacing to

memories (and memory-mapped peripherals) when the

ADSP-21262 is accessing external memory space.

Table 15. 8-Bit Memory Read Cycle

Name

Parameter

Min

Max

Units

Timing Requirements

t_DRS

t_DRH

t_DAD

Address/data [7:0] setup before RD high

Address/data [7:0] hold after RD high

Address [15:8] to data valid

2

0.5

ns

D + 0.5 x t_CCLK- 2.5

Switching Characteristics

t_ALEW

t_ADAS

t_ADAH

t_ALEHZ

t_RW

ALE pulse width

2 x t_CCLK- 2

Address/data [15:0] setup before ALE deasserted¹2.5 x t_CCLK- 1.0

Address/data [15:0] hold after ALE deasserted¹

ALE deasserted¹to Address/Data[7:0] in high Z

RD pulse width

0.5 x t_CCLK- 0.8

D - 2

0.5 x t_CCLK

ns

t_ADRH

Address/data [15:8] hold after RD high

0.5 x t_CCLK- 1 + H

D = (Data Cycle Duration) x t_CCLK

H= t_CCLK(if a hold cycle is specified, else H = 0)

1

On reset, ALE is an active high cycle. However, it can be configured by software to be active low

t_ALEW

ALE

t_RW

RD

WR

t_ALEHZ

t_ADAH

t_ADAS

t_ADRH

AD[15:8]

VALID ADDRESS

t_DRS

t_DRH

AD[7:0]

VALID DATA

t_DAD

Figure 15. Read Cycle For 8-bit Memory Timing

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Table 16. 16-bit Memory Read Cycle

Name

Parameter

Min

Max

Units

Timing Requirements

t_DRS

t_DRH

Switching Characteristics

Address/data [15:0] setup before RD high

Address/data [15:0] hold after RD high

2

0.5

ns

t_ALEW

t_ADAS

t_ADAH

t_ALEHZ

t_RW

ALE pulse width

2 x t_CCLK- 2

2.5 x t_CCLK- 1.0

0.5 x t_CCLK- 0.8

D - 2

Address/data [15:0] setup before ALE deasserted¹

Address/data [15:0] hold after ALE deasserted¹

ALE deasserted¹to Address/Data[15:0] in high Z

RD pulse width

D = (Data Cycle Duration) x t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

1

On reset, ALE is an active high cycle. However, it can be configured by software to be active low

ALE

t_ALEW

RD

t_RW

WR

t_ADAH

t_DRS

t_DRH

t_ADAS

VALID DATA

AD[15:0]

VALID ADDRESS

t_ALEHZ

Figure 16. Read Cycle For 16-bit Memory Timing

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Memory Write—Parallel Port

Use these specifications for asynchronous interfacing to

memories (and memory-mapped peripherals) when the

ADSP-21262 is accessing external memory space.

Table 17. 8-bit Memory Write Cycle

Name

Parameter

Min

Max

Units

Switching Characteristics:

t_ALEW

t_ADAS

t_ADAH

t_WW

t_ADWL

t_ADWH

t_ALEHZ

t_DWS

ALE pulse width

2 x t_CCLK- 2

2.5 x t_CCLK- 1.0

0.5 x t_CCLK- 0.5

D - 2

0.5 x t_CCLK- 1.5

0.5 x t_CCLK- 1 + H

0.5 x t_CCLK- 1.5

D

ns

Address/data [15:0] setup before ALE deasserted¹

Address/data [15:0] hold after ALE deasserted ¹

WR pulse width

Address/data [15:8] to WR low

Address/data [15:8] hold after WR high

ALE deasserted¹to Address/Data[15:0] in high Z

Address/data [7:0] setup before WR high

Address/data [7:0] hold after WR high

Address/data to WR high

t_DWH

t_DAWH

0.5 x t_CCLK- 1.5 + H

D

D = (Data Cycle Duration) x t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

1

On reset, ALE is an active high cycle. However, it can be configured by software to be active low

ALE

t_ALEW

t_DAWH

WR

t_WW

RD

t_ALEHZ

t_ADAH

t_ADWL

t_ADWH

t_ADAS

AD[15:8]

VALID ADDRESS

t_DWS

t_DWH

VALID ADDRESS

VALID DATA

AD[7:0]

Figure 17. Write Cycle For 8-bit Memory Timing

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Table 18. 16-bit Memory Write Cycle

Name Parameter

Switching Characteristics

Min

Max

Units

t_ALEW

t_ADAS

t_ADAH

t_WW

t_ALEHZ

t_DWS

ALE pulse width

2 x t_CCLK- 2

2.5 x t_CCLK- 1.0

0.5 x t_CCLK- 0.5

D - 2

0.5 x t_CCLK- 1.5

D

ns

Address/data [15:0] setup before ALE deasserted¹

Address/data [15:0] hold after ALE deasserted¹

WR pulse width

ALE deasserted¹to Address/Data[15:0] in high Z

Address/data [15:0] setup before WR high

Address/data [15:0] hold after WR high

t_DWH

0.5 x t_CCLK- 1.5 + H

D = (Data Cycle Duration) x t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

1

On reset, ALE is an active high cycle. However, it can be configured by software to be active low

ALE

t_ALEW

t_WW

WR

RD

t_ALEHZ

t_ADAH

t_ADAS

t_DWS

t_DWH

VALID ADDRESS

AD[15:0]

VALID DATA

Figure 18. Write Cycle For 16-bit Memory Timing

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Serial Ports

Serial port signals (SCLK, FS, DxA,/DxB) are routed to the

DAI_P[20:1] pins using the SRU. Therefore, the timing specifi-

cations provided below are valid at the DAI_P[20:1] pins.

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 19. Serial Ports—External Clock

Parameter

Min

Max

Units

Timing Requirements

t_SFSE

FS Setup Before SCLK

(Externally Generated FS in either Transmit or Receive Mode)¹

FS Hold After SCLK

4

ns

t_HFSE

(Externally Generated FS in either Transmit or Receive Mode)¹5.5

ns

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

Receive Data Setup Before Receive SCLK¹

Receive Data Hold After SCLK¹

SCLK Width

4

5.5

20

40

SCLK Period

Switching Characteristics

t_DFSE

FS Delay After SCLK

(Internally Generated FS in either Transmit or Receive Mode) ²

FS Hold After SCLK

16

ns

t_HOFSE

(Internally Generated FS in either Transmit or Receive Mode)1

Transmit Data Delay After Transmit SCLK¹

Transmit Data Hold After Transmit SCLK¹

1

0

ns

t_DDTE

t_HDTE

1

Referenced to sample edge.

Referenced to drive edge.

2

Table 20. Serial Ports—Internal Clock

Parameter

Min

Max

Units

Timing Requirements

t_SFSI

FS Setup Before SCLK

(Externally Generated FS in either Transmit or Receive Mode)¹14.5

FS Hold After SCLK

ns

t_HFSI

(Externally Generated FS in either Transmit or Receive Mode)¹-4

ns

t_SDRI

t_HDRI

Receive Data Setup Before SCLK¹

Receive Data Hold After SCLK¹

9.5

-2

Switching Characteristics

t_DFSI

FS Delay After SCLK

(Internally Generated FS in Transmit Mode)²

FS Hold After SCLK

7.5

ns

t_HOFSI

t_DFSI

(Internally Generated FS in Transmit Mode)¹

FS Delay After SCLK

-1.5

-4

(Internally Generated FS in Receive or Mode)

FS Hold After SCLK

(Internally Generated FS in Receive Mode)

Transmit Data Delay After SCLK¹

Transmit Data Hold After SCLK¹

Transmit or Receive SCLK Width

11

t_HOFSI

ns

t_DDTI

t_HDTI

t_SCLKIW

7.5

-1.5

0.5t_SCLK-2

0.5t_SCLK+2 ns

1

Referenced to the sample edge.

Referenced to drive edge.

2

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Table 21. Serial Ports—Enable and Three-State

Parameter

Min

Max

Units

Switching Characteristics

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

Data Enable from External Transmit SCLK¹

Data Disable from External Transmit SCLK¹

Data Enable from Internal Transmit SCLK¹

Data Disable from Internal Transmit SCLK¹

2

0

ns

13

3

1

Referenced to drive edge.

Table 22. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Units

Switching Characteristics

t_DDTLFSE

Data Delay from Late External Transmit FS or External

Receive FS with MCE = 1, MFD = 0¹

Data Enable for MCE = 1, MFD = 0¹

16

ns

t_DDTENFS

0.5

1

The t

and t

parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.

DDTENFS

DDTLFSE

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

t_HFSE/I

DRIVE

DIA_P[20:0]

(SCLK)

t_SFSE/I

DIA_P[20:0]

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DIA_P[20:0]

(D A/D B)

X

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE

SAMPLE

t_HFSE/I

DRIVE

DIA_P[20:0]

(SCLK)

t_SFSE/I

DIA_P[20:0]

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DIA_P[20:0]

(D A/D B)

X

2ND BIT

t_DDTLFSE

NOTE

SERIAL PORT SIGNALS (SCLK, FS, DXA,/DXB) ARE ROUTED TO THE DAI_P[20:1] PINS USING THE SRU.

THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.

Figure 19. External Late Frame Sync¹

1

This figure reflects changes made to support Left-justified Sample Pair mode.

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DATA RECEIVE— INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE— EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(SCLK)

t_DFSI

t_DFSE

t_HFSE

t_HFSI

t_SFSI

t_SFSE

t_HOFSI

t_HOFSE

DAI_P[20:1]

(FS)

DAI_P[20:1]

(FS)

t_HDRE

t_SDRI

t_HDRI

t_SDRE

DAI_P[20:1]

(D A/D B)

X X

X

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT — INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT — EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(SCLK)

t_DFSI

t_DFSE

t_HFSI

t_HOFSI

t_SFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P[20:1]

(FS)

DAI_P[20:1]

(FS)

t_DDTE

t_DDTI

t_HDTE

t_HDTI

DAI_P[20:1]

(D A/D B)

X X

X

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

DAI_P[20:1]

SCLK (EXT)

SCLK

t_DDTEN

t_DDTTE

DAI_P[20:1]

D

A/D B

X

DRIVE EDGE

SCLK

DAI_P[20:1]

SCLK (INT)

t_DDTIN

t_DDTTI

DAI_P[20:1]

D

A/D B

X

Figure 20. Serial Ports

This information applies to a product under development. Its characteristics and specifications are subject to change without

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Input Data Port

The timing requirements for the IDP are given in Table 23.IDP

Signals(SCLK, FS, SDATA)areroutedtotheDAI_P[20:1]pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P[20:1] pins.

Table 23. IDP

Parameter

Min

Max

Units

Timing Requirements

t_SIFS

t_SIHFS

t_SISD

t_SIHD

t_IDPCLKW

t_IDPCLK

FS Setup Before SCLK Rising Edge¹

FS Hold After SCLK Rising Edge¹

SData Setup Before SCLK Rising Edge¹

SData Hold After SCLK Rising Edge¹

Clock Width

4

5.5

4

5.5

9

20

ns

Clock Period

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any

of the DAI pins.

SAMPLE EDGE

t_SISCLKW

DAI_P[20:1]

(SCLK)

t_SIHFS

t_SISFS

DAI_P[20:1]

(FS)

t_SISD

t_SIHD

DAI_P[20:1]

(SDATA)

Figure 21. IDP Master Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without

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Parallel Data Acquisition Port (PDAP)

significant16bitsofexternalPDAPdatacanbeprovidedthrough

either the parallel port AD[15:0] or the DAI_P[20:5] pins. The

remaining 4 bits can only be sourced through DAI_P[4:1]. The

timing below is valid at the DAI_P[20:1] pins or at the AD[15:0]

pins.

The timing requirements for the PDAP are provided in Table 24.

PDAP is the parallel mode operation of channel 0 of the IDP. For

details on the operation of the IDP, see the IDP chapter of the

ADSP-2126x Hardware Reference Manual. Note that the most

Table 24. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Units

Timing Requirements

t_SPCLKEN

t_HPCLKEN

t_PDSD

t_PDHD

t_PDCLKW

t_PDCLK

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge¹

4

5.5

4

5.5

9

20

ns

PDAP_CLKEN Hold After PDAP_CLK Sample Edge¹

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge¹

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge¹

Clock Width

Clock Period

t_PDHLDD

Delay of PDAP strobe after last PDAP_CLK capture edge for

a word

2 x t_CCLK

1 x t_CCLK

ns

t_PDSTRB

PDAP Strobe Pulse Width

1

Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI

pins through PCG.

SAMPLE EDGE

t_PDCLKW

DAI_P[20:1]

(PDAP_CLK)

t_SPHLD

t_HPHLD

DAI_P[20:1]

(PDAP_CLKEN)

t_PDSD

t_PDHD

DATA

DAI_P[20:1]

(PDAP_STROBE)

t_PDSTRB

t_PDHLDD

Figure 22. PDAP Timing

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SPI Interface—Master

Table 25. SPI Interface Protocol — Master Switching and Timing Specifications

Name

Parameter

Min

Max

Units

Switching Characteristics

t_SPICLKM

t_SPICHM

t_SPICLM

Serial clock cycle

Serial clock high period

Serial clock low period

8 x t_CCLK

4 x t_CCLK

4 x t_CCLK- 2

ns

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

SPICLK edge to data out valid (data out delay time)

SPICLK edge to data out not valid (data out hold time)

FLAG3-0IN (SPI device select)

low to first SPICLK edge

Last SPICLK edge to FLAG3-0IN high

Sequential transfer delay

0

2

ns

2 x t_CCLK- 2.5

2 x t_CCLK

ns

t_HDSM

t_SPITDM

Timing Requirements

t_SSPIDM

Data input valid to SPICLK edge

(data input set-up time)

8

0

ns

t_HSPIDM

SPICLK last sampling edge to data input not valid

FLAG3-0

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICHM

t_DDSPIDM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0)

(OUTPUT)

t_SPICLM

SPICLK

(CP = 1)

(OUTPUT)

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

t_{SSPID M}

CPHASE=1

t_HSPIDM

t_HSSPIDM

MISO

MSB

LSB

(INPUT)

VALID

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_{SSPID M}

t_HSPIDM

CPHASE=0

MSB

VALID

LSB

VALID

MISO

(INPUT)

Figure 23. SPI Master Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without

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SPI Interface—Slave

Table 26. SPI Interface Protocol —Slave Switching and Timing Specifications

Name

Parameter

Min

Max

Units

Switching Characteristics

t_DSOE

t_DSDHI

t_DDSPIDS

t_HDSPIDS

t_DSOV

SPIDS assertion to data out active

SPIDS deassertion to data high impedance

SPICLK edge to data out valid (data out delay time)

SPICLK edge to data out not valid (data out hold time) 2 x t_CCLK

0

4

9.4

ns

SPIDS assertion to data out valid (CPHASE=0)

5 x t_CCLK

ns

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial clock cycle

Serial clock high period

Serial clock low period

SPIDS assertion to first SPICLK edge

CPHASE = 0

CPHASE = 1

Last SPICLK edge to SPIDS not asserted

CPHASE = 0

4 x t_CCLK

2 x t_CCLK

2 x t_CCLK- 2

ns

2 x t_CCLK

t_HDS

ns

t_SSPIDS

Data input valid to SPICLK edge

(data input set-up time)

2

ns

t_HSPIDS

t_SDPPW

SPICLK last sampling edge to data input not valid

SPIDS deassertion pulse width (CPHASE=0)

2 x t_CCLK

SPIDS

(INPUT)

t_{SPIC HS}

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0)

(INPUT)

t_SPICLS

t_SDSCO

t_SPICHS

SPICLK

(CP = 1)

(INPUT)

t_DSDHI

t_DDSPIDS

t_DSOE

t_DDSPIDS

t_{HD LSB S}

MISO

(OUTPUT)

MSB

LSB

t_HSPIDS

CPHASE=1

t_SSPIDS

MOSI

(INPUT)

LSB VALID

MSB VALID

t_DSOV

t_DSOE

t_HDLSBS

t_DDSPIDS

t_DSDHI

MISO

(OUTPUT)

LSB

MSB

t_HSPIDS

CPHASE=0

t_SSPIDS

MOSI

MSB VALID

LSB VALID

(INPUT)

Figure 24. SPI Slave Timing

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JTAG Test Access Port and Emulation

Table 27. JTAG Test Access Port and Emulation

Parameter

Min

Max

Units

Timing Requirements

t_TCK

TCK Period

t_CK

5

6

7

18

4t_CK

ns

t_STAP

t_HTAP

t_SSYS

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low¹

TRST Pulse Width

t_HSYS

t_TRSTW

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low²

13

30

ns

1

2

System Inputs = AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0

System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15-0, RD, WR, FLAG3-0, CLKOUT, EMU, ALE.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 25. IEEE 11499.1 JTAG Test Access Port

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ADSP-21262

Output Drive Currents

Example System Hold Time Calculation

Figure 26 shows typical I-V characteristics for the output drivers

oftheADSP-21262. Thecurvesrepresentthecurrentdrivecapa-

bility of the output drivers as a function of output voltage.

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given in “Output Disable

Time” above. Choose

ADSP-21262's output voltage and the input threshold for the

device requiring the hold time. A typical V will be 0.4 V. CL is

∆V to be the difference between the

∆

thetotalbuscapacitance(perdataline),andIListhetotalleakage

or three-state current (per data line). The hold time will be t_DECAY

plus the minimum disable time (that is, t_DATRWHfor the write

cycle).

120

100

80

60

40

3.47V, TBD

3.3V, TBD

3.13V, TBD

V

OH

20

0

REFERENCE

SIGNAL

-20

-40

-60

-80

V

t_MEASURED

OL

3.47V, TBD

3.3V, TBD

3.13V, TBD

t_DIS

t_ENA

V

OH

-100

-120

(MEASURED)

V

(MEASURED) – ⌬V

(MEASURED) + ⌬V

2.0V

1.0V

OH

0

0.5

1

1.5

2

2.5

3

3.5

V

OL

V

OL

SOURCE (VDDEXT) VOLTAGE - V

(MEASURED)

t_DECAY

Figure 26. ADSP-21262 Typical Drive

OUTPUT

STOPS DRIVING

OUTPUT

STARTS DRIVING

Test Conditions

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

TBD

VOLTAGE TO BE APPROXIMATELY 1.5V.

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving. The output enable time t_ENAis the interval from the

point when a reference signal reaches a high or low voltage level

to the point when the output has reached a specified high or low

trip point, as shown in the Output Enable/Disable diagram

(Figure 27). If multiple pins (such as the data bus) are enabled,

the measurement value is that of the first pin to start driving.

Figure 27. Output Enable/Disable

50⍀

TO

OUTPUT

1.5V

Output Disable Time

30pF

Outputpinsareconsideredtobedisabledwhentheystopdriving,

go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by ∆V is dependent on the capacitive load, C_Land the

load current, I_L. This decay time can be approximated by the

following equation:

Figure 28. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

C ∆V

L

----------------

t

=

DECAY

I

L

INPUT

OR

1.5V

Output disable time t_DISis the difference between t_MEASUREDand

t_DECAYas shown in Figure 27. The time t_MEASUREDis the interval

from when the reference signal switches to when the output

OUTPUT

voltage decays

voltage. The t_DECAYis calculated with test loads C_Land I_L, and

with V equal to 0.5 V.

∆V from the measured output high or output low

Figure 29. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

∆

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ADSP-21262

16.0

14.0

12.0

10.0

25

20

15

8.0

6.0

4.0

10

5

2.0

0

NOMINAL

0

20

40 60 80 100 120 140 160 180 200

LOAD CAPACITANCE - pF

-5

0

30

60

90

120

150

180

210

LOAD CAPACITANCE - pF

Figure 32. Typical Output Rise Time (10%-90%,

V_DDEXT= Min)

Figure 30. Typical Output Delay or Hold vs. Load

Capacitance (at Max Case Temperature)

Thermal Characteristics

The ADSP-21262 is specified for a case temperature (TCASE).

To ensure that the TCASE data sheet specification is not

exceeded, a heat sink and/or an air flow source may be used. Use

thecentergroundlandtoprovidethermalpathwaystotheprinted

circuit board’s (PCB) ground plane. A heat sink should be

attached to the ground plane (as close as possible to the thermal

pathways) with a thermal adhesive (136-Ball BGA only).

16.0

14.0

12.0

10.0

8.0

Table 28 and Table 29 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junc-

tion-to-board measurement complies with JESD51-8. The

junction-to-case measurement complies with MIL- STD-883.

All measurements use a 2S2P JEDEC test board.

6.0

4.0

2.0

Table 28. Thermal Characteristics for 136 Ball BGA

0

20

40

60

80

100 120 140 160 180 200

Parameter Condition

Typical

Units

LOAD CAPACITANCE - PF

θ_JA

Airflow = 0 m/s

TBD

°C/W

Airflow = 1 m/s

Airflow = 2 m/s

–

Figure 31. Typical Output Rise Time (10%-90%,

_DDEXT= Max)

V

θ_JC

θ_JB

–

Capacitive Loading

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

Output delays and holds are based on standard capacitive loads:

12 pF on all pins (see Figure 28on page 35). Figure 30 shows

graphically how output delays and holds vary with load capaci-

tance (Note that this graph or derating does not apply to output

disabledelays;seeOutputDisableTimeonpage 35).Thegraphs

of Figure 30, Figure 31 and Figure 32 may not be linear outside

the ranges shown for TypicalOutput Delay vs. Load Capacitance

and Typical Output Rise Time (10%-90%, V=Min) vs. Load

Capacitance.

Environmental Conditions

The ADSP-21262 is available in 136-Ball Grid Array (BGA) and

144-lead LQFP packages.

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notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Table 29. Thermal Characteristics for 144 Lead LQFP

Parameter

Typical

Units

θ_JA

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

–

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

TBD

°C/W

θ_JC

Ψ_JT

• To determine the Junction Temperature of the device

while on the application PCB, use:

T_J= T_CASE+ (Ψ_JT× PD)

Where:

0

T = Junction temperature C

J

T

= Case temperature measured at the top center of the

CASE

package

Ψ

= PSI junction temperature = Typical value from the tables

JT

above

PD= Power dissipation see EE Note #TBD

• Values of θ_JAare provided for package comparison and

PCB design considerations. θ_JAcan be used for a 1^storder

approximation of T_Jby the equation:

T_J= T_A+ (θ_JA× PD)

Where:

0

T

= Ambient Temperature C

A

• Values of θ_JCare provided for package comparison and

PCB design considerations when an external heatsink is

required.

• Values of θ_JBare provided for package comparison and

PCB design considerations.

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notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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136-BALL BGA PIN CONFIGURATIONS

Table 30. 136-Ball BGA Pin Assignments

BGA

Pin#

BGA

Pin#

BGA

Pin#

Pin Name

Pin#

Pin Name

CLKCFG0

XTAL

TMS

TCK

TDI

CLKOUT

TDO

EMU

MOSI

MISO

SPIDS

V_DDINT

GND

V_DDINT

GND

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

E01

E02

E04

E05

E06

E09

E10

E11

E13

E14

CLKCFG1

GND

V_DDEXT

CLKIN

TRST

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

F01

F02

F04

F05

F06

F09

F10

F11

F13

F14

BOOTCFG1

BOOTCFG0

GND

C01

C02

C03

C12

C13

C14

V_DDINT

GND

V_DDINT

D01

D02

D04

D05

D06

D09

D10

D11

D13

D14

A_VSS

A_VDD

V_DDINT

V_DDEXT

SPICLK

RESET

V_DDINT

GND

FLAG1

FLAG0

GND

FLAG2

DAI_P20 (SFS45)

AD7

V_DDINT

V_DDEXT

G01

G02

G13

AD6

V_DDEXT

DAI_P18 (SD5B)

DAI_P17 (SD5A)

H01

H02

H13

H14

DAI_P19 (SCLK45) G14

GND

FLAG3

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notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Table 30. 136-Ball BGA Pin Assignments (Continued)

BGA

Pin#

J01

J02

J04

J05

J06

J09

J10

BGA

Pin#

BGA

Pin#

BGA

Pin#

Pin Name

AD5

AD4

GND

V_DDINT

DAI_P16 (SD4B)

AD15

ALE

RD

V_DDINT

V_DDEXT

AD8

V_DDINT

DAI_P2 (SD0B)

V_DDEXT

DAI_P4 (SFS0)

V_DDINT

GND

Pin Name

AD3

V_DDINT

GND

DAI_P15 (SD4A)

AD14

AD13

AD12

AD11

AD10

AD9

DAI_P1 (SD0A)

DAI_P3 (SCLK0)

DAI_P5 (SD1A)

DAI_P6 (SD1B)

DAI_P7 (SCLK1)

DAI_P8 (SFS1)

DAI_P9 (SD2A)

DAI_P11 (SD3A)

Pin Name

AD2

AD1

GND

Pin Name

K01

K02

K04

K05

K06

K09

K10

K11

K13

K14

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

L01

L02

L04

L05

L06

L09

L10

L11

L13

L14

AD0

WR

GND

M01

M02

M03

M12

M13

DAI_P12 (SD3B)

DAI_P13 (SCLK23) M14

J11

J13

J14

GND

DAI_P14 (SFS23)

N01

N02

N03

N04

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

DAI_P10 (SD2B)

This information applies to a product under development. Its characteristics and specifications are subject to change without

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ADSP-21262

14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

KEY

V

A

VDD

GND*

DDINT

V

A

I/O SIGNALS

DDEXT

VSS

*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED

CIRCUIT BOARD’S GROUND PLANE.

Figure 33. 136-Ball BGA Pin Assignments (Bottom View, Summary)

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144-LQFP PIN CONFIGURATIONS

August 2003

ADSP-21262

Table 31. 144 Lead LQFP Pin Assignments

LQFP

Pin #

LQFP

Pin #

LQFP

Pin #

Pin Name

Pin #

Pin Name

V_DDINT

CLKCFG0

CLKCFG1

BOOTCFG0

BOOTCFG1

GND

V_DDEXT

GND

V_DDINT

GND

V_DDINT

GND

V_DDINT

GND

FLAG0

FLAG1

AD7

GND

V_DDINT

GND

V_DDEXT

GND

V_DDINT

AD6

AD5

AD4

V_DDINT

GND

AD3

1

2

3

4

5

6

7

8

V_DDINT

GND

RD

ALE

AD15

AD14

AD13

GND

V_DDEXT

AD12

V_DDINT

GND

AD11

AD10

AD9

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

V_DDEXT

GND

V_DDINT

GND

DAI_P10 (SD2B)

DAI_P11 (SD3A)

DAI_P12 (SD3B)

73

74

75

76

77

78

79

GND

V_DDINT

GND

V_DDINT

GND

V_DDINT

GND

V_DDEXT

GND

V_DDINT

GND

V_DDINT

RESET

SPIDS

GND

V_DDINT

SPICLK

MISO

MOSI

GND

V_DDINT

V_DDEXT

A_VDD

A_VSS

GND

CLKOUT

EMU

TDO

TDI

TRST

TCK

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

DAI_P13 (SCLK23) 80

9

DAI_P14 (SFS23)

DAI_P15 (SD4A)

V_DDINT

GND

DAI_P16 (SD4B)

DAI_P17 (SD5A)

DAI_P18 (SD5B)

DAI_P19 (SCLK45) 89

V_DDINT

GND

81

82

83

84

85

86

87

88

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

AD8

DAI_P1 (SD0A)

V_DDINT

GND

DAI_P2 (SD0B)

DAI_P3 (SCLK0) 57

GND

V_DDEXT

V_DDINT

GND

DAI_P4 (SFS0)

DAI_P5 (SD1A)

DAI_P6 (SD1B)

DAI_P7 (SCLK1) 65

V_DDINT

GND

V_DDINT

GND

90

91

92

93

94

95

96

97

GND

V_DDEXT

DAI_P20 (SFS45)

GND

V_DDINT

FLAG2

FLAG3

V_DDINT

GND

V_DDINT

GND

V_DDINT

GND

58

59

60

61

62

63

64

98

99

100

101

102

103

104

105

106

107

108

AD2

V_DDEXT

GND

AD1

AD0

66

67

68

69

70

71

72

TMS

GND

CLKIN

XTAL

V_DDEXT

V_DDINT

GND

V_DDINT

DAI_P8 (SFS1)

DAI_P9 (SD2A)

V_DDINT

WR

V_DDINT

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

PrB

41

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

PACKAGE DIMENSIONS

August 2003

ADSP-21262

The ADSP-21262 is available in a 136-ball BGA package. All

dimensions are in millimeters (mm).

136-BALL BGA ()

10.40

BSC

12.00

SQ

BSC

A1 BALL

PAD CORNER

0.80

TYP

A

B

C

D

E

F

G

H

J

A1 BALL

PAD CORNER

12.00

SQ

BSC

10.40

BSC

Top View

K

L

M

N

P

14 13 12 11 10 9

8 7 6 5 4 3 2 1

0.80

TYP

DETAIL A

1.70

MAX

DETAIL A

0.85

MIN

ALL DIMENSIONS IN MILIMETERS (MM).

NOTE

0.25

MIN

1. THE ACTUAL POSITION OF THE BALL GRID IS

0.50

0.46

0.40

SEATING

PLANE

WITHIN 0.150 MM OF ITS IDEAL POSITION RELATIVE

TO THE PACKAGE EDGES. THE ACTUAL POSITION

OF EACH BALL IS WITHIN 0.08 MM OF ITS IDEAL

POSITION RELATIVE TO THE BALL GRID.

0.12

MAX

BALL

2. COMPLIANT TO JEDEC REGISTERED OUTLINE

MO-205-AE WITH THE EXCEPTION OF DIMENSION “b”

DIAMETER

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

PrB

42

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

OUTLINE DIMENSIONS

August 2003

ADSP-21262

The ADSP-21262 is available in a 144-lead LQFP package. All

dimensions are in millimeters (mm).

144-LEAD LQFP (ST-144)

22.00 BSC SQ

20.00 BSC SQ

109

144

1

108

PIN 1 INDICATOR

0.50

BSC

TYP

(LEAD

PITCH)

0.27

0.22

0.17

TYP

SEATING

PLANE

0.08 MAX (LEAD

COPLANARITY)

0.15

0.05

1.45

1.40

1.35

0.75

0.60 TYP

0.45

73

3 6

72

37

1.60 MAX

DETAIL A

TOP VIEW (PINS DOWN)

NOTES:

1.

2.

DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB.

ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS

IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

3.

CENTER DIMENSIONS ARE NOMINAL.

ORDERING GUIDE

Case Temperature

Range

On-Chip

SRAM

Part Number

Instruction Rate

ROM

Operating Voltage

ADSP-21262SKBC-200x

ADSP-21262SKSTZx

(Pb-free)

0°C to +85°C

200 MHz

2 Mbit

4 Mbit

1.2 INT/3.3 EXT V

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

PrB

43

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

August 2003

ADSP-21262

This information applies to a product under development. Its characteristics and specifications are subject to change without

notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

PrB

44


型号：	ADSP-21262SKBC-200X
厂家：	ADI
描述：	IC 16-BIT, 66.66 MHz, OTHER DSP, PBGA136, MO-205AE, BGA-136, Digital Signal Processor 时钟外围集成电路
文件：	总44页 (文件大小：1381K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21262SKBC-200X [ADI]

相关型号：

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ADSP-21262SKSTZ200

ADSP-21262SKSTZX

ADSP-21262_05

ADSP-21266

ADSP-21266SKBC-200X

ADSP-21266SKBC-2B

ADSP-21266SKBCZ-2B

ADSP-21266SKBCZ-2C

ADSP-21266SKBCZ-2D

ADSP-21266SKSTZ-150X

ADSP-21266SKSTZ-1B