ADSP-21266SKSTZ-150X [ADI]
IC,DSP,32-BIT,CMOS,QFP,144PIN,PLASTIC;型号: | ADSP-21266SKSTZ-150X |
厂家: | ADI |
描述: | IC,DSP,32-BIT,CMOS,QFP,144PIN,PLASTIC |
文件: | 总44页 (文件大小:1410K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
S
a
High Performance SHARC Audio Processor
ADSP-21266
DAI incorporates a Precision Clock Generator (PCG), and
an Input Data Port (IDP) that includes a Parallel Data
Acquisition Port (PDAP), all under software control by
the Signal Routing Unit (SRU)
On-chip memory — 2 Mbits of on-chip SRAM and a
dedicated 4 Mbits of on-chip mask-programmable
ROM
Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for audio processing
The ADSP-21266 processes high performance audio
while enabling low system costs
Audio decoder and post processor-algorithm support.
Non-volatile memory can be configured to contain a
combination of PCM 96kHz, Dolby Digital, Dolby
Digital EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1,
DTS 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, Dolby
Pro Logic II and DTS Neo:6
Single-Instruction Multiple-Data (SIMD) computational
architecture—two 32-bit IEEE floating-point/32-bit
fixed point/ 40-bit extended precision floating point
computational units, each with a multiplier, ALU,
shifter, and register file
Serial ports offer Left-justified Sample Pair and I2S
support via 12 programmable and simultaneous
receive or transmit pins, which support up to 24
transmit or 24 receive I2S channels of audio when all
6 Serial Ports (SPORTs) are enabled or 6 full duplex
TDM streams of up to 128 channels per frame
The ADSP-21266 is available with a 150 MHz or a
200MHz core instruction rate. For complete ordering
information, see Ordering Guide on page 43
High bandwidth I/O — a parallel port, SPI port, 6 serial
ports, a digital audio interface (DAI) and JTAG
FUNCTIONAL BLOCK DIAGRAM
CORE PROCESSOR
DUAL-PORTED SRAM
DUAL-PORTED ROM
TWO INDEPENDENT
INSTRUCTION
CACHE
32 X 48-BIT
TWO INDEPENDENT
BLOCKS
BLOCKS
TIMER
ADDR
DATA
DATA
ADDR
ADDR
DATA
ADDR
DATA
DATA
ADDR
ADDR
DATA
DAG1
8X4X32
DAG2
8X4X32
PROGRAM
SEQUENCER
IOD
32
IOA
18
32
PM ADDRESS BUS
32
64
DM ADDRESS BUS
PM DATA BUS
PX REGISTER
64
DM DATA BUS
6
4
JTAG TEST & EMULATION
GPIO FLAGS/IRQ/TIMEXP
DMA CONTROLLER
22 CHANNELS
PARALLEL PORT
DATA
REGISTER
FI LE
(PEX)
DATA
REGISTER
FILE
(PEY)
IOP
RE GIS TE RS
(MEMORY MAPPED)
16
3
ADDRES S/DATA BUS / GP IO
C ONT RO L/GPIO
BARREL
SHIFTER
BARREL
SHIFTER
16 X 40-BIT
16 X 40-BIT
CONTROL,
STATUS, &
4
MULT
MULT
SPI PORT (1)
DATA BUFFE RS
SERIAL PORTS (6)
SIGNAL
ROUTING
UNIT
ALU
ALU
INPUT
DATA PO RT (8)
20
PRECISION CLOCK
GENERATOR (1)
DAI
3
TIMERS (3)
I/O PROCESSOR
REV. PrB
This information applies to a product under development. Its characteristics and One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
specifications are subject to change without notice. Analog Devices assumes Tel:781/329-4700
no obligation regarding future manufacturing unless otherwise agreed to in Fax:781/326-8703
writing.
www.analog.com
©Analog Devices,Inc., 2003
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
ADSP-21266
August 2003
KEY FEATURES
Serial Ports provide:
At 200 MHz (5 ns) core instruction rate, the
ADSP-21266 performs 1200 MFLOPS/800 MMACS
At 150 MHz (6.6 ns) core instruction rate, the
ADSP-21266 performs 900 MFLOPS/600 MMACS
Super Harvard Architecture—three independent buses for
dual data fetch, instruction fetch, and nonintrusive,
zero-overhead I/O
2 Mbits on-chip dual-ported SRAM (1Mbit block 0, 1Mbit
block 1) for simultaneous access by core processor and
DMA
Six dual data line serial ports that operate at up to 50
Mbits/s for a 200 MHz core and up to 37.5 Mbits/s for
a 150 MHz core on each data line — each has a clock,
frame sync and two data lines that can be configured
as either a receiver or transmitter pair
Left-justified Sample Pair and I2S Support,
programmable direction for up to 24 simultaneous
receive or transmit channels using two I2S
compatible stereo devices per serial port
TDM support for telecommunications interfaces
including 128 TDM channel support for newer
telephony interfaces such as H.100/H.110
Up to 12 TDM stream support, each with 128 channels
per frame
4 Mbits on-chip dual-ported mask-programmable ROM (2
Mbits in block 0 and 2 Mbits in block 1)
Dual Data Address Generators (DAGs) with modulo and
bit-reverse addressing
Zero-overhead looping with single-cycle loop setup,
providing efficient program sequencing
Single Instruction Multiple Data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution— Each processing element
executes the same instruction, but operates on
different data
Companding selection on a per channel basis in TDM
mode
Input Data Port provides an additional input path to the
DSP core configurable as 8 channels of serial data or 7
channels of serial data and a single channel of up to a
20-bit wide parallel data
Signal Routing Unit (SRU) provides configurable and
flexible connections between all DAI components, 6
serial ports, 3 timers, 10 interrupts, 6 flag inputs, 6 flag
outputs, and 20 SRU I/O pins (DAI_Px)
Serial Peripheral Interface (SPI)
Master or slave serial boot through SPI
Full-duplex operation
Master-Slave mode multi-master support
Open drain outputs
Programmable baud rates, clock polarities and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
Code compatibility— At assembly level, uses the same
instruction set as other SHARC DSPs
Parallelism in buses and computational units allows:
Single-cycle executions (with or without SIMD) of: a
multiply operation, an ALU operation, a dual
memory read or write, and an instruction fetch
Transfers between memory and core at up to four
32-bit floating- or fixed-point words per cycle,
sustained 2.4 Gbytes/s bandwidth at 200 MHz core
instruction rate
Accelerated FFT butterfly computation through a
multiply with add and subtract instruction
DMA Controller supports:
22 zero-overhead DMA channels for transfers between
ADSP-21266 internal memory and serial ports (12),
the input data port (IDP) (8), SPI-compatible port (1),
and the parallel port (1)
32-bit background DMA transfers at core clock speed, in
parallel with full-speed processor execution
Asynchronous parallel/external port provides:
Access to asynchronous external memory
16 multiplexed address/data lines that can support
24-bit address external address range with 8-bit data
or 16-bit address external address range with 16-bit
data
ROM Based Security features:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware
multiplier/divider ratios
JTAG background telemetry for enhanced emulation
features
IEEE 1149.1 JTAG standard test access port and on-chip
emulation
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packages
66 Mbyte per sec transfer rate for 200 MHz core rate
50 Mbyte per sec transfer rate for 150 MHz core rate
256 word page boundaries
External memory access in a dedicated DMA channel
8- to 32- bit and 16- to 32-bit word packing options
Programmable wait state options: 2 to 31 CCLK
Digital Audio Interface (DAI) includes 6 serial ports, a
Precision Clock generator, an Input Data Port, 3 timers
and a Signal Routing Unit
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
2
PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
GENERAL DESCRIPTION
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core
processor cycle
The ADSP-21266 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices' Super
Harvard Architecture. The ADSP-21266 is source code compat-
ible with the ADSP-21160 and ADSP-21161 DSPs as well as
with first generation ADSP-2106x SHARC processors in SISD
(Single-Instruction, Single-Data) mode. Like other SHARC
DSPs, the ADSP-21266 is a 32-bit processor optimized for high
performance audio applications. The ADSP-21266 is available
in a 200 MHz or a 150 MHz core, dual-ported on-chip SRAM
and mask-programmable ROM, multiple internal buses to
eliminate I/O bottlenecks, and an innovative Digital Audio
Interface (DAI).
• Three Programmable Interval Timers with PWM Gener-
ation, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities
• On-Chip SRAM (2 Mbits)
• On-Chip dual-ported, mask-programmable ROM (4
Mbits)
• 8- or 16-bit Parallel port that supports interfaces to
off-chip memory peripherals
• DMA controller
The ADSP-21266 offers a Single-Instruction Multiple-Data
(SIMD) architecture, which was first introduced with the
ADSP- 21160 and ADSP-21161. As shown in the Functional
Block Diagram on page 1, the ADSP-21266 uses two computa-
tional units to deliver a 5 to 10 times performance increase over
the ADSP-2106x on a range of DSP algorithms. Fabricated in a
state-of-the-art, high speed, low power CMOS process, the
ADSP-21266 DSP achieves an instruction cycle time of 5 ns at
200 MHz or 6.6 ns at150 MHz. With its SIMD computational
hardware, the ADSP-21266 can perform 1200 MFLOPS
running at 200 MHz, or 900 MFLOPS running at150 MHz.
• Six serial ports
• SPI-compatible interface
• Digital Audio Interface that includes a precision clock
generator (PCG), an input data port (IDP), 6 serialports,
8 serial interfaces, a 20-bit parallel input port, 10 inter-
rupts, 6 flag outputs, 6 flag inputs, 3 timers, and a flexible
signal routing unit (SRU)
• JTAG test access port
Figure 1 on page 4 shows one sample configuration of a SPORT
2
using the precision clock generator to interface with an I S ADC
2
Table 1 shows performance benchmarks for the ADSP-21266.
and an I S DAC with a much lower jitter clock than the serial
port would generate itself. Many other SRU configurations are
possible.
Table 1. ADSP-21266 Benchmarks (at 200 MHz)
Speed
ADSP-21266 Family Core Architecture
Benchmark Algorithm
(at 200 MHz)
The ADSP-21266 is code compatible at the assembly level with
theADSP-21160andADSP-21161,andwiththefirstgeneration
ADSP-2106x SHARC DSPs. The ADSP-21266 shares architec-
tural features with the ADSP-2126x and ADSP-2116x SIMD
SHARC family of DSPs, as detailed in the following sections.
1024 Point Complex FFT (Radix 4,
with reversal)
46 µs
FIR Filter (per tap)1
IIR Filter (per biquad)1
Matrix Multiply (pipelined)
[3x3] x [3x1]
2.5 ns
10 ns
SIMD Computational Engine
22.5 ns
40 ns
The ADSP-21266 contains two computational processing
elements that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and
register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
[4x4] x [4x1]
Divide (y/x)
15 ns
Inverse Square Root
22.5 ns
1
Assumes two files in multichannel SIMD mode
The ADSP-21266 continues SHARC’s industry leading
standardsofintegrationforDSPs,combiningahighperformance
32-bit DSP core with integrated, on-chip system features. These
features include 2 Mbits dual-ported SRAM memory, 4 Mbits
dual-ported ROM, an I/O processor that supports 22 DMA
channels, six serial ports, an SPI interface, external parallel bus,
and Digital Audio Interface (DAI).
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
The block diagram of the ADSP-21266 on page 1, illustrates the
following architectural features:
• Two processing elements, each of which comprises an
ALU, Multiplier, Shifter and Data Register File
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
3
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
ADSP-21266
August 2003
ADSP-21266
CLKOUT
CLKIN
CLOCK
XTAL
ALE
2
CLK_CFG1-0
LATCH
AD15-0
ADDR
PARALLEL
PORT
RAM ROM
BOOT ROM
I/O DEVICE
2
3
BOOTCFG1-0
FLAG3-1
DATA
OE
RD
WR
WE
CS
FLAG0
ADC
(OPTIONAL)
CLK
FS
DAI_P1
DAI_P2
DAI_P3
SDAT
SCLK0
SFS0
SRU
SD0A
SD0B
DAC
(OPTIONAL)
CLK
DAI_ P1 8
DAI_P19
DAI_ P20
SPORT0
SPORT 1
SPORT2
SPORT3
SPORT4
FS
SDAT
SPORT5
CLK
FS
PCGA
PCGB
DAI
RESET
JTAG
6
Figure 1. ADSP-21266 System Sample Configuration
Independent, Parallel Computation Units
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21266 features an enhanced Harvard architecture in
whichthedatamemory(DM)bustransfersdataandtheprogram
memory (PM) bus transfers both instructions and data (see the
Figure on page 1). With the ADSP-21266’s separate program
and data memory buses and on-chip instruction cache, the
processor can simultaneously fetch four operands (two over each
data bus) and one instruction (from the cache), all in a single
cycle.
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier and shifter. Theseunitsperform alloperations
in a single cycle. The three units within each processing element
are arranged in parallel, maximizing computational throughput.
Single multi-function instructions execute parallel ALU and
multiplier operations. InSIMD mode, the parallelALU and mul-
tiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision float-
ing-point, 40-bit extended precision floating-point, and 32-bit
fixed-point data formats.
Instruction Cache
TheADSP-21266 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective — only the instructions whose
fetchesconflictwithPMbusdataaccessesarecached. Thiscache
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Register File
A general purpose data register file is contained in each process-
ing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
registerfiles,combinedwiththeADSP-2126xenhancedHarvard
architecture, allow unconstrained data flow between computa-
tionunitsandinternalmemory. TheregistersinPEXarereferred
to as R0-R15 and in PEY as S0-S15.
Data Address Generators With Zero-Overhead
Hardware Circular Buffer Support
The ADSP-21266’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffersinhardware.Circularbuffersallowefficientprogramming
of delay lines and other data structures required in digital signal
processing, and are commonly used in digital filters and Fourier
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
4
PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
transforms. The two DAGs of the ADSP-21266 contain suffi-
cient registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs automati-
cally handle address pointer wrap-around, reduce overhead,
increase performance, and simplify implementation. Circular
buffers can start and end at any memory location.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate “Emulator Hardware User's Guide”.
DMA Controller
The ADSP-21266’s on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions. DMA transfers can
occur between the ADSP-21266’s internal memory and its serial
ports, the SPI-compatible (Serial Peripheral Interface) port, the
IDP (Input Data Port) or the parallel port. Twenty-two channels
of DMA are available on the ADSP-21266 — one for the SPI
interface, twelve via the serial ports, eight via the Input Data Port
and one via the processor’s parallel port. Programs can be down-
loaded to the ADSP-21266 using DMA transfers. Other DMA
features include interrupt generation upon completion of DMA
transfers, and DMA chaining for automatic linked DMA
transfers.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21266 can conditionally execute a multiply, an add, and
a subtract in both processing elements while branching and
fetching up to four 32-bit values from memory; all in a single
instruction.
ADSP-21266 Memory and I/O Interface Features
TheADSP-21266addsthefollowingarchitecturalfeaturestothe
SIMD SHARC family core:
Dual-Ported On-Chip Memory
The ADSP-21266 contains two megabits of internal SRAM and
four megabits of internal mask-programmable ROM. Each block
can be configured for different combinations of code and data
storage (see ADSP-21266 Memory Map on page 6). Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The
dual-portedmemory,incombinationwiththreeseparateon-chip
buses, allow two data transfers from the core and one from the
I/O processor, in a single cycle.
Digital Audio Interface (DAI)
TheDigitalAudioInterface(DAI)providestheabilitytoconnect
various peripherals to any of the DSPs DAI pins (DAI_P[20:1]).
You make these connections using the Signal Routing Unit
(SRU).
The SRU is a matrix routing unit (or group of multiplexers) that
enablestheperipherals providedby theDAItobeinterconnected
under software control. This lets you use the DAI associated
peripherals for a much wider variety of applications by using a
larger set of algorithms than is possible with non-configurable
signal paths.
On the ADSP-21266, the SRAM can be configured as a
maximum of 64K words of 32-bit data, 128K words of 16-bit
data, 42.67K words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to two megabits. All of
the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit
words. A 16-bit floating-point storage format is supported that
effectivelydoublestheamountofdatathatmaybestoredon-chip.
Conversion between the 32-bit floating-point and 16-bit float-
ing-pointformatsisperformedinasingleinstruction. Whileeach
memory block can store combinations of code and data, accesses
are most efficient when one block stores data using the DM bus
for transfers, and the other block stores instructions and data
using the PM bus for transfers.
The DAI also includes 6 serial ports, a precision clock generator
(PCG), aninputdataport(IDP), 6flagoutputsand6flaginputs,
and 3 timers. The IDP provides an additional input path to the
DSP core, which can be configured for up to eight channels of
2
input serial data (including I S format). Each data channel has
its own DMA channel that is independent from the
ADSP-21266's serial ports.
ForcompleteinformationonusingtheDAI, seetheADSP-2126x
SHARC DSP Hardware Reference.
Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data trans-
fers. In this case, the instruction must be available in the cache.
Serial Ports
The ADSP-21266 features six full duplex synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices. The serial ports are
made up of two data lines, a clock and frame sync. The data lines
can be programmed to either transmit or receive.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21266
processor to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processorstacks. Theprocessor'sJTAGinterfaceensuresthatthe
emulator will not affect target system loading or timing.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
2
receive I S channels of audio when all six SPORTS are enabled,
or six full duplex TDM streams of 128 channels per frame.
The serial ports operate at up to one-quarter of the DSP core
clockrate,providingeachwithamaximumdatarateof50Mbits/s
for a 200 MHz core and 37.5 Mbits/s for a 150 MHz core. Serial
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
5
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
ADDRESS
IOP REGISTERS
0x0000 0000 - 0x0003 FFFF
0x0004 0000
BLOCK 0 SRAM (1Mbit)
0x0004 3FFF
RESERVED
0x0004 4000 - 0x0005 7FFF
0x0005 8000
BLOCK 0 ROM (2 Mbit)
LONG WORD
ADDRESS
SPACE
0x0005 FFFF
0x0006 0000
BLOCK 1 SRAM (1 Mbit)
ADDRESS
0x0006 3FFF
RESERVED
0x0006 4000 - 0x0007 7FFF
0x0020 0000
0x0007 8000
BLOCK 1 ROM (2 Mbit)
RESERVED
0x00FF FFFF
0x0100 0000
0x0007 FFFF
0x0008 0000
BLOCK 0 SRAM (1 Mbit)
RESERVED
EXTERNAL DMA
ADDRESS SPACE
0x0008 7FFF
1
0x0008 8000 - 0x000A FFFF
0x000B 0000
NORMAL WORD
ADDRESS
2
BLOCK 0 ROM (2 Mbit)
0x02FF FFFF
0x0300 0000
0x000B FFFF
0x000C 0000
SPACE
RESERVED
0x3FFF FFFF
BLOCK 1 SRAM (1 Mbit)
RESERVED
0x000C 7FFF
EXTERNAL MEMORY
SPACE
0x000C 8000 - 0x000E FFFF
0x000F 0000
3
BLOCK 1 ROM (2 Mbit)
0x000F FFFF
0x0010 0000
1
EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE BY THE
CORE. DMA MUST BE USED TO READ OR WRITE TO THIS
MEMORY USING THE SPI OR PARALLEL PORT.
BLOCK 0 SRAM (1 Mbit)
2
3
BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE
(0x000A 0000 - 0x000A AAAA).
0x0010 FFFF
0x0011 0000 - 0x0015 FFFF
RESERVED
BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE
0x0016 0000
(0x000E 0000 - 0x000E AAA).
BLOCK 0 ROM (2 Mbit)
0x0017 FFFF
0x0018 0000
SHORT WORD
ADDRESS
SPACE
BLOCK 1 SRAM (1 Mbit)
0x0018 FFFF
0x0019 0000 - 0x001D FFFF
0x001E 0000
RESERVED
BLOCK 1 ROM (2 Mbit)
0x001F FFFF
INTERNAL MEMORY
SPACE
Figure 2.ADSP-21266 Memory Map
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
6
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
port data can be automatically transferred to and from on-chip
memory via a dedicated DMA. Each of the serial ports can work
in conjunction with another serial port to provide TDM support.
One SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the parallel
port register read/write functions. The RD, WR, and ALE
(Address Latch Enable) pins are the control pins for the parallel
port.
Timers
Serial ports operate in four modes:
• Standard DSP serial mode
• Multichannel (TDM) mode
• I2S mode
The ADSP-21266 has a total of four timers: a core timer able to
generate periodic interrupts and three general purpose timers
that can that can generate periodic interrupts and be indepen-
dently set to operate in one of three modes:
• Pulse Waveform Generation mode
• Pulse Width Count /Capture mode
• External Event Watchdog mode
• Left-justified sample pair mode
Left-justified Sample Pair Mode is a mode in which each Frame
Sync cycle two samples of data are transmitted/received — one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. The user has control over various
attributes of this mode.
The core timer can be configured to use FLAG3 as a Timer
Expired signal, and each general purpose timer has one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bitperiodregister, anda 32-bitpulsewidthregister. Asingle
control and status register enables or disables all three general
purpose timers independently.
Each of the serial ports supports the Left-justified Sample Pair
2
2
and I S protocols (I S is an industry standard interface
commonly used by audio codecs, ADCs and DACs), with two
datapins,allowingfourLeft-justifiedSamplePairorI Schannels
2
(using two stereo devices) per serial port, with a maximum of up
to 24 I S channels. The serial ports permit little-endian or
ROM Based Security
2
The ADSP-21266 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
Whenusingthisfeature, theDSPdoesnotboot-loadanyexternal
code, executing exclusively from internal SRAM/ROM. Addi-
tionally, the DSP is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port, will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
big-endian transmission formats and word lengths selectable
from 3 bits to 32 bits. For the Left-justified Sample Pair and I S
modes, data-word lengths are selectable between 8 bits and 32
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding selection
2
on a per channel basis. Serial port clocks and frame syncs can be
internally or externally generated.
Serial Peripheral (Compatible) Interface
Serial Peripheral Interface (SPI) is an industry standard synchro-
nous serial link, enabling the ADSP-21266 SPI-compatible port
to communicate with other SPI-compatible devices. SPI is an
interface consisting of two data pins, one device select pin, and
one clock pin. It is a full-duplex synchronous serial interface,
supporting both master and slave modes. The SPI port can
operate in a multi-master environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-21266 SPI-compatible peripheral
implementation also features programmable baud rate and clock
phase and polarities. The ADSP-21266 SPI-compatible port
uses open drain drivers to support a multi-master configuration
and to avoid data contention.
Program Booting
The internal memory of the ADSP-21266 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1-0) pins. Selection of
the boot source is controlled via SPI as either a master or slave
device, or it can immediately begin executing from ROM.
Phased Locked Loop
The ADSP-21266 uses an on-chip Phase Locked Loop (PLL) to
generate the internal clock for the core. On power up, the
CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via software
control.
Parallel Port
The Parallel Port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15-0) can
access8-bitdeviceswithupto24bits of address, or 16-bit devices
with up to 16 bits of address. In either mode, 8- or 16-bit, the
maximum data transfer rate is one-third the core clock speed. As
an example, for a clock rate of 200 MHz, this is equivalent to 66
Mbytes/sec, and for a clock rate of 150 MHz is equivalent to 50
Mbytes/sec.
Theratiosaremadeupofsoftwareconfigurablenumeratorvalues
from 1 to 32 and software configurable divisor values of 1, 2, 4,
8, and 16.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
7
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Power Supplies
real-time characteristics of the program. Essentially, the
The ADSP-21266 has separate power supply connections for the
internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS
power supplies. The internal and analog supplies must meet the
1.2V requirement. The external supply must meet the 3.3V
requirement. All external supply pins must be connected to the
same power supply.
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on those
areasintheprogramthatimpactperformanceandtakecorrective
action.
)
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
Note that the analog supply (AVDD) powers the ADSP-21266’s
clock generator PLL. To produce a stable clock, you should
provide an external circuit to filter the power input to the AVDD
pin. Place the filter as close as possible to the pin. For an example
circuit, see Figure 3. To prevent noise coupling, use a wide trace
for the analog ground (AVSS) signal and install a decoupling
capacitor as close as possible to the pin. Note that the AVSS and
AVDD pins specified in Figure 3 are inputs to the DSP and not the
analog ground plane on the board.
• View mixed C/C++ and assembly code (interleaved
source and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program
execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
10⍀
V
A
VDD
DDINT
• Create custom debugger windows
0.1F
0.01F
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-21xxx
development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
A
VSS
Figure 3. Analog Power (AVDD) Filter Circuit
• Control how the development tools process inputs and
generate outputs
Development Tools
The ADSP-21266 is supported with a complete set of
• Maintain a one-to-one correspondence with the tool’s
command line switches
CROSSCORE™ software and hardware development tools,
including Analog Devices emulators and VisualDSP++™ devel-
opment environment. The same emulator hardware that
supports other ADSP-21xxx processors also fully emulates the
ADSP-21266.
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resourcemanagementtailoredspecificallytoaddressthememory
and timing constraints of DSP programming. These capabilities
enableengineerstodevelopcodemoreeffectively,eliminatingthe
need to start from the very beginning, when developing new
application code. The VDK features include Threads, Critical
andUnscheduledregions,Semaphores,Events,andDeviceflags.
The VDK also supports Priority-based, Preemptive, Coopera-
tive, and Time-Sliced scheduling approaches. In addition, the
VDK was designed to be scalable. If the application does not use
a specific feature, the support code for that feature is excluded
from the target system.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic
syntax), an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathemat-
ical functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient transla-
tion of C/C++ code to DSP assembly. The DSP has architectural
features that improve the efficiency of compiled C/C++ code.
Because the VDK is a library, a developer can decide whether to
use it or not. TheVDKis integrated intothe VisualDSP++ devel-
opment environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gener-
ation of various VDK based objects, and visualizing the system
state, when debugging an application that uses the VDK.
TheVisualDSP++debuggerhasanumberofimportantfeatures.
Data visualization is enhanced by a plotting package that offers
a significant level of flexibility. This graphical representation of
user data enables the programmer to quickly determine the per-
formance of an algorithm. As algorithms grow in complexity, this
capability can have increasing significance on the designer’s
development schedule, increasing productivity. Statistical
profiling enables the programmer to non intrusively poll the
processor as it is running the program. This feature, unique to
VisualDSP++, enables the software developer to passively gather
important code execution metrics without interrupting the
VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices technology for creating, using, and reusing
software components (independent modules of substantial func-
tionality) to quickly and reliably assemble software applications.
Download components from the Web and drop them into the
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
8
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
application. Publish component archives from within Visu-
alDSP++. VCSE supports component implementation in
C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
codeanddataontheembeddedsystem. Viewmemoryutilization
in a color-coded graphical form, easily move code and data to
different areas of the DSP or external memory with the drag of
the mouse, examine run time stack and heap usage. The Expert
Linker is fully compatible with existing Linker Definition File
(LDF), allowing the developer to move between the graphical
and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the ADSP-21xxx processor family. Hardware
tools include ADSP-21xxx processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
Designing an Emulator-Compatible DSP
Board (Target)
The Analog Devices family of emulators are tools that every DSP
developer needs to test and debug hardware and software
systems.AnalogDeviceshassuppliedanIEEE1149.1JTAGTest
Access Port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator usestheTAP toaccess the internalfeatures
of the DSP, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
DSP must be halted to send data and commands, but once an
operation has been completed by the emulator, the DSP system
is set running at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, singleprocessorconnections, multiprocessorscanchains,
signal buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical Reference on
the Analog Devices website (www.analog.com)—use site search
on “EE-68.” This document is updated regularly to keep pace
with improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-21266
architecture and functionality. For detailed information on the
ADSP-2126x Family core architecture and instruction set, refer
to the ADSP-2126x DSP Hardware Reference and the
ADSP-21160 SHARC DSP Instruction Set Reference.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
9
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of Table 2:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State.
ADSP-21266 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST).Tie or pull unused inputs to
Unlike previous SHARC processors, the ADSP-21266 contains
internal series resistance equivalent to 360
Ω on the input paths
V
DDEXT or GND, except for the following:
of all pins. Therefore, for traces longer than six inches, external
series resisters on control, data, clock or frame sync pins are not
required to dampen reflections from transmission line effects for
point-to-point connections. However, for more complex
networks such as a star configuration, series termination is still
recommended.
• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST,
TDI and AD15-0 (NOTE: These pins have internal
pull-up resistors.)
Table 2. Pin Descriptions
State During &
Pin
Type
After Reset
Function
AD15-0
I/O/T
Three-state with Parallel Port Address/Data. The ADSP-21266 parallel port and
pull-up enabled
its corresponding DMA unit output addresses and data for periph-
erals on these multiplexed pins. The multiplex state is determined
by the ALE pin. The parallel port can operate in either 8-bit or 16-bit
mode. Each AD pin has a 22.5 KΩ internal pull-up resistor. See
Address Data Modes on page 14 for details of the AD pin operation:
For 8-bit mode: ALE is automatically asserted whenever a change
occurs in the upper 16 external address bits, A23-8; ALE is used in
conjunction with an external latch to retain the values of the A23-8.
For 16-bit mode: ALE is automatically asserted whenever a change
occurs in the address bits, A15-0; ALE is used in conjunction with
an external latch to retain the values of the A15-0.
To use these pins as flags (FLAGS15-0) set (=1) bit 20 of the
SYSCTL register and disable the parallel port. See Table 3 on
page 14 for a list of how the AD15-0 pins map to the FLAG pins.
When used as an input, the IDP Channel0 can use these pins for
parallel input data.
RD
O
O
O
Parallel Port Read Enable. RD is asserted low whenever the DSP
reads 8-bit or 16-bit data from an external memory device. When
AD15-0 are flags, this pin remains deasserted.
Parallel Port Write Enable. WR isasserted lowwhenever theDSP
writes 8-bit or 16-bit data to an external memory device. When
AD15-0 are flags, this pin remains deasserted.
Parallel Port Address Latch enable. ALE is asserted whenever
the DSP drives a new address on the parallel port address pins. On
reset, ALE is active high. However, it can be reconfigured using
software to be active low. When AD15-0 are flags, this pin remains
deasserted.
Output only,
driven high1
WR
ALE
Output only,
driven high1
Output only,
driven low1
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
10
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Table 2. Pin Descriptions (Continued)
State During &
Pin
Type
After Reset
Function
FLAG3-0
I/O/A
Flag Pins. Each FLAG pin is configured via control bits as either
an input or output. As an input, it can be tested as a condition. As
an output, it can be used to signal external peripherals.These pins
can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx and the
TIMEXP signals.
Three-state
In SPI master boot mode, FLAG0 is the slave select pin that must
be connected to an SPI EPROM. FLAG0 is configured as a slave
select during SPI master boot. When bit 16 is set (=1) in the
SYSCTL register, FLAG0 is configured as IRQ0.
When bit 17 is set (=1) in the SYSCTL register, FLAG1 is
configured as IRQ1.
When bit 18 is set (=1) in the SYSCTL register, FLAG2 is
configured as IRQ2.
When bit 19 is set (=1) in the SYSCTL register, FLAG3 is
configured as TIMEXP which indicates that the system timer has
expired.
DAI_P20-1
I/O/T
Digital Audio Interface Pins.These pins provide the physical
interface to the SRU. The SRU configuration registers define the
combination of on-chip peripheral inputs or outputs connected to
the pin and to the pin’s output enable. The configuration registers
of these peripherals then determines the exact behavior of the pin.
Any input or output signal present in the SRU may be routed to any
ofthesepins.TheSRUprovidestheconnectionfromtheSerialports,
Input data port, precision clock generator and timer to the
DAI_P20-1 pins These pins have internal 22.5 KΩ pull-up resistors
which are enabled on reset. These pull-ups can be disabled in the
DAI_PIN_PULLUP register.
Three-state with
programmable
pull-up
SPICLK
I/O
Serial Peripheral Interface Clock Signal. Driven by the master,
this signal controls the rate at which data is transferred. The master
may transmit data at a variety of baud rates. SPICLK cycles once for
each bit transmitted. SPICLK is a gated clock that is active during
data transfers, only for the length of the transferred word. Slave
devices ignore the serial clock if the slave select input is driven
inactive (HIGH). SPICLK is used to shift out and shift in the data
driven on the MISO and MOSI lines. The data is always shifted out
on one clock edge and sampled on the opposite edge of the clock.
Clock polarity and clock phase relative to data are programmable
into the SPICTL control register and define the transfer format.
SPICLK has a 22.5 KΩ internal pull-up resistor.
Three-state with
pull-up enabled
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
11
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Table 2. Pin Descriptions (Continued)
State During &
Pin
Type
After Reset
Function
SPIDS
I
Serial Peripheral Interface Slave Device Select. An active low
signal used to select the DSP as an SPI slave device. This input signal
behaves like a chip select, and is provided by the master device for
the slave devices. In multi-master mode the DSPs SPIDS signal can
be driven by a slave device to signal to the DSP (as SPI master) that
an error has occurred, as some other device is also trying to be the
master device. If asserted low when the device is in master mode, it
is considered a multi-master error. For a single-master,
multiple-slave configuration where FLAG pins are used, this pin
must be tied or pulled high to VDDEXT on the master device. For
ADSP-21266 to ADSP-21266 SPI interaction, any of the master
ADSP-21266's FLAG pins can be used to drive the SPIDS signal on
the ADSP-21266 SPI slave device.
Input only
MOSI
MISO
I/O (O/D)
SPI Master Out Slave In. If the ADSP-21266 is configured as a
master, the MOSI pin becomes a data transmit (output) pin, trans-
mitting output data. If the ADSP-21266 is configured as a slave, the
MOSI pin becomes a data receive (input) pin, receiving input data.
In an ADSP-21266 SPI interconnection, the data is shifted out from
the MOSI output pin of the master and shifted into the MOSI
input(s) of the slave(s). MOSI has a 22.5 KΩ internal pull-up
resistor.
SPI Master In Slave Out. If the ADSP-21266 is configured as a
master, the MISO pin becomes a data receive (input) pin, receiving
input data. If the ADSP-21266 is configured as a slave, the MISO
pin becomes a data transmit (output) pin, transmitting output data.
In an ADSP-21266 SPI interconnection, the data is shifted out from
the MISO output pin of the slave and shifted into the MISO input
pin of the master. MISO has a 22.5KΩ internal pull-up resistor.
MISO can be configured as O/D by setting the OPD bit in the
SPICTL register.
Three-state with
pull-up enabled
I/O (O/D)
Three-state with
pull-up enabled
Note: Only one slave is allowed to transmit data at any given time.To
enable broadcast transmission to multiple SPI-slaves, the DSP's
MISO pin may be disabled by setting (=1) bit 5 (DMISO) of the
SPICTL register.
BOOTCFG1-0
CLKIN
I
I
Input only
Input only
Boot Configuration Select. This pin is used to select the boot
mode for the DSP. The BOOTCFG pins must be valid before reset
is asserted. See Table 4 for a description of the boot modes.
Local Clock In. Used in conjunction with XTAL. CLKIN is the
ADSP-21266 clock input. It configures the ADSP-21266 to use
either its internal clock generator or an external clock source.
Connecting the necessary components to CLKIN and XTAL
enables the internal clock generator. Connecting the external clock
to CLKIN while leaving XTAL unconnected configures the
ADSP-21266 to use the external clock source such as an external
clock oscillator.The core is clocked either by the PLL output or this
clock input depending on the CLKCFG1-0 pin settings. CLKIN
may not be halted, changed, or operated below the specified
frequency.
XTAL
O
Output only2
Crystal Oscillator Terminal. Used in conjunction with CLKIN
to drive an external crystal.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
12
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Table 2. Pin Descriptions (Continued)
State During &
Pin
Type
After Reset
Function
CLKCFG1-0
I
Input only
Core/CLKIN Ratio Control. These pins set the start up clock
frequency. See Table 5 for a description of the clock configuration
modes.
Note that the operating frequency can be changed by programming
the PLL multiplier and divider in the PMCTL register at any time
after the core comes out of reset.
CLKOUT
RESET
TCK
O
I/A
I
Output only
Input only
Input only3
Local Clock Out/ Reset Out. Drives out the core reset signal to an
external device. CLKOUT can also be configured as a reset out
pin.The functionality can be switched between the PLL output clock
andresetoutbysettingbit12ofthePMCTREGregister. Thedefault
is reset out.
Processor Reset. Resets the ADSP-21266 to a known state. Upon
deassertion, thereis a4096CLKIN cycle latencyforthe PLLtolock.
Afterthistime, thecorebeginsprogramexecutionfromthehardware
reset vector address. The RESET input must be asserted (low) at
power-up.
Test Clock (JTAG). Provides a clockfor JTAG boundaryscan. must
be asserted (pulsed low) after power-up or held low for proper
operation of the ADSP-21266.
TMS
TDI
I/S
I/S
O
Three-state with Test Mode Select (JTAG). Used to control the test state machine.
pull-up enabled TMS has a 22.5 KΩ internal pull-up resistor.
Three-state with Test Data Input (JTAG). Provides serial data for theboundaryscan
pull-up enabled
logic. TDI has a 22.5 KΩ internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan
path.
TDO
TRST
Three-state4
I/A
Three-state with Test Reset (JTAG). Resets the test state machine. TRST must be
pull-up enabled
asserted (pulsed low) afterpower-up or held lowforproper operation
of the ADSP-21266. TRST has a 22.5 KΩ internal pull-up resistor.
EMU
O (O/D)
P
Three-state with Emulation Status. Must be connected to the ADSP-21266 Analog
pull-up enabled
Devices DSP Tools product line of JTAG emulators target board
connector only. EMU has a 22.5 KΩ internal pullup resistor.
Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s
core processor (13 pins on the BGA package, 32 pins on the LQFP
package).
VDDINT
VDDEXT
AVDD
P
P
I/O Power Supply. Nominally +3.3 V dc. (6 pins on the BGA
package, 10 pins on the LQFP package).
Analog Power Supply. Nominally +1.2 V dc and supplies the
DSP’s internal PLL (clock generator). This pin has the same speci-
fications as
VDDINT, except that added filtering circuitry is required. see Power
Supplies on page 8.
AVSS
GND
G
G
Analog Power Supply Return.
Power Supply Return. (54 pins on the BGA package, 39 pins on
the LQFP package).
1
RD, WR, and ALE are continuously driven by the DSP and won’t be three-stated.
Output only is a three-state driver with its output path always enabled.
Input only is three-state driver with both output path.
2
3
4
Three-state is three-state driver.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
13
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Address Data Pins as FLAGs
To use these pins as flags (FLAGS15-0) set (=1) bit 20 of
the SYSCTL register and disable the parallel port.
by address bits A7-A0 and data bits D7-D0 when deasserted. For
16-bit data transfers, ALE latches address bits A15-A0 when
asserted, followed by data bits D15-D0 when deasserted.
Table 3. AD[15:0] to FLAG Pin Mapping
Table 6. Address/ Data Mode Selection
AD Pin
FLAG Pin
EP Data
Mode
AD7-0
Function
AD15-8
Function
ALE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
FLAG8
FLAG9
FLAG10
FLAG11
FLAG12
FLAG13
FLAG14
FLAG15
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
8-bit
8-bit
16-bit
16-bit
Asserted
Deasserted
Asserted
A15-8
D7-0
A7-0
D7-0
A23-16
A7-0
A15-8
D15-8
Deasserted
AD14
AD15
FLAG6
FLAG7
Boot Modes
Table 4. Boot Mode Selection
BOOTCFG1-0 Booting Mode
00
01
10
11
SPI Slave Boot
SPI Master Boot
Parallel Port boot via EPROM
Internal Boot Mode (ROM code only)
Core Instruction Rate to CLKIN Ratio Modes
Table 5. Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1-0
Core to CLKIN Ratio
00
01
10
11
3:1
16:1
8:1
Reserved
Address Data Modes
The following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data trans-
fers, ALE latches address bits A23-A8 when asserted, followed
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
14
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
ADSP-21266 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
Min
Signal
Parameter1
Max
Unit
VDDINT
AVDD
VDDEXT
VIH
Internal (Core) Supply Voltage
1.14
1.14
3.13
2.0
1.26
V
V
Analog (PLL) Supply Voltage
1.26
External (I/O) Supply Voltage
3.47
V
High Level Input Voltage2, @ VDDEXT = max
Low Level Input Voltage2 @ VDDEXT = min
Case Operating Temperature3
VDDEXT+0.5
0.8
V
VIL
-0.5
0
V
TCASE
+85
°C
1
2
Specifications subject to change without notice.
Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKIN, CLKCFGx, RESET, TCK,
TMS, TDI, TRST.
3
See Thermal Characteristics on page 36 for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter1
Test Conditions
Min
Max
Unit
VOH
VOL
IIH
High Level Output Voltage 2
Low Level Output Voltage2
High Level Input Current4,5
Low Level Input Current4
@ VDDEXT = min, IOH = -1.0 mA3
@ VDDEXT = min, IOL = 1.0 mA3
@ VDDEXT = max, VIN = VDDEXT max
@ VDDEXT = max, VIN = 0 V
2.4
V
V
µA
µA
0.4
10
10
IIL
IILPU
IOZH
IOZL
IOZLPU
Low Level Input Current Pull-Up5 @ VDDEXT = max, VIN = 0 V
TBD µA
Three-State Leakage Current 6,7
Three-State Leakage Current6
Three-State Leakage Current
Pull-Up1 7
@ VDDEXT= max, VIN = VDDEXT max
@ VDDEXT = max, VIN = 0 V
@ VDDEXT = max, VIN = 0 V
10
10
250
µA
µA
µA
IDD-INTYP
AIDD
CIN
Supply Current (Internal)8,9
Supply Current (Analog)10
Input Capacitance11, 12
tCCLK = 5.0 ns, VDDINT = max
AVDD = max
fIN=1 MHz, TCASE=25°C, VIN=1.2V
500
10
4.7
mA
mA
pF
1
Specifications subject to change without notice.
2
3
4
5
6
Applies to output and bidirectional pins: AD15-0, RD, WR, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.
See Output Drive Currents on page 35 for typical drive current capabilities.
Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.
Applies to input pins with 22.5 KΩ internal pull-ups: TRST, TMS, TDI.
Applies to three-statable pins: AD15-0, FLAG3-0.
7
Applies to three-statable pins with 22.5 KΩ pull-ups: DAI_Px, SPICLK, EMU, MISO, MOSI.
Typical internal current data reflects nominal operating conditions.
See Engineering-to-Engineering Note (No. TBD) for further information.
Characterized, but not tested.
Applies to all signal pins.
8
9
10
11
12
Guaranteed, but not tested.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
15
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
ABSOLUTE MAXIMUM RATINGS
1
Internal (Core) Supply Voltage (VDDINT
)
0.3 V to +1.5 V
1
Analog (PLL) Supply Voltage (AVDD
)
-0.3 V to +1.5 V
-0.3 V to +4.6 V
-0.5 V to VDDEXT1 + 0.5 V
-0.5 V to VDDEXT1 + 0.5 V
200 pF
1
External (I/O) Supply Voltage (VDDEXT
Input Voltage
)
Output Voltage Swing
Load Capacitance1
Storage Temperature Range1
-65°C to +150°C
1
Stresses greater than those listed above may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21266 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.
TIMING SPECIFICATIONS
The ADSP-21266’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobesinasynchronousaccessmode).Duringreset,programthe
ratio between the DSP’s internal clock frequency and external
(CLKIN) clock frequency with the CLKCFG1-0 pins. To
determine switching frequencies for the serial ports, divide down
the internal clock, using the programmable divider control of
each port (DIVx for the serial ports).
The ADSP-21266’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP’s internal clock (the clock
source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (Table 7).
Table 7. ADSP-21266 CLKOUT and CCLK Clock Generation Operation
Timing Requirements
Description
Calculation
CLKIN
CCLK
Input Clock
Core Clock
1/tCK
1/tCCLK
Timing Requirements
Description1
tCK
CLKIN Clock Period
tCCLK
tSCLK
tSPICLK
(Processor) Core Clock Period
Serial Port Clock Period = (tCCLK) x SR
SPI Clock Period = (tCCLK) x SPIR
1
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
16
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Figure 4 shows Core to CLKIN ratios of 3:1, 8:1 and 16:1 with
external oscillator or crystal.
CLKOUT
CLKIN
XTAL
OSC
PLL
3:1, 8:1,
16:1
CCLK
(CORE CLOCK)
PLLILCLK
XTAL
CLK-CFG [1:0]
Figure 4. Core Clock and System Clock Relationship to CLKIN
Use the exact timing information given. Do not attempt to derive
parameters from the addition or subtraction of others. While
addition or subtraction would yield meaningful results for an
individual device, the values given in this data sheet reflect sta-
tistical variations and worst cases. Consequently, it is not
meaningful to add parameters to derive longer times.
See Figure 29 on page 35 under Test Conditions for voltage
reference levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching charac-
teristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
The ADSP-21266’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobesinasynchronousaccessmode).Duringreset,programthe
ratio between the DSP’s internal clock frequency and external
(CLKIN) clock frequency with the CLKCFG1-0 pins. To
determine switching frequencies for the serial ports, divide down
the internal clock, using the programmable divider control of
each port (DIVx for the serial ports).
The ADSP-21266’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP’s internal clock (the clock
source for the parallel port logic and I/O pads).
Note the following definitions of various clock periods that are a
function of CLKIN and the appropriate ratio control.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
17
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Power up Sequencing
The timing requirements for DSP startup are given in Table 8.
Table 8. Power Up Sequencing Timing Requirements (DSP Startup)
Name
Parameter
Min
Max
Units
Timing Requirements
tRSTVDD
tIVDDEVDD
tCLKVDD
tCLKRST
tPLLRST
RESET low before VDDINT/VDDEXT on
VDDINT on before VDDEXT
0
ns
ms
ms
µs
µs
ns
-50
0
200
200
CLKIN valid after VDDINT/VDDEXT valid1
CLKIN valid before RESET de-asserted
PLL control setup before RESET de-asserted
Subsequent RESET low pulse width4
102
203
4tCK
tWRST
Switching Characteristics
tCORERST DSP core reset de-asserted after RESET de-asserted
4, 5
4096tCK +512 tCCLK
1
Valid V
/V
assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds
DDINT DDEXT
of milliseconds depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for
startup time. Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
Based on CLKIN cycles
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly
initialize and propagate default states at all I/O pins.
3
4
5
The 4096 cycle count depends on t
specification in Table 10. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time,
SRST
resulting in 4097 cycles maximum.
RESET
tRSTVDD
V
DDINT
tIVDDEVDD
V
tCLKVDD
DDEXT
CLKIN
tCLKRST
CLK_CFG1-0
tCORERST
tPLLRST
RSTOUT
Figure 5. Power Up Sequencing
DuringthepowerupsequenceoftheDSP,differencesintheramp
up rates and activation time between the two supplies can cause
current to flow in the I/O ESD protection circuitry. To prevent
this damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
Including a Schottky diode will shorten the delay between the
supply ramps and prevent damage to the ESD diode protection
circuitry. With this technique, if the 1.2V rail rises ahead of the
3.3V rail, the Schottky diode pulls the 3.3V rail along with the
1.2V rail.
ThebootstrapSchottkydiodeisconnectedbetweenthe1.2Vand
3.3V power supplies as shown in Figure 6 on page 19. It protects
the ADSP-21266 from partially powering the 3.3V supply.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
18
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
DC INPUT
SOURCE
VDDEXT
3.3V I/O
VOLTAGE
REGULATOR
ADSP-21266
1.2V CORE
VOLTAGE
VDDINT
REGULATOR
Figure 6. Schottky Diode
Clock Input
Table 9. Clock Input
150 MHz
Min
200 MHz
Min
Parameter
Max
Max
Units
Timing Requirements
tCK
CLKIN Period
201
1602
802
151
61
1602
802
ns
ns
ns
tCKL
tCKH
tCKRF
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall
(0.4V-2.0V)
7.51
7.51
802
61
802
3
10
3
10
ns
ns
tCCLK
CCLK Period3
6.66
5
1
2
3
Applies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
.
CCLK
tCK
CLKIN
CLKIN
XTAL
1M⍀
tCKH
tCKL
Figure 7. Clock Input
C1
C2
X1
Clock Signals
The ADSP-21266 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21266 to use its internal clock generator by connecting
thenecessarycomponentstoCLKINandXTAL.Figure 8shows
the component connections used for a crystal operating in fun-
damental mode.
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
Figure 8. 150 MHz or 200 MHz Operation
(Fundamental Mode Crystal)
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
19
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Reset
Table 10. Reset
Parameter
Min
Max
Units
Timing Requirements
tWRST
tSRST
RESET Pulse Width Low1
RESET Setup Before CLKIN High
4tCK
8
ns
ns
1
Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET
is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
tSRST
tWRST
RESET
Figure 9. Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0
,
IRQ1, and IRQ2 interrupts.
Table 11. Interrupts
Parameter
Min
2 x tCCLK +2
Max
Units
Timing Requirements
tIPW
IRQx Pulse Width
ns
FLAG2-0
(IRQ2-0)
tIPW
Figure 10. Interrupts
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
20
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 12. Core Timer
Parameter
Min
Max
Units
Switching Characteristic
tWCTIM
CTIMER Pulse width
4 x tCCLK
ns
tWCTIM
FLAG3
(CTIMER)
Figure 11. Core Timer
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer[2:0] in
PWM_OUT (pulse width modulation) mode. Timer signals are
routed to the DAI_P[20:1] pins through the SRU. Therefore, the
timingspecificationsprovidedbelowarevalidattheDAI_P[20:1]
pins.
Table 13. Timer[2:0] PWM_OUT Timing
Parameter
Min
2 tCCLK
Max
2(231-1) tCCLK
Units
Switching Characteristic
tPWMO
Timer[2:0] Pulse width Output
ns
tPWMO
DAI_P[20:1]
(TIMER[2:0])
Figure 12. Timer[2:0] PWM_OUT Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
21
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Timer WDTH_CAP Timing
The following timing specification applies to Timer[2:0] in
WDTH_CAP (pulse width count and capture) mode. Timer
signals are routed to the DAI_P[20:1] pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P[20:1] pins.
Table 14. Timer[2:0] Width Capture Timing
Parameter
Min
2 tCCLK
Max
Units
Timing Requirement
tPWI
Timer[2:0] Pulse width
2(231-1) tCCLK
ns
tPWI
DAI_P[20:1]
(TIMER[2:0])
Figure 13. Timer[2:0] Width Capture Timing
Flags
The timing specifications provided below apply to the
FLAG[3:0]andDAI_P[20:1]pins,theparallelportandtheserial
peripheral interface (SPI). See Table 2, “Pin Descriptions,” on
page 10 for more information on flag use.
Table 15. Flags
Parameter
Min
Max
Units
Timing Requirement
tFIPW
Switching Characteristic
tFOPW FLAGx OUT Pulse Width
FLAGx IN Pulse Width1
2 x tCCLK+3
2 x tCCLK
ns
ns
1
Where N = 0-2 (CLKCFG1-0 = 00), 0-15 (CLKCFG1-0 = 01) or 0-7(CLKCFG1-0 = 10)
DAI_P[20:1]
(FLAG3-0 )
IN
(AD[15:0]
tFIPW
DAI_P[20:1]
(FLAG3-0OUT
)
(AD[15:0]
tFOPW
Figure 14. Flags
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
22
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Memory Read–Parallel Port
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) when the
ADSP-21266 is accessing external memory space
.
Table 16. 8-Bit Memory Read Cycle
Name
Parameter
Min
Max
Units
Timing Requirements
tDRS
tDRH
tDAD
Address/data [7:0] setup before RD high
Address/data [7:0] hold after RD high
Address [15:8] to data valid
2
0.5
ns
ns
ns
D + 0.5 x tCCLK - 2.5
Switching Characteristics
tALEW
tADAS
tADAH
tALEHZ
tRW
ALE pulse width
2 x tCCLK - 2
ns
ns
ns
ns
ns
ns
Address/data [15:0] setup before ALE deasserted1 2.5 x tCCLK - 1.0
Address/data [15:0] hold after ALE deasserted1
ALE deasserted1 to Address/Data[7:0] in high Z
RD pulse width
0.5 x tCCLK - 0.8
0.5 x tCCLK - 0.8
D - 2
0.5 x tCCLK
tADRH
Address/data [15:8] hold after RD high
0.5 x tCCLK - 1 + H
D = (Data Cycle Duration) x tCCLK
H= tCCLK (if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
tALEW
ALE
tRW
RD
WR
tALEHZ
tADAH
tADAS
tADRH
AD[15:8]
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
tDRS
tDRH
AD[7:0]
VALID DATA
tDAD
Figure 15. Read Cycle For 8-bit Memory Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
23
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Table 17. 16-bit Memory Read Cycle
Name
Parameter
Min
Max
Units
Timing Requirements
tDRS
tDRH
Switching Characteristics
Address/data [15:0] setup before RD high
Address/data [15:0] hold after RD high
2
0.5
ns
ns
ns
ns
ns
ns
ns
ns
tALEW
tADAS
tADAH
tALEHZ
tRW
ALE pulse width
2 x tCCLK - 2
2.5 x tCCLK - 1.0
0.5 x tCCLK - 0.8
0.5 x tCCLK - 0.8
D - 2
Address/data [15:0] setup before ALE deasserted1
Address/data [15:0] hold after ALE deaserted1
ALE deasserted1 to Address/Data[15:0] in high Z
RD pulse width
D = (Data Cycle Duration) x tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALE
tALEW
RD
tRW
WR
tADAH
tDRS
tDRH
tADAS
VALID DATA
AD[15:0]
VALID ADDRESS
tALEHZ
Figure 16. Read Cycle For 16-bit Memory Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
24
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) when the
ADSP-21266 is accessing external memory space.
Table 18. 8-bit Memory Write Cycle
Name
Parameter
Min
Max
Units
Switching Characteristics:
tALEW
tADAS
tADAH
tWW
tADWL
tADWH
tALEHZ
tDWS
ALE pulse width
2 x tCCLK - 2
2.5 x tCCLK - 1.0
0.5 x tCCLK - 0.5
D - 2
0.5 x tCCLK - 1.5
0.5 x tCCLK - 1 + H
0.5 x tCCLK - 1.5
D
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address/data [15:0] setup before ALE deasserted1
Address/data [15:0] hold after ALE low deasserted1
WR pulse width
Address/data [15:8] to WR low
Address/data [15:8] hold after WR high
ALE deasserted1 to Address/Data[15:0] in high Z
Address/data [7:0] setup before WR high
Address/data [7:0] hold after WR high
Address/data to WR high
tDWH
tDAWH
0.5 x tCCLK - 1.5 + H
D
D = (Data Cycle Duration) x tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALE
tALEW
tDAWH
WR
tWW
RD
tALEHZ
tADAH
tADWL
tADWH
tADAS
AD[15:8]
VALID ADDRESS
VALID ADDRESS
tDWS
tDWH
VALID ADDRESS
VALID DATA
AD[7:0]
Figure 17. Write Cycle For 8-bit Memory Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
25
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Table 19. 16-bit Memory Write Cycle
Name Parameter
Switching Characteristics
Min
Max
Units
tALEW
tADAS
tADAH
tWW
tALEHZ
tDWS
ALE pulse width
2 x tCCLK - 2
2.5 x tCCLK - 1.0
0.5 x tCCLK - 0.5
D - 2
0.5 x tCCLK - 1.5
D
ns
ns
ns
ns
ns
ns
ns
Address/data [15:0] setup before ALE deasserted1
Address/data [15:0] hold after ALE deasserted1
WR pulse width
ALE deasserted1 to Address/Data[15:0] in high Z
Address/data [15:0] setup before WR high
Address/data [15:0] hold after WR high
tDWH
0.5 x tCCLK - 1.5 + H
D = (Data Cycle Duration) x tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALE
tALEW
tWW
WR
RD
tALEHZ
tADAH
tADAS
tDWS
tDWH
VALID ADDRESS
AD[15:0]
VALID DATA
Figure 18. Write Cycle For 16-bit Memory Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
26
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Serial Ports
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P[20:1] pins through the SRU. The timing specifications
provided below are valid at the DAI_P[20:1] pins.
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 20. Serial Ports—External Clock
Parameter
Min
Max
Units
Timing Requirements
tSFSE
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)1
FS Hold After SCLK
4
ns
tHFSE
(Externally Generated FS in either Transmit or Receive Mode)1 5.5
ns
ns
ns
ns
ns
tSDRE
tHDRE
tSCLKW
tSCLK
Receive Data Setup Before Receive SCLK1
Receive Data Hold After SCLK1
SCLK Width
4
5.5
20
40
SCLK Period
Switching Characteristics
tDFSE
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode) 2
FS Hold After SCLK
16
16
ns
tHOFSE
(Internally Generated FS in either Transmit or Receive Mode)1
Transmit Data Delay After Transmit SCLK1
Transmit Data Hold After Transmit SCLK1
1
0
ns
ns
ns
tDDTE
tHDTE
1
Referenced to sample edge.
Referenced to drive edge.
2
Table 21. Serial Ports—Internal Clock
Parameter
Min
Max
Units
Timing Requirements
tSFSI
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)1 14.5
FS Hold After SCLK
ns
tHFSI
(Externally Generated FS in either Transmit or Receive Mode)1 -4
ns
ns
ns
tSDRI
tHDRI
Receive Data Setup Before SCLK1
Receive Data Hold After SCLK1
9.5
-2
Switching Characteristics
tDFSI
FS Delay After SCLK
(Internally Generated FS in Transmit Mode)2
FS Hold After SCLK
7.5
11
ns
ns
ns
tHOFSI
tDFSI
(Internally Generated FS in Transmit Mode)1
FS Delay After SCLK
-1.5
-4
(Internally Generated FS in Receive or Mode)
FS Hold After SCLK
(Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK1
Transmit Data Hold After SCLK1
Transmit or Receive SCLK Width
tHOFSI
ns
ns
ns
ns
tDDTI
tHDTI
tSCLKIW
7.5
-1.5
0.5tSCLK-2
0.5tSCLK+2
1
Referenced to the sample edge.
Referenced to drive edge.
2
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
27
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Table 22. Serial Ports—Enable and Three-State
Parameter
Min
Max
Units
Switching Characteristics
tDDTEN
tDDTTE
tDDTIN
tDDTTI
Data Enable from External Transmit SCLK1
Data Disable from External Transmit SCLK1
Data Enable from Internal Transmit SCLK1
Data Disable from Internal Transmit SCLK1
2
0
ns
ns
ns
ns
13
3
1
Referenced to drive edge.
Table 23. Serial Ports—External Late Frame Sync
Parameter
Min
Max
Units
Switching Characteristics
tDDTLFSE
Data Delay from Late External Transmit FS or External
Receive FS with MCE = 1, MFD = 01
Data Enable for MCE = 1, MFD = 01
16
ns
ns
tDDTENFS
0.5
1
The t
and t
parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.
DDTENFS
DDTLFSE
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
tHFSE/I
DRIVE
DIA_P[20:0]
(SCLK)
tSFSE/I
DIA_P[20:0]
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
1ST BIT
DIA_P[20:0]
(D A/D B)
X
X
2ND BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE
SAMPLE
tHFSE/I
DRIVE
DIA_P[20:0]
(SCLK)
tSFSE/I
DIA_P[20:0]
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
1ST BIT
DIA_P[20:0]
(D A/D B)
X
X
2ND BIT
tDDTLFSE
NOTE
SERIAL PORT SIGNALS (SCLK, FS, DXA,/DXB) ARE ROUTED TO THE DAI_P[20:1] PINS USING THE SRU.
THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.
Figure 19. External Late Frame Sync1
1
This figure reflects changes made to support Left-justified Sample Pair mode.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
28
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
DATA RECEIVE— INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA RECEIVE— EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
tSCLKW
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(SCLK)
tDFSI
tDFSE
tHFSE
tHFSI
tSFSI
tSFSE
tHOFSI
tHOFSE
DAI_P[20:1]
(FS)
DAI_P[20:1]
(FS)
tHDRE
tSDRI
tHDRI
tSDRE
DAI_P[20:1]
DAI_P[20:1]
(D A/D B)
(D A/D B)
X X
X
X
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT — INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT — EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
tSCLKW
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(SCLK)
tDFSI
tDFSE
tHFSI
tHOFSI
tSFSI
tHOFSE
tSFSE
tHFSE
DAI_P[20:1]
(FS)
DAI_P[20:1]
(FS)
tDDTE
tDDTI
tHDTE
tHDTI
DAI_P[20:1]
DAI_P[20:1]
(D A/D B)
(D A/D B)
X X
X
X
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
DAI_P[20:1]
SCLK (EXT)
SCLK
tDDTEN
tDDTTE
DAI_P[20:1]
D
X
A/D B
X
DRIVE EDGE
DRIVE EDGE
SCLK
DAI_P[20:1]
SCLK (INT)
tDDTIN
tDDTTI
DAI_P[20:1]
D
X
A/D B
X
Figure 20. Serial Ports
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
29
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 24. IDP
Signals(SCLK, FS, SDATA)areroutedtotheDAI_P[20:1]pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P[20:1] pins.
Table 24. Input Data Port
Parameter
Min
Max
Units
Timing Requirements
tSISFS
tSIHFS
tSISD
tSIHD
tIDPCLKW
tIDPCLK
FS Setup Before SCLK Rising Edge1
FS Hold After SCLK Rising Edge1
SData Setup Before SCLK Rising Edge1
SData Hold After SCLK Rising Edge1
Clock Width
4
5.5
4
5.5
9
20
ns
ns
ns
ns
ns
ns
Clock Period
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any
of the DAI pins.
SAMPLE EDGE
tSISCLKW
DAI_P[20:1]
(SCLK)
tSIHFS
tSISFS
DAI_P[20:1]
(FS)
tSISD
tSIHD
DAI_P[20:1]
(SDATA)
Figure 21. IDP Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
30
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Parallel Data Acquisition Port (PDAP)
significant16bitsofexternalPDAPdatacanbeprovidedthrough
either the parallel port AD[15:0] or the DAI_P[20:5] pins. The
remaining 4 bits can only be sourced through DAI_P[4:1]. The
timing below is valid at the DAI_P[20:1] pins or at the AD[15:0]
pins.
ThetimingrequirementsforthePDAPareprovidedinTable 25.
PDAP is the parallel mode operation of channel 0 of the IDP. For
details on the operation of the IDP, see the IDP chapter of the
ADSP-2126x Hardware Reference Manual. Note that the most
Table 25. Parallel Data Acquisition Port (PDAP)
Parameter
Min
Max
Units
Timing Requirements
tSPCLKEN
tHPCLKEN
tPDSD
tPDHD
tPDCLKW
tPDCLK
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge1
4
5.5
4
5.5
9
20
ns
ns
ns
ns
ns
ns
PDAP_CLKEN Hold After PDAP_CLK Sample Edge1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge1
Clock Width
Clock Period
tPDHLDD
Delay of PDAP strobe after last PDAP_CLK capture edge for
a word
2 x tCCLK
1 x tCCLK
ns
ns
tPDSTRB
PDAP Strobe Pulse Width
1
Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI
pins through PCG.
SAMPLE EDGE
tPDCLKW
DAI_P[20:1]
(PDAP_CLK)
tSPHLD
tHPHLD
DAI_P[20:1]
(PDAP_CLKEN)
tPDSD
tPDHD
DATA
DAI_P[20:1]
(PDAP_STROBE)
tPDSTRB
tPDHLDD
Figure 22. PDAP Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
31
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
SPI Interface—Master
Table 26. SPI Interface Protocol — Master Switching and Timing Specifications
Name
Parameter
Min
Max
Units
Switching Characteristics
tSPICLKM
tSPICHM
tSPICLM
Serial clock cycle
Serial clock high period
Serial clock low period
8 x tCCLK
4 x tCCLK
4 x tCCLK - 2
ns
ns
ns
tDDSPIDM
tHDSPIDM
tSDSCIM
SPICLK edge to data out valid (data out delay time)
SPICLK edge to data out not valid (data out hold time)
FLAG3-0 OUT (SPI device select)
low to first SPICLK edge
Last SPICLK edge to FLAG3-0 OUT high
Sequential transfer delay
0
2
ns
2 x tCCLK - 2.5
2 x tCCLK
2 x tCCLK
ns
ns
ns
tHDSM
tSPITDM
Timing Requirements
tSSPIDM
Data input valid to SPICLK edge
(data input set-up time)
2
2
ns
ns
tHSPIDM
SPICLK last sampling edge to data input not valid
FLAG3-0
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICHM
tDDSPIDM
tSPICLKM
tHDSM
tSPITDM
SPICLK
(CP = 0)
(OUTPUT)
tSPICLM
SPICLK
(CP = 1)
(OUTPUT)
tHDSPIDM
MOSI
(OUTPUT)
MSB
LSB
tSSPIDM
tSSPID M
CPHASE=1
tHSPIDM
tHSSPIDM
MISO
MSB
LSB
(INPUT)
VALID
VALID
tHDSPIDM
tDDSPIDM
MOSI
(OUTPUT)
MSB
LSB
tSSPID M
tHSPIDM
CPHASE=0
MSB
VALID
LSB
VALID
MISO
(INPUT)
Figure 23. SPI Master Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
32
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
SPI Interface—Slave
Table 27. SPI Interface Protocol —Slave Switching and Timing Specifications
Name
Parameter
Min
Max
Units
Switching Characteristics
tDSOE
tDSDHI
tDDSPIDS
tHDLSBS
tDSOV
SPIDS assertion to data out active
SPIDS deassertion to data high impedance
SPICLK edge to data out valid (data out delay time)
SPICLK edge to data out not valid (data out hold time) 2 x tCCLK
0
0
4
4
9.4
ns
ns
ns
ns
SPIDS assertion to data out valid (CPHASE=0)
5 x tCCLK
ns
Timing Requirements
tSPICLKS
tSPICHS
tSPICLS
tSDSCO
Serial clock cycle
Serial clock high period
Serial clock low period
SPIDS assertion to first SPICLK edge
CPHASE = 0
CPHASE = 1
Last SPICLK edge to SPIDS not asserted
CPHASE = 0
4 x tCCLK
2 x tCCLK
2 x tCCLK - 2
ns
ns
ns
ns
2 x tCCLK
2 x tCCLK
2 x tCCLK
tHDS
ns
tSSPIDS
Data input valid to SPICLK edge
(data input set-up time)
2
2
ns
ns
ns
tHSPIDS
tSDPPW
SPICLK last sampling edge to data input not valid
SPIDS deassertion pulse width (CPHASE=0)
2 x tCCLK
SPIDS
(INPUT)
tSPIC HS
tSPICLS
tSPICLKS
tHDS
tSDPPW
SPICLK
(CP = 0)
(INPUT)
tSPICLS
tSDSCO
tSPICHS
SPICLK
(CP = 1)
(INPUT)
tDSDHI
tDDSPIDS
tDSOE
tDDSPIDS
tHD LSB S
MISO
(OUTPUT)
MSB
LSB
tHSPIDS
CPHASE=1
tSSPIDS
tSSPIDS
MOSI
(INPUT)
LSB VALID
MSB VALID
tDSOV
tDSOE
tHDLSBS
tDDSPIDS
tDSDHI
MISO
(OUTPUT)
LSB
MSB
tHSPIDS
CPHASE=0
tSSPIDS
MOSI
MSB VALID
LSB VALID
(INPUT)
Figure 24. SPI Slave Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
33
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
JTAG Test Access Port and Emulation
Table 28. JTAG Test Access Port and Emulation
Parameter
Min
Max
Units
Timing Requirements
tTCK
TCK Period
tCK
5
6
7
18
4tCK
ns
ns
ns
ns
ns
ns
tSTAP
tHTAP
tSSYS
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1
TRST Pulse Width
tHSYS
tTRSTW
Switching Characteristics
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low2
13
30
ns
ns
1
2
System Inputs = AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15-0, RD, WR, FLAG3-0, CLKOUT, EMU, ALE.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 25. IEEE 11499.1 JTAG Test Access Port
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
34
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Output Drive Currents
Example System Hold Time Calculation
Figure 26 shows typical I-V characteristics for the output drivers
oftheADSP-21266. Thecurvesrepresentthecurrentdrivecapa-
bility of the output drivers as a function of output voltage.
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given in “Output Disable
Time” above. Choose
ADSP-21266's output voltage and the input threshold for the
device requiring the hold time. A typical V will be 0.4 V. CL is
∆V to be the difference between the
∆
thetotalbuscapacitance(perdataline),andIListhetotalleakage
or three-state current (per data line). The hold time will be tDECAY
plus the minimum disable time (that is, tDATRWH for the write
cycle).
120
100
80
60
40
3.47V, TBD
3.3V, TBD
3.13V, TBD
V
OH
20
0
REFERENCE
SIGNAL
-20
-40
-60
-80
V
tMEASURED
OL
3.47V, TBD
3.3V, TBD
3.13V, TBD
tDIS
tENA
V
OH
-100
-120
(MEASURED)
V
(MEASURED) – ⌬V
(MEASURED) + ⌬V
2.0V
1.0V
OH
0
0.5
1
1.5
2
2.5
3
3.5
V
OL
V
OL
SOURCE (VDDEXT) VOLTAGE - V
(MEASURED)
tDECAY
Figure 26. ADSP-21266 Typical Drive
OUTPUT
STOPS DRIVING
OUTPUT
STARTS DRIVING
Test Conditions
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
TBD
VOLTAGE TO BE APPROXIMATELY 1.5V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from the
point when a reference signal reaches a high or low voltage level
to the point when the output has reached a specified high or low
trip point, as shown in the Output Enable/Disable diagram
(Figure 27). If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
Figure 27. Output Enable/Disable
50⍀
TO
OUTPUT
PIN
1.5V
Output Disable Time
Outputpinsareconsideredtobedisabledwhentheystopdriving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
30pF
to decay by ∆V is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the
following equation:
Figure 28. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
C ∆V
L
----------------
t
=
DECAY
I
L
Output disable time tDIS is the difference between tMEASURED and
tDECAY as shown in Figure 27. The time tMEASURED is the interval
from when the reference signal switches to when the output
INPUT
OR
OUTPUT
1.5V
1.5V
voltage decays
voltage. The tDECAY is calculated with test loads CL and IL, and
with V equal to 0.5 V.
∆V from the measured output high or output low
Figure 29. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
∆
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
35
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
16.0
14.0
12.0
10.0
8.0
25
20
15
6.0
10
5
4.0
2.0
NOMINAL
0
0
20
40
60
80
100 120 140 160 180 200
LOAD CAPACITANCE - PF
-5
0
30
60
90
120
150
180
210
LOAD CAPACITANCE - pF
Figure 32. Typical Output Rise Time
(10%-90%, VDDEXT = Max)
Figure 30. Typical Output Rise Time
(10%-90%, VDDEXT = Min)
Thermal Characteristics
The ADSP-21266 is specified for a case temperature (TCASE).
To ensure that the TCASE data sheet specification is not
exceeded, a heat sink and/or an air flow source may be used. Use
thecentergroundlandtoprovidethermalpathwaystotheprinted
circuit board’s (PCB) ground plane. A heat sink should be
attached to the ground plane (as close as possible to the thermal
pathways) with a thermal adhesive (136-Ball BGA only).
16.0
14.0
12.0
10.0
8.0
Table 29 and Table 30 airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6 and the junc-
tion-to-board measurement complies with JESD51-8. The
junction-to-case measurement complies with MIL -STD-883.
All measurements use a 2S2P JEDEC test board.
6.0
4.0
2.0
Table 29. Thermal Characteristics for 136 Ball BGA
0
0
20
40
60
80
100 120 140 160 180 200
Parameter Condition
Typical
Units
LOAD CAPACITANCE - PF
θJA
Airflow = 0 m/s
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Airflow = 1 m/s
Airflow = 2 m/s
–
Figure 31. Typical Output Delay or Hold vs. Load
Capacitance (at Max Case Temperature)
θJC
θJB
ΨJT
–
Capacitive Loading
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Output delays and holds are based on standard capacitive loads:
12 pF on all pins (see Figure 28). Figure 31 shows graphically
how output delays and holds vary with load capacitance (Note
thatthisgraphorderatingdoesnotapplytooutputdisabledelays;
see Output Disable Time on page 35). The graphs of Figure 31,
Figure 32 and Figure 30 may not be linear outside the ranges
shown for Typical Output Delay vs. Load Capacitance and
Typical Output Rise Time (10%-90%, V=Min) vs. Load
Capacitance.
ENVIRONMENTAL CONDITIONS
The ADSP-21266 is available in 136-Ball Grid Array (BGA) and
144-lead LQFP packages. For more information, see “Ordering
Guide” on page 43.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
36
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Table 30. Thermal Characteristics for 144 Lead LQFP
Parameter
Typical
Units
θJA
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
–
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
TBD
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJC
ΨJT
• To determine the Junction Temperature of the device
while on the application PCB, use:
TJ = TCASE + (ΨJT × PD)
Where:
0
T = Junction temperature C
J
T
= Case temperature measured at the top center of the
CASE
package
Ψ
= PSI junction temperature = Typical value from the tables
JT
above
PD= Power dissipation see EE Note #TBD
• Values of θJA are provided for package comparison and
PCB design considerations. θJA can be used for a 1st order
approximation of TJ by the equation:
TJ = TA + (θJA × PD)
Where:
0
T
= Ambient Temperature C
A
• Values of θJC are provided for package comparison and
PCB design considerations when an external heatsink is
required.
• Values of θJB are provided for package comparison and
PCB design considerations.
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
37
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
136-BALL BGA PIN CONFIGURATIONS
Table 31. 136-ball BGA Pin Assignments
BGA
BGA
Pin#
BGA
Pin#
BGA
Pin#
Pin Name
Pin#
Pin Name
Pin Name
Pin Name
CLKCFG0
XTAL
TMS
TCK
TDI
CLKOUT
TDO
EMU
MOSI
MISO
SPIDS
VDDINT
GND
GND
VDDINT
GND
GND
GND
GND
GND
GND
GND
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
E01
E02
E04
E05
E06
E09
E10
E11
E13
E14
CLKCFG1
GND
VDDEXT
CLKIN
TRST
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
F01
F02
F04
F05
F06
F09
F10
F11
F13
F14
BOOTCFG1
BOOTCFG0
GND
GND
GND
C01
C02
C03
C12
C13
C14
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
D01
D02
D04
D05
D06
D09
D10
D11
D13
D14
AVSS
AVDD
VDDINT
VDDEXT
SPICLK
RESET
VDDINT
GND
GND
GND
FLAG1
FLAG0
GND
GND
GND
GND
GND
GND
FLAG2
DAI_P20 (SFS45)
AD7
VDDINT
VDDEXT
G01
G02
G13
AD6
VDDEXT
DAI_P18 (SD5B)
DAI_P17 (SD5A)
H01
H02
H13
H14
DAI_P19 (SCLK45) G14
GND
FLAG3
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
38
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
Table 31. 136-ball BGA Pin Assignments (Continued)
BGA
Pin#
BGA
BGA
Pin#
BGA
Pin Name
AD5
AD4
GND
GND
GND
GND
GND
GND
VDDINT
Pin Name
AD3
VDDINT
GND
GND
GND
GND
GND
GND
GND
DAI_P15 (SD4A)
AD14
AD13
AD12
AD11
AD10
AD9
DAI_P1 (SD0A)
DAI_P3 (SCLK0)
DAI_P5 (SD1A)
DAI_P6 (SD1B)
DAI_P7 (SCLK1)
DAI_P8 (SFS1)
DAI_P9 (SD2A)
DAI_P11 (SD3A)
Pin#
K01
K02
K04
K05
K06
K09
K10
K11
K13
K14
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
Pin Name
AD2
AD1
GND
GND
GND
GND
GND
GND
Pin Name
AD0
WR
GND
GND
Pin#
M01
M02
M03
M12
M13
J01
J02
J04
J05
J06
J09
J10
J11
J13
L01
L02
L04
L05
L06
L09
L10
L11
L13
L14
DAI_P12 (SD3B)
DAI_P13 (SCLK23) M14
GND
DAI_P14 (SFS23)
DAI_P16 (SD4B) J14
AD15
ALE
RD
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
VDDINT
VDDEXT
AD8
VDDINT
DAI_P2 (SD0B)
VDDEXT
DAI_P4 (SFS0)
VDDINT
VDDINT
GND
DAI_P10 (SD2B) N14
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
39
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY
V
A
VDD
GND*
DDINT
V
A
I/O SIGNALS
DDEXT
VSS
*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE
THERMAL PATHWAYS TO YOUR PRINTED
CIRCUIT BOARD’S GROUND PLANE.
Figure 33. 136-ball BGA Pin Assignments (Bottom View, Summary)
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
40
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
144-LEAD LQFP PIN CONFIGURATIONS
Table 32. 144-Lead LQFP Pin Assignments
LQFP
LQFP
Pin #
LQFP
Pin #
LQFP
Pin #
Pin Name
Pin #
Pin Name
Pin Name
Pin Name
VDDINT
CLKCFG0
CLKCFG1
BOOTCFG0
BOOTCFG1
GND
VDDEXT
GND
VDDINT
GND
VDDINT
GND
VDDINT
GND
FLAG0
FLAG1
AD7
GND
VDDINT
GND
VDDEXT
GND
VDDINT
AD6
AD5
AD4
VDDINT
GND
AD3
1
2
3
4
5
6
7
8
VDDINT
GND
RD
ALE
AD15
AD14
AD13
GND
VDDEXT
AD12
VDDINT
GND
AD11
AD10
AD9
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
VDDEXT
GND
VDDINT
GND
DAI_P10 (SD2B)
DAI_P11 (SD3A)
DAI_P12 (SD3B)
73
74
75
76
77
78
79
GND
VDDINT
GND
VDDINT
GND
VDDINT
GND
VDDEXT
GND
VDDINT
GND
VDDINT
RESET
SPIDS
GND
VDDINT
SPICLK
MISO
MOSI
GND
VDDINT
VDDEXT
AVDD
AVSS
GND
CLKOUT
EMU
TDO
TDI
TRST
TCK
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DAI_P13 (SCLK23) 80
9
DAI_P14 (SFS23)
DAI_P15 (SD4A)
VDDINT
GND
GND
DAI_P16 (SD4B)
DAI_P17 (SD5A)
DAI_P18 (SD5B)
DAI_P19 (SCLK45) 89
VDDINT
GND
81
82
83
84
85
86
87
88
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AD8
DAI_P1 (SD0A)
VDDINT
GND
DAI_P2 (SD0B)
DAI_P3 (SCLK0) 57
GND
VDDEXT
VDDINT
GND
DAI_P4 (SFS0)
DAI_P5 (SD1A)
DAI_P6 (SD1B)
DAI_P7 (SCLK1) 65
VDDINT
GND
VDDINT
GND
90
91
92
93
94
95
96
97
GND
VDDEXT
DAI_P20 (SFS45)
GND
VDDINT
FLAG2
FLAG3
VDDINT
GND
VDDINT
GND
VDDINT
GND
58
59
60
61
62
63
64
98
99
100
101
102
103
104
105
106
107
108
AD2
VDDEXT
GND
AD1
AD0
66
67
68
69
70
71
72
TMS
GND
CLKIN
XTAL
VDDEXT
VDDINT
GND
VDDINT
VDDINT
DAI_P8 (SFS1)
DAI_P9 (SD2A)
VDDINT
WR
VDDINT
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
41
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
PACKAGE DIMENSIONS
August 2003
ADSP-21266
The ADSP-21266 is available in a 136-ball BGA package. All
dimensions are in millimeters (mm).
136-BALL BGA
10.40
BSC
12.00
SQ
BSC
A1 BALL
PAD CORNER
0.80
TYP
A
B
C
D
E
F
G
H
J
A1 BALL
PAD CORNER
12.00
SQ
BSC
10.40
BSC
Top View
K
L
M
N
P
14 13 12 11 10 9
8 7 6 5 4 3 2 1
0.80
TYP
DETAIL A
1.70
MAX
DETAIL A
0.85
MIN
ALL DIMENSIONS IN MILIMETERS (MM).
NOTE
0.25
MIN
1. THE ACTUAL POSITION OF THE BALL GRID IS
0.50
0.46
0.40
SEATING
PLANE
WITHIN 0.150 MM OF ITS IDEAL POSITION RELATIVE
TO THE PACKAGE EDGES. THE ACTUAL POSITION
OF EACH BALL IS WITHIN 0.08 MM OF ITS IDEAL
POSITION RELATIVE TO THE BALL GRID.
0.12
MAX
BALL
2. COMPLIANT TO JEDEC REGISTERED OUTLINE
MO-205-AE WITH THE EXCEPTION OF DIMENSION “b”
DIAMETER
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
42
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
OUTLINE DIMENSIONS
August 2003
ADSP-21266
The ADSP-21266 is available in a 144-lead LQFP package. All
dimensions are in millimeters (mm).
144-LEAD LQFP (ST-144)
22.00 BSC SQ
20.00 BSC SQ
109
144
1
108
PIN 1 INDICATOR
0.50
BSC
TYP
(LEAD
PITCH)
0.27
0.22
0.17
TYP
SEATING
PLANE
0.08 MAX (LEAD
COPLANARITY)
0.15
0.05
1.45
1.40
1.35
0.75
0.60 TYP
0.45
73
3 6
72
37
1.60 MAX
DETAIL A
DETAIL A
TOP VIEW (PINS DOWN)
NOTES:
1.
2.
DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB.
ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.
3.
CENTER DIMENSIONS ARE NOMINAL.
ORDERING GUIDE
Case Temperature
Range
On-Chip
SRAM
Part Number
Instruction Rate
ROM
Operating Voltage
ADSP-21266SKBC-200x
ADSP-21266SKSTZx
(Pb-free)
0°C to +85°C
0°C to +85°C
200 MHz
150 MHz
2 Mbit
2 Mbit
4 Mbit
4 Mbit
1.2 INT/3.3 EXT V
1.2 INT/3.3 EXT V
ADSP-21266SKSTZx
(Pb-free)
0°C to +85°C
200 MHz
2 Mbit
4 Mbit
1.2 INT/3.3 EXT V
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
43
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
August 2003
ADSP-21266
This information applies to a product under development. Its characteristics and specifications are subject to change without
notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PrB
44
相关型号:
©2020 ICPDF网 联系我们和版权申明