ADSP-21266_07_技术文档

SHARC^®

Embedded Processor

ADSP-21266

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Code compatibility—at assembly level, uses the same

instruction set as other SHARC DSPs

Processes high performance audio while enabling low

system costs

Single-instruction multiple-data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/

40-bit extended precision floating-point computational

units, each with a multiplier, ALU, shifter, and register file

High bandwidth I/O—a parallel port, an SPI port, six serial

ports, a digital audio interface (DAI), and JTAG

DAI incorporates two precision clock generators (PCGs), an

input data port (IDP) that includes a parallel data acquisi-

tion port (PDAP), and three programmable timers, all

under software control by the signal routing unit (SRU)

On-chip memory—2M bits on-chip SRAM and a dedicated 4M

bits on-chip mask-programmable ROM

The ADSP-21266 is available with a 150 MHz or a 200 MHz

core instruction rate. For complete ordering information,

see Ordering Guide on Page 44.

Audio decoders and postprocessor algorithms support

nonvolatile memory that can be configured to contain a

combination of PCM 96 kHz, Dolby^®Digital, Dolby Digital

Surround EX^TM, DTS-ES^TMDiscrete 6.1, DTS-ES Matrix 6.1,

DTS^®96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-

PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and

DTS Neo:6^TM

Various multichannel surround-sound decoders are con-

tained in ROM. For configurations of decoder algorithms,

see Table 2 on Page 6.

DUAL PORTED MEMORY

BLOCK 0

DUAL PORTED MEMORY

BLO CK 1

CORE PROCESSOR

INSTRUCTION

SRAM

1M BIT

SRAM

1M BIT

CACHE

TIMER

ROM

32

؋

48-BIT

2M BIT

DAG1

8

؋

4

؋

32

DAG2

8

؋

4

؋

32

PROGRAM

SEQ UENCER

ADDR

DATA

ADDR

DATA

PM ADDRESS BUS

DM ADDRESS BUS

32

64 PM DATA BUS

64 DM DATA BUS

IOD

(32)

IOA

(18)

DMA CONTROLLER

PX REGISTER

4

22 CHANNELS

GPIO FLAGS/

IRQ/TIMEXP

PROCESSING

ELEMENT

(PEX)

PROCESSING

ELEMENT

(PEY)

4

SPI PORT (1)

16

ADDRES S/

DATA BUS / GPIO

3

6

CONTROL/GPIO

SERIAL PORTS (6)

JTAG TEST & EMULATION

PARALLEL

PORT

IOP

REGISTERS

(MEMORY MAPPED)

20

SIGNAL

RO UTI NG

UNIT

INPUT

DATA PORTS (8)

PARALLEL DATA

ACQUISITION PORT

CONTROL,

STATUS,

DATA BUFFERS

PRECISION CLOCK

GENERATORS (2)

S

3

TIMERS (3)

DIGITAL AUDIO INTERFACE

I/O PROCESSOR

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

FAX: 781.461.3113

www.analog.com

ADSP-21266

KEY FEATURES

Serial ports offer left-justified sample-pair and I²S support

via 12 programmable and simultaneous receive or trans-

mit pins, which support up to 24 transmit or 24 receive I²S

channels of audio when all 6 serial ports (SPORTs) are

enabled or 6 full duplex TDM streams of up to 128

channels per frame

At 200 MHz (5 ns) core instruction rate, the ADSP-21266

operates at 1200 MFLOPS peak/800 MFLOPS sustained

performance whether operating on fixed- or floating-point

data; 400 MMACS sustained performance at 200 MHz

Super Harvard Architecture—three independent buses for

dual data fetch, instruction fetch, and nonintrusive, zero-

overhead I/O

Asynchronous parallel/external port provides:

Access to asynchronous external memory

16 multiplexed address/data lines that can support 24-bit

address external address range with 8-bit data or 16-bit

address external address range with 16-bit data

66M byte/sec transfer rate for 200 MHz core rate

50M byte/sec transfer rate for 150 MHz core rate

256 word page boundaries

External memory access in a dedicated DMA channel

8- to 32-bit and 16- to 32-bit word packing options

Programmable wait state options: 2 to 31 CCLKs

Serial ports provide:

Six dual data line serial ports that operate at up to

50M bits/sec for a 200 MHz core and up to 37.5M bits/sec

for a 150 MHz core on each data line—each has a clock,

frame sync, and two data lines that can be configured as

either a receiver or transmitter pair

Left-justified sample-pair and I²S support, programmable

direction for up to 24 simultaneous receive or transmit

channels using two I²S-compatible stereo devices per

serial port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony inter-

faces such as H.100/H.110

Up to 12 TDM stream support, each with 128 channels

per frame

Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the

SHARC core configurable as either eight channels of I²S or

serial data or as seven channels plus a single 20-bit wide

synchronous parallel data acquisition port

Supports receive audio channel data in I²S, left-justified

sample pair, or right-justified mode

Signal routing unit (SRU) provides configurable and flexible

connections between all DAI components, six serial ports,

two precision clock generators, three timers, an input data

port/parallel data acquisition port, 10 interrupts, six flag

inputs, six flag outputs, and 20 SRU I/O pins (DAI_Px)

Serial peripheral interface (SPI)

2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit

block 1) for simultaneous access by core processor and

DMA

4M bits on-chip dual-ported mask-programmable ROM

(2M bits in block 0 and 2M bits in block 1)

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup,

providing efficient program sequencing

Single instruction multiple data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution—each processing element executes

the same instruction, but operates on different data

Parallelism in buses and computational units allows single

cycle executions (with or without SIMD) of a multiply

operation; an ALU operation; a dual memory read or

write; and an instruction fetch

Transfers between memory and core at up to four 32-bit

floating- or fixed-point words per cycle, sustained

2.4 GBps bandwidth at 200 MHz core instruction rate; 900

Mbps is available via DMA

Accelerated FFT butterfly computation through a multiply

with add and subtract instruction

DMA controller supports:

22 zero-overhead DMA channels for transfers between the

ADSP-21266 internal memory and serial ports (12), the

input data ports (IDP) (eight), the SPI-compatible port

(one), and the parallel port (one)

32-bit background DMA transfers at core clock speed, in

parallel with full-speed processor execution

JTAG background telemetry for enhanced emulation

features

Master or slave serial boot through SPI

Full-duplex operation

Master-slave mode multimaster support

Open-drain outputs

Programmable baud rates, clock polarities, and phases

3 muxed flag/IRQ lines

1 muxed flag/timer expired line

IEEE 1149.1 JTAG standard test access port and on-chip

emulation

ROM-based security features:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.2 V core

Available in 136-ball BGA and 144-lead LQFP packages; avail-

able in RoHS compliant packages

Digital audio interface includes six serial ports, two precision

clock generators, an input data port, three programmable

timers, and a signal routing unit

Rev. C

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ADSP-21266

TABLE OF CONTENTS

Summary ............................................................... 1

Key Features ........................................................... 2

Table of Contents .................................................... 3

Revision History ...................................................... 3

General Description ................................................. 4

ADSP-21266 Family Core Architecture ...................... 4

ADSP-21266 Memory and I/O Interface Features ......... 6

Target Board JTAG Emulator Connector .................... 9

Development Tools ............................................... 9

Evaluation Kit ..................................................... 10

Designing an Emulator-Compatible DSP Board (Target) 10

Additional Information ......................................... 10

Pin Function Descriptions ........................................ 11

Address Data Pins as Flags ..................................... 14

Core Instruction Rate to CLKIN Ratio Modes ............. 14

Address Data Modes ............................................. 14

ADSP-21266 Specifications ....................................... 15

Operating Conditions ........................................... 15

Electrical Characteristics ........................................ 15

Package Information ............................................ 16

ESD Caution ...................................................... 16

Absolute Maximum Ratings ................................... 16

Timing Specifications ........................................... 16

Output Drive Currents .......................................... 37

Test Conditions ................................................... 37

Capacitive Loading ............................................... 37

Environmental Conditions ..................................... 38

Thermal Characteristics ........................................ 38

136-Ball BGA Pin Configurations ............................... 39

144-Lead LQFP Pin Configurations ............................. 42

Package Dimensions ................................................ 43

Surface-Mount Design .......................................... 44

Ordering Guide ...................................................... 44

REVISION HISTORY

9/07—Rev. B to Rev. C

Corrected all outstanding document errata.

Added new section Package Information .................. 16

Revised Timing Specifications ................................ 16

Ordering Guide .................................................. 44

Rev. C

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ADSP-21266

GENERAL DESCRIPTION

The ADSP-21266 SHARC DSP is a member of the SIMD

SHARC family of DSPs featuring Analog Devices Super Har-

vard Architecture. The ADSP-21266 is source code compatible

with the ADSP-2126x, ADSP-21160, and ADSP-21161 DSPs as

well as with first generation ADSP-2106x SHARC processors in

SISD (single-instruction, single-data) mode. Like other SHARC

DSPs, the ADSP-21266 is a 32-bit/40-bit floating-point proces-

sor optimized for high performance audio applications with its

dual-ported on-chip SRAM, mask-programmable ROM, multi-

ple internal buses to eliminate I/O bottlenecks, and an

innovative digital audio interface.

• Three programmable interval timers with PWM genera-

tion, PWM capture/pulse width measurement, and

external event counter capabilities

• On-chip dual-ported SRAM (2M bit)

• On-chip dual-ported, mask-programmable ROM

(4M bit)

• JTAG test access port

• 8- or 16-bit parallel port that supports interfaces to off-chip

memory peripherals

• DMA controller

As shown in the functional block diagram in Figure 1 on Page 1,

the ADSP-21266 uses two computational units to deliver a 5 to

10 times performance increase over previous SHARC proces-

sors on a range of DSP algorithms. Fabricated in a state-of-the-

art, high speed, CMOS process, the ADSP-21266 DSP achieves

an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at

150 MHz. With its SIMD computational hardware, the ADSP-

21266 can perform 1200 MFLOPS running at 200 MHz, or 900

MFLOPS running at 150 MHz.

• Six full-duplex serial ports

• SPI-compatible interface

• Digital audio interface that includes two precision clock

generators (PCG), an input data port (IDP), six serial ports,

eight serial interfaces, a 20-bit synchronous parallel input

port, 10 interrupts, six flag outputs, six flag inputs, three

programmable timers, and a flexible signal routing unit

(SRU)

Table 1 shows performance benchmarks for the ADSP-21266.

Figure 2 shows one sample configuration of a SPORT using the

precision clock generator to interface with an I²S ADC and an

I²S DAC with a much lower jitter clock than the serial port

would generate itself. Many other SRU configurations are

possible.

Table 1. ADSP-21266 Benchmarks (at 200 MHz)

Speed

(at 200 MHz)

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with reversal) 61.3 μs

ADSP-21266 FAMILY CORE ARCHITECTURE

FIR Filter (per tap)¹

3.3 ns

The ADSP-21266 is code compatible at the assembly level with

the ADSP-2136x and ADSP-2116x, and with the first generation

ADSP-2106x SHARC DSPs. The ADSP-21266 shares architec-

tural features with the ADSP-2136x and ADSP-2116x SIMD

SHARC family of DSPs, as detailed in the following sections.

IIR Filter (per biquad)¹

13.3 ns

Matrix Multiply (pipelined)

[3×3] × [3×1]

30 ns

[4×4] × [4×1]

53.3 ns

Divide (y/x)

20 ns

30 ns

SIMD Computational Engine

Inverse Square Root

The ADSP-21266 contains two computational processing ele-

ments that operate as a single-instruction multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive audio

algorithms.

¹Assumes two files in multichannel SIMD mode.

The ADSP-21266 continues SHARC’s industry-leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features. These

features include 2M bit dual-ported SRAM memory, 4M bit

dual-ported ROM, an I/O processor that supports 22 DMA

channels, six serial ports, an SPI interface, external parallel bus,

and digital audio interface.

The block diagram of the ADSP-21266 in on Page 1 illustrates

the following architectural features:

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

• Two processing elements, each containing an ALU, multi-

plier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

Rev. C

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ADSP-21266

CLKOUT

CLKIN

XTAL

CLOCK

ALE

2

CLK_CFG 1–0

LATCH

AD15–0

ADDR

PARALLEL

2

3

BOOTCFG1–0

FLAG 3–1

PO RT

DATA

OE

RAM , ROM

BOOT ROM

I/O DEVICE

RD

WR

WE

CS

FLA G0

ADC

(OPTIONAL)

CLK

FS

SDAT

DAI_ P1

DAI_P2

DAI_P3

SCLK0

SFS0

SRU

SD0A

SD0B

DAC

(OPTIONAL)

CLK

DAI_ P1 8

DAI_ P19

DAI_P 20

SPORT0

SPORT1

SPO RT2

FS

SDAT

SPORT3

SPO RT4

SPORT5

CLK

FS

PCG A

PCGB

DAI

RESET

JTAG

6

Figure 2. ADSP-21266 System Sample Configuration

Independent, Parallel Computation Units

Single-Cycle Fetch of Instruction and Four Operands

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

The ADSP-21266 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on Page 1). With the ADSP-21266’s separate pro-

gram and data memory buses and on-chip instruction cache,

the processor can simultaneously fetch four operands (two over

each data bus) and one instruction (from the cache), all in a

single cycle.

Instruction Cache

The ADSP-21266 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Register File

A general-purpose data register file is contained in each

processing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the ADSP-2126x enhanced Har-

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0–R15 and in PEY as S0–S15.

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21266’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

signal processing, and are commonly used in digital filters and

Rev. C

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ADSP-21266

Fourier transforms. The two DAGs of the ADSP-21266 contain

sufficient registers to allow the creation of up to 32 circular buff-

ers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

between the 32-bit floating-point and 16-bit floating-point for-

mats is performed in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Using the DM bus and PM buses, with one dedicated to each

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in

the cache.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations for concise programming. For example, the

ADSP-21266 can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

DMA Controller

The ADSP-21266’s on-chip DMA controller allows zero-over-

head data transfers without processor intervention. The DMA

controller operates independently and invisibly to the processor

core, allowing DMA operations to occur while the core is simul-

taneously executing its program instructions. DMA transfers

can occur between the ADSP-21266’s internal memory and its

serial ports, the SPI-compatible (serial peripheral interface)

port, the IDP (input data port), parallel data acquisition port

(PDAP), or the parallel port. Twenty-two channels of DMA are

available on the ADSP-21266—one for the SPI interface, 12 via

the serial ports, eight via the input data port, and one via the

processor’s parallel port. Programs can be downloaded to the

ADSP-21266 using DMA transfers. Other DMA features

include interrupt generation upon completion of DMA trans-

fers, and DMA chaining for automatic linked DMA transfers.

ADSP-21266 MEMORY AND I/O INTERFACE

FEATURES

The ADSP-21266 adds the following architectural features to

the SIMD SHARC family core:

Dual-Ported On-Chip Memory

The ADSP-21266 contains two megabits of internal SRAM and

four megabits of internal mask-programmable ROM. Each

block can be configured for different combinations of code and

data storage (see memory map, Figure 3). Each memory block is

dual-ported for single-cycle, independent accesses by the core

processor and I/O processor. The dual-ported memory, in com-

bination with three separate on-chip buses, allows two data

transfers from the core and one from the I/O processor, in a sin-

gle cycle.

Digital Audio Interface (DAI)

The digital audio interface provides the ability to connect vari-

ous peripherals to any of the SHARC DSP’s DAI pins

(DAI_P20–1).

The ADSP-21266 is available with a variety of multichannel

surround-sound decoders, preprogrammed in on-chip ROM

memory. Table 2 indicates the configurations of decoder algo-

rithms provided.

Connections are made using the signal routing unit (SRU,

shown in the block diagram on Page 1).

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

Table 2. Multichannel Surround-Sound Decoder Algorithms

in On-Chip ROM

Algorithms

PCM

B ROM

Yes

C ROM

Yes

D ROM

Yes

AC-3

Yes

The DAI also includes six serial ports, two precision clock gen-

erators (PCGs), an input data port (IDP), six flag outputs and

six flag inputs, and three timers. The IDP provides an additional

input path to the ADSP-21266 core, configurable as either eight

channels of I²S or serial data, or as seven channels plus a single

20-bit wide synchronous parallel data acquisition port. Each

data channel has its own DMA channel that is independent

from the ADSP-21266’s serial ports.

DTS 96/24

AAC (LC)

v2.2

Yes

v2.3

Yes

v2.3

Coefficients only

WMAPRO 7.1 96 KHz No

No

Yes

No

MPEG2 BC 2ch

Noise

Yes

DPL2x/EX

DPL2

Yes

Neo:6/ES (v2.5046)

Yes

For complete information on using the DAI, see the

ADSP-2126x SHARC DSP Peripherals Manual.

The ADSP-21266’s SRAM can be configured as a maximum of

64K words of 32-bit data, 128K words of 16-bit data, 42K words

of 48-bit instructions (or 40-bit data), or combinations of differ-

ent word sizes up to two megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-

ing-point storage format is supported that effectively doubles

the amount of data that can be stored on-chip. Conversion

Serial Ports

The ADSP-21266 features six full duplex synchronous serial

ports that provide an inexpensive interface to a wide variety of

digital and mixed-signal peripheral devices such as the Analog

Devices AD183x family of audio codecs, ADCs, and DACs. The

Rev. C

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ADSP-21266

ADDRESS

IOP REGISTERS

0x0000 0000–0x0003 FFFF

0x0004 0000

BLOCK 0 SRAM (1M BIT)

0x0004 3FFF

0x0004 4000–0x0005 7FFF

0x0005 8000

RESERVED

LONG WORD

ADDRESS

SPACE

BLOCK 0 ROM (2M BIT)

0x0005 FFFF

0x0006 0000

ADDRESS

BLOCK 1 SRAM (1M BIT)

0x0006 3FFF

0x0020 0000

0x0006 4000–0x0007 7FFF

0x0007 8000

RESERVED

0x00FF FFFF

0x0100 0000

BLOCK 1 ROM (2M BIT)

0x0007 FFFF

0x0008 0000

BLOCK 0 SRAM (1M BIT)

RESERVED

EXTERNAL DMA

1, 4

0x0008 7FFF

ADDRESS SPACE

0x0008 8000–0x000A FFFF

0x000B 0000

NORMAL WORD

ADDRESS

2

BLOCK 0 ROM (2M BIT)

0x02FF FFFF

0x0300 0000

0x000B FFFF

0x000C 0000

SPACE

RESERVED

0x3FFF FFFF

BLOCK 1 SRAM (1M BIT)

RESERVED

0x000C 7FFF

EXTERNAL MEMORY

SPACE

0x000C 8000–0x000E FFFF

0x000F 0000

3

BLOCK 1 ROM (2M BIT)

0x000F FFFF

0x0010 0000

BLOCK 0 SRAM (1M BIT)

0x0010 FFFF

RESERVED

0x0011 0000–0x0015 FFFF

0x0016 0000

1

EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE BY THE

CORE. DMA MUST BE USED TO READ OR WRITE TO THIS

MEMORY USING THE SPI OR PARALLEL PORT.

SHORT WORD

ADDRESS

SPACE

BLOCK 0 ROM (2M BIT)

0x0017 FFFF

0x0018 0000

2

3

4

BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE

(0x000A 0000–0x000A AAAA).

BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE

(0x000E 0000–0x000E AAAA).

BLOCK 1 SRAM (1M BIT)

0x0018 FFFF

USE THE EXTERNAL ADDRESSES LISTED HERE WITH THE

PARALLEL PORT DMA REGISTERS. THE PARALLEL PORT

GENERATES ADDRESS WITHIN THE RANGE

0x0000 0000–0x00FF FFFF.

0x0019 0000–0x001D FFFF

0x001E 0000

RESERVED

BLOCK 1 ROM (2M BIT)

0x001F FFFF

INTERNAL MEMORY

SPACE

Figure 3. ADSP-21266 Memory Map

serial ports are made up of two data lines, a clock, and frame

sync. The data lines can be programmed to either transmit or

receive and each data line has its own dedicated DMA channel.

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides two receive signals. The

frame sync and clock are shared.

Serial ports are enabled via 12 programmable and simultaneous

receive or transmit pins that support up to 24 transmit or 24

receive channels of audio data when all six SPORTs are enabled,

or six full duplex TDM streams of 128 channels per frame.

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I²S mode

The serial ports operate at up to one-quarter of the DSP core

clock rate, providing each with a maximum data rate of

50M bits/sec for a 200 MHz core and 37.5M bits/sec for a

150 MHz core. Serial port data can be automatically transferred

to and from on-chip memory via a dedicated DMA. Each of the

• Left-justified sample pair mode

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ADSP-21266

Left-justified sample pair mode is a mode where in each frame

sync cycle, two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Timers

The ADSP-21266 has a total of four timers: a core timer able to

generate periodic software interrupts, and three general-pur-

pose timers that can generate periodic interrupts and be

independently set to operate in one of three modes:

Each of the serial ports supports the left-justified sample-pair

and I²S protocols (I²S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs) with two data

pins, allowing four left-justified sample-pair or I²S channels

(using two stereo devices) per serial port with a maximum of up

to 24 audio channels. The serial ports permit little-endian or

big-endian transmission formats and word lengths selectable

from 3 bits to 32 bits. For the left-justified sample pair and I²S

modes, data-word lengths are selectable between 8 bits and 32

bits. Serial ports offer selectable synchronization and transmit

modes as well as optional μ-law or A-law companding selection

on a per channel basis. Serial port clocks and frame syncs can be

internally or externally generated.

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use flag3 as a timer expired

output signal, and each general-purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables all three

general-purpose timers independently.

ROM-Based Security

The ADSP-21266 has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the DSP does not boot-load any exter-

nal code, executing exclusively from internal SRAM/ROM.

Additionally, the DSP is not freely accessible via the JTAG port.

Instead, a unique 64-bit key, which must be scanned in through

the JTAG or test access port, will be assigned to each customer.

The device will ignore a wrong key. Emulation features and

external boot modes are only available after the correct key is

scanned.

Serial Peripheral (Compatible) Interface

Serial peripheral interface is an industry-standard synchronous

serial link, enabling the ADSP-21266 SPI-compatible port to

communicate with other SPI-compatible devices. SPI is an

interface consisting of two data pins, one device select pin, and

one clock pin. It is a full-duplex synchronous serial interface,

supporting both master and slave modes. The SPI port can

operate in a multimaster environment by interfacing with up to

four other SPI-compatible devices, either acting as a master or

slave device. The ADSP-21266 SPI-compatible peripheral

implementation also features programmable baud rates at up to

50 MHz for a core clock of 200 MHz and up to 37.5 MHz for a

core clock of 150 MHz, clock phases, and polarities. The ADSP-

21266 SPI-compatible port uses open-drain drivers to support a

multimaster configuration and to avoid data contention.

Program Booting

The internal memory of the ADSP-21266 boots at system

power-up from an 8-bit EPROM via the parallel port, an SPI

master, an SPI slave, or an internal boot. Booting is determined

by the boot configuration (BOOT_CFG1–0) pins. Selection of

the boot source is controlled via the SPI as either a master or

slave device, or it can immediately begin executing from ROM.

Parallel Port

The parallel port provides interfaces to SRAM and peripheral

devices. The multiplexed address and data pins (AD15–0) can

access 8-bit devices with up to 24 bits of address, or 16-bit

devices with up to 16 bits of address. In either mode, 8- or 16-

bit, the maximum data transfer rate is one-third the core clock

speed. As an example, a clock rate of 200 MHz is equivalent to

66M byte/sec, and a clock rate of 150 MHz is equivalent to

50M byte/sec.

Phase-Locked Loop

The ADSP-21266 uses an on-chip phase-locked loop (PLL) to

generate the internal clock for the core. On power-up, the

CLK_CFG1–0 pins are used to select ratios of 16:1, 8:1, and 3:1.

After booting, numerous other ratios can be selected via soft-

ware control. The ratios are made up of software configurable

numerator values from 1 to 64 and software configurable divi-

sor values of 2, 4, 8, and 16.

DMA transfers are used to move data to and from internal

memory. Access to the core is also facilitated through the paral-

lel port register read/write functions. The RD, WR, and ALE

(address latch enable) pins are the control pins for the

parallel port.

Power Supplies

The ADSP-21266 has separate power supply connections for the

internal (V_DDINT), external (V_DDEXT), and analog (A_VDD/A_VSS

)

power supplies. The internal and analog supplies must meet the

1.2 V requirement. The external supply must meet the 3.3 V

requirement. All external supply pins must be connected to the

same power supply.

Note that the analog supply pin (A_VDD) powers the

ADSP-21266’s internal clock generator PLL. To produce a sta-

ble clock, it is recommended that PCB designs use an external

Rev. C

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October 2007

ADSP-21266

filter circuit for the A_VDDpin. Place the filter components as

close as possible to the A_VDD/A_VSSpins. For an example circuit,

see Figure 4. (A recommended ferrite chip is the muRata

BLM18AG102SN1D). To reduce noise coupling, the PCB

should use a parallel pair of power and ground planes for V_DDINT

and GND. Use wide traces to connect the bypass capacitors to

the analog power (A_VDD) and ground (A_VSS) pins. Note that the

A_VDDand A_VSSpins specified in Figure 4 are inputs to the pro-

cessor and not the analog ground plane on the board—the A_VSS

pin should connect directly to digital ground (GND) at the chip.

The ADSP-21266 is also supported with a complete set of

CROSSCORE^®^†software and hardware development tools,

‡

including Analog Devices emulators and VisualDSP++^®

development environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-21266.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The ADSP-21266

SHARC DSP has architectural features that improve the

efficiency of compiled C/C++ code.

ADSP-212xx

100nF

10nF

1nF

A

V

VDD

VSS

DDINT

HI Z FERRITE

BEAD CHIP

A

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

LOCATE ALL COMPONENTS

CLOSE TO A AND A PINS

VDD VSS

Figure 4. Analog Power Filter Circuit

TARGET BOARD JTAG EMULATOR CONNECTOR

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21266 pro-

cessor to monitor and control the target board processor during

emulation. Analog Devices DSP Tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor’s JTAG interface ensures that the

emulator will not affect target system loading or timing.

For complete information on Analog Devices SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate emulator hardware user’s guide.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

DEVELOPMENT TOOLS

The ADSP-21266 is supported by a complete automotive refer-

ence design and development board as well as by a complete

home audio reference design board available from Analog

Devices. These boards implement complete audio decoding and

postprocessing algorithms that are factory programmed into the

ROM space of the ADSP-21266. SIMD optimized libraries con-

sume less processing resources, which results in more available

processing power for custom proprietary features.

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

The nonvolatile memory of the ADSP-21266 can be configured

to contain a combination of Dolby Digital, Dolby Pro Logic,

Dolby Pro Logic II, Dolby Pro Logic IIx, DTSES, DTS 96/24,

and Neo:6. Multiple S/PDIF and analog I/Os are provided to

maximize end system flexibility.

• Create custom debugger windows

^†CROSSCORE is a registered trademark of Analog Devices, Inc.

^‡VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. C

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ADSP-21266

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++ development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

• Control how the development tools process inputs and

generate outputs

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

• Maintain a one-to-one correspondence with the tools’

command line switches

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board flash device to store

user-specific boot code, enabling the board to run as a standal-

one unit, without being connected to the PC.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom-defined system. Connecting one of Analog Devices JTAG

emulators to the EZ-KIT Lite board enables high speed, nonin-

trusive emulation.

DESIGNING AN EMULATOR-COMPATIBLE DSP

BOARD (TARGET)

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state when debugging an application that uses the VDK.

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG test

access port (TAP) on each JTAG DSP. Nonintrusive in-circuit

emulation is assured by the use of the processor’s JTAG inter-

face—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the DSP, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The DSP must be halted to send data and commands,

but once an operation has been completed by the emulator, the

DSP system is set running at full speed with no impact on sys-

tem timing.

VisualDSP++ Component Software Engineering (VCSE) is

Analog Devices’ technology for creating, using, and reusing

software components (independent modules of substantial

functionality) to quickly and reliably assemble software applica-

tions. It also is used for downloading components from the

Web, dropping them into the application, and publishing com-

ponent archives from within VisualDSP++. VCSE supports

component implementation in C/C++ or assembly language.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

Use the expert linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the DSP or external memory with a drag of

the mouse, and examine run-time stack and heap usage. The

expert linker is fully compatible with existing linker definition

file (LDF), allowing the developer to move between the graphi-

cal and textual environments.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC processor PC plug-in cards. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21266

architecture and functionality. For detailed information on the

ADSP-2126x family core architecture and instruction set, refer

to the ADSP-2126x SHARC DSP Core Manual and the

ADSP-21160 SHARC DSP Instruction Set Reference.

EVALUATION KIT

Analog Devices offers a range of EZ-KIT Lite^®†evaluation plat-

forms to use as a cost-effective method to learn more about

developing or prototyping applications with Analog Devices

^†EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

Rev. C

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October 2007

ADSP-21266

PIN FUNCTION DESCRIPTIONS

ADSP-21266 pin definitions are listed below. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-

tified as asynchronous (A) can be asserted asynchronously to

CLKIN (or to TCK for TRST). Tie or pull unused inputs to

DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI

and AD15–0 (NOTE: These pins have internal pull-up

resistors.)

The following symbols appear in the Type column of Table 3:

A = asynchronous, G = ground, I = input, O = output,

P = power supply, S = synchronous, (A/D) = active drive,

(O/D) = open-drain, and T = three-state.

V_DDEXTor GND, except for the following:

Table 3. Pin Descriptions

State During and

After Reset

Type

Function

AD15–0

I/O/T

Rev. 0.1 silicon—

AD15–0 pins are

driven low both

during and after

reset.

Parallel Port Address/Data. The ADSP-21266 parallel port and its corresponding

DMA unit output addresses and data for peripherals on these multiplexed pins. The

multiplex state is determined by the ALE pin. The parallel port can operate in either

8-bit or 16-bit mode. Each AD pin has a 22.5 kΩinternal pull-up resistor. See Address

Data Modes on Page 14 for details of the AD pin operation.

Rev. 0.2 silicon—

AD15–0 pins are

three-stated and

pulled high both

during and after

reset.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the

upper 16 external address bits, A23–8; ALE is used in conjunction with an external

latch to retain the values of the A23–8.

For 16-bit mode: ALE is automatically asserted whenever a change occurs in the

address bits, A15–0; ALE is used in conjunction with an external latch to retain the

values of the A15–0. To use these pins as flags (FLAG15–0), set (=1) Bit 20 of the

SYSCTL register and disable the parallel port. See Table 4 on Page 14 for a list of how

the AD15–0 pins map to the flag pins. When configured in the IDP_PDAP_CTL

register, the IDP Channel 0 can use these pins for parallel input data.

RD

O

Output only, driven Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or

high¹

16-bit data from an external memory device. When AD15–0 are flags, this pin

remains deasserted.

WR

ALE

Output only, driven Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or

high¹

16-bit data to an external memory device. When AD15–0 are flags, this pin remains

deasserted.

Output only, driven Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a

low¹

new address on the parallel port address pin. On reset, ALE is active high. However,

it can be reconfigured using software to be active low. When AD15–0 are flags, this

pin remains deasserted.

FLAG3–0

I/O/A

Three-state

Flag Pins. Each FLAG pin is configured via control bits as either an input or output.

As an input, it can be tested as a condition. As an output, it can be used to signal

external peripherals. These pins can be used as an SPI interface slave select output

during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP

signals.

In SPI master boot mode, FLAG0 is the slave select pin that must be connected to

an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When

Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.

When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.

When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.

When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which

indicates that the system timer has expired.

Rev. C

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October 2007

ADSP-21266

Table 3. Pin Descriptions (Continued)

State During and

Type

After Reset

Function

DAI_P20–1

I/O/T

Three-state with

programmable

pull-up

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.

The SRU configuration registers define the combination of on-chip peripheral

inputs or outputs connected to the pin and to the pin’s output enable. The config-

uration registers of these peripherals then determine the exact behavior of the pin.

Any input or output signal present in the SRU can be routed to any of these pins.

The SRU provides the connection from the serial ports, input data port, precision

clock generators, and timers to the DAI_P20–1 pins. These pins have internal

22.5 kΩpull-up resistors which are enabled on reset. These pull-ups can be disabled

in the DAI_PIN_PULLUP register.

SPICLK

I/O

Three-state with

pull-up enabled

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls

the rate at which data is transferred. The master may transmit data at a variety of

baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that

is active during data transfers, only for the length of the transferred word. Slave

devices ignore the serial clock if the slave select input is driven inactive (HIGH).

SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines.

The data is always shifted out on one clock edge and sampled on the opposite edge

of the clock. Clock polarity and clock phase relative to data are programmable into

the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ

internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins

are driven during reset. These pins are not three-stated during reset in SPI master

boot mode.

SPIDS

I

Input only

SerialPeripheralInterfaceSlaveDeviceSelect. Anactivelowsignalusedtoselect

the DSP as an SPI slave device. This input signal behaves like a chip select, and is

provided by the master device for the slave devices. In multimaster mode, the DSP’s

SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that

an error has occurred, as some other device is also trying to be the master device.

If asserted low when the device is in master mode, it is considered a multimaster

error. For a single master, multiple-slave configuration where flag pins are used, this

pin must be tied or pulled high to V_DDEXTon the master device. For ADSP-21266 to

ADSP-21266 SPI interaction, any of the master ADSP-21266’s flag pins can be used

to drive the SPIDS signal on the ADSP-21266 SPI slave device.

MOSI

MISO

I/O (O/D)

Three-state with

pull-up enabled

SPI Master Out Slave In. If the ADSP-21266 is configured as a master, the MOSI pin

becomes a data transmit (output) pin, transmitting output data. If the ADSP-21266

is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving

input data. In an ADSP-21266 SPI interconnection, the data is shifted out from the

MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s).

MOSI has a 22.5 kΩ internal pull-up resistor. If SPI master boot mode is selected,

MOSIandSPICLKpinsaredrivenduringreset.Thesepinsarenotthree-statedduring

reset in SPI master boot mode.

I/O (O/D)

Three-state with

pull-up enabled

SPI Master In Slave Out. If the ADSP-21266 is configured as a master, the MISO pin

becomes a data receive (input) pin, receiving input data. If the ADSP-21266 is

configured as a slave, the MISO pin becomes a data transmit (output) pin, trans-

mitting output data. In an ADSP-21266 SPI interconnection, the data is shifted out

from the MISO output pin of the slave and shifted into the MISO input pin of the

master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D

by setting the OPD bit in the SPICTL register.

Note:Onlyone slave isallowedtotransmitdataatanygiventime. Toenablebroadcast

transmission to multiple SPI slaves, the DSP’s MISO pin can be disabled by setting

(=1) Bit 5 (DMISO) of the SPICTL register.

BOOT_CFG1–0

I

Input only

Boot Configuration Select. Selects the boot mode for the DSP. The BOOT_CFG pins

must be valid before reset is asserted. See Table 5 on Page 14 for a description of

the boot modes.

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ADSP-21266

Table 3. Pin Descriptions (Continued)

State During and

Type

After Reset

Function

CLKIN

I

Input only

LocalClockIn. UsedinconjunctionwithXTAL. CLKINistheADSP-21266clockinput.

It configures the ADSP-21266 to use either its internal clock generator or an external

clocksource. Connecting thenecessary componentsto CLKINandXTALenablesthe

internal clock generator. Connecting the external clock to CLKIN while leaving XTAL

unconnected configures the ADSP-21266 to use the external clock source such as

an external clock oscillator. The core is clocked either by the PLL output or this clock

input depending on the CLK_CFG1–0 pin settings. CLKIN should not be halted,

changed, or operated below the specified frequency.

XTAL

O

I

Output only²

Input only

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

CLK_CFG1–0

Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 6

for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multi-

plier and divider in the PMCTL register at any time after the core comes out of reset.

RESETOUT/CLKOUT O

Output only

Input only

Input only³

Reset Out/Local Clock Out. Drives out the core reset signal to an external device.

CLKOUT can also be configured as a reset out pin (RESETOUT). The functionality can

be switched between the PLL output clock and reset out by setting Bit 12 of the

PMCTL register. The default is reset out.

RESET

I/A

Processor Reset. Resets the ADSP-21266 to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from the hardware reset vector address. The RESET input must

be asserted (low) at power-up.

TCK

TMS

TDI

I

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the ADSP-21266.

I/S

Three-state with

pull-up enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a

22.5 kΩ internal pull-up resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

Three-state with

pull-up enabled

Three-state⁴

TDO

TRST

O

Test Data Output (JTAG). Serial scan output of the boundary scan path.

I/A

Three-state with

pull-up enabled

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed

low) after power-up or held low for proper operation of the ADSP-21266. TRST has

a 22.5 kΩ internal pull-up resistor.

EMU

O (O/D)

Three-state with

pull-up enabled

Emulation Status. Must be connected to the ADSP-21266 Analog Devices DSP

Tools product line of JTAG emulators target board connector only. EMU has a

22.5 kΩ internal pull-up resistor.

V_DDINT

V_DDEXT

A_VDD

P

Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor

(13 pins on the BGA package, 32 pins on the LQFP package).

I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the

LQFP package).

Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL

(clock generator). This pin has the same specifications as V_DDINT, except that added

filtering circuitry is required. For more information, see Power Supplies on Page 8.

A_VSS

G

Analog Power Supply Return.

GND

Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

¹RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.

²Output only is a three-state driver with its output path always enabled.

³Input only is a three-state driver, with both output path and pull-up disabled.

⁴Three-state is a three-state driver, with pull-up disabled.

Rev. C

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October 2007

ADSP-21266

ADDRESS DATA PINS AS FLAGS

ADDRESS DATA MODES

To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the

SYSCTL register and disable the parallel port.

Table 7 shows the functionality of the AD pins for 8-bit and

16-bit transfers to the parallel port. For 8-bit data transfers, ALE

latches address bits A23–A8 when asserted, followed by address

bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit

data transfers, ALE latches address bits A15–A0 when asserted,

followed by data bits D15–D0 when deasserted.

Table 4. AD15–0 to FLAG Pin Mapping

AD Pin

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

Flag Pin

FLAG8

AD Pin

AD8

Flag Pin

FLAG0

FLAG1

FLAG2

FLAG3

FLAG4

FLAG5

FLAG6

FLAG7

Table 7. Address/Data Mode Selection

FLAG9

AD9

FLAG10

FLAG11

FLAG12

FLAG13

FLAG14

FLAG15

AD10

AD11

AD12

AD13

AD14

AD15

EP Data

Mode

AD7–0

Function

AD15–8

Function

ALE

8-bit

Asserted

Deasserted

Asserted

Deasserted

A15–8

D7–0

A7–0

D7–0

A23–16

A7–0

8-bit

16-bit

A15–8

D15–8

Boot Modes

Table 5. Boot Mode Selection

BOOT_CFG1–0

Booting Mode

SPI Slave Boot

00

01

10

11

SPI Master Boot

Parallel Port Boot via EPROM

Internal Boot Mode (ROM code only)

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

Table 6. Core Instruction Rate/CLKIN Ratio Selection

CLK_CFG1–0

Core to CLKIN Ratio

00

01

10

11

3:1

16:1

8:1

Reserved

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ADSP-21266

ADSP-21266 SPECIFICATIONS

OPERATING CONDITIONS

Parameter¹

Min

1.14

3.13

2.0

Max

1.26

3.47

Unit

V_DDINT

A_VDD

Internal (Core) Supply Voltage

V

Analog (PLL) Supply Voltage

V_DDEXT

V_IH

External (I/O) Supply Voltage

High Level Input Voltage²@ V_DDEXT= Max

Low Level Input Voltage²@ V_DDEXT= Min

High Level Input Voltage³@ V_DDEXT= Max

Low Level Input Voltage @ V_DDEXT= Min

Ambient Operating Temperature^{4, 5}

V_DDEXT+ 0.5 V

+0.8

V_DDEXT+ 0.5 V

V_IL

–0.5

1.74

–0.5

0

V

V_{IH_CLKIN}

V_{IL_CLKIN}

T_AMBK Grade

+1.19

+70

V

°C

¹Specifications subject to change without notice.

²Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.

³Applies to input pin CLKIN.

⁴See Thermal Characteristics on Page 38 for information on thermal specifications.

⁵See Engineer-to-Engineer Note (No. 216) for further information.

ELECTRICAL CHARACTERISTICS

Parameter¹

V_OH

Test Conditions

Min

Max

Unit

V

High Level Output Voltage²

Low Level Output Voltage²

High Level Input Current^{4, 5}

Low Level Input Current⁴

Low Level Input Current Pull-Up⁵

Three-State Leakage Current ^{6, 7, 8}

Three-State Leakage Current⁶

Three-State Leakage Current Pull-Up⁷

Supply Current (Internal)^{9, 10, 11}

Supply Current (Analog)¹¹

@ V_DDEXT= Min, I_OH= –1.0 mA³

@ V_DDEXT= Min, I_OL= 1.0 mA³

@ V_DDEXT= Max, V_IN= V_DDEXTMax

@ V_DDEXT= Max, V_IN= 0 V

2.4

V_OL

0.4

10

V

I_IH

μA

mA

pF

I_IL

10

I_ILPU

@ V_DDEXT= Max, V_IN= 0 V

200

10

I_OZH

@ V_DDEXT= Max, V_IN= V_DDEXTMax

@ V_DDEXT= Max, V_IN= 0 V

I_OZL

10

I_OZLPU

I_DD-INTYP

AI_DD

C_IN

@ V_DDEXT= Max, V_IN= 0 V

200

500

10

t_CCLK= 5.0 ns, V_DDINT= 1.2 V, T_AMB= +25°C

A_VDD= Max

Input Capacitance^{12, 13}

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 1.2 V

4.7

¹Specifications subject to change without notice.

²Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

³See Output Drive Currents on Page 37 for typical drive current capabilities.

⁴Applies to input pins: SPIDS, BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

⁵Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

⁶Applies to three-statable pins: FLAG3–0.

⁷Applies to three-statable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, MISO, MOSI.

⁸Applies to open-drain output pins: EMU, MISO, MOSI.

⁹Typical internal current data reflects nominal operating conditions.

¹⁰See Engineer-to-Engineer Note (No. 216) for further information.

¹¹Characterized, but not tested.

¹²Applies to all signal pins.

¹³Guaranteed, but not tested.

Rev. C

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Page 15 of 44

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October 2007

ADSP-21266

Table 9. Absolute Maximum Ratings

PACKAGE INFORMATION

The information presented in Figure 5 provides details about

the package branding for the ADSP-21266 processors. For a

complete listing of product availability, see Ordering Guide on

Page 44.

Parameter

Rating

Output Voltage Swing –0.5 V to V_DDEXT

Load Capacitance

+0.5 V

200 pF

Storage Temperature Range

Junction Temperature Under Bias

–65°C to +150°C

125°C

TIMING SPECIFICATIONS

a

ADSP-2126x

The ADSP-21266’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, serial ports, and parallel port (as required for read/write

strobes in asynchronous access mode). During reset, program

the ratio between the DSP’s internal clock frequency and exter-

nal (CLKIN) clock frequency with the CLK_CFG1–0 pins. To

determine switching frequencies for the serial ports, divide

down the internal clock, using the programmable divider con-

trol of each port (DIVx for the serial ports).

tppZ-cc

vvvvvv.x n.n

yyww country_of_origin

S

Figure 5. Typical Package Brand

Table 8. Package Brand Information

The ADSP-21266’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the DSP uses an internal phase-locked loop (PLL). This

PLL-based clocking minimizes the skew between the system

clock (CLKIN) signal and the DSP’s internal clock (the clock

source for the parallel port logic and I/O pads).

Brand Key

Field Description

Temperature Range

Package Type

t

pp

Z

RoHS Compliant Option (optional)

See Ordering Guide

Assembly Lot Code

Silicon Revision

cc

Figure 6 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the ADSP-2126x SHARC DSP Core

Manual.

vvvvvv.x

n.n

yyww

Date Code

ESD CAUTION

The VCO frequency is calculated as follows:

f

_VCO= 2 × PLLM × f_INPUT

where:

_VCO= VCO frequency.

PLLM = multiplier value programmed.

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

f

_INPUT= input frequency to the PLL.

_INPUT= CLKIN when the input divider is disabled.

_INPUT= CLKIN/2 when the input divider is enabled.

ABSOLUTE MAXIMUM RATINGS

Note the definitions of various clock periods shown in Table 10

which are a function of CLKIN and the appropriate ratio con-

trol shown in Table 11.

Stresses greater than those listed in Table 9 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

In Table 11, CCLK is defined as:

f

_CCLK= (2 × PLLM × f_INPUT) ÷ (2 × PLLN)

where:

_CCLK= CCLK frequency

f

Table 9. Absolute Maximum Ratings

PLLM = Multiplier value programmed

PLLN = Divider value programmed.

Parameter

Rating

Internal (Core) Supply Voltage (V_DDINT

)

–0.3 V to +1.4 V

–0.3 V to +3.8 V

+0.5 V

Analog (PLL) Supply Voltage (A_VDD

)

External (I/O) Supply Voltage (V_DDEXT

Input Voltage –0.5 V to V_DDEXT

)

Rev. C

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Page 16 of 44

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October 2007

ADSP-21266

Table 10. Clock Periods

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times.

Timing

Requirements

Description¹

t_CK

CLKIN Clock Period

t_CCLK

(Processor) Core Clock Period

Serial Port Clock Period = (t_CCLK) × SR

SPI Clock Period = (t_CCLK) × SPIR

See Figure 31 on Page 37 under Test Conditions for voltage

reference levels.

t_SCLK

t_SPICLK

¹where:

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

SR = serial port-to-core clock ratio (wide range, determined by SPORT

CLKDIV)

SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register)

SCLK = serial port clock

SPICLK = SPI clock

Switching characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Table 11. CLKOUT and CCLK Clock Generation Operation

Timing

Requirements

Description

Input Clock

Core Clock

Calculation

1/t_CK

CLKIN

CCLK

Variable, see equation

PLL

PLLI

CLKIN

BUF

CLK

CLKIN

DIVIDER

MCLK

LOOP

FILTER

PLL

DIVIDER

VCO

XTAL

DIVIDE

BY 2

PMCTL

CLK_CFGx/

PMCTL

CCLK

PLL

MULTIPLIER

PMCTL

CLK_CFGx/PMCTL

CLKOUT

RESETOUT

CLKOUT

BUF

DELAY OF

4096 CLKIN

CYCLES

RESETOUT

RESET

CORERST

Figure 6. Core Clock and System Clock Relationship to CLKIN

Rev. C

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Page 17 of 44

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October 2007

ADSP-21266

Power-Up Sequencing

The timing requirements for DSP startup are given in Table 12

and Figure 7.

Table 12. Power-Up Sequencing (DSP Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

t_IVDDEVDD

t_CLKVDD

t_CLKRST

RESET Low Before V_DDINT/V_DDEXTOn

V_DDINTOn Before V_DDEXT

CLKIN Valid After V_DDINT/V_DDEXTValid¹

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

0

ns

–50

0

10²

20³

200

ms

μs

t_PLLRST

μs

Switching Characteristic

4, 5

t_CORERST

DSP Core Reset Deasserted After RESET Deasserted

4096 × t_CK

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.2 V and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer’s data sheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles.

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4096 cycle count depends on t_SRSTspecification in Table 14. If setup time is not met, one additional CLKIN cycle can be added to the core reset time, resulting in 4097

cycles maximum.

RESET

t_RSTVDD

V

DDINT

t

IVDDEVDD

V

t_CLKVDD

DDEXT

CLKIN

t_CLKRST

CLK_CFG1–0

t_CORERST

t_PLLRST

*

RSTOUT

MULTIPLEXED WITH CLKOUT

*

Figure 7. Power-Up Sequencing

Rev. C

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Page 18 of 44

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October 2007

ADSP-21266

Clock Input

See Table 13 and Figure 8.

Table 13. Clock Input

150 MHz

Max

200 MHz

Max

Parameter

Unit

Min

Timing Requirements

t_CK

CLKIN Period

20¹

7.5¹

160²

80²

3

15¹

6¹

160²

80²

3

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V – 2.0 V)

CCLK Period³

6.66

10

5

10

¹Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.

²Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.

³Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

.

t_CK

CLKIN

t_CKH

t_CKL

Figure 8. Clock Input

Clock Signals

The ADSP-21266 can use an external clock or a crystal. See

CLKIN pin description. The programmer can configure the

ADSP-21266 to use its internal clock generator by connecting

the necessary components to CLKIN and XTAL. Figure 9 shows

the component connections used for a crystal operating in fun-

damental mode. Note that the 200 MHz clock rate is achieved

using a 12.5 MHz crystal and a PLL multiplier ratio 16:1

(CCLK:CLKIN).

CLKIN

XTAL

1M⍀

C1

C2

X1

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL

SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

Figure 9. 150 MHz or 200 MHz Operation with a 12.5 MHz

Fundamental Mode Crystal

Rev. C

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Page 19 of 44

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October 2007

ADSP-21266

Reset

See Table 14 and Figure 10.

Table 14. Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRST

t_SRST

RESET Pulse Width Low¹

4 × t_CK

8

ns

RESET Setup Before CLKIN Low

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_WRST

t_SRST

RESET

Figure 10. Reset

Interrupts

The timing specification in Table 15 and Figure 11 applies to the

FLAG0, FLAG1, and FLAG2 pins when they are configured as

IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1

pins when configured as interrupts.

Table 15. Interrupts

Parameter

Min

2 t_CCLK+2

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

ns

DAI_P20–1

(FLG2–0)

(IRQ2–0)

t_IPW

Figure 11. Interrupts

Core Timer

The timing specification in Table 16 and Figure 12 applies to

FLAG3 when it is configured as the core timer (CTIMER).

Table 16. Core Timer

Parameter

Min

Max

Unit

ns

Switching Characteristic

t_WCTIM

CTIMER Pulse Width

4 × t_CCLK– 1

FLG 3

(C TIM ER)

t_{W C T IM}

Figure 12. Core Timer

Rev. C

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Page 20 of 44

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October 2007

ADSP-21266

Timer PWM_OUT Cycle Timing

The timing specification in Table 17 and Figure 13 applies to

Timer in PWM_OUT (pulse-width modulation) mode. Timer

signals are routed to the DAI_P20–1 pins through the SRU.

Therefore, the timing specifications provided below are valid at

the DAI_P20–1 pins.

Table 17. Timer PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

t_PWMO

Timer Pulse Width Output

2 × t_CCLK– 1

2(2³¹– 1) × t_CCLK

ns

t_PWMO

DAI_P20–1

(TIMER)

Figure 13. Timer PWM_OUT Timing

Timer WDTH_CAP Timing

The timing specification in Table 18 and Figure 14 applies to

Timer in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 18. Timer Width Capture Timing

Parameter

Min

2 × t_CCLK

Max

Unit

Timing Requirement

t_PWI

Timer Pulse Width

2(2³¹– 1) × t_CCLK

ns

t_PWI

DAI_P20–1

(TIMER)

Figure 14. Timer Width Capture Timing

Rev. C

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Page 21 of 44

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October 2007

ADSP-21266

DAI Pin-to-Pin Direct Routing

See Table 19 and Figure 15 for direct pin connections only (for

example, DAI_PB01_I to DAI_PB02_O).

Table 19. DAI Pin-to-Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI Pin Input Valid to DAI Output Valid

1.5

10

ns

DAI_Pn

DAI_Pm

t_DPIO

Figure 15. DAI Pin-to-Pin Direct Routing

Rev. C

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Page 22 of 44

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October 2007

ADSP-21266

cases where the PCG’s inputs and outputs are not directly

Precision Clock Generator (Direct Pin Routing)

routed to/from DAI pins (via pin buffers), there is no timing

data available. All timing parameters and switching characteris-

tics apply to external DAI pins (DAI_P07 – DAI_P20).

The timing in Table 20 and Figure 16 is valid only when the

SRU is configured such that the precision clock generator

(PCG) takes its inputs directly from the DAI pins (via pin buff-

ers) and sends its outputs directly to the DAI pins. For the other

Table 20. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIW

t_STRIG

t_HTRIG

Input Clock Pulse Width

20

2

ns

PCG Trigger Setup Before Falling Edge of PCG Input Clock

PCG Trigger Hold After Falling Edge of PCG Input Clock

2

Switching Characteristics

t_DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After PCG Input

Clock Falling Edge

2.5

10

ns

t_DTRIG

PCG Output Clock and Frame Sync Delay After PCG Trigger

Output Clock Pulse Width

2.5 + 2.5 × t_PCGOW10 + 2.5 × t_PCGOWns

40 ns

t_PCGOW

t_STRIG

DAI_Pn

PCG_TRIGx_I

t_HTRIG

t_PCGIW

DAI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

DAI_Py

PCG_CLKx_O

t_PCGOW

DAI_Pz

PCG_FSx_O

t_DTRIG

Figure 16. Precision Clock Generator (Direct Pin Routing)

Rev. C

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Page 23 of 44

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October 2007

ADSP-21266

Flags

The timing specifications in Table 21 and Figure 17 apply to the

FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial

peripheral interface. See Table 3 on Page 11 for more informa-

tion on flag use.

Table 21. Flags

Parameter

Min

Max

Unit

Timing Requirement

t_FIPW

FLAG3–0 IN Pulse Width

2 × t_CCLK+ 3

ns

Switching Characteristic

t_FOPWFLAG3–0 OUT Pulse Width

2 × t_CCLK– 1

ns

DAI_P20–1

(FLAG3–0_IN

)

(AD15–0)

t_FIPW

DAI_P20–1

(FLAG3–0_OUT

)

(AD15–0)

t_FOPW

Figure 17. Flags

Rev. C

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Page 24 of 44

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October 2007

ADSP-21266

Memory Read—Parallel Port

The specifications in Table 22, Table 23, Figure 18, and

Figure 19 are for asynchronous interfacing to memories (and

memory-mapped peripherals) when the ADSP-21266 is access-

ing external memory space.

Table 22. 8-Bit Memory Read Cycle

Parameter

Min

Max

Unit

Timing Requirements

t_DRS

t_DRH

t_DAD

Address/Data 7–0 Setup Before RD High

Address/Data 7–0 Hold After RD High

Address 15–8 to Data Valid

3.3

0

ns

D + 0.5 × t_CCLK– 3.5

ns

Switching Characteristics

t_ALEW

ALE Pulse Width

2 × t_CCLK– 2

ns

t_ALERW

ALE Deasserted to Read/Write Asserted

Address/Data 15–0 Setup Before ALE Deasserted

Address/Data 15–0 Hold After ALE Deasserted

ALE Deasserted to Address/Data7–0 in High-Z

RD Pulse Width

1 × t_CCLK– 0.5

2.5 × t_CCLK– 2.0

0.5 × t_CCLK– 0.8

D – 2

1

t_ADAS

t

_ADAH1

1

t_ALEHZ

t_RW

0.5 × t_CCLK+ 2.0

t_ADRH

Address/Data 15–8 Hold After RD High

0.5 × t_CCLK– 1 + H

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

¹On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE

t_ALEW

t_ALERW

t_RW

RD

WR

t_ALEHZ

t_ADAH

t_ADAS

t_ADRH

AD15-8

VALID ADDRESS

t_DRS

t_DRH

AD7-0

VALID DATA

t_DAD

Figure 18. 8-Bit Memory Read Cycle

Rev. C

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Page 25 of 44

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October 2007

ADSP-21266

Table 23. 16-Bit Memory Read Cycle

Parameter

Min

Max

Unit

Timing Requirements

t_DRS

t_DRH

Address/Data 15–0 Setup Before RD high

3.3

0

ns

Address/Data 15–0 Hold After RD high

Switching Characteristics

ns

t_ALEW

ALE Pulse Width

2 × t_CCLK– 2

1 × t_CCLK– 0.5

2.5 × t_CCLK– 2.0

0.5 × t_CCLK– 0.8

D – 2

t_ALERW

ALE Deasserted to Read/Write Asserted

Address/Data 15–0 Setup Before ALE Deasserted

Address/Data 15–0 Hold After ALE Deaserted

ALE Deasserted to Address/Data 15–0 in High-Z

RD Pulse Width

1

t_ADAS

t

_ADAH1

1

t_ALEHZ

t_RW

0.5 × t_CCLK+ 2.0 ns

ns

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

¹On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE

t_ALEW

t_ALERW

RD

t_RW

WR

t_ADAH

t_DRS

t_DRH

t_ADAS

VALID ADDRESS

VALID DATA

AD15-0

t_ALEHZ

Figure 19. 16-Bit Memory Read Cycle

Rev. C

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Page 26 of 44

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October 2007

ADSP-21266

Memory Write—Parallel Port

Use the specifications in Table 24, Table 25, Figure 20, and

Figure 21 for asynchronous interfacing to memories (and

memory-mapped peripherals) when the ADSP-21266 is access-

ing external memory space.

Table 24. 8-Bit Memory Write Cycle

Parameter

Min

Max

Unit

Switching Characteristics

t_ALEW

ALE Pulse Width

2 × t_CCLK– 2

1 × t_CCLK– 0.5

2.5 × t_CCLK– 2.0

0.5 × t_CCLK– 0.8

D – 2

ns

t_ALERW

ALE Deasserted to Read/Write Asserted

Address/Data 15–0 Setup Before ALE Deasserted

Address/Data 15–0 Hold After ALE Deasserted

WR Pulse Width

1

t_ADAS

1

t_ADAH

t_WW

t_ADWL

t_ADWH

t_ALEHZ

t_DWS

Address/Data 15–8 to WR Low

0.5 × t_CCLK– 1.5

0.5 × t_CCLK– 1 + H

0.5 × t_CCLK– 0.8

D

Address/Data 15–8 Hold After WR High

ALE Deasserted to Address/Data 15–0 in High-Z

Address/Data 7–0 Setup Before WR High

Address/Data 7–0 Hold After WR High

Address/Data to WR High

0.5 × t_CCLK+ 2.0 ns

ns

t_DWH

t_DAWH

0.5 × t_CCLK– 1.5 + H

D

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

¹On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

t_ALERW

ALE

t_ALEW

t_DAWH

WR

t_WW

RD

t_ALEHZ

t_ADAH

t_ADWL

t_ADWH

t_ADAS

AD15-8

VALID ADDRESS

t_DWS

t_DWH

VALID ADDRESS

VALID DATA

AD7-0

Figure 20. 8-Bit Memory Write Cycle

Rev. C

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Page 27 of 44

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October 2007

ADSP-21266

Table 25. 16-Bit Memory Write Cycle

Parameter

Min

Max

Unit

Switching Characteristics

t_ALEW

ALE Pulse Width

2 × t_CCLK– 2

1 × t_CCLK– 0.5

2.5 × t_CCLK– 2.0

0.5 × t_CCLK– 0.8

D – 2

ns

t_ALERW

ALE Deasserted to Read/Write Asserted

Address/Data 15–0 Setup Before ALE Deasserted

Address/Data 15–0 Hold After ALE Deasserted

WR Pulse Width

1

t_ADAS

1

t_ADAH

t_WW

t

_ALEHZ1

t_DWS

t_DWH

ALE Deasserted to Address/Data 15–0 in High-Z

Address/Data 15–0 Setup Before WR High

Address/Data 15–0 Hold After WR High

0.5 × t_CCLK– 0.8

D

0.5 × t_CCLK+ 2.0 ns

ns

0.5 × t_CCLK– 1.5 + H

D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t_CCLK

H = t_CCLK(if a hold cycle is specified, else H = 0)

¹On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

ALE

t_ALEW

t_ALERW

t_WW

WR

RD

t_ALEH

t_ADAS

t_ADAH

t_DWS

t_DWH

VALID ADDRESS

AD15-0

VALID DATA

Figure 21. 16-Bit Memory Write Cycle

Rev. C

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Page 28 of 44

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October 2007

ADSP-21266

Serial port signals (SCLK, FS, DxA,/DxB) are routed to the

Serial Ports

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

To determine whether communication is possible between two

devices at given clock speed, the specifications in Table 26,

Table 27, Table 28, Table 29, Figure 22, and Figure 23 must be

confirmed: 1) frame sync delay and frame sync setup and hold;

2) data delay and data setup and hold; and 3) SCLK width.

Table 26. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSE

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)¹

2.5

ns

t_HFSE

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)¹

2.5

7

ns

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

Receive Data Setup Before Receive SCLK¹

Receive Data Hold After SCLK¹

SCLK Width

SCLK Period

20

Switching Characteristics

t_DFSE

FS Delay After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)²

7

ns

t_HOFSE

FS Hold After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)²

2

ns

t_DDTE

t_HDTE

Transmit Data Delay After Transmit SCLK²

Transmit Data Hold After Transmit SCLK²

¹Referenced to sample edge.

²Referenced to drive edge.

Table 27. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSI

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)¹

6

ns

t_HFSI

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)¹

1.5

6

ns

t_SDRI

t_HDRI

Receive Data Setup Before SCLK¹

Receive Data Hold After SCLK¹

1.5

Switching Characteristics

t_DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)²

3

ns

t_HOFSI

t_DFSI

t_HOFSI

t_DDTI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)²

FS Delay After SCLK (Internally Generated FS in Receive Mode)²

FS Hold After SCLK (Internally Generated FS in Receive Mode)²

Transmit Data Delay After SCLK²

–1.0

3

t_HDTI

Transmit Data Hold After SCLK²

–1.0

t_SCLKIW

Transmit or Receive SCLK Width

0.5t_SCLK– 2

0.5t_SCLK+ 2

¹Referenced to the sample edge.

²Referenced to drive edge.

Rev. C

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Page 29 of 44

|

October 2007

ADSP-21266

Table 28. Serial Ports—Enable and Three-State

Parameter

Min

2

Max

Unit

Switching Characteristics

t_DDTEN

t_DDTTE

t_DDTIN

Data Enable from External Transmit SCLK¹

Data Disable from External Transmit SCLK¹

Data Enable from Internal Transmit SCLK¹

ns

7

–1

¹Referenced to drive edge.

Table 29. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

t_DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS

with MCE = 1, MFD = 0¹

7

ns

t_DDTENFS

Data Enable for MCE = 1, MFD = 0¹

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20-1

(SCLK)

t_SFSE/I

t_HFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

SAMPLE DRIVE

DRIVE

DAI_P201

(SCLK)

t_SFSE/I

t_HFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P[20:1] PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.

Figure 22. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified sample pair mode.

Rev. C

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Page 30 of 44

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October 2007

ADSP-21266

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HFSE

t_HFSI

t_SFSI

t_SFSE

t_HOFSI

t_HOFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_HDRE

t_SDRI

t_HDRI

t_SDRE

DAI_P20–1

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HFSI

t_HOFSI

t_SFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_DDTE

t_DDTI

t_HDTE

t_HDTI

DAI_P20–1

(DATA CHANNEL A/B)

DAI_P20–1

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

DAI_P20–1

SCLK (EXT)

SCLK

t_DDTEN

t_DDTTE

DAI_P20–1

(DATA CHANNEL A/B)

DRIVE EDGE

DAI_P20–1

SCLK (INT)

t_DDTIN

DAI_P20–1

(DATA CHANNEL A/B)

Figure 23. Serial Ports

Rev. C

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Page 31 of 44

|

October 2007

ADSP-21266

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 30 and

Figure 24. IDP Signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Table 30. Input Data Port (IDP)

Parameter

Min

Max

Unit

Timing Requirements

t_SISFS

FS Setup Before SCLK Rising Edge¹

FS Hold After SCLK Rising Edge¹

SData Setup Before SCLK Rising Edge¹

SData Hold After SCLK Rising Edge¹

Clock Width

2.5

7

ns

t_SIHFS

t_SISD

t_SIHD

t_IDPCLKW

t_IDPCLK

Clock Period

20

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either

CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IDPCLKW

DAI_P20–1

(SCLK)

t_SIHFS

t_SISFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 24. Input Data Port (IDP)

Rev. C

|

Page 32 of 44

|

October 2007

ADSP-21266

Note that the most significant 16 bits of external PDAP data can

be provided through either the parallel port AD15–0 or the

DAI_P20–5 pins. The remaining four bits can only be sourced

through DAI_P4–1. The timing below is valid at the

DAI_P20–1 pins or at the AD15–0 pins.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in Table 31

and Figure 25. PDAP is the parallel mode operation of

Channel 0 of the IDP. For details on the operation of the IDP,

see the IDP chapter of the ADSP-2126x Peripherals Manual.

Table 31. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

t_SPCLKEN

t_HPCLKEN

t_PDSD

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge¹

PDAP_CLKEN Hold After PDAP_CLK Sample Edge¹

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge¹

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge¹

Clock Width

2.5

7

ns

t_PDHD

t_PDCLKW

t_PDCLK

Clock Period

20

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

2 × t_CCLK

ns

1 × t_CCLK– 1

1

Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20–1

(PDAP_CLK)

t_SPCLKEN

t_HPCLKEN

DAI_P20–1

(PDAP_CLKEN)

t_PDSD

t_PDHD

DATA

DAI_P20–1

(PDAP_STROBE)

t_PDSTRB

t_PDHLDD

Figure 25. Parallel Data Acquisition Port (PDAP)

Rev. C

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Page 33 of 44

|

October 2007

ADSP-21266

SPI Interface Protocol—Master

Table 32. SPI Interface Protocol—Master

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

5

2

ns

Switching Characteristics

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × t_CCLK

ns

Serial Clock High Period

4 × t_CCLK– 2

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

FLAG3–0 OUT (SPI Device Select) Low to First SPICLK Edge

Last SPICLK Edge to FLAG3–0 OUT High

Sequential Transfer Delay

3

10

4 × t_CCLK– 2

4 × t_CCLK– 1

t_SPITDM

FLG3-0

(OUTPUT)

t_{SD SCIM}

t_{SPICH M}

t_{SPIC LM}

t_SPICHM

t_DDSPIDM

t_{SPIC LK M}

t_HDSM

t_SPITDM

SPICLK

(CP = 0)

(OUTPUT)

t_{SPIC LM}

SPICLK

(CP = 1)

(OUTPUT)

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_{SSPID M}

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

MSB

LSB

(INPUT)

VALID

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

t_{H SPID M}

CPHASE = 0

MSB

VALID

LSB

VALID

MISO

(INPUT)

Figure 26. SPI Interface Protocol—Master

Rev. C

|

Page 34 of 44

|

October 2007

ADSP-21266

SPI Interface Protocol—Slave

Table 33. SPI Interface Protocol—Slave

Parameter

Min

Max

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial Clock Cycle

4 × t_CCLK

ns

Serial Clock High Period

Serial Clock Low Period

2 × t_CCLK– 2

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t_CCLK+ 1

ns

t_HDS

Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE = 0)

2 × t_CCLK

ns

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_CCLK

Switching Characteristics

t_DSOE

SPIDS Assertion to Data Out Active

0

5

ns

t_DSDHI

t_DDSPIDS

t_HDSPIDS

t_DSOV

SPIDS Deassertion to Data High Impedance

5

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE = 0)

7.5

2 × t_CCLK– 2

5 × t_CCLK+ 2

ns

SPIDS

(INPUT)

t_{SPIC HS}

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0)

(INPUT)

t_SPICLS

t_SDSCO

t_SPICHS

SPICLK

(CP = 1)

(INPUT)

t_DSDHI

t_HDSPIDS

t_DDSPIDS

t_DSOE

t_DDSPIDS

MISO

(OUTPUT)

MSB

LSB

t_HSPIDS

CPHASE = 1

t_SSPIDS

MOSI

(INPUT)

LSB VALID

MSB VALID

t_DSOV

t_{DSO E}

t_HDSPIDS

t_DDSPIDS

t_DSDHI

MISO

(OUTPUT)

LSB

MSB

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

(INPUT)

MSB VALID

LSB VALID

Figure 27. SPI Interface Protocol—Slave

Rev. C

|

Page 35 of 44

|

October 2007

ADSP-21266

JTAG Test Access Port and Emulation

Table 34. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

20

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High¹

System Inputs Hold After TCK High¹

TRST Pulse Width

5

6

7

8

4 × t_CK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low²

7

ns

10

¹System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

²System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 28. JTAG Test Access Port and Emulation

Rev. C

|

Page 36 of 44

|

October 2007

ADSP-21266

OUTPUT DRIVE CURRENTS

CAPACITIVE LOADING

Figure 29 shows typical I-V characteristics for the output driv-

ers of the ADSP-21266. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 30). Figure 33 shows graphically

how output delays and holds vary with load capacitance (note

that this graph or derating does not apply to output disable

delays). The graphs of Figure 32, Figure 33, and Figure 34 may

not be linear outside the ranges shown for Typical Output Delay

vs. Load Capacitance and Typical Output Rise Time (20%–80%,

V = Min) vs. Load Capacitance.

40

V

OH

30

20

3.3V, 25°C

3.47V, –45°C

10

0

12

10

3.11V, 125°C

RISE

–10

y = 0.0467x + 1.6323

FALL

3.11V, 125°C

8

–20

3.3V, 25°C

3.5

V

–30

–40

OL

6

3.47V, –45°C

0

0.5

1

1.5

2

2.5

3

4

SWEEP (V

) VOLTAGE (V)

y = 0.045x + 1.524

DDEXT

2

0

Figure 29. Typical Drive

TEST CONDITIONS

50

100

150

200

250

0

LOAD CAPACITANCE (pF)

The ac signal specifications (timing parameters) appear in

Table 13 on Page 19 through Table 34 on Page 36. These include

output disable time, output enable time, and capacitive loading.

Figure 32. Typical Output Rise Time

(20%–80%, V_DDEXT= Max)

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 31. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

12

10

RISE

y = 0.049x + 1.5105

FALL

50⍀

8

6

4

2

0

TO

OUTPUT

1.5V

y = 0.0482x + 1.4604

30pF

Figure 30. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

INPUT

OR

OUTPUT

1.5V

Figure 33. Typical Output Rise/Fall Time

(20%–80%, V_DDEXT= Min)

Figure 31. Voltage Reference Levels for AC Measurements

Rev. C

|

Page 37 of 44

|

October 2007

ADSP-21266

where:

T_A= ambient temperature ^×C

10

8

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heat sink is required.

Y = 0.0488X – 1.5923

6

4

Table 35. Thermal Characteristics for 136-Ball BGA

Parameter

θ_JA

θ_JMA

θ_JC

Ψ_JT

Ψ_JMT

Condition

Typical

31.0

Unit

°C/W

2

0

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

27.3

26.0

6.99

–2

–4

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.16

0.30

0

50

100

150

200

0.35

LOAD CAPACITANCE (pF)

Table 36. Thermal Characteristics for 144-Lead LQFP

Figure 34. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

Parameter

θ_JA

Typical

32.5

28.9

27.8

7.8

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

ENVIRONMENTAL CONDITIONS

θ_JMA

θ_JC

The ADSP-21266 processor is rated for performance under

T

_AMBenvironmental conditions specified in the Operating Con-

ditions on Page 15.

Ψ_JT

Ψ_JMT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.5

0.8

THERMAL CHARACTERISTICS

1.0

Table 35 and Table 36 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. The junction-to-

case measurement complies with MIL-STD-883. All measure-

ments use a 2S2P JEDEC test board.

To determine the junction temperature of the device while on

the application PCB, use

T = T

+ (Ψ × P )

JT D

J

CASE

where:

T_J= junction temperature (^×C)

T

_CASE= case temperature (^×C) measured at the top center of the

package

Ψ_JT= junction-to-top (of package) characterization parameter is

the typical value from Table 35 and Table 36 (YJMT indicates

moving air).

P_D= power dissipation (see EE Note No. 216)

Values of θ_JAare provided for package comparison and PCB

design considerations (θJMA indicates moving air). θ_JAcan be

used for a first order approximation of T_Jby the equation

T = T + (θ × P )

J

A

JA

D

Rev. C

|

Page 38 of 44

|

October 2007

ADSP-21266

144-LEAD LQFP PIN CONFIGURATIONS

Table 37 shows the ADSP-21266’s pin names and their default

function after reset (in parentheses).

Table 37. 144-Lead LQFP Pin Assignments

LQFP

Pin Name

V_DDINT

CLK_CFG0

CLK_CFG1

BOOT_CFG0

BOOT_CFG1

GND

Pin No.

Pin Name

V_DDINT

GND

Pin No.

Pin Name

V_DDEXT

Pin No.

Pin Name

GND

Pin No.

1

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

73

74

75

76

77

78

79

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

2

GND

V_DDINT

GND

3

RD

V_DDINT

4

ALE

GND

V_DDINT

GND

5

AD15

AD14

AD13

GND

DAI_P10 (SD2B)

DAI_P11 (SD3A)

DAI_P12 (SD3B)

6

V_DDINT

GND

V_DDEXT

GND

7

8

DAI_P13 (SCLK23) 80

V_DDEXT

GND

V_DDINT

GND

9

V_DDEXT

AD12

V_DDINT

GND

DAI_P14 (SFS23)

DAI_P15 (SD4A)

V_DDINT

81

82

83

84

85

86

87

88

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

V_DDINT

GND

V_DDINT

GND

V_DDINT

RESET

SPIDS

GND

V_DDINT

GND

AD11

AD10

AD9

GND

DAI_P16 (SD4B)

DAI_P17 (SD5A)

DAI_P18 (SD5B)

FLAG0

FLAG1

AD7

AD8

V_DDINT

SPICLK

MISO

MOSI

GND

DAI_P1 (SD0A) 53

DAI_P19 (SCLK45) 89

GND

V_DDINT

GND

54

55

V_DDINT

GND

90

V_DDINT

GND

91

DAI_P2 (SD0B) 56

DAI_P3 (SCLK0) 57

GND

92

V_DDEXT

GND

V_DDEXT

DAI_P20 (SFS45)

GND

93

V_DDINT

V_DDEXT

A_VDD

GND

V_DDEXT

V_DDINT

GND

58

59

60

61

94

V_DDINT

AD6

95

V_DDINT

FLAG2

FLAG3

V_DDINT

GND

96

A_VSS

AD5

97

GND

AD4

DAI_P4 (SFS0) 62

DAI_P5 (SD1A) 63

DAI_P6 (SD1B) 64

DAI_P7 (SCLK1) 65

98

CLKOUT/RESETOUT 134

V_DDINT

GND

99

EMU

TDO

TDI

135

136

137

138

139

140

141

142

143

144

100

101

102

103

104

105

106

107

108

AD3

V_DDINT

GND

AD2

V_DDINT

GND

V_DDINT

GND

66

67

68

69

TRST

TCK

V_DDEXT

GND

V_DDINT

GND

TMS

GND

CLKIN

XTAL

V_DDEXT

AD1

V_DDINT

GND

AD0

DAI_P8 (SFS1) 70

DAI_P9 (SD2A) 71

WR

V_DDINT

72

Rev. C

|

Page 39 of 44

|

October 2007

ADSP-21266

136-BALL BGA PIN CONFIGURATIONS

Table 38 shows the ADSP-21266’s pin names and their default

function after reset (in parentheses). Figure 35 on Page 42

shows the BGA package pin assignments.

Table 38. 136-Ball BGA Pin Assignments

BGA Pin

No.

BGA Pin

No.

BGA Pin

No.

Pin Name

CLK_CFG0

XTAL

Pin Name

CLK_CFG1

GND

No.

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

F01

F02

F04

F05

F06

F09

F10

F11

F13

F14

Pin Name

BOOT_CFG1

BOOT_CFG0

GND

Pin Name

V_DDINT

GND

A01

A02

A03

A04

A05

C01

C02

C03

C12

C13

C14

D01

D02

D04

D05

D06

D09

D10

D11

D13

D14

TMS

V_DDEXT

CLKIN

TRST

GND

TCK

GND

TDI

GND

CLKOUT/RESETOUT A06

A_VSS

V_DDINT

GND

TDO

A07

A08

A09

A10

A11

A12

A13

A14

E01

E02

E04

E05

E06

E09

E10

E11

E13

E14

A_VDD

GND

EMU

MOSI

MISO

SPIDS

V_DDINT

GND

V_DDINT

GND

FLAG3

V_DDEXT

SPICLK

RESET

V_DDINT

GND

V_DDINT

GND

FLAG1

FLAG0

GND

AD7

G01

G02

G13

G14

AD6

H01

H02

H13

H14

V_DDINT

V_DDEXT

DAI_P18 (SD5B)

DAI_P17 (SD5A)

GND

DAI_P19 (SCLK45)

GND

FLAG2

DAI_P20 (SFS45)

Rev. C

|

Page 40 of 44

|

October 2007

ADSP-21266

Table 38. 136-Ball BGA Pin Assignments (Continued)

BGA Pin

No.

BGA Pin

No.

BGA Pin

No.

BGA Pin

No.

Pin Name

AD5

Pin Name

AD3

Pin Name

AD2

Pin Name

AD0

J01

K01

K02

K04

K05

K06

K09

K10

K11

K13

K14

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

L01

L02

L04

L05

L06

L09

L10

L11

L13

L14

M01

M02

M03

M12

AD4

J02

V_DDINT

AD1

WR

GND

J04

GND

J05

GND

J06

GND

DAI_P12 (SD3B)

M13

M14

GND

J09

GND

DAI_P13 (SCLK23)

GND

J10

GND

J11

GND

V_DDINT

J13

GND

DAI_P16 (SD4B)

AD15

J14

DAI_P15 (SD4A)

AD14

DAI_P14 (SFS23)

N01

N02

N03

N04

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

ALE

AD13

RD

AD12

V_DDINT

AD11

V_DDEXT

AD10

AD8

AD9

V_DDINT

DAI_P1 (SD0A)

DAI_P3 (SCLK0)

DAI_P5 (SD1A)

DAI_P6 (SD1B)

DAI_P7 (SCLK1)

DAI_P8 (SFS1)

DAI_P9 (SD2A)

DAI_P11 (SD3A)

DAI_P2 (SD0B)

V_DDEXT

DAI_P4 (SFS0)

V_DDINT

GND

DAI_P10 (SD2B)

Rev. C

|

Page 41 of 44

|

October 2007

ADSP-21266

14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

KEY

V_DDINT

V_DDEXT

A_VDD

I/O SIGNALS

GND

A_VSS

*

USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED

CIRCUIT BOARD’S GROUND PLANE.

Figure 35. 136-Ball BGA Pin Assignments (Bottom View, Summary)

Rev. C

|

Page 42 of 44

|

October 2007

ADSP-21266

PACKAGE DIMENSIONS

The ADSP-21266 is available in a 136-ball BGA package and a

144-lead LQFP package shown in Figure 37 and Figure 36.

22.20

22.00 SQ

21.80

0.75

0.60

0.45

1.60

MAX

109

144

1

108

PIN 1

20.20

20.00 SQ

19.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.15

0.05

73

36

SEATING

PLANE

0.08

72

37

COPLANARITY

0.27

0.22

0.17

VIEW A

0.50

BSC

VIEW A

LEAD PITCH

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BFB

Figure 36. 144-Lead LQFP (ST-144)

A1 CORNER

INDEX AREA

12.10

12.00 SQ

11.90

13

11

9

7

5

3

1

14

12

10

8

6

4

2

A

B

C

D

E

F

BALL A1

INDICATOR

10.40

BSC SQ

TOP VIEW

G

J

BOTTOM VIEW

0.80 BSC

H

K

L

M

N

P

DETAIL A

1.70 MAX

1.31

1.21

1.10

DETAIL A

0.25 MIN

0.12 MAX

COPLANARITY

*

0.50

0.45

0.40

SEATING

PLANE

BALL DIAMETER

*

COMPLIANT WITH JEDEC STANDARDS MO-205-AE

WITH EXCEPTION TO BALL DIAMETER.

Figure 37. 136-Ball CSP_BGA (BC-136)

Rev. C

|

Page 43 of 44

|

October 2007

ADSP-21266

SURFACE-MOUNT DESIGN

Table 39 is provided as an aide to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements

for Surface-Mount Design and Land Pattern Standard.

Table 39. BGA_ED Data for Use with Surface-Mount Design

Package

Ball Attach Type

Solder Mask Opening

Ball Pad Size

136-Lead CSP_BGA (BC-136)

Solder Mask Defined (SMD)

0.4 mm

0.53 mm

ORDERING GUIDE

Analog Devices offers a wide variety of audio algorithms and combinations to run on the ADSP-21266 DSP. For a complete list, visit our

website at www.analog.com/SHARC.

Temperature Instruction On-Chip

Operating

Voltage

Package

Description

Package

Option

Model^{1, 2, 3}

Range⁴

Rate

SRAM

2M bit

ROM

ADSP-21266SKSTZ-1B

ADSP-21266SKSTZ-2B

ADSP-21266SKBCZ-2B

ADSP-21266SKSTZ-1C

ADSP-21266SKSTZ-2C

ADSP-21266SKBCZ-2C

ADSP-21266SKSTZ-1D

ADSP-21266SKSTZ-2D

ADSP-21266SKBCZ-2D

¹Z = RoHS Compliant Part.

0°C to +70°C

150 MHz

200 MHz

150 MHz

200 MHz

150 MHz

200 MHz

4M bit

1.2 INT/3.3 EXT V 144-Lead LQFP

1.2 INT/3.3 EXT V 136-Ball CSP_BGA

1.2 INT/3.3 EXT V 144-Lead LQFP

1.2 INT/3.3 EXT V 136-Ball CSP_BGA

1.2 INT/3.3 EXT V 144-Lead LQFP

1.2 INT/3.3 EXT V 136-Ball CSP_BGA

ST-144

BC-136

ST-144

BC-136

ST-144

BC-136

²B at end of part number indicates Rev. 0.1 silicon. See Table 2 on Page 6 for multichannel surround-sound decoder algorithms in on-chip B ROM.

³C and D at end of part number indicate Rev. 0.2 silicon. See Table 2 on Page 6 for multichannel surround-sound decoder algorithms in on-chip C and D ROM.

⁴Referenced temperature is ambient temperature.

registered trademarks are the property of their respective owners.

D03758-0-10/07(C)

Rev. C

|

Page 44 of 44

|

October 2007


型号：	ADSP-21266_07
厂家：	ADI
描述：	Embedded Processor 嵌入式处理器
文件：	总44页 (文件大小：548K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21266_07 [ADI]

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