ADSP-21465W_技术文档

SHARC Processor

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Code compatible with all other members of the SHARC family

The ADSP-21462W/ADSP-21465W/ADSP-21467 are available

SUMMARY

Note: This datasheet is preliminary. This document contains

material that is subject to change without notice.

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

with unique audiocentric peripherals such as the digital

applications interface, DTCP (digital transmission content

protection protocol), serial ports, precision clock genera-

tors, S/PDIF transceiver, asynchronous sample rate

converters, input data port, and more.

For complete ordering information, see Automotive Prod-

ucts on Page 59 and Ordering Guide on Page 59.

On-chip memory—5 Mbits of on-chip RAM, 4 Mbits of on-chip

ROM

Automotive applications—the ADSP-21462W and the ADSP-

21465W are available exclusively as automotive products

CORE PROCESSOR

THERMAL

PLL

DIODE

4 BLOCKS OF

ON-CHIP MEMORY

INSTRUCTION

JTAGTEST & EMULATION

EXTERNAL PORT

CACHE

32 48-BIT

TIMER

x

5M BIT RAM

4M BIT ROM

DATA

8

FLAGS

PWM

DAG1

8 x 4 x 32

DAG2

8 x 4 x 32

ADDR

32

DATA

48

ASYNCHRONOUS

MEMORY

INTERFACE

(AMI)

PROGRAM

SEQUENCER

24 ADDRESS

3

7

AMI CONTROL

PM ADDRESS BUS

DMADDRESS BUS

32

DDR2 CONTROL

16

19

DDR2 DRAM

CONTROLLER

DATA

64

PM DATA BUS

DM DATA BUS

ADDRESS

IOA(19)

IOD(32)

ACCELERATORS

FFT FIR IIR

PX REGISTER

PROCESSING

ELEMENT

(PEX)

PROCESSING

ELEMENT

(PEY)

IOP REGISTER CONTROL

STATUS, & DATA BUFFERS

3/5

20

MLB

DMA

ARBITER

LINK

PORTS

4

GPIO

IRQ/FLAGS

SPI PORT (2)

SERIAL PORTS (8)

PRECISION CLOCK

GENERATORS (4)

TWOWIRE

INTERFACE

UART

DTCP

GP TIMERS (2)

INPUT DATA PORT/

PDAP

GPIO

S/PDIF (RX/TX)

ASRC

DPI PINS (14)

S

DAI PINS (20)

DIGITAL PERIPHERAL INTERFACE

I/O PROCESSOR

DIGITAL APPLICATIONS INTERFACE

20

14

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.326.3113

www.analog.com

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Delay-line DMA engine maintains circular buffers in exter-

nal memory with tap/offset based reads

16-bit data access for synchronous DDR2 DRAM memory

8-bit data access for asynchronous memory

4 memory select lines allows multiple external memory

devices

Digital audio interface (DAI) includes eight serial ports, four

precision clock generators, an input data port, an S/PDIF

transceiver, and a signal routing unit

KEY FEATURES—PROCESSOR CORE

At up to 450 MHz core instruction rate, the processor per-

forms at 2.7 GFLOPS/900 MMACs

5 Mbits on-chip RAM, 4 Mbits on-chip ROM for simultaneous

access by the core processor and DMA

DDR2 DRAM interface (16-bit) operating at maximum fre-

quency of half the core clock frequency

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Digital peripheral interface (DPI) includes, two timers, one

UART, and two SPI ports, a DTCP cipher (ADSP-21462W

and ADSP-21465W), and a two-wire interface port

Outputs of PCG A and B can be routed through DAI pins

Outputs of PCG C and D can be driven on to DAI as well as

DPI pins

Eight dual data line serial ports — each has a clock, frame

sync, and two data lines that can be configured as either a

receiver or transmitter pair

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Up to 16 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port (IDP), configurable as eight channels of serial

data or seven channels of serial data and up to a 20-bit

wide parallel data channel

Signal routing unit provides configurable and flexible con-

nections between the various peripherals and the DAI/DPI

components

4 independent asynchronous sample rate converters (ASRC).

Each converter has separate serial input and output ports,

a de-emphasis filter providing up to –128 dB SNR perfor-

mance, stereo sample rate converter and supports left-

justified, I2S, TDM, and right-justified modes and 24-, 20-,

18-, and 16-audio data word lengths.

An MLB (media local bus) interface allows the processor to

support for both 3-pin as well as 5-pin media local bus pro-

tocols (ADSP-21462W and ADSP-21465W).

2 muxed flag/IRQ lines

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

VISA (variable instruction set) execution support

Single instruction multiple data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

Parallelism in buses and computational units allows:

Single cycle executions (with or without SIMD) of a mul-

tiply operation, an ALU operation, a dual memory read

or write, and an instruction fetch

Transfers between memory and core at a sustained

7.2 Gbytes/second bandwidth

FFT accelerator implements radix-2 complex/real input, com-

plex output FFT with no core intervention

IIR accelerators perform dedicated IIR filtering with high-per-

formance, fixed- and floating-point processing capabilities

with no core intervention

FIR accelerators perform dedicated FIR filtering with high-

performance, fixed- and floating-point processing capabil-

ities with no core intervention

Program sequencer can execute code directly from external

memory bank 0 (SRAM, as well as DDR2 DRAM). This allows

more options to a user in terms of code storage.

New opcodes of 16 and 32 bits are supported in addition to

the existing 48 bit opcodes. Variable Instruction Set Archi-

tecture (VISA) execution from external DDR2 DRAM

memory is also supported.

1 muxed flag/IRQ /AMI_MS pin

INPUT/OUTPUT FEATURES

1 muxed flag/Timer expired line /AMI_MS pin

S/PDIF-compatible digital audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I²S or right-justified serial data input with

16-, 18-, 20- or 24-bit word widths (transmitter)

Pulse-width modulation provides:

16 PWM outputs configured as four groups of four outputs

supports center-aligned or edge-aligned PWM waveforms

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Two 8-bit wide link ports can connect to the link ports of

other SHARCs or peripherals. Link ports are bidirectional

programmable ports having eight data lines, an acknowl-

edge line and a clock line

DMA controller supports

67 DMA channels for transfers between internal memory

and a variety of peripherals

DMA transfers at peripheral clock speed, in parallel with

full-speed processor execution

External port provides glueless connection to 16-bit wide

synchronous DDR2 DRAM using a dedicated DDR2 DRAM

controller, and 8-bit wide asynchronous memory devices

using asynchronous memory interface (AMI)

Programmable wait state options (for AMI) 2 to 31

DDR2_CLK cycles

Thermal diode to monitor die temperature

Available in 19 mm by 19 mm PBGA package (see Ordering

Guide on Page 59)

Rev. PrA

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Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

TABLE OF CONTENTS

Summary ............................................................... 1

Key Features—Processor Core ................................. 2

Input/Output Features ........................................... 2

Table Of Contents .................................................... 3

Revision History ...................................................... 3

General Description ................................................. 4

Family Core Architecture ....................................... 5

Memory ............................................................. 6

External Memory .................................................. 6

Input/Output Features ........................................... 8

System Design ..................................................... 11

Development Tools .............................................. 12

Additional Information ......................................... 12

Pin Function Descriptions ........................................ 13

Data Modes ........................................................ 17

Boot Modes ........................................................ 17

Core Instruction Rate to CLKIN Ratio Modes ............. 17

Specifications ......................................................... 18

Operating Conditions ........................................... 18

Electrical Characteristics ........................................ 19

Maximum Power Dissipation ................................. 20

Absolute Maximum Ratings ................................... 20

ESD Sensitivity .................................................... 20

Timing Specifications ........................................... 21

Output Drive Currents .......................................... 53

Test Conditions ................................................... 53

Capacitive Loading ............................................... 53

Thermal Characteristics ........................................ 54

Ball configuration - ADSP-2146x ............................. 55

PBGA Pinout ......................................................... 56

Outline Dimensions ................................................ 58

Automotive Products ............................................... 59

Ordering Guide ...................................................... 59

REVISION HISTORY

11/08—Revision PrA

Initial version

Rev. PrA

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ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-21462W/ADSP-21465W/ADSP-21467 SHARC^®

processors are members of the SIMD SHARC family of DSPs

that feature Analog Devices' Super Harvard Architecture. The

processors are source code compatible with the ADSP-2126x,

ADSP-2136x, ADSP-2137x, and ADSP-2116x DSPs as well as

with first generation ADSP-2106x SHARC processors in SISD

(single-instruction, single-data) mode. These new processors

are 32-bit/40-bit floating point processors optimized for high

performance audio applications with its large on-chip SRAM,

multiple internal buses to eliminate I/O bottlenecks, and an

innovative digital applications interface (DAI).

Table 1. SHARC Family Features (Continued)

Feature

AMI interface with 8-bit

support

Yes

SPI

2

TWI

Yes

Table 1. SHARC Family Features

Package

324-ball

PBGA

324-ball

PBGA

324-ball

PBGA

SRC Performance

128 dB

¹Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,

DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass

management, delay, speaker equalization, graphic equalization, and more.

Decoder/post-processor algorithm combination support varies depending

upon the chip version and the system configurations. Please visit

www.analog.com for complete information.

Feature

Frequency

400 MHz 400 MHz 450 MHz

RAM

ROM¹

5M bits

4M bits

No

5M bits

4M bits

Yes

5M bits

4M bits

Yes

²The ADSP-21462W and ADSP-21465W processors provide the Digital Trans-

mission Content Protection protocol, a proprietary security protocol. Contact

your Analog Devices sales office for more information.

Audio Decoders in ROM

Pulse-Width Modulation

S/PDIF

As shown in the functional block diagram on Page 1, the

processor uses two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. Fabricated in a state-of-the-art, high

speed, CMOS process, the processor achieves an instruction

cycle time of 2.22 ns at 450 MHz (ADSP-21467) and 2.5 ns at

400 MHz (ADSP-21462W, ADSP-21465W). With its SIMD

computational hardware, the processors can perform 2.7

GFLOPS running at 450 MHz (ADSP-21467) and 2.4 GFLOPS

running at 400 MHz (ADSP-21462W, ADSP-21465W).

Yes

DTCP²

Yes

No

DDR2 Memory Interface

1/2 CCLK 1/2 CCLK 1/2 CCLK

Max

DDR2 Memory Bus Width 16 bits

16 bits

Yes

16 bits

Yes

Direct DMA from SPORTs

to external memory

Yes

Table 2 shows performance benchmarks for the ADSP-2146x

processors.

FIR accelerator

IIR accelerator

FFT accelerator

MLB Interface

IDP

Yes

8

Yes

8

Yes

No

Yes

8

Table 2. Processor Benchmarks

Speed

(at 450 MHz)

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, With Reversal) 20.44 μs

Serial Ports

SRU

FIR Filter (per Tap)¹

IIR Filter (per Biquad)¹

1.11 ns

4.43 ns

2

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]

[4 × 4] × [4 × 1]

DDR2 Memory Interface

UART

Yes

1

Yes

1

Yes

1

10.0 ns

17.78 ns

DAI and DPI

20/14

pins

20/14

pins

20/14

pins

Divide (y/×)

6.67 ns

10.0 ns

Inverse Square Root

¹Assumes two files in multichannel SIMD mode

Link ports

2

1

2

1

2

1

S/PDIF transceiver

Rev. PrA

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Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

The ADSP-21462W/ADSP-21465W/ADSP-21467 continues

SHARC’s industry-leading standards of integration for DSPs,

combining a high performance 32-bit DSP core with integrated,

on-chip system features.

The block diagram on Page 1 illustrates the following architec-

tural features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

tion is executed in both processing elements, but each

processing element operates on different data. This architecture

is efficient at executing math intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• Two programmable interval timers with external event

counter capabilities

• On-chip SRAM

• JTAG test access port

• FFT, FIR, IIR accelerators

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

The block diagram of the processor on Page 1 also illustrates the

following architectural features:

• DMA controller

Data Register File

• Digital applications interface that includes four precision

clock generators (PCG), an S/PDIF-compatible digital

audio receiver/transmitter with four independent asyn-

chronous sample rate converters, an input data port (IDP)

with eight serial ports, DTCP cipher, eight serial interfaces,

a 20-bit parallel input port (PDAP), and a flexible signal

routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, one

UART, two serial peripheral interfaces (SPI), a 2-wire

interface (TWI), and a flexible signal routing unit

(DPI SRU).

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the processor’s enhanced Harvard

architecture, allow unconstrained data flow between computa-

tion units and internal memory. The registers in PEX are

referred to as R0-R15 and in PEY as S0-S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21462W/ADSP-21465W/ADSP-21467 features an

enhanced Harvard architecture in which the data memory

(DM) bus transfers data and the program memory (PM) bus

transfers both instructions and data (see Figure 1 on page 1).

With the its separate program and data memory buses and on-

chip instruction cache, the processor can simultaneously fetch

four operands (two over each data bus) and one instruction

(from the cache), all in a single cycle.

FAMILY CORE ARCHITECTURE

The ADSP-21462W/ADSP-21465W/ADSP-21467 is code com-

patible at the assembly level with the ADSP-2137x, ADSP-

2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with

the first generation ADSP-2106x SHARC processors. The

ADSP-21462W/ADSP-21465W/ADSP-21467 shares architec-

tural features with the ADSP-2126x, ADSP-2136x, ADSP-

2137x, and ADSP-2116x SIMD SHARC processors, as detailed

in the following sections.

Instruction Cache

The ADSP-21462W/ADSP-21465W/ADSP-21467 includes an

on-chip instruction cache that enables three-bus operation for

fetching an instruction and four data values. The cache is selec-

tive—only the instructions whose fetches conflict with PM bus

SIMD Computational Engine

The ADSP-21462W/ADSP-21465W/ADSP-21467 contains two

computational processing elements that operate as a single-

instruction, multiple-data (SIMD) engine. The processing ele-

ments are referred to as PEX and PEY and each contains an

ALU, multiplier, shifter, and register file. PEX is always active,

and PEY may be enabled by setting the PEYEN mode bit in the

MODE1 register. When this mode is enabled, the same instruc-

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ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

data accesses are cached. This cache allows full speed execution

of core, looped operations such as digital filter multiply-accu-

mulates, and FFT butterfly processing.

MEMORY

The ADSP-21462W/ADSP-21465W/ADSP-21467 adds the fol-

lowing architectural features to the SIMD SHARC family core.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

On-Chip Memory

The processors contain 5 Mbits of internal RAM. Each block

can be configured for different combinations of code and data

storage (see Table 3 on Page 7). Each memory block supports

single-cycle, independent accesses by the core processor and I/O

processor. The ADSP-21462W/ADSP-21465W/ADSP-21467

memory architecture, in combination with its separate on-chip

buses, allow two data transfers from the core and one from the

I/O processor, in a single cycle.

The processor’s SRAM can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data, 106.7k

words of 48-bit instructions (or 40-bit data), or combinations of

different word sizes up to 5 megabit. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-

ing-point storage format is supported that effectively doubles

the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point for-

mats is performed in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

The memory map in Table 3 displays the internal memory

address space of the ADSP-21462W/ADSP-21465W/ADSP-

21467.

The 48-bit space section describes what this address range looks

like to an instruction that retrieves 48-bit memory.

The 32-bit section describes what this address range looks like

to an instruction that retrieves 32-bit memory.

The ADSP-21462W/ADSP-21465W/ADSP-21467’s two data

address generators (DAGs) are used for indirect addressing and

implementing circular data buffers in hardware. Circular buff-

ers allow efficient programming of delay lines and other data

structures required in digital signal processing, and are com-

monly used in digital filters and Fourier transforms. The two

DAGs of the processors contain sufficient registers to allow the

creation of up to 32 circular buffers (16 primary register sets, 16

secondary). The DAGs automatically handle address pointer

wraparound, reduce overhead, increase performance, and sim-

plify implementation. Circular buffers can start and end at any

memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21462W/ADSP-21465W/ADSP-21467 can conditionally

execute a multiply, an add, and a subtract in both processing

elements while branching and fetching up to four 32-bit values

from memory—all in a single instruction.

Variable Instruction Set Architecture

In addition to supporting the standard 48-bit instructions from

previously existing SHARC family of processors, the ADSP-

21462W/ADSP-21465W/ADSP-21467 support new instruc-

tions of 16 and 32 bits in addition to the existing 48 bit

instructions. This feature, called Variable Instruction Set Archi-

tecture (VISA), is based on dropping redundant/unused bits

within the 48-bit instruction to create more efficient and com-

pact code. The program sequencer will now support fetching

these 16-bit and 32-bit instructions as well in addition to the

standard 48-bit instructions, both from internal as well as exter-

nal memory. Source modules will need to be built using the

VISA option, in order to allow code generation tools to create

these more efficient opcodes.

EXTERNAL MEMORY

The external port on the ADSP-21462W/ADSP-

FFT Accelerator

21465W/ADSP-21467 SHARC provides a high performance,

glueless interface to a wide variety of industry-standard memory

devices. The external port may be used to interface to synchro-

nous and/or asynchronous memory devices through the use of

its separate internal DDR2 memory controller. The 16-bit

DDR2 DRAM controller connects to industry-standard syn-

chronous DRAM devices, while the second 8-bit asynchronous

memory controller is intended to interface to a variety of mem-

ory devices. Four memory select pins enable up to four separate

devices to coexist, supporting any desired combination of syn-

chronous and asynchronous device types. Non DDR2 DRAM

external memory address space is shown in Table 4.

FFT accelerator implements radix-2 complex/real input, com-

plex output FFT with no core intervention.

FIR Accelerators

The FIR (finite impulse response) accelerator consists of a 1024

word coefficient memory, a 1024 word deep delay line for the

data, and four MAC units. A controller manages the accelerator.

The FIR accelerator runs at the peripheral clock frequency.

IIR Accelerators

The IIR (infinite impulse response) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency.

Rev. PrA

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Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

instructions are fetched in parts from a 16-bit external bus cou-

pled with the inherent latency of fetching instructions from

DDR2 DRAM. VISA mode and SIMD mode accesses are sup-

ported for DDR2 space. However, external memory execution

from DDR2 space is different for VISA and non-VISA mode.

External Memory Execution

In the ADSP-21462W/ADSP-21465W/ADSP-21467, the pro-

gram sequencer can execute code directly from external

memory bank 0 (SRAM, as well as DDR2 DRAM). This allows

more options to a user in terms of code and data storage. With

external execution, programs run at slower speeds since 48-bit

Table 3. ADSP-21462W/ADSP-21465W/ADSP-21467 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 bits)

Instruction Word (48 bits)

Normal Word (32 bits)

Short Word (16 bits)

BLOCK 0 ROM

0x0004 0000–0x0004 7FFF

0x0008 0000–0x0008 AAA9

0x0008 0000–0x0008 FFFF

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

0x0009 0000–0x0009 1FFF

0x0012 0000–0x0012 3FFF

BLOCK 0 RAM

0x0004 9000–0x0004 EFFF

0x0008 C000-0x0009 3FFF

0x0009 2000-0x0009 DFFF

0x0012 4000–0x0013 BFFF

Reserved

0x0004 F000–0x0004 FFFF

0x0009 E000–0x0009 FFFF

0x0013 C000–0x0013 FFFF

BLOCK 1 ROM

0x0005 0000–0x0005 7FFF

0x000A 0000–0x000A AAA9

0x000A 0000–0x000A FFFF

0x0014 0000-0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

0x000B 000–0x000B 1FFF

0x000B 0000–0x000B 1FFF

0x0016 0000-0x0016 3FFF

BLOCK 1 RAM

0x0005 9000–0x0005 EFFF

0x000A C000-0x000B 3FFF

0x000B 2000-0x000B DFFF

0x0016 4000-0x0017 BFFF

Reserved

0x0005 F000–0x0005 FFFF

0x000B E000–0x000B FFFF

0x0017 C000–0x0017 FFFF

BLOCK 2 RAM

0x0006 0000–0x0006 3FFF

0x000C 0000–0x000C 5554

0x000C 0000-0x000C 7FFF

0x0018 0000–0x0018 FFFF

Reserved

0x0006 4000–0x0006 FFFF

0x000C 8000–0x000D FFFF

0x0019 0000–0x001B FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 3FFF

0x000E 0000–0x000E 5554

0x000E 0000–0x000E 7FFF

0x001C 0000–0x001C FFFF

Reserved

0x0007 4000–0x0007 FFFF

0x000E 8000–0x000F FFFF

0x001D 0000–0x001F FFFF

DDR2_CS0), and can be configured to contain between 32M

bytes and 256M bytes of memory. DDR2 DRAM external mem-

ory address space is shown in Table 5

A set of programmable timing parameters is available to config-

ure the DDR2 DRAM banks to support memory devices.

DDR2 Support

The ADSP-21462W/ADSP-21465W/ADSP-21467 supports a

16-bit DDR2 interface operating at a maximum frequency of

half the core clock. Execution from external memory is sup-

ported. External memory devices up to 2 Gbits in size can be

supported. Delay line DMA functionality supported.

DDR2 DRAM Controller

The DDR2 DRAM controller provides an 16-bit interface to up

to four separate banks of industry-standard DDR2 DRAM

devices. Fully compliant with the DDR2 DRAM standard, each

bank can has its own memory select line (DDR2_CS3-

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ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Table 5. External Memory for DDR2 DRAM Addresses

Shared External Memory

The ADSP-21462W/ADSP-21465W/ADSP-21467 processor

supports connecting to common shared external DDR2 mem-

ory with other ADSP-2146x processors to create shared external

bus processor systems. This support includes:

• Distributed, on-chip arbitration for the shared external bus

• Fixed and rotating priority bus arbitration

• Bus time-out logic

Size in

Words

Bank

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

62M

0x0020 0000 – 0x03FF FFFF

0x0400 0000 – 0x07FF FFFF

0x0800 0000 – 0x0BFF FFFF

0x0C00 0000 – 0x0FFF FFFF

64M

• Bus lock

Table 4. External Memory for Non DDR2 DRAM Addresses

Multiple processors can share the external bus with no addi-

tional arbitration logic. Arbitration logic is included on-chip to

allow the connection of up to TBD processors.

Bus arbitration is accomplished through the BR6-1 signals and

the priority scheme for bus arbitration is determined by the set-

ting of the RPBA pin. Table 6 on Page 13 provides descriptions

of the pins used in multiprocessor systems.

Size in

Words

Bank

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

14M

0x0020 0000 – 0x00FF FFFF

0x0400 0000 – 0x04FF FFFF

0x0800 0000 – 0x08FF FFFF

0x0C00 0000 – 0x0CFF FFFF

16M

INPUT/OUTPUT FEATURES

16M

The ADSP-21462W and ADSP-21465W I/O processors provide

67 channels of DMA, while ADSP-21467 I/O processors pro-

vide 36 channels of DMA as well as an extensive set of

peripherals. These include a 20 lead digital applications inter-

face, which controls:

• Eight serial ports

• S/PDIF receiver/transmitter

• Four precision clock generators

• Input data port/parallel data acquisition port

• Four asynchronous sample rate converters

The ADSP-21462W/ADSP-21465W/ADSP-21467 processor

also contains a 14 lead digital peripheral interface, which

controls:

Note that the external memory bank addresses shown are for

normal-word (32-bit) accesses. If 48-bit instructions as well as

32-bit data are both placed in the same external memory bank,

care must be taken while mapping them to avoid overlap. In

case of 32-bit wide external memory, two 48-bit instructions

will be stored in three 32-bit wide memory locations. For exam-

ple, if 2k instructions are placed in 32-bit wide external memory

starting at the bank 0 normal-word base address 0x0030 0000

(corresponding to instruction address 0x0020 0000) and ending

at address 0x0030 0BFF (corresponding to instruction address

0x0020 07FF), then data buffers can be placed starting at an

address that is offset by 3k 32-bit words (for example, starting at

0x0030 0C00).

Asynchronous Memory Controller

• Two general-purpose timers

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, flash, and EPROM, as well

as I/O devices that interface with standard memory control

lines. Bank 0 occupies a 14M word window and banks 1, 2, and

3 occupy a 16M word window in the processor’s address space

but, if not fully populated, these windows are not made contigu-

ous by the memory controller logic.

The asynchronous memory controller is capable of a maximum

throughput of TBD Mbps using a TBD MHz external bus speed.

Other features include 8 to 32-bit packing and unpacking, boot-

ing from bank select 1, and support for delay line DMA.

• Two serial peripheral interfaces

• One universal asynchronous receiver/transmitter (UART)

• An I²C^®-compatible 2-wire interface

• Two PCGs (C and D) can also be routed through DPI

DMA Controller

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the ADSP-21462W/ADSP-21465W/ADSP-21467’s

internal memory and its serial ports, the SPI-compatible (serial

peripheral interface) ports, the IDP (input data port), the paral-

lel data acquisition port (PDAP) or the UART.

Sixty-seven channels of DMA are available on the

ADSP-21462W and ADSP-21465W devices, and thirty-six

channels on the ADSP-21467. The breakdown is as follows: 16

via the serial ports, eight via the input data port, two for the

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Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

UART, two for the SPI interface, two for the external port, two

for DTCP (or memory-to-memory data transfer when DTCP is

not used), two for the link port, two for the FFT/FIR/IIR accel-

erators, and up to 31 DMA channels for the media local bus

interface on the ADSP-21462W and ADSP-21465W.

Programs can be downloaded to the ADSP-21462W/ADSP-

21465W/ADSP-21467 using DMA transfers. Other DMA fea-

tures include interrupt generation upon completion of DMA

transfers, and DMA chaining for automatic linked DMA

transfers.

The serial ports operate at a maximum data rate of 56.25 Mbps.

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. One SPORT pro-

vides two transmit signals while the other SPORT provides the

two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I²S mode

• Packed I²S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Delay Line DMA

The ADSP-21462W/ADSP-21465W/ADSP-21467 processor

provides delay line DMA functionality. This allows processor

reads and writes to external delay line buffers (and hence to

external memory) with limited core interaction.

Scatter/Gather DMA

The ADSP-21462W/ADSP-21465W/ADSP-21467 processor

provides scatter/gather DMA functionality.

This allows processor DMA reads/writes to/from non-contin-

geous memory blocks.

Each of the serial ports supports the left-justified sample pair

and I²S protocols (I²S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I²S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I²S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I²S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional μ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the DAI pins

(DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The DAI also includes eight serial ports, four precision clock

generators (PCG), S/PDIF transceiver, four ASRCs, and an

input data port (IDP). The IDP provides an additional input

path to the SHARC core, configurable as either eight channels

of serial data, or a single 20-bit wide synchronous parallel data

acquisition port. Each data channel has its own DMA channel

that is independent from the processor’s serial ports.

The serial ports also contain frame sync error detection logic

where the serial ports detect frame syncs that arrive early (for

example frame syncs that arrive while the transmission/recep-

tion of the previous word is occurring). All the serial ports also

share one dedicated error interrupt.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the

Serial Ports

The ADSP-21462W/ADSP-21465W/ADSP-21467 features

eight synchronous serial ports that provide an inexpensive

interface to a wide variety of digital and mixed-signal peripheral

devices such as Analog Devices’ AD183x family of audio codecs,

ADCs, and DACs. The serial ports are made up of two data

lines, a clock, and frame sync. The data lines can be pro-

grammed to either transmit or receive and each data line has a

dedicated DMA channel.

receiver/transmitter can be formatted as left justified, I²S or

right justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources such as the

SPORTs, external pins, the precision clock generators (PCGs),

and are controlled by the SRU control registers.

The sample rate converter (ASRC) contains four ASRC blocks

and is the same core as that used in the AD1896 192 kHz stereo

asynchronous sample rate converter and provides up to 128 dB

SNR. The ASRC block is used to perform synchronous or asyn-

Serial ports can support up to 16 transmit or 16 receive channels

of audio data when all eight SPORTs are enabled, or four full

duplex TDM streams of 128 channels per frame.

Rev. PrA

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ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

chronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to con-

vert multichannel audio data without phase mismatches.

Finally, the ASRC can be used to clean up audio data from jit-

tery clock sources such as the S/PDIF receiver.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_PCLK/ 1,048,576) to

(f_PCLK/16) bits per second.

• Supporting data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

Digital Transmission Content Protection

The DTCP specification defines a cryptographic protocol for

protecting audio entertainment content from illegal copying,

intercepting, and tampering as it traverses high performance

digital buses, such as the IEEE 1394 standard. Only legitimate

entertainment content delivered to a source device via another

approved copy protection system (such as the DVD content

scrambling system) will be protected by this copy protection

system. This feature is available on the ADSP-21462W and

ADSP-21465W processors only. Licensing through DTLA is

required for these products. Visit www.dtcp.com for more

information.

Timers

Digital Peripheral Interface (DPI)

The ADSP-21462W/ADSP-21465W/ADSP-21467 has a total of

three timers: a core timer that can generate periodic software

interrupts and two general purpose timers that can generate

periodic interrupts and be independently set to operate in one

of three modes:

The digital peripheral interface provides connections to two

serial peripheral interface ports (SPI), one universal asynchro-

nous receiver-transmitter (UART), 12 flags, a 2-wire interface

(TWI), and two general-purpose timers.

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer

expired signal, and each general-purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables both general-

purpose timers independently.

Serial Peripheral (Compatible) Interface

The ADSP-2146x SHARC processors contain two serial periph-

eral interface ports (SPIs). The SPI is an industry-standard

synchronous serial link, enabling the SPI-compatible port to

communicate with other SPI compatible devices. The SPI con-

sists of two data pins, one device select pin, and one clock pin. It

is a full-duplex synchronous serial interface, supporting both

master and slave modes. The SPI port can operate in a multi-

master environment by interfacing with up to four other SPI-

compatible devices, either acting as a master or slave device. The

SPI-compatible peripheral implementation also features pro-

grammable baud rate and clock phase and polarities. The SPI-

compatible port uses open drain drivers to support a multimas-

ter configuration and to avoid data contention.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I²C bus protocol.

The TWI master incorporates the following features:

UART Port

• 7-bit addressing

The processors provide a full-duplex Universal Asynchronous

Receiver/Transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface stan-

dard. The UART port also includes support for 5 to 8 data bits, 1

or 2 stop bits, and none, even, or odd parity. The UART port

supports two modes of operation:

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

Rev. PrA

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Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The “Running Reset” feature allows a user to perform a reset of

the processor core and peripherals, but without resetting the

PLL and DDR2 DRAM controller, or performing a Boot. The

functionality of the CLKOUT/RESETOUT/RUNRSTIN pin has

now been extended to also act as the input for initiating a Run-

ning Reset. For more information, see the ADSP-2146x SHARC

Processor Hardware Reference.

Power Supplies

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

mid-point of the PWM period. In double update mode, a sec-

ond updating of the PWM registers is implemented at the mid-

point of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

The processors have separate power supply connections for the

internal (V_{DD_INT}), external (V_{DD_EXT}), and analog

(V_{DD_A}/V_{SS_A}) power supplies. The internal and analog supplies

must meet the V_{DD_INT}specifications. The external supply must

meet the V_{DD_EXT}specification. All external supply pins must

be connected to the same power supply.

Note that the analog supply pin (V_{DD_A}) powers the processor’s

internal clock generator PLL. To produce a stable clock, it is rec-

ommended that PCB designs use an external filter circuit for the

Link Ports

V

_{DD_A}pin. Place the filter components as close as possible to

the V_{DD_A}/V_{SS_A}pins. For an example circuit, see Figure 2. (A

recommended ferrite chip is the muRata BLM18AG102SN1D).

Two 8-bit wide link ports can connect to the link ports of other

DSPs or peripherals. Link ports are bidirectional ports having

eight data lines, an acknowledge line and a clock line. Link ports

can operate at a maximum frequency of 166 MHz.

ADSP-213xx

100nF

10nF

1nF

MediaLB

A

V

VDD

DDINT

The ADSP-21462W and ADSP-21465W have an MLB interface

which allows the processor to function as a media local bus

device. It includes support for both 3-pin as well as 5-pin media

local bus protocols. It supports speeds up to 1024 FS (49.25

Mbits/sec, FS = 48.1 kHz) and up to 31 logical channels, with up

to 124 bytes of data per media local bus frame.

HI Z FERRITE

BEAD CHIP

A

VSS

LOCATE ALL COMPONENTS

CLOSE TO A AND A PINS

VDD

VSS

ROM Based Security

Figure 2. Analog Power (V_{DD_A}) Filter Circuit

The ADSP-21462W/ADSP-21465W/ADSP-21467 has a ROM

security feature that provides hardware support for securing

user software code by preventing unauthorized reading from

the internal code when enabled. When using this feature, the

processor does not boot-load any external code, executing

exclusively from internal SRAM/ROM. Additionally, the pro-

cessor is not freely accessible via the JTAG port. Instead, a

unique 64-bit key, which must be scanned in through the JTAG

or Test Access Port will be assigned to each customer. The

device will ignore a wrong key. Emulation features and external

boot modes are only available after the correct key is scanned.

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V_{DD_INT}and V_SS. Use wide traces

to connect the bypass capacitors to the analog power (V_{DD_A}

)

and ground (V_{SS_A}) pins. Note that the V_{DD_A}and V_{SS_A}pins

specified in Figure 2 are inputs to the processor and not the ana-

log ground plane on the board—the V_{SS_A}pin should connect

directly to digital ground (V_SS) at the chip

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-2146x pro-

cessors to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processor stacks. The processor's JTAG interface ensures that

the emulator will not affect target system loading or timing.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

The internal memory of the ADSP-2146x boots at system

power-up from an 8-bit EPROM via the external port, link port,

an SPI master, or an SPI slave. Booting is determined by the

boot configuration (BOOTCFG2–0) pins (see Table 8 on

Page 17).

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User's Guide”.

Rev. PrA

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November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Evaluation Kit

DEVELOPMENT TOOLS

Analog Devices offers a range of EZ-KIT Lite^®evaluation plat-

forms to use as a cost effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++^®development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

The ADSP-21462W/ADSP-21465W/ADSP-21467 processors

are supported with a complete set of CROSSCORE^®software

and hardware development tools, including Analog Devices

emulators and VisualDSP++^®development environment. The

same emulator hardware that supports other SHARC proces-

sors also fully emulates the ADSP-2146x processors.

EZ-KIT Lite Evaluation Board

For evaluation of the processors, use the EZ-KIT Lite^®board

being developed by Analog Devices. The board comes with on-

chip emulation capabilities and is equipped to enable software

development. Multiple daughter cards are available.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board Flash device to store

user-specific boot code, enabling the board to run as a standal-

one unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom defined system. Connecting one of Analog Devices JTAG

emulators to the EZ-KIT Lite board enables high speed, non-

intrusive emulation.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-

circuit emulation is assured by the use of the processor’s JTAG

interface—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the processor, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The processor must be halted to send data and com-

mands, but once an operation has been completed by the

emulator, the DSP system is set running at full speed with no

impact on system timing.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2146x

architecture and functionality. For detailed information on the

ADSP-21462W/ADSP-21465W/ADSP-21467 family core archi-

tecture and instruction set, refer to the ADSP-2136x/ADSP-

2146x SHARC Processor Programming Reference.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

Rev. PrA

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Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 6:

A = asynchronous, I = input, O = output, S = synchronous,

(A/D) = active drive, (O/D) = open drain, and T = three-state,

(pd) = pull-down resistor, (pu) = pull-up resistor.

Table 6. Pin List

State

During

and After

LVTTL SSTL18 Reset

Name

Type

Description

AMI_ADDR_23–0

I/O/T

3

High-Z/

External Address. The ADSP-21462W/ADSP-21465W/ADSP-21467 outputs

driven low addresses for external memory and peripherals on these pins. The data pins

(boot)

High-Z

can be multiplexed to support the PDAP (I) and PWM (O). After reset, all

AMI_ADDR_23-0pins are in EMIF mode and FLAG(0-3) pins will be in FLAGS

mode (default). When configured in the IDP_PDAP_CTL register, IDP

channel 0 scans the AMI_ADDR_23–0pins for parallel input data.

AMI_DATA_7–0

DAI _P_20–1

I/O/T

3

External Data. The data pins can be multiplexed to support the external

memoryinterfacedata(I/O),thePDAP(I),FLAGS(I/O)andPWM(O).Afterreset,

all AMI_DATApinsareinEMIF modeandFLAG(0-3) pinswillbeinFLAGS mode

(default).

I/O with fixed weak 3

pull-up on input

path ^{1, 2}

Digital Applications Interface Pins. These pins provide the physical

interface to the DAI SRU. The DAI SRU configuration registers define the com-

bination of on-chip audiocentric peripheral inputs or outputs connected to

the pin and to the pin’s output enable. The configuration registers of these

peripherals then determine the exact behavior of the pin. Any input or output

signal present in the DAI SRU may be routed to any of these pins. The DAI SRU

provides the connection from the serial ports, the S/PDIF module, input data

ports (2), and the precision clock generators (4), to the DAI_P20–1 pins.

DPI _P_14–1

I/O with fixed weak 3

pull-up only on

High-Z

Digital Peripheral Interface. These pins provide the physical interface to the

DPI SRU. The DPI SRU configuration registers define the combination of on-

chip peripheral inputs or outputs connected to the pin and to the pin’s output

enable. The configuration registers of these peripherals then determines the

exact behavior of the pin. Any input or output signal present in the DPI SRU

may be routed to any of these pins. The DPI SRU provides the connection from

the timers (2), SPIs (2), UART (1), flags (12), and general-purpose I/O (9) to the

DPI_P14–1 pins.

input path^{1, 2}

AMI_ACK

AMI_RD

I (pu)

3

Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK

(low) to add wait states to an external memory access. AMI_ACK is used by I/O

devices, memory controllers, or other peripherals to hold off completion of

an external memory access.

O/T

3

High-Z

AMI Port Read Enable. AMI_RD is asserted whenever the ADSP-

21462W/ADSP-21465W/ADSP-21467 reads a word from external memory.

AMI_RD has fixed internal pull-up resistor^{1, 2}

.

External Port Write Enable. AMI_WR is asserted when the ADSP-

AMI_WR

21462W/ADSP-21465W/ADSP-21467 writes a word to external memory.

AMI_WR has fixed internal pull-up resistor^{1, 2}

.

DDR2_ADDR_15–0

DDR2_BA_2-0

O/T

3

High-Z/

Driven low

DDR2 Address pins. DDR2 address pins.

High-Z/

Driven low

DDR2 Bank Address Input pins. Define which bank an ACTIVATE,

READ, WRITE, or PRECHARGE command is being applied. BA2–0

define which mode register including MR, EMR, EMR(2), and

EMR(3) is loaded during the LOAD MODE command.

Rev. PrA

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ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Table 6. Pin List (Continued)

State

During

and After

LVTTL SSTL18 Reset

Name

Type

Description

O/T

3

High-Z/

Driven

high

DDR2 Column Address Strobe. Connect to DDR2_CAS pin, in conjunction

with other DDR2 command pins, defines the operation for the DDR2 to

perform.

DDR2_CAS

DDR2_CKE

O/T

3

High-Z/

Driven low CKE signal.

DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2

High-Z/

Driven

high

DDR2 Chip Select. All commands are masked when DDR2_CS_3-0is driven

high. DDR2_CS_3-0are decoded emory address lines. Each DDR2_CS_3-0lines

select the corresponding bank.

DDR2_CS_3-0

DDR2_DATA_15-0

DDR2_DM_1-0

I/O/T

O/T

3

High-Z

DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.

High-Z/

Driven

high

DDR2InputDataMask. Maskfor theDDR2writedata ifdrivenhigh. Sampled

on both edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA

7–0 and DM1 corresponds to DDR2_DATA 15–8.

DDR2_DQS_1-0

I/O/T (Differential)

O/T

3

High-Z

Data Strobe. Output with Write Data. Input with Read Data. DQS0 corre-

sponds to DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8.

High-Z/

Driven

high

DDR2 Row Address Strobe. Connect to DDR2_RAS pin, in conjunction with

other DDR2 command pins, defines the operation for the DDR2 to perform.

DDR2_RAS

DDR2_WE

O/T

3

High-Z/

Driven

high

DDR2 Write Enable. Connect to DDR2_WE pin, in conjunction with other

DDR2 command pins, defines the operation for the DDR2 to perform

DDR2_CLK0,

DDR2_CLK1,

DDR2_CLK1

DDR2_ODT

O/T (Differential)

High-Z/

driven low

DDR2 Clock. Freerunning, minimum frequency not guaranteed during reset.

O/T

3

High-Z/

DDR2 On Die Termination. ODT pin when driven high (along with other

Driven low requirements) enables the DDR2 termination resistances.

AMI_MS_0–1

3

High-Z

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for

the corresponding banks of external memory on the AMI interface. The MS_1-

₀lines are decoded memory address lines that change at the same time as the

other address lines. When no external memory access is occurring the MS_1-0

lines are inactive; they are active however when a conditional memory access

instruction is executed, whether or not the condition is true.

The MS1 pin can be used in EPORT/FLASH boot mode. For more information,

see the ADSP-2146x SHARC Processor Hardware Reference.

FLAG[0]/IRQ0

FLAG[1]/IRQ1

I/O

3

High-Z

FLAG0/Interrupt Request0.

FLAG1/Interrupt Request1.

FLAG2/Interrupt Request2/Async Memory Select2.

FLAG[2]/IRQ2/

AMI_MS2

FLAG[3]/TIMEX P/ I/O

AMI_MS3

3

High-Z

FLAG3/Timer Expired/Async Memory Select3.

LDAT0_7–0

LDAT1_7–0

I/0

Link Port Data (Link Ports 0-1).

LCLK0

LCLK1

I/O

Link Port Clock (Link Ports 0–1).

LACK0

LACK1

Link Port Acknowledge (Link Port 0-1).

THD_P

THD_M

I

Thermal Diode Anode

Thermal Diode Cathode

O

Rev. PrA

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Page 14 of 60

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November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Table 6. Pin List (Continued)

State

During

and After

LVTTL SSTL18 Reset

Name

Type

Description

TDI

I (pu)

3

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI

has a fixed internal pull-up resistor^{1, 2}

.

TDO

TMS

O /T

3

High-Z

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a

I (pu)

fixed internal pull-up resistor^{1, 2}

.

TCK

I (pu)

3

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be

asserted (pulsed low) after power-up or held low for proper operation of the

device.

TRST

EMU

I (pu)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted

(pulsed low) after power-up or held low for proper operation of the processor.

TRST has a fixed internal pull-up resistor^{1, 2}

.

O/T (pu)

High-Z

Emulation Status. Must be connected to the ADSP-21462W/ADSP-

21465W/ADSP-21467 Analog Devices DSP Tools product line of JTAG

emulators target board connector only. EMU has a fixed internal pull-up

resistor^{1, 2}

.

CLK_CFG_1–0

I

3

Core to CLKIN Ratio Control. These pins set the start up clock frequency. See

Table 9 for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL

multiplier and divider in the PMCTL register at any time after the core comes

out of reset.

BOOT_CFG_2–0

RESET

I

3

Boot Configuration Select. These pins select the boot mode for the proces-

sor. The BOOTCFG pins must be valid before reset is asserted. See Table 8 for

a description of the boot modes.

I (pu)

Processor Reset. Resets the processor to a known state. Upon deassertion,

there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core

begins program execution fromthe hardwarereset vectoraddress. The RESET

input must be asserted (low) at power-up.

XTAL

O

I

3

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an

external crystal.

CLKIN

Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It

configures the processors to use either its internal clock generator or an

external clock source. Connecting the necessary components to CLKIN and

XTAL enables the internal clock generator. Connecting the external clock to

CLKIN while leaving XTAL unconnected configures the processors to use the

external clock source such as an external clock oscillator. CLKIN may not be

halted, changed, or operated below the specified frequency.

CLKOUT/

RESETOUT/

RUNRSTIN

I/O (pu)

I (pd)

3

Clock Out/Reset Out/Running Reset In. The functionality can be switched

between the PLL output clock and reset out by setting Bit 12 of the PMCTL

register. The default is reset out. Thispin also has a third function as RUNRSTIN

which is enabled by setting bit 0 of the RUNRSTCTL register. For more infor-

mation, see the ADSP-2146x SHARC Processor Hardware Reference.

MLBCLK

MLBDAT

3

High-Z

Media Local Bus Clock. This clock is generated by the MLB controller that is

synchronizedtotheMOSTnetworkandprovidesthetimingfortheentireMLB

interface. 49.152 MHz at Fs=48 kHz

I/O (pd) in 3 pin

mode. Input in 5 pin

mode.

Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB

device and is received by all other MLB devices including the MLB controller.

The MLBDAT line carries the actual data. In 5-pin MLB mode, this pin will be

an input only.

Rev. PrA

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Page 15 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Table 6. Pin List (Continued)

State

During

and After

LVTTL SSTL18 Reset

Name

Type

Description

MLBSIG

I/O (pd) in 3 pin

mode. Input in 5 pin

mode

3

High-Z

Media Local Bus Signal. This is a multiplexed signal which carries the Chan-

nel/Address generated by the MLB Controller, as well as the Command and

RxStatus bytes from MLB devices. In 5-pin mode, this pin will be input only.

MLBDO

MLBSO

BR_6-1

O (pd)

I/O

3

High-Z

Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin

MLB mode. This serves as the output data pin in 5-pin mode.

Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-

pin MLB mode. This serves as the output signal pin in 5-pin mode.

High-Z/

Bus request. Bus request pins for external DDR2 bus arbitration.

Driven low

RPBA

ID_2-0

I

3

Rotating priority bus arbitration.

Chip ID

¹Pull-up/pull-down resistor can not be enabled/disabled and the value of the pull-up/pull-down resistor cannot be programmed.

²Range of fixed pull-up resistor can be between 26k-63kΩ. Range of fixed pull-down resistor can be between 31k-85kΩ.

Rev. PrA

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Page 16 of 60

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November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-

DATA MODES

The address and data pins of the external memory interface are muxed (using bits in the SYSCTL register) to support the external memory

interface data (input/output), the PDAP (input only), and the FLAGS (input/output). Table 7 provides the pin settings.

Table 7. Function of Data Pins

DATA PIN MODE

AMI_ADDR [23:8]

AMI_ADDR [23:0]

AMI_ADDR [7:0]

AMI_DATA [7:0]

000

001

010

011

100

101

110

111

Reserved

FLAGS/PWM [15–0]

PDAP (DATA + CTRL)

FLAGS [15–0]

FLAGS [7–0]

Reserved

Three-state all pins

BOOT MODES

Table 8. Boot Mode Selection

BOOTCFG2–0

Booting Mode

000

001

010

011

100

101

SPI Slave Boot

SPI Master Boot

AMI user boot (for 8-bit Flash boot)

Reserved

Link Port 0 Boot

Reserved

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and Figure 3 on Page 21.

Table 9. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1–0

Core to CLKIN Ratio

00

01

11

10

6:1

32:1

Reserved

16:1

Rev. PrA

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Page 17 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

SPECIFICATIONS

OPERATING CONDITIONS

Parameter¹

Description

Min

Max

Unit

V_{DD_INT}

V_{DD_EXT}

Internal (Core) Supply Voltage

TBD²

3.14

TBD²

V

External (I/O) Supply Voltage

3.46

V

3

V_{DD_DDR2}

DDR2 Controller Supply Voltage

DDR2 Reference Voltage

1.71

1.89

V

V_REF

0.84

0.96

V

4

V_IH

High Level Input Voltage @ V_{DD_EXT}= max

Low Level Input Voltage @ V_{DD_EXT}= min

High Level Input Voltage @ V_{DD_EXT}= max

Low Level Input Voltage @ V_{DD_EXT}= min

DC Low Level Input Voltage

2.0

3.6

V

4

V_IL

-0.3

0.8

V

5

V_{IH_CLKIN}

TBD

V

5

V_{IL_CLKIN}

TBD

V

V_{IL_DDR2}(DC)

V_{IH_DDR2}(DC)

V_{IL_DDR2}(AC)

V_{IH_DDR2}(AC)

T_J

-0.3

V_REF- 0.12

V_{DD_DDR2}+ 0.3

V_REF- 250

V

DC High Level Input Voltage

V_REF+ 0.13

V

AC Low Level Input Voltage

mV

°C

AC High Level Input Voltage

V_REF+ 250

0

Junction Temperature 208-Lead PBGA @ T_AMBIENT0 °C to +70 °C

125

¹Specifications subject to change without notice.

²The expected value is 1.1V and initial customer designs should design with a programmable regulator that can be adjusted from 0.95V to 1.15V +/-50mV

³Applies to DDR2 signals.

⁴Appliestoinputandbidirectionalpins:AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOTCFGx, CLKCFGx, CLKOUT(RUNRSTIN), RESET,

TCK, TMS, TDI, TRST.

⁵Applies to input pin CLKIN.

Rev. PrA

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Page 18 of 60

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November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

ELECTRICAL CHARACTERISTICS

Parameter¹

Description

Test Conditions

Min

Typical Max

Unit

2

V_OH

High Level Output Voltage

Low Level Output Voltage

Output Source DC Current

Output Sink DC Current

@ V_{DD_EXT}= min, I_OH= –1.0 mA³

@ V_{DD_EXT}= min, I_OL= 1.0 mA³

@ V_{OH_DDR2}(DC) = V_{DD_DDR2}-0.28 V

@ V_{OL_DDR2}(DC)=0.28

2.4

V

2

V_OL

0.4

V

4

I_{OH_DDR2}

TBD

mA

μA

mA

pF

4

I_{OL_DDR2}

TBD

V_{OH_DDR2}

V_{OL_DDR2}

@

TBD

10

5, 6

I_IH

High Level Input Current

@ V_{DD_EXT}= max, V_IN= V_{DD_EXT}max

@ V_{DD_EXT}= max, V_IN= 0 V

@ V_{DD_EXT}= max, V_IN= V_{DD_EXT}max

@ V_{DD_EXT}= max, V_IN= 0 V

5

I_IL

Low Level Input Current

10

6

I_ILPU

Low Level Input Current Pull-up

Three-State Leakage Current

TBD

10

7, 8

I_OZH

7

I_OZL

10

8

I_OZLPU

Three-State Leakage Current Pull-up @ V_{DD_EXT}= max, V_IN= 0 V

TBD

9, 10

I_DD-INTYP

Supply Current (Internal)

Input Capacitance

TBD

11, 12

C_IN

1

Specifications subject to change without notice.

²Applies to output and bidirectional pins: AMI_ADDR23-0, AMI_DATA7-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, CLKOUT.

³See Output Drive Currents on Page 53 for typical drive current capabilities.

⁴Applies to DDR2_ADDR18-0, DDR2_CAS, DDR2_CS3-0, DDR2_DQ1-0, DDR2_DM1-0, DDR2_DQS1-0, DDR2_DATA15-0, DDR2_RAS, DDR2_WE, DDR2_CLK0,

DDR2_CLK0, DDR2_CLK1 and, DDR2_CLK1.

⁵Applies to input pins: BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

⁶Applies to input pins with internal pull-ups: TRST, TMS, TDI.

⁷Applies to three-statable pins: FLAG3–0.

⁸Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

⁹Typical internal current data reflects nominal operating conditions.

¹⁰See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2146x SHARC Processors” for further information.

¹¹Applies to all signal pins.

¹²Guaranteed, but not tested.

Rev. PrA

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Page 19 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note “Estimating Power Dissipation

for ADSP-2146x SHARC Processors” for detailed thermal and

power information regarding maximum power dissipation. For

information on package thermal specifications, see Thermal

Characteristics on Page 54.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 10 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Table 10. Absolute Maximum Ratings

Parameter

Rating

Internal (Core) Supply Voltage

–0.3 V to +1.32V

(V_{DD_INT}

)

Analog (PLL) Supply Voltage (V_{DD_A}

)

TBD

External (I/O) Supply Voltage(V_{DD_EXT}) –0.3 V to +4.6V

DDR2 Controller Supply Voltage

(V_{DD_DDR2)}

–0.5 V to +2.7V

Input Voltage

–0.5 V to +3.8V

–0.5 V to V_{DD_EXT}+0.5V

200 pF

Output Voltage Swing

Load Capacitance

Storage Temperature Range

Junction Temperature under Bias

–65°C to +150°C

125°C

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

Rev. PrA

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Page 20 of 60

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November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Figure 3 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the

ADSP-2136x SHARC Processor Programming Reference.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock.

TIMING SPECIFICATIONS

The ADSP-21462W/ADSP-21465W/ADSP-21467’s internal

clock (a multiple of CLKIN) provides the clock signal for timing

internal memory, processor core, and serial ports. During reset,

program the ratio between the processor’s internal clock fre-

quency and external (CLKIN) clock frequency with the

CLKCFG1–0 pins (see Table 9 on Page 17). To determine

switching frequencies for the serial ports, divide down the inter-

nal clock, using the programmable divider control of each port

(DIVx for the serial ports).

CLK_CFGx/

PMCTL

LINKPORT

CLOCK

DIVIDER

LCLK

PMCTL

CLK_CFGx/

PMCTL

PLL

PLLI

CLK

CLKIN

DDR2

DIVIDER

CLKIN

DIVIDER

LOOP

FILTER

PLL

DIVIDER

VCO

CCLK

DDR2_CLK

XTAL

BUF

PMCTL

PCLK

DIVIDE

BY 2

PLL

MULTIPLIER

CLK_CFGx/

PMCTL

PCLK

CCLK

CLK_CFGx/PMCTL

CLK_CFGx/

PMCTL

MLBSYSCLK

MLB CLOCK

DIVIDER

PMCTL

CLKOUT

RESETOUT/

CLKOUT

DELAY OF

4096 CLKIN

RESETOUT

BUF

RESET

CYCLES

CORERST

Figure 3. Core Clock and System Clock Relationship to CLKIN

Core clock frequency can be calculated as:

_CCLK= (2 × PLLM × f_INPUT) ÷ (2 × PLLN)

f

_INPUT= CLKIN when the input divider is disabled

_INPUT= CLKIN ÷ 2 when the input divider is enabled

f

Note that in the user application, the PLL multiplier value

should be selected in such a way that the VCO frequency falls in

between 160 MHz and 800 MHz. The VCO frequency is calcu-

lated as follows:

Note the definitions of various clock periods shown in Table 12

which are a function of CLKIN and the appropriate ratio con-

trol shown in Table 11.

Table 11. CLKOUT and CCLK Clock Generation Operation

f

_VCO= 2 × PLLM × f_INPUT

where:

_VCOis the VCO frequency

PLLM is the multiplier value programmed

_INPUTis the input frequency to the PLL in MHz.

Timing

Requirements

CLKIN

Description

Input Clock

Core Clock

Calculation

1/t_CK

f

CCLK

1/t_CCLK

f

Rev. PrA

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Page 21 of 60

|

November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Table 12. Clock Periods

Timing

Requirements

Description¹

t_CK

CLKIN Clock Period

t_CCLK

(Processor) Core Clock Period

(Peripheral) Clock Period = 2 × t_CCLK

Serial Port Clock Period = (t_PCLK) × SR

DDR2 DRAM Clock Period = (t_CCLK) × SDR

SPI Clock Period = (t_PCLLK) × SPIR

t_PCLK

t_SCLK

t_{DDR2_CLK}

t_SPICLK

¹where:

SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV

bits in DIVx register)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register

setting)

SDR=DDR2 DRAM-to-Core Clock Ratio (Values determined by bits 20-18 of

the PMCTL register)

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 41 on Page 53 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Rev. PrA

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Page 22 of 60

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November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 13.

Table 13. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_{DD_EXT}or V_{DD_DDR2}On

V_{DD_EXT}on Before V_{DD_DDR2}

0

ms

t_EVDD-DDR2VDD

TBD

0

10²

20³

t_{DDR2VDD_IVDD}

V_{DD_DDR2}on Before V_{DD_INT}

1

t_CLKVDD

CLKIN Valid After V_{DD_INT}Valid

200

t_CLKRST

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

t_PLLRST

Switching Characteristic

t_CORERST

4, 5

Core Reset Deasserted After RESET Deasserted

4096 × t_CK+ 2 × t_CCLK

ms

¹Valid V_{DD_INT}assumes that the supply is fully ramped to its 1 volt rail. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design

of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles.

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4096 cycle count depends on t_SRSTspecification in Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

t_RSTVDD

RESET

V

t_EVDD-DDR2VDD

DDEXT

V

DD_DDR2

DDINT

t_{DDR2VDD_IVDD}

t_CLKVDD

CLKIN

t_CLKRST

CLK_CFG1-0

t_CORERST

t_PLLRST

RESETOUT

Figure 4. Power-Up Sequencing

Rev. PrA

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Page 23 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Clock Input

Table 14. Clock Input

400 MHz

Max

450 MHz

Unit

Parameter

Min

Max

Timing Requirements

t_CK

CLKIN Period

TBD¹

TBD²

TBD

TBD¹

TBD²

TBD

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK Period

3

2.5¹

TBD

2.22¹

TBD

¹Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

²Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.

³Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

.

t_CK

CLKIN

t_CKH

t_CKL

Figure 5. Clock Input

Clock Signals

The ADSP-2146x can use an external clock or a crystal. See the

CLKIN pin description in Table 6. Programs can configure the

processor to use its internal clock generator by connecting the

necessary components to CLKIN and XTAL. Figure 6 shows the

component connections used for a crystal operating in funda-

mental mode. Note that the clock rate is achieved using a 28.125

MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN

achieves a clock speed of 450 MHz). To achieve the full core

clock rate, programs need to configure the multiplier bits in the

PMCTL register. In case of ADSP-21462W and ADSP-21465W,

the maximum clock speed of 400 MHz is arrived at by using a 25

MHz crystal with the default multiplier of 16:1.

ADSP-2146X

R1

1M⍀*

XTAL

CLKIN

R2

47⍀*

C1

22pF

C2

22pF

Y1

29.125 MHz

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’S SPECIFICATIONS

*TYPICAL VALUES

Figure 6. 450 MHz Operation (Fundamental Mode Crystal)

Rev. PrA

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Page 24 of 60

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November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Reset

Table 15. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

RESET Pulse Width Low

TBD

ns

t_SRST

RESET Setup Before CLKIN Low

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 ms while RESET is low, assuming stable

V_DDand CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_WRST

t_SRST

RESET

Figure 7. Reset

Running Reset

The following timing specification applies to CLKOUT/

RESETOUT/RUNRSTIN pin when it is configured as

RUNRSTIN.

Table 16. Running Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRUNRST

t_SRUNRST

Running RESET Pulse Width Low

TBD

ns

Running RESET Setup Before CLKIN High

CLKIN

t

SRUNRST

WRUNRST

RUNRSTIN

Figure 8. Running Reset

Rev. PrA

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Page 25 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts as well as the DAI_P20-1 and

DPI_P14-1 pins when they are configured as interrupts.

Table 17. Interrupts

Parameter

Min

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

TBD

ns

DAI_P20

DPI_P14

1

-

FLAG2

(IRQ2

-0

t_IPW

-0)

Figure 9. Interrupts

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Table 18. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_WCTIM

CTIMER Pulse Width

TBD

ns

t_WCTIM

FLAG3

(CTIMER)

Figure 10. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0 and

Timer1 in PWM_OUT (pulse-width modulation) mode. Timer

signals are routed to the DPI_P14–1 pins through the DPI SRU.

Therefore, the timing specifications provided below are valid at

the DPI_P14–1 pins.

Table 19. Timer PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

t_PWMO

Timer Pulse Width Output

TBD

ns

t_PWMO

DPI_P14

(TIMER1

-

1

-0)

Figure 11. Timer PWM_OUT Timing

Rev. PrA

|

Page 26 of 60

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November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Timer WDTH_CAP Timing

The following timing specification applies to timer0 and timer1,

and in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the timing specification provided below is valid

at the DPI_P14–1 pins.

Table 20. Timer Width Capture Timing

Parameter

Timing Requirement

Min

TBD

Max

Unit

t_PWI

Timer Pulse Width

TBD

ns

t_PWI

DPI_P14

-1

(TIMER1-0)

Figure 12. Timer Width Capture Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to

DAI_PB02_O).

Table 21. DAI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI/DPI Pin Input Valid to DAI Output Valid

TBD

ns

DAI_Pn

DPI_Pn

DAI_Pm

DPI_Pm

t_DPIO

Figure 13. DAI Pin to Pin Direct Routing

Rev. PrA

|

Page 27 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 22. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIW

t_STRIG

Input Clock Period

TBD

ns

PCG Trigger Setup Before Falling Edge of PCG Input TBD

Clock

t_HTRIG

PCG Trigger Hold After Falling Edge of PCG Input

Clock

TBD

ns

Switching Characteristics

t_DPCGIO

PCGOutputClockandFrameSyncActiveEdgeDelay

After PCG Input Clock

TBD

ns

t_DTRIGCLK

PCG Output Clock Delay After PCG Trigger

PCG Frame Sync Delay After PCG Trigger

Output Clock Period

t_DTRIGFS

1

t_PCGOW

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2146x SHARC Processor Hardware Reference, “Precision Clock Generators”

chapter.

¹Normal mode of operation.

t_STRIG

t_HTRIG

DAI_Pn

DPI_Pn

PCG_TRIGx_I

t_PCGIW

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

DAI_Py

DPI_Py

PCG_CLKx_O

t_DTRIGCLK

t_DPCGIO

t_PCGOW

DAI_Pz

DPI_Pz

PCG_FSx_O

t_DTRIGFS

Figure 14. Precision Clock Generator (Direct Pin Routing)

Rev. PrA

|

Page 28 of 60

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November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Flags

The timing specifications provided below apply to

AMI_ADDR23-0 and AMI_DATA7-0 when configured as

FLAGS. See Table 6 on page 13 for more information on flag

use.

Table 23. Flags

Parameter

Timing Requirement

Min

Max

TBD

Unit

ns

t_FIPW

Switching Characteristic

t_FOPWDPI_P14-1, AMI_ADDR23-0, AMI_DATA7-0, FLAG3–0 OUT Pulse Width TBD

DPI_P14-1, AMI_ADDR23-0, AMI_DATA7-0, FLAG3–0 IN Pulse Width TBD

ns

DPI_P14

(FLAG3

(AMI_DATA7

(AMI_ADDR23-0)

-1

-0 )

IN

-

0)

t_FIPW

DPI_P14

(FLAG3

(AMI_DATA7

-1

-

0

)

OUT

-

0)

t_FOPW

AMI_ADDR23-0)

Figure 15. Flags

Rev. PrA

|

Page 29 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

DDR2 SDRAM Read Cycle Timing

Table 24. DDR2 SDRAM Read Cycle Timing, V_DD-DDR2nominal 1.8V

Parameter

Timing Requirements

TBD

Symbol

Minimum

Maximum Unit

TBD TBD

TBD

Figure 16. DDR2 SDRAM Controller Input AC Timing

Rev. PrA

|

Page 30 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

DDR2 SDRAM Write Cycle Timing

Table 25. DDR2 SDRAM Write Cycle Timing, V_DD-DDR2nominal 1.8V

Parameter

Switching Characteristics

TBD

Symbol

Minimum

Maximum Unit

TBD TBD

TBD

Figure 17. DDR2 SDRAM Controller Output AC Timing

Rev. PrA

|

Page 31 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 26. Memory Read—Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_DAD

Address, Selects Delay to Data Valid^{1, 2}

TBD

ns

t_DRLD

t_SDS

AMI_RD Low to Data Valid¹

Data Setup to AMI_RD High

t_HDRH

t_DAAK

t_DSAK

Data Hold from AMI_RD High^{3, 4}

AMI_ACK Delay from Address, Selects^{2, 5}

AMI_ACK Delay from AMI_RD Low⁴

Switching Characteristics

t_DRHA

t_DARL

t_RW

Address Selects Hold After AMI_RD High

Address Selects to AMI_RD Low²

ns

AMI_RD Pulse Width

t_RWR

AMI_RD High to AMI_WR, AMI_RD, Low

W = (number of wait states specified in AMICTLx register) × t_{DDR2_CLK}

.

HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x t_{DDR2_CLK}

IC = (number of idle cycles specified in AMICTLx register) x t_{DDR2_CLK}).

H = (number of hold cycles specified in AMICTLx register) x t_{DDR2_CLK}

.

¹Data delay/setup: System must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of AMI_MSx, is referenced.

³Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.

⁴Data hold: User must meet t_HDRHin asynchronous access mode. See Test Conditions on Page 53 for the calculation of hold times given capacitive and dc loads.

⁵AMI_ACK delay/setup: User must meet t_DAAK, or t_DSAK, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet t_DAAKor t_DSAK

.

ADDRESS

MSx

t_DRHA

t_DARL

t_RW

RD

t_DRLD

t_SDS

t_DAD

t_HDRH

DATA

t_DSAK

t_DAAK

t_RWR

ACK

WR

Figure 18. Memory Read—Bus Master

Rev. PrA

|

Page 32 of 60

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November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 27. Memory Write—Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_DAAK

t_DSAK

AMI_ACK Delay from Address, Selects^{1, 2}

AMI_ACK Delay from AMI_WR Low ^{1, 3}

TBD

ns

Switching Characteristics

t_DAWH

t_DAWL

t_WW

Address, Selects to AMI_WR Deasserted²

Address, Selects to AMI_WR Low²

ns

AMI_WR Pulse Width

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

t_WWR

Data Setup Before AMI_WR High

Address Hold After AMI_WR Deasserted

Data Hold After AMI_WR Deasserted

Data Disable After AMI_WR Deasserted⁴

AMI_WR High to AMI_WR, AMI_RD Low

Data Disable Before AMI_RD Low

AMI_WR Low to Data Enabled

t_DDWR

t_WDE

W = (number of wait states specified in AMICTLx register) × t_S_{DDR2_CLK}H = (number of hold cycles specified in AMICTLx register) x t_{DDR2_CLK}

¹AMI_ACK delay/setup: System must meet t_DAAK, or t_DSAK, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK(high) user must meet t_DAAKor t_DSAK

.

²The falling edge of AMI_MSx is referenced.

³Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.

⁴See Test Conditions on Page 53 for calculation of hold times given capacitive and dc loads.

ADDRESS

MSx

t_DAWH

t_DWHA

t_DAWL

t_WW

WR

t_WWR

t_WDE

t_DATRWH

t_DDWR

t_DDWH

DATA

t_DSAK

t_DWHD

t_DAAK

ACK

RD

Figure 19. Memory Write—Bus Master

that can be introduced in the transmission path between

Link Ports

LDATA and LCLK. Setup skew is the maximum delay that can

Calculation of link receiver data setup and hold relative to link

clock is required to determine the maximum allowable skew

be introduced in LDATA relative to LCLK, (setup skew = t_LCLK-

Rev. PrA

|

Page 33 of 60

|

November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

_TWHmin– t_DLDCH– t_SLDCL). Hold skew is the maximum delay

that can be introduced in LCLK relative to LDATA, (hold skew

= t_LCLKTWLmin – t_HLDCH– t_HLDCL). Calculations made directly

from speed specifications will result in unrealistically small skew

times because they include multiple tester guardbands. The

setup and hold skew times shown below are calculated to

include only one tester guardband.

Setup Skew = TBD ns max

Hold Skew = TBD ns max

Note that there is a two-cycle effect latency between the link

port enable instruction and the DSP enabling the link port.

Table 28. Link Ports – Receive

Parameter

Min

Max

Unit

Timing Requirements

t_SLDCL

Data Setup Before LCLK Low

Data Hold After LCLK Low

LCLK Period

TBD

ns

t_HLDCL

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

LCLK Width Low

LCLK Width High

Switching Characteristics

t_DLALC

LACK Low Delay After LCLK High¹

ns

¹LACK goes low with tDLALC relative to rise of LCLK after first byte, but does not go low if the receiver's link buffer is not about to fill.

t_LCLKIW

t_LCLKRWH

t_LCLKRWL

LCLK

t_HLDCL

t_SLDCL

IN

LDAT7-0

t_DLALC

LACK (OUT)

Figure 20. Link Ports—Receive

Rev. PrA

|

Page 34 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Table 29. Link Ports – Transmit

Parameter

Min

Max

Unit

Timing Requirements

t_SLACH

t_HLACH

LACK Setup Before LCLK High

LACK Hold After LCLK High

TBD

ns

Switching Characteristics

t_DLDCH

Data Delay After LCLK High

ns

t_HLDCH

Data Hold After LCLK High

LCLK Width Low

t_LCLKTWL

t_LCLKTWH

t_DLACLK

LCLK Width High

LCLK Low Delay After LACK High

LCLK INACTIVE

(HIGH)

LAST BYTE

TRANSMITTED

FIRST BYTE

TRANSMITTED

t_LCLKTWH

t_LCLKTWL

LCLK

t_DLDCH

t_HLDCH

LDAT7-0

OUT

t_DLACLK

t_SLACH

t_HLACH

LACK (IN)

THE t_SLACHREQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST BYTE TRANSMITTED.

Figure 21. Link Ports—Transmit

Rev. PrA

|

Page 35 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals (SCLK, FS, Data Channel A, Data Channel B)

are routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 30. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSE

FS Setup Before SCLK

(Externally Generated FS in either Transmit or Receive Mode)

TBD

ns

1

t_HFSE

FS Hold After SCLK

(Externally Generated FS in either Transmit or Receive Mode)

TBD

ns

1

t_SDRE

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

SCLK Width

1

t_HDRE

t_SCLKW

t_SCLK

SCLK Period

Switching Characteristics

2

t_DFSE

FS Delay After SCLK

(Internally Generated FS in either Transmit or Receive Mode)

TBD

ns

2

t_HOFSE

FS Hold After SCLK

(Internally Generated FS in either Transmit or Receive Mode)

TBD

ns

2

t_DDTE

Transmit Data Delay After Transmit SCLK

Transmit Data Hold After Transmit SCLK

2

t_HDTE

¹Referenced to sample edge.

²Referenced to drive edge.

Table 31. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSI

FS Setup Before SCLK

(Externally Generated FS in either Transmit or Receive Mode)

TBD

ns

1

t_HFSI

FS Hold After SCLK

(Externally Generated FS in either Transmit or Receive Mode)

TBD

ns

1

t_SDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

1

t_HDRI

Switching Characteristics

2

t_DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)

ns

2

t_HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)

FS Delay After SCLK (Internally Generated FS in Receive Mode)

FS Hold After SCLK (Internally Generated FS in Receive Mode)

Transmit Data Delay After SCLK

2

t_DFSIR

2

t_HOFSIR

2

t_DDTI

2

t_HDTI

Transmit Data Hold After SCLK

t_SCKLIW

Transmit or Receive SCLK Width

¹Referenced to the sample edge.

²Referenced to drive edge.

Rev. PrA

|

Page 36 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Table 32. Serial Ports—Enable and Three-State

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

TBD

ns

1

t_DDTTE

1

t_DDTIN

¹Referenced to drive edge.

Table 33. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS

with MCE = 1, MFD = 0

TBD

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

SAMPLE

DRIVE

DAI_P20-1

(SCLK)

t_SFSE/I

t_HFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

SAMPLE

DRIVE

DAI_P20-1

(SCLK)

t_SFSE/I

t_HFSE/I

DAI_P20-1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20

(DATA CHANNEL A/B)

-1

2ND BIT

t_DDTLFSE

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20

-

1 PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20

-

1 PINS.

THE CHARACTERIZED AC SPORT TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES

ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH SAU.

Figure 22. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified sample pair mode.

Rev. PrA

|

Page 37 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

DATA RECEIVE—INTERNAL CLOCK

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20

(SCLK)

-1

DAI_P20

(SCLK)

-1

t_DFSIR

t_DFSE

t_HFSE

t_HFSI

t_SFSI

t_SFSE

t_HOFSIR

t_HOFSE

DAI_P20

(FS)

-1

DAI_P20-1

(FS)

t_HDRE

t_SDRI

t_HDRI

t_SDRE

DAI_P20

(DATA CHANNEL A/B)

-

1

DAI_P20

(DATA CHANNEL A/B)

-1

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20

(SCLK)

-

1

DAI_P20

(SCLK)

-1

t_DFSI

t_DFSE

t_HFSI

t_HOFSI

t_SFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20

(FS)

-

1

DAI_P20-1

(FS)

t_DDTE

t_DDTI

t_HDTE

t_HDTI

DAI_P20

(DATA CHANNEL A/B)

-

1

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

SCLK

DAI_P20

SCLK (EXT)

-1

t_DDTEN

t_DDTTE

DAI_P20

(DATA CHANNEL A/B)

-1

DRIVE EDGE

DAI_P20

SCLK (INT)

-1

t_DDTIN

DAI_P20

-1

(DATA CHANNEL A/B)

Figure 23. Serial Ports

Rev. PrA

|

Page 38 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 34. IDP

signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1

pins using the SRU. Therefore, the timing specifications pro-

vided below are valid at the DAI_P20–1 pins.

Table 34. Input Data Port (IDP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SData Setup Before SCLK Rising Edge

SData Hold After SCLK Rising Edge

Clock Width

TBD

ns

1

t_SIHFS

1

t_SISD

1

t_SIHD

t_IDPCLKW

t_IDPCLK

Clock Period

1

AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t

IPDCLK

t_IPDCLKW

DAI_P20

(SCLK)

-1

t_SISFS

t_SIHFS

DAI_P20

(FS)

-1

t_SISD

t_SIHD

DAI_P20

(SDATA)

-

1

Figure 24. IDP Master Timing

Rev. PrA

|

Page 39 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Sample Rate Converter—Serial Input Port

The ASRC input signals (SCLK, FS, and SDATA) are routed

from the DAI_P20–1 pins using the SRU. Therefore, the timing

specifications provided in Table 35 are valid at the DAI_P20–1

pins.

Table 35. ASRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SDATA Setup Before SCLK Rising Edge

SDATA Hold After SCLK Rising Edge

Clock Width

TBD

ns

1

t_SRCHFS

1

t_SRCSD

1

t_SRCHD

t_SRCCLKW

t_SRCCLK

Clock Period

1

AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

t_SRCCLKW

DAI_P20

(SCLK)

-

1

t_SRCSFS

t_SRCHFS

DAI_P20

-

(FS)

t_SRCSD

t_SRCHD

DAI_P20

(SDATA)

-

Figure 25. ASRC Serial Input Port Timing

Rev. PrA

|

Page 40 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

and delay specification with regard to SCLK. Note that SCLK

rising edge is the sampling edge and the falling edge is the

drive edge.

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output, SDATA, has a hold time

Table 36. ASRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

Clock Width

TBD

ns

1

t_SRCHFS

t_SRCCLKW

t_SRCCLK

Clock Period

Switching Characteristics

1

t_SRCTDD

Transmit Data Delay After SCLK Falling Edge

Transmit Data Hold After SCLK Falling Edge

ns

1

t_SRCTDH

1

AMI_DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

t_SRCCLKW

DAI_P20

(SCLK)

-

1

t_SRCSFS

t_SRCHFS

DAI_P20

-

(FS)

t_SRCTDD

DAI_P20

(SDATA)

-

1

t_SRCTDH

Figure 26. ASRC Serial Output Port Timing

Rev. PrA

|

Page 41 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Reference. Note that the most significant 16 bits of external

PDAP data can be provided through the DATA7-0 pins. The

remaining four bits can only be sourced through DAI_P4–1.

The timing below is valid at the DATA7–0 pins.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 37. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the PDAP, see the

PDAP chapter of the ADSP-2146x SHARC Processor Hardware

Table 37. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge

PDAP_CLKEN Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

Clock Width

TBD

ns

1

t_HPCLKEN

1

t_PDSD

1

t_PDHD

t_PDCLKW

t_PDCLK

Clock Period

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

ns

1

Source pins of AMI_DATA are DATA7–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20

(PDAP_CLK)

-1

t_SPCLKEN

t_HPCLKEN

DAI_P20-1

(PDAP_CLKEN)

t_PDSD

t_PDHD

DATA

DAI_P20

(PDAP_STROBE)

-1

t_PDSTRB

t_PDHLDD

Figure 27. PDAP Timing

Rev. PrA

|

Page 42 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Pulse-Width Modulation Generators (PWM)

The following timing specifications apply when the

AMI_ADDR23-8 pins are configured as PWM.

Table 38. Pulse-Width Modulation (PWM) Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_PWMW

t_PWMP

PWM Output Pulse Width

PWM Output Period

TBD

ns

t_PWMW

PWM

OUTPUTS

t_PWMP

Figure 28. PWM Timing

Rev. PrA

|

Page 43 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left justified, I²S, or right justified with word widths of 16-, 18-,

20-, or 24-bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 29 shows the right-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data will be

right-justified to the next LRCLK transition.

DAI_P20-1

LRCLK

RIGHT CHANNEL

LEFT CHANNEL

DAI_P20-1

SCLK

LSB

MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB

DAI_P20-1

SDATA

Figure 29. Right-Justified Mode

Figure 30 shows the default I²S-justified mode. LRCLK is low

for the left channel and HI for the right channel. Data is valid on

the rising edge of SCLK. The MSB is left-justified to an LRCLK

transition but with a single SCLK period delay.

RIGHT CHANNEL

DAI_P20-1

LEFT CHANNEL

LRCLK

DAI_P20-1

SCLK

DAI_P20-1

MSB

MSB-1 MSB-2

LSB+2 LSB+1 LSB

MSB

MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB

SDATA

Figure 30. I²S-Justified Mode

Figure 31 shows the left-justified mode. LRCLK is high for the

left channel and LO for the right channel. Data is valid on the

rising edge of SCLK. The MSB is left-justified to an LRCLK

transition with no MSB delay.

DAI_P20-1

LRCLK

RIGHT CHANNEL

LEFT CHANNEL

DAI_P20-1

SCLK

LSB+2 LSB+1 LSB

MSB

MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB

MSB-1 MSB-2

MSB MSB+1

DAI_P20-1

SDATA

Figure 31. Left-Justified Mode

Rev. PrA

|

Page 44 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 39. Input signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Table 39. S/PDIF Transmitter Input Data Timing

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SData Setup Before SCLK Rising Edge

SData Hold After SCLK Rising Edge

Transmit Clock Width

TBD

ns

1

t_SIHFS

1

t_SISD

1

t_SIHD

t_SITXCLKW

t_SITXCLK

t_SISCLKW

t_SISCLK

Transmit Clock Period

Clock Width

Clock Period

1

AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

t_SITXCLKW

t_SITXCLK

SAMPLE EDGE

DAI_P20-1

(TXCLK)

t_SISCLKW

DAI_P20-1

(SCLK)

t_SISCLK

t_SIHFS

t_SISFS

DAI_P20-1

(FS)

t_SISD

t_SIHD

DAI_P20-1

(SDATA)

Figure 32. S/PDIF Transmitter Input Timing

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter has an oversampling clock. This TxCLK

input is divided down to generate the biphase clock.

Table 40. Over Sampling Clock (TxCLK) Switching Characteristics

Parameter

Min

TBD

Max

TBD

Unit

MHz

kHz

TxCLK Frequency for TxCLK = 384 × FS

TxCLK Frequency for TxCLK = 256 × FS

Frame Rate

Rev. PrA

|

Page 45 of 60

|

November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the TBD × FS clock.

Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

LRCLK Delay After SCLK

LRCLK Hold After SCLK

TBD

ns

t_HOFSI

t_DDTI

Transmit Data Delay After SCLK

Transmit Data Hold After SCLK

Transmit SCLK Width

t_HDTI

1

t_SCLKIW

¹SCLK frequency is TBD x FS where FS = the frequency of LRCLK.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20-1

(SCLK)

t_DFSI

t_HOFSI

DAI_P20-1

(FS)

t_DDTI

t_HDTI

DAI_P20-1

(DATA CHANNEL A/B)

Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. PrA

|

Page 46 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

SPI Interface—Master

The ADSP-21462W/ADSP-21465W/ADSP-21467 contains two

SPI ports. Both primary and secondary are available through

DPI only. The timing provided in Table 42 and Table 43 applies

to both.

Table 42. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid To SPICLK Edge (Data Input Setup Time)

TBD

ns

SPICLK Last Sampling Edge To Data Input Not Valid

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

TBD

ns

Serial Clock High Period

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

FLAG3–0IN (SPI device select) Low to First SPICLK Edge

Last SPICLK Edge to FLAG3–0IN High

Sequential Transfer Delay

ns

t_SPITDM

FLAG3-0

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICHM

t_DDSPIDM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0)

(OUTPUT)

t_SPICLM

SPICLK

(CP = 1)

(OUTPUT)

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

MSB

LSB

(INPUT)

VALID

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

t_HSPIDM

CPHASE = 0

MSB

VALID

LSB

VALID

MISO

(INPUT)

Figure 34. SPI Master Timing

Rev. PrA

|

Page 47 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

SPI Interface—Slave

Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial Clock Cycle

TBD

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

TBD

ns

t_HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

Data Input Valid to SPICLK edge (Data Input Set-up Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE=0)

TBD

ns

t_SSPIDS

t_HSPIDS

t_SDPPW

Switching Characteristics

t_DSOE

SPIDS Assertion to Data Out Active

TBD

ns

t_DSDHI

t_DDSPIDS

t_HDSPIDS

t_DSOV

SPIDS Deassertion to Data High Impedance

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHAS E = 0)

SPIDS

(INPUT)

t_{SPIC HS}

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0)

(INPUT)

t_SPICLS

t_SDSCO

t_SPICHS

SPICLK

(CP = 1)

(INPUT)

t_DSDHI

t_DDSPIDS

t_DSOE

t_DDSPIDS

t_HDSPIDS

MISO

(OUTPUT)

MSB

LSB

t_HSPIDS

CPHASE = 1

t_SSPIDS

MOSI

(INPUT)

MSB VALID

LSB VALID

t_HDSPIDS

t_DDSPIDS

t_DSDHI

MISO

(OUTPUT)

MSB

LSB

t_DSOV

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

(INPUT)

MSB VALID

LSB VALID

Figure 35. SPI Slave Timing

Rev. PrA

|

Page 48 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

ation of internal UART interrupts and the external data

operations. These latencies are negligible at the data transmis-

sion rates for the UART.

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing

Figure 36 describes UART port receive and transmit operations.

The maximum baud rate is PCLK/16 where PCLK = 1/tPCLK.

As shown in Figure 36 there is some latency between the gener-

Table 44. UART Port

Parameter

Min

Max

Unit

ns

Timing Requirement

1

t_RXD

Incoming Data Pulse Width

TBD

Switching Characteristic

t

_TXD1 Outgoing Data Pulse Width

ns

¹UART signals RXD and TXD are routed through DPI P14-1 pins using the SRU.

DPI_P14

[RXD]

-1

DATA(5-8)

STOP

RECEIVE

tRXD

INTERNAL

UART RECEIVE

INTERRUPT

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

START

DPI_P14

[TXD]

-1

DATA(5-8)

STOP(1-2)

TRANSMIT

tTXD

INTERNAL

UART TRANSMIT

INTERRUPT

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

Figure 36. UART Port—Receive and Transmit Timing

Rev. PrA

|

Page 49 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

TWI Controller Timing

Table 45 and Figure 37 provide timing information for the TWI

interface. Input Signals (SCL, SDA) are routed to the

DPI_P14–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DPI_P14–1 pins.

Table 45. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices¹

Standard Mode

Fast Mode

Parameter

f_SCL

Min

TBD

Max

TBD

Min

TBD

Max

TBD

Unit

kHz

SCL Clock Frequency

t_HDSTA

Hold Time (repeated) Start Condition. After This

Period, the First Clock Pulse is Generated.

TBD

μs

ns

μs

ns

t_LOW

Low Period of the SCL Clock

t_HIGH

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTO

t_BUF

High Period of the SCL Clock

TBD

Setup Time for a Repeated Start Condition

Data Hold Time for TWI-bus Devices

Data Setup Time

Setup Time for Stop Condition

Bus Free Time Between a Stop and Start Condition

t_SP

Pulse Width of Spikes Suppressed By the Input Filter n/a

n/a

TBD

¹All values referred to V_IHminand V_ILmaxlevels. For more information, see Electrical Characteristics on page 19.

DPI_P14-1

SDA

t_SUDAT

t_{HDS TA}

t_BUF

t_LOW

t_SP

DPI_P14-1

SCL

t_{SUS TA}

t_SUSTO

t_{HDS TA}

t_HIGH

S

P

Sr

S

t_{H DDAT}

Figure 37. Fast and Standard Mode Timing on the TWI Bus

Rev. PrA

|

Page 50 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

JTAG Test Access Port and Emulation

Table 46. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

TBD

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

1

t_SSYS

1

t_HSYS

t_TRSTW

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

ns

2

t_DSYS

¹System Inputs = AD15–0, CLKCFG1–0, RESET, BOOTCFG1–0, DAI_Px, and FLAG3–0.

²System Outputs = DAI_Px, AD15–0, AMI_RD, AMI_WR, FLAG3–0, CLKOUT, and EMU.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 38. IEEE 1149.1 JTAG Test Access Port

Rev. PrA

|

Page 51 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

Thermal Diode

TBD

Media Local Bus

TBD

Rev. PrA

|

Page 52 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

OUTPUT DRIVE CURRENTS

TESTER PIN ELECTRONICS

Figure 39 shows typical I-V characteristics for the output driv-

ers of the ADSP-21462W/ADSP-21465W/ADSP-21467. The

curves represent the current drive capability of the output driv-

ers as a function of output voltage.

50:

V

LOAD

T1

DUT

OUTPUT

45:

70:

ZO = 50:ꢀ(impedance)

TD = 4.04 r 1.18 ns

50:

0.5pF

4pF

2pF

12

10

400:

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

8

TBD

6

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

4

Figure 40. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

2

0

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

50

100

150

200

250

0

Figure 39. ADSP-21462W/ADSP-21465W/ADSP-21467 Typical Drive at Junc-

tion Temperature

TEST CONDITIONS

12

10

The ac signal specifications (timing parameters) appear in

Table 15 on Page 25 through Table 46 on Page 51. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 40.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 41. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

8

TBD

6

4

2

0

50

100

150

200

250

0

INPUT

OR

OUTPUT

Figure 42. Typical Output Rise/Fall Time (20% to 80%,

V_{DD_EXT}= Max)

1.5V

Figure 41. Voltage Reference Levels for AC Measurements

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 40). Figure 44 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 42, Figure 43, and Figure 44 may not be linear

Rev. PrA

|

Page 53 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

T_J= junction temperature °C

_CASE= case temperature (°C) measured at the top center of the

package

_JT= junction-to-top (of package) characterization parameter

is the Typical value from Table 47.

_D= power dissipation

T

12

10

Ψ

P

8

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first order approxi-

mation of T_Jby the equation:

TBD

6

4

T = T + (θ × P )

J

A

JA

D

2

0

where:

T_A= ambient temperature °C

50

100

150

200

250

0

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heatsink is required.

Figure 43. Typical Output Rise/Fall Time (20% to 80%,

V_{DD_EXT}= Min)

Values of θ_JBare provided for package comparison and PCB

design considerations. Note that the thermal characteristics val-

ues provided in Table 47 are modeled values.

12

10

Table 47. Thermal Characteristics for 324-Lead PBGA

Parameter

θ_JA

Condition

Typical

TBD

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

θ_JMA

TBD

8

θ_JMA

TBD

6

θ_JC

TBD

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

TBD

4

Ψ_JMT

TBD

2

0

50

100

150

200

250

0

Figure 44. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

THERMAL CHARACTERISTICS

The ADSP-21462W/ADSP-21465W/ADSP-21467 processor is

rated for performance over the temperature range specified in

Operating Conditions on Page 18.

Table 47 airflow measurements comply with JEDEC standards

JESD51-2 and JESD51-6 and the junction-to-board measure-

ment complies with JESD51-8. Test board design complies with

JEDEC standards JESD51-7 (PBGA). The junction-to-case mea-

surement complies with MIL- STD-883. All measurements use a

2S2P JEDEC test board.

To determine the junction temperature of the device while on

the application PCB, use:

T = T

+ (Ψ × P )

JT

D

J

CASE

where:

Rev. PrA

|

Page 54 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

BALL CONFIGURATION - ADSP-2146x

Figure 45 shows the ball configuration for the ASDP-2146x.

A1 CORNER

INDEX AREA

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18

A

B

C

D

E

F

D

R

D

S

D

G

A

H

J

K

L

M

N

P

R

T

U

V

D

R

V

DDINT

DD_DDR2

V

DDEXT

V

REF

T

A

S

V

SS

DD_THD

DD_A

V

NC

SS_A

I/O SIGNALS

Figure 45. ADSP-21462W/ADSP-21465W/ADSP-21467 Ball Configuration - Pin Out

Rev. PrA

|

Page 55 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

PBGA PINOUT

Table 48 lists the pin assignments of the SHARC processors.

Table 48. 19 mm by 19 mm PBGA Pin Assignment (Alphabetically by Signal)

Signal

AMI_ACK

Ball

R10

V16

U16

T16

R16

V15

U15

T15

Signal

BR3

Ball

T8

Signal

Ball

B17

A17

C18

C17

B18

C7

Signal

Ball

T1

DDR2_ADDR14

DDR2_ADDR15

DDR2_BA0

DDR2_BA1

DDR2_BA2

DDR2_CAS

DDR2_CKE

DDR2_CLK0

DPI_P03

DPI_P04

DPI_P05

DPI_P06

DPI_P07

DPI_P08

DPI_P09

DPI_P10

AMI_ADDR0

AMI_ADDR01

AMI_ADDR02

AMI_ADDR03

AMI_ADDR04

AMI_ADDR05

AMI_ADDR06

BR4

V9

U9

T9

R1

P1

P2

P3

P4

N1

N2

BR5

BR6

CLK_CFG0

CLK_CFG1

CLKIN

G1

G2

L1

E1

CLKOUT/RESETOUT M2

/RUNRSTIN

B7

AMI_ADDR07

AMI_ADDR08

AMI_ADDR09

AMI_ADDR10

AMI_ADDR11

AMI_ADDR12

AMI_ADDR13

AMI_ADDR14

AMI_ADDR15

AMI_ADDR16

AMI_ADDR17

AMI_ADDR18

AMI_ADDR19

AMI_ADDR20

AMI_ADDR21

AMI_ADDR22

AMI_ADDR23

AMI_DATA0

AMI_DATA1

AMI_DATA2

AMI_DATA3

AMI_DATA4

AMI_DATA5

AMI_DATA6

AMI_DATA7

AMI_MS0

R15

V14

U14

T14

R14

V13

U13

T13

R13

V12

U12

T12

R12

V11

U11

T11

R11

U18

T18

R18

P18

V17

U17

T17

R17

T10

U10

J4

DAI_P01

R7

DDR2_CLK0

DDR2_CLK1

DDR2_CS0

A7

DPI_P11

DPI_P12

DPI_P13

DPI_P14

EMU

N3

DAI_P02

V6

B13

A13

C1

N4

DAI_P03

U6

M3

M4

K2

DAI_P04

T6

DAI_P05

R6

DDR2_CS1

D1

C2

DAI_P06

V5

DDR2_CS2

FLAG0

R8

DAI_P07

U5

DDR2_CS3

D2

B2

FLAG1

V7

DAI_P08

T5

DDR2_DATA0

DDR2_DATA01

DDR2_DATA02

DDR2_DATA03

DDR2_DATA04

DDR2_DATA05

DDR2_DATA06

DDR2_DATA07

DDR2_DATA08

DDR2_DATA09

DDR2_DATA10

DDR2_DATA11

DDR2_DATA12

DDR2_DATA13

DDR2_DATA14

DDR2_DATA15

DDR2_DM0

DDR2_DM1

DDR2_DQS0

DDR2_DQS1

DDR2_ODT

FLAG2

U7

DAI_P09

R5

A2

FLAG3

T7

DAI_P10

V4

B3

ID_0

G3

DAI_P11

U4

A3

ID_1

G4

DAI_P12

T4

B5

ID_2

G5

DAI_P13

R4

A5

LACK_0

LACK_1

LCLK_0

LCLK_1

LDAT0_0

LDAT0_1

LDAT0_2

LDAT0_3

LDAT0_4

LDAT0_5

LDAT0_6

LDAT0_7

LDAT1_0

LDAT1_1

LDAT1_2

LDAT1_3

LDAT1_4

LDAT1_5

LDAT1_6

LDAT1_7

MLBCLK

MLBDO

K17

P17

J18

N18

E18

F17

F18

G17

G18

H16

H17

J16

K18

L16

L17

L18

M16

M17

N16

P16

K3

DAI_P14

V3

B6

DAI_P15

U3

A6

DAI_P16

T3

B8

DAI_P17

R3

A8

DAI_P18

V2

B9

DAI_P19

U2

A9

DAI_P20

T2

A11

B11

A12

B12

C3

DDR2_ADDR0

DDR2_ADDR01

DDR2_ADDR02

DDR2_ADDR03

DDR2_ADDR04

DDR2_ADDR05

DDR2_ADDR06

DDR2_ADDR07

DDR2_ADDR08

DDR2_ADDR09

DDR2_ADDR10

DDR2_ADDR11

DDR2_ADDR12

DDR2_ADDR13

D13

C13

D14

C14

B14

A14

D15

C15

B15

A15

D16

C16

B16

A16

C11

B4

AMI_MS1

A4

AMI_RD

B10

A10

B1

AMI_WR

V10

J2

BOOT_CFG0

BOOT_CFG1

BOOT_CFG2

BR1

J3

DDR2_RAS

C9

H3

DDR2_WE

C10

R2

V8

DPI_P01

BR2

U8

DPI_P02

U1

L4

Rev. PrA

|

Page 56 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

Table 48. 19 mm by 19 mm PBGA Pin Assignment (Alphabetically by Signal)

Signal

MLBSIG

MLBSO

MLDAT

RESET

RPBA

Ball

L2

Signal

Ball

N9

Signal

V_SS

Ball

E3

Signal

V_SS

Ball

L12

L10

L11

L9

V_DD

_

INT

THD

INT

L3

N8

D10

D17

D9

V_SS

K4

N7

V_SS

M1

R9

N6

V_SS

N13

M6

M13

L6

E5

V_SS

L14

M5

M7

M8

M9

M10

M11

M12

N14

N17

P5

TCK

K15

L15

M15

N12

N11

K16

N15

H1

E12

E13

E16

F2

V_SS

TDI

V_SS

TDO

V_SS

THD_M

THD_P

TMS

L13

K6

V_SS

F4

V_SS

K13

J6

F14

F16

G7

V_SS

TRST

V_SS

VDD_A

J13

H6

V_SS

V_DD

G16

G14

F5

G8

V_SS

_

DDR

EXT

2

H5

G9

V_SS

H14

H13

G6

G10

G11

G12

G15

H4

V_SS

P7

F3

V_SS

P9

F15

E7

V_SS

P11

P13

V1

G13

F9

V_SS

E2

V_SS

E17

E11

E10

D8

F8

H7

V_SS

V18

D4

F7

H8

V_REF

XTAL

F6

H9

D11

K1

F13

F12

F11

F10

E9

H10

H11

H12

J1

D6

D3

D18

C5

J7

C12

E17

P8

E8

J8

E6

J9

E15

E14

D12

N10

N9

J10

J11

J12

J14

J17

K5

P6

EXT

P15

P14

P12

P10

N5

EXT

N8

EXT

V_SS

H2

K7

EXT

_A

M18

M14

L5

A1

K8

EXT

A18

C4

K9

EXT

K10

K11

K12

L7

EXT

K14

J5

C6

EXT

C8

EXT

J15

F1

D5

EXT

D7

L8

INT

Rev. PrA

|

Page 57 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

OUTLINE DIMENSIONS

The ADSP-21462W/ADSP-21465W/ADSP-21467 processors

are available in a 19 mm by 19 mm PBGA lead-free package.

19.20

19.00 SQ

18.80

BALL A1

18 16 14 12 10

17 15 13 11

8

6

4

2

PAD CORNER

9

7

5

3

1

A

B

C

D

E

F

17.00

17.05

16.95 SQ

16.85

G

H

J

BSC SQ

K

L

M

N

P

R

T

1.00

BSC

U

V

BOTTOM VIEW

TOP VIEW

1.00 REF

DETAIL A

2.40

2.28

2.16

1.22

1.17

1.12

DETAIL A

0.61

NOM

0.50 NOM

0.40 MIN

0.70

0.60

0.50

0.20

COPLANARITY

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MS-034-BAR-2

Figure 46. 324-Ball Plastic Ball Grid Array [PBGA]

(B-324)

Dimensions shown in millimeters

Rev. PrA

|

Page 58 of 60

|

November 2008

Preliminary Technical Data

ADSP-21462W/ADSP-21465W/ADSP-21467

AUTOMOTIVE PRODUCTS

The ADSP-21462W and ADSP-21465W are available for auto-

motive applications with controlled manufacturing. Note that

these special models may have specifications that differ from the

general release models.

The automotive grade products shown in Table 49 are available

for use in automotive applications. Contact your local ADI

account representative or authorized ADI product distributor

for specific product ordering information. Note that all automo-

tive products are RoHS compliant.

Table 49. Automotive Products

On-Chip

Temperature Range¹SRAM

Model

ROM

Package Description

Package Option

–40°C to +85°C

5M bit

4M bit

324-Ball Plastic Ball Grid Array B-324-2

(PBGA)

AD21462WBBZ3xx

–40°C to +85°C

5M bit

4M bit

324-Ball Plastic Ball Grid Array B-324-2

(PBGA)

AD21465WBBZ3xx

¹Referenced temperature is ambient temperature.

ORDERING GUIDE

Temperature Range¹On-Chip

SRAM

Model

ADSP-21467KBZ-ENG^{2, 3, 4}

ROM

4 Mbit

Package Description

324-Ball Plastic Ball Grid Array B-324-2

(PBGA)

Package Option

0 °C to +70 °C

5 Mbit

1

2

3

4

Referenced temperature is ambient temperature.

Z =Part number subject to change.

Z =RoHS Compliant Part

Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/SHARC

Rev. PrA

|

Page 59 of 60 | November 2008

ADSP-21462W/ADSP-21465W/ADSP-21467

Preliminary Technical Data

registered trademarks are the property of their respective owners.

PR07900-0-11/08(PrA)

Rev. PrA

|

Page 60 of 60

|

November 2008


型号：	ADSP-21465W
厂家：	ADI
描述：	SHARC Processor material that is subject to change without notice SHARC处理器的材料，如有变更，恕不另行通知
文件：	总60页 (文件大小：814K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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