ADSP-21469KBCZ-4_技术文档

SHARC Processor

ADSP-21469

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM

Up to 450 MHz operating frequency

The ADSP-21469 processor is available with unique audio-

centric peripherals such as the digital applications

interface, DTCP (digital transmission content protection

protocol), serial ports, precision clock generators, S/PDIF

transceiver, asynchronous sample rate converters, input

data port, and more.

For complete ordering information, see Ordering Guide on

Page 70

Qualified for automotive applications, see Automotive Prod-

ucts on Page 70

Code compatible with all other members of the SHARC family

Internal Memory

SIMD Core

Block 0

RAM/ROM

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

Instruction

Cache

5 Stage

Sequencer

B2D

64-BIT

B0D

64-BIT

B3D

64-BIT

B1D

64-BIT

S

DAG1/2

PEx

Timer

PEy

DMD

64-BIT

DMD

64-BIT

Core Bus

Cross Bar

Internal Memory I/F

PMD 64-BIT

PMD

64-BIT

FLAGx/IRQx/

TMREXP

THERMAL

DIODE

IOD0 32-BIT

EPD BUS 64-BIT

JTAG

IOD1

32-BIT

PERIPHERAL

BUS 32-BIT

IOD0 BUS

FFT

DTCP/

MTM

FIR

IIR

PERIPHERAL BUS

EP

SPEP BUS

LINK

PORT

1-0

PDAP/

IDP

7-0

S/PDIF PCG ASRC

Tx/Rx

SPORT

7-0

CORE PCG

FLAGS

TIMER

CORE PWM

DDR2

CTL

TWI

SPI/B

UART

AMI

MLB

C

-

D

1-

0

A

-

D

3

-

0

FLAGS

3-0

External

Port

DPI Routing/Pins

DAI Routing/Pins

External Port Pin MUX

DPI Peripherals

DAI Peripherals

Peripherals

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.326.3113

www.analog.com

ADSP-21469

TABLE OF CONTENTS

Summary ............................................................... 1

Revision History ...................................................... 2

General Description ................................................. 3

Family Core Architecture ........................................ 4

Family Peripheral Architecture ................................ 7

System Design .................................................... 10

Development Tools ............................................. 11

Additional Information ........................................ 11

Related Signal Chains .......................................... 11

Pin Function Descriptions ....................................... 12

Unused DDR2 Pins ............................................. 12

Specifications ........................................................ 17

Operating Conditions .......................................... 17

Electrical Characteristics ....................................... 18

Absolute Maximum Ratings ................................... 20

ESD Sensitivity ................................................... 20

Package Information ............................................ 20

Timing Specifications ........................................... 21

Test Conditions .................................................. 58

Output Drive Currents ......................................... 58

Capacitive Loading .............................................. 59

Thermal Characteristics ........................................ 61

CSP_BGA Ball Assignment—Automotive Models .......... 63

CSP_BGA Ball Assignment—Standard Models .............. 66

Outline Dimensions ................................................ 69

Surface-Mount Design .......................................... 69

Automotive Products .............................................. 70

Ordering Guide ..................................................... 70

REVISION HISTORY

6/10—Revision 0: Initial Version

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ADSP-21469

GENERAL DESCRIPTION

The ADSP-21469 SHARC^®processor is a member of the SIMD

SHARC family of DSPs that feature Analog Devices’ Super Har-

vard Architecture. The processor is source code compatible with

the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x

DSPs, as well as with first generation ADSP-2106x SHARC pro-

cessors in SISD (single-instruction, single-data) mode. The

processor is a 32-bit/40-bit floating point processor optimized

for high performance audio applications with its large on-chip

SRAM, multiple internal buses to eliminate I/O bottlenecks, and

an innovative digital applications interface (DAI).

Table 2. SHARC Family Features (Continued)

Feature

ADSP-21469

UART

1

Link Ports

2

AMI Interface with 8-bit Support

Yes

SPI

2

Yes

TWI

Table 1 shows performance benchmarks for the ADSP-21469

processor, and Table 2 shows the product’s features.

SRC Performance

–128 dB

Package

324-ball CSP_BGA

Table 1. Processor Benchmarks

¹Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx,

DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass

management, delay, speaker equalization, graphic equalization, and more.

Decoder/postprocessor algorithm combination support varies depending upon

the chip version and the system configurations. Please visit www.analog.com for

complete product information and availability.

Speed

(at 450 MHz)

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with Reversal) 20.44 s

FIR Filter (Per Tap)¹

IIR Filter (Per Biquad)¹

²These products contain the Digital Transmission Content Protection protocol, a

proprietary security protocol. Contact your Analog Devices sales office for more

information.

1.11 ns

4.43 ns

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]

[4 × 4] × [4 × 1]

Figure 1 on Page 1 shows the two clock domains that make up

the ADSP-21469 processors. The core clock domain contains

the following features:

10.0 ns

17.78 ns

Divide (y/x)

6.67 ns

10.0 ns

• Two processing elements (PEx, PEy), each of which com-

prises an ALU, multiplier, shifter, and data register file

Inverse Square Root

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• One periodic interval timer with pinout

¹Assumes two files in multichannel SIMD mode

Table 2. SHARC Family Features

• PM and DM buses capable of supporting 2 × 64-bit data

transfers between memory and the core at every core pro-

cessor cycle

• On-chip SRAM (5M bit)

• On-chip mask-programmable ROM (4M bit)

Feature

ADSP-21469

450 MHz

5M Bits

N/A

Maximum Frequency

RAM

ROM

• JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points which allows flexible exception handling.

Figure 1 on Page 1 also shows the peripheral clock domain (also

known as the I/O processor) which contains the following

features:

Audio Decoders in ROM¹

DTCP Hardware Accelerator²

Pulse-Width Modulation

S/PDIF

No

Yes

DDR2 Memory Interface

DDR2 Memory Bus Width

Yes

• IOD0 (peripheral DMA) and IOD1 (external port DMA)

buses for 32-bit data transfers

16 Bits

Direct DMA from SPORTs to

External Memory

• Peripheral and external port buses for core connection

• External port with an AMI and DDR2 controller

• 4 units for PWM control

Yes

FIR, IIR, FFT Accelerator

MLB Interface

IDP

Yes

Automotive Models Only

• 1 MTM unit for internal-to-internal memory transfers

Yes

8

Serial Ports

DAI (SRU)/DPI (SRU2)

20/14 pins

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ADSP-21469

• Digital applications interface that includes four precision

clock generators (PCG), an input data port (IDP) for serial

and parallel interconnect, an S/PDIF receiver/transmitter,

four asynchronous sample rate converters, eight serial

ports, a flexible signal routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, a 2-

wire interface, one UART, two serial peripheral interfaces

(SPI), 2 precision clock generators (PCG) and a flexible

signal routing unit (DPI SRU).

As shown in Figure 1 on Page 1, the processor uses two compu-

tational units to deliver a significant performance increase over

the previous SHARC processors on a range of DSP algorithms.

With its SIMD computational hardware, the processors can

perform 2.7 GFLOPS running at 450 MHz and 2.4 GFLOPS

running at 400 MHz.

Timer

A core timer that can generate periodic software Interrupts. The

core timer can be configured to use FLAG3 as a timer expired

signal.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the processor’s enhanced Harvard

architecture, allow unconstrained data flow between computa-

tion units and internal memory. The registers in PEX are

referred to as R0-R15 and in PEY as S0-S15.

Context Switch

FAMILY CORE ARCHITECTURE

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result registers all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

The ADSP-21469 is code compatible at the assembly level with

the ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160,

and ADSP-21161, and with the first generation ADSP-2106x

SHARC processors. The ADSP-21469 shares architectural fea-

tures with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and

ADSP-2116x SIMD SHARC processors, as shown in Figure 2

and detailed in the following sections.

Universal Registers

These registers can be used for general-purpose tasks. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all system registers (control/status) of

the core.

The data bus exchange register (PX) permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM/DM data buses.

These registers contain hardware to handle the data width

difference.

SIMD Computational Engine

The ADSP-21469 contains two computational processing

elements that operate as a single-instruction, multiple-data

(SIMD) engine. The processing elements are referred to as PEX

and PEY and each contains an ALU, multiplier, shifter, and

register file. PEX is always active, and PEY may be enabled by

setting the PEYEN mode bit in the MODE1 register. When this

mode is enabled, the same instruction is executed in both pro-

cessing elements, but each processing element operates on

different data. This architecture is efficient at executing math

intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

Single-Cycle Fetch of Instruction and Four Operands

The processors feature an enhanced Harvard Architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 2). With the its separate program and data memory

buses and on-chip instruction cache, the processor can simulta-

neously fetch four operands (two over each data bus) and one

instruction (from the cache), all in a single cycle.

Instruction Cache

The processors contain an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

The two data address generators (DAGs) are used for indirect

addressing and implementing circular data buffers in hardware.

Circular buffers allow efficient programming of delay lines and

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ADSP-21469

S

JTAG

FLAG TIMER INTERRUPT CACHE

SIMD Core

PM ADDRESS 24

PM DATA 48

DMD/PMD 64

5 STAGE

PROGRAM SEQUENCER

DAG2

16x32

DAG1

16x32

PM ADDRESS 32

SYSTEM

I/F

DM ADDRESS 32

PM DATA 64

USTAT

4x32-BIT

PX

64-BIT

DM DATA 64

DATA

SWAP

RF

Rx/Fx

PEx

RF

Sx/SFx

PEy

ALU

SHIFTER

MULTIPLIER

ALU

SHIFTER MULTIPLIER

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MRF

80-BIT

MSF

80-BIT

ASTATy

STYKy

ASTATx

STYKx

Figure 2. SHARC Core Block Diagram

other data structures required in digital signal processing, and

are commonly used in digital filters and Fourier transforms.

The two DAGs of the processors contain sufficient registers to

allow the creation of up to 32 circular buffers (16 primary regis-

ter sets, 16 secondary). The DAGs automatically handle address

pointer wraparound, reduce overhead, increase performance,

and simplify implementation. Circular buffers can start and end

at any memory location.

Instruction Set Architecture (VISA), drops redundant/unused

bits within the 48-bit instruction to create more efficient and

compact code. The program sequencer supports fetching these

16-bit and 32-bit instructions from both internal and external

DDR2 memory. Source modules need to be built using the

VISA option in order to allow code generation tools to create

these more efficient opcodes.

On-Chip Memory

Flexible Instruction Set

The processors contain 5 Mbits of internal RAM. Each block

can be configured for different combinations of code and data

storage (see Table 4). Each memory block supports single-cycle,

independent accesses by the core processor and I/O processor.

The ADSP-21469 memory architecture, in combination with its

separate on-chip buses, allows two data transfers from the core

and one from the I/O processor in a single cycle.

The 48-bit instruction word accommodates a variety of parallel

operations for concise programming. For example, the

ADSP-21469 can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

The processor’s SRAM can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data, 106.7k

words of 48-bit instructions (or 40-bit data), or combinations of

different word sizes up to 5 Mbits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from

previous SHARC processors, the ADSP-21469 supports new

instructions of 16 and 32 bits. This feature, called Variable

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ADSP-21469

floating-point storage format is supported that effectively

doubles the amount of data that may be stored on-chip. Conver-

sion between the 32-bit floating-point and 16-bit floating-point

formats is performed in a single instruction. While each

memory block can store combinations of code and data,

accesses are most efficient when one block stores data using the

DM bus for transfers, and the other block stores instructions

and data using the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

The memory map in Table 3 displays the internal memory

address space of the ADSP-21469 processor.

The 48-bit space section describes what this address range looks

like to an instruction that retrieves 48-bit memory. The 32-bit

section describes what this address range looks like to an

instruction that retrieves 32-bit memory.

Non-Secured ROM

For non-secured ROM, booting modes are selected using the

BOOTCFG pins as shown in Table 8 on Page 10. In this mode,

emulation is always enabled, and the IVT is placed on the inter-

nal RAM except for the case where BOOTCFGx = 011.

ROM Based Security

The ADSP-21469 has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the processor does not boot-load any

external code, executing exclusively from internal ROM. Addi-

tionally, the processor is not freely accessible via the JTAG port.

Instead, a unique 64-bit key, which must be scanned in through

the JTAG or Test Access Port will be assigned to each customer.

The device ignores a wrong key. Emulation features are avail-

able after the correct key is scanned.

Digital Transmission Content Protection

The DTCP specification defines a cryptographic protocol for

protecting audio entertainment content from illegal copying,

intercepting, and tampering as it traverses high performance

digital buses, such as the IEEE 1394 standard. Only legitimate

entertainment content delivered to a source device via another

approved copy protection system (such as the DVD content

scrambling system) is protected by this copy protection system.

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming

there are no block conflicts). The total bandwidth is realized

using the DMD and PMD buses (2 × 64-bits, CCLK speed) and

the IOD0/1 buses (2 × 32-bit, PCLK speed).

Table 3. ADSP-21469 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 bits)

Instruction Word (48 bits)

Normal Word (32 bits)

Short Word (16 bits)

BLOCK 0 RAM

0x0004 9000–0x0004 EFFF

0x0008 C000-0x0009 3FFF

0x0009 2000-0x0009 DFFF

0x0012 4000–0x0013 BFFF

Reserved

0x0004 F000–0x0005 8FFF

0x0009 4000–0x0009 5554

0x0009 E000–0x000B 1FFF

0x0013 C000–0x0016 3FFF

BLOCK 1 RAM

0x0005 9000–0x0005 EFFF

0x000A C000-0x000B 3FFF

0x000B 2000-0x000B DFFF

0x0016 4000-0x0017 BFFF

Reserved

0x0005 F000–0x0005 FFFF

0x000B 4000–0x000B 5554

0x000B E000–0x000B FFFF

0x0017 C000–0x0017 FFFF

BLOCK 2 RAM

0x0006 0000–0x0006 3FFF

0x000C 0000–0x000C 5554

0x000C 0000-0x000C 7FFF

0x0018 0000–0x0018 FFFF

Reserved

0x0006 4000–0x0006 FFFF

0x000C 5555–0x000D 5554

0x000C 8000–0x000D FFFF

0x0019 0000–0x001B FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 3FFF

0x000E 0000–0x000E 5554

0x000E 0000–0x000E 7FFF

0x001C 0000–0x001C FFFF

Reserved

0x0007 4000–0x0007 FFFF

0x000E 5555–0x000F 5554

0x000E 8000–0x000F FFFF

0x001D 0000–0x001F FFFF

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ADSP-21469

VISA and ISA Access to External Memory

FAMILY PERIPHERAL ARCHITECTURE

The DDR2 controller on the ADSP-21469 processor supports

VISA code operation which reduces the memory load since the

VISA instructions are compressed. Moreover, bus fetching is

reduced because, in the best case, one 48-bit fetch contains three

valid instructions. Code execution from the traditional ISA

operation is also supported. Note that code execution is only

supported from bank 0 regardless of VISA/ISA. Table 5 shows

the address ranges for instruction fetch in each mode.

The ADSP-21469 family contains a rich set of peripherals that

support a wide variety of applications including high quality

audio, medical imaging, communications, military, test equip-

ment, 3D graphics, speech recognition, motor control, imaging,

and other applications.

External Port

The external port interface supports access to the external mem-

ory through core and DMA accesses. The external memory

address space is divided into four banks. Any bank can be pro-

grammed as either asynchronous or synchronous memory. The

external ports are comprised of the following modules.

• An Asynchronous Memory Interface which communicates

with SRAM, Flash, and other devices that meet the stan-

dard asynchronous SRAM access protocol. The AMI

supports 2M words of external memory in bank 0 and 4M

words of external memory in bank 1, bank 2, and bank 3.

• A DDR2 DRAM controller. External memory devices up to

2 Gbits in size can be supported.

• Arbitration Logic to coordinate core and DMA transfers

between internal and external memory over the external

port.

Table 5. External Bank 0 Instruction Fetch

Size in

Access Type Words

Address Range

ISA (NW)

4M

0x0020 0000 - 0x005F FFFF

0x0060 0000 – 0x00FF FFFF

VISA (SW)

10M

DDR2 Support

The ADSP-21469 supports a 16-bit DDR2 interface operating at

a maximum frequency of half the core clock. Execution from

external memory is supported. External memory devices up to

2 Gbits in size can be supported.

DDR2 DRAM Controller

External Memory

The DDR2 DRAM controller provides a 16-bit interface to up to

four separate banks of industry-standard DDR2 DRAM devices.

Fully compliant with the DDR2 DRAM standard, each bank can

have its own memory select line (DDR2_CS3 – DDR2_CS0),

and can be configured to contain between 32M bytes and

256M bytes of memory. DDR2 DRAM external memory

address space is shown in Table 6.

The external port on the processor provides a high perfor-

mance, glueless interface to a wide variety of industry-standard

memory devices. The external port may be used to interface to

synchronous and/or asynchronous memory devices through the

use of its separate internal DDR2 memory controller. The 16-bit

DDR2 DRAM controller connects to industry-standard syn-

chronous DRAM devices, while the second 8-bit asynchronous

memory controller is intended to interface to a variety of mem-

ory devices. Four memory select pins enable up to four separate

devices to coexist, supporting any desired combination of syn-

chronous and asynchronous device types. Non-DDR2 DRAM

external memory address space is shown in Table 4.

A set of programmable timing parameters is available to config-

ure the DDR2 DRAM banks to support memory devices.

Table 6. External Memory for DDR2 DRAM Addresses

Size in

Words

Table 4. External Memory for Non-DDR2 DRAM Addresses

Bank

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

62M

0x0020 0000 – 0x03FF FFFF

0x0400 0000 – 0x07FF FFFF

0x0800 0000 – 0x0BFF FFFF

0x0C00 0000 – 0x0FFF FFFF

Size in

Words

64M

Bank

Address Range

64M

Bank 0

Bank 1

Bank 2

Bank 3

2M

0x0020 0000 – 0x003F FFFF

0x0400 0000 – 0x043F FFFF

0x0800 0000 – 0x083F FFFF

0x0C00 0000 – 0x0C3F FFFF

64M

4M

Note that the external memory bank addresses shown are for

normal-word (32-bit) accesses. If 48-bit instructions, as well as

32-bit data, are both placed in the same external memory bank,

care must be taken while mapping them to avoid overlap.

4M

SIMD Access to External Memory

The DDR2 controller on the ADSP-21469 processor supports

SIMD access on the 64-bit EPD (external port data bus) which

allows to access the complementary registers on the PEy unit in

the normal word space (NW). This improves performance since

there is no need to explicitly load the complimentary registers as

in SISD mode.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

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ADSP-21469

of memory devices including SRAM, Flash, and EPROM, as well

as I/O devices that interface with standard memory control

lines. Bank 0 occupies a 2M word window and banks 1, 2, and 3

occupy a 4M word window in the processor’s address space but,

if not fully populated, these windows are not made contiguous

by the memory controller logic.

The DAI includes the peripherals described in the following

sections.

Serial Ports

The ADSP-21469 features eight synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports can support up to 16 transmit or 16 receive DMA

channels of audio data when all eight SPORTs are enabled, or

four full duplex TDM streams of 128 channels per frame.

The serial ports operate at a maximum data rate of f_PCLK/4.

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. One SPORT pro-

vides two transmit signals while the other SPORT provides the

two receive signals. The frame sync and clock are shared.

External Port Throughput

The throughput for the external port, based on a 400 MHz

clock, is 66M bytes/s for the AMI and 800M bytes/s for DDR2.

Link Ports

Two 8-bit wide link ports can connect to the link ports of other

DSPs or peripherals. Link ports are bidirectional ports having

eight data lines, an acknowledge line, and a clock line. Link

ports can operate at a maximum frequency of 166 MHz.

MediaLB

The ADSP-21469 automotive model has a MLB interface which

allows the processor to function as a media local bus device. It

includes support for both 3-pin and 5-pin media local bus pro-

tocols. It supports speeds up to 1024 FS (49.25 Mbits/sec,

FS = 48.1 kHz) and up to 31 logical channels, with up to 124

bytes of data per media local bus frame.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I²S mode

The MLB interface supports MOST25 and MOST50 data rates.

The isochronous mode of transfer is not supported.

• Packed I²S mode

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms). The PWM generator is capable of operating in two

distinct modes while generating center-aligned PWM wave-

forms: single update mode or double update mode.

• Left-justified mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the receiver/

transmitter can be formatted as left justified, I²S or right justi-

fied with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources, such as the

SPORTs, external pins, and the precision clock generators

(PCGs), and are controlled by the SRU control registers.

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

Asynchronous Sample Rate Converter

The asynchronous sample rate converter (ASRC) contains four

ASRC blocks, is the same core as that used in the AD1896 192

kHz stereo asynchronous sample rate converter, and provides

up to 128 dB SNR. The ASRC block is used to perform synchro-

nous or asynchronous sample rate conversion across

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the DAI pins

(DAI_P20–1).

independent stereo channels, without using internal processor

resources. The four SRC blocks can also be configured to oper-

ate together to convert multichannel audio data without phase

mismatches. Finally, the ASRC can be used to clean up audio

data from jittery clock sources such as the S/PDIF receiver.

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1 on Page 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

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ADSP-21469

Input Data Port

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory.

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

audio channels in I²S, left-justified sample pair, or right-justified

mode. One frame sync cycle indicates one 64-bit left/right pair,

but data is sent to the FIFO as 32-bit words (that is, one-half of a

frame at a time). The processor supports 24- and 32-bit I²S, 24-

and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-

justified formats.

Timers

The ADSP-21469 has a total of three timers: a core timer that

can generate periodic software interrupts and two general-

purpose timers that can generate periodic interrupts and be

independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

Precision Clock Generators

The precision clock generators (PCG) consist of four units—A,

B, C, and D, each of which generates a pair of signals (clock and

frame sync) derived from a clock input signal. The units are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

The core timer can be configured to use FLAG3 as a timer

expired signal, and each general-purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation. A single control and status register enables or dis-

ables both general-purpose timers independently.

2-Wire Interface Port (TWI)

Digital Peripheral Interface (DPI)

The TWI is a bidirectional, 2-wire serial bus used to move 8-bit

data while maintaining compliance with the I²C bus protocol.

The TWI master incorporates the following features:

The digital peripheral interface provides connections to two

serial peripheral interface (SPI) ports, one universal asynchro-

nous receiver-transmitter (UART), 12 flags, a 2-wire interface

(TWI), and two general-purpose timers. The DPI includes the

peripherals described in the following sections.

• 7-bit addressing

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

Serial Peripheral Interface

The ADSP-21469 SHARC processors contain two serial periph-

eral interface ports (SPI). The SPI is an industry-standard

synchronous serial link, enabling the SPI-compatible port to

communicate with other SPI compatible devices. The SPI con-

sists of two data pins, one device select pin, and one clock pin. It

is a full-duplex synchronous serial interface, supporting both

master and slave modes. The SPI port can operate in a multi-

master environment by interfacing with up to four other

SPI-compatible devices, either acting as a master or slave device.

The SPI-compatible peripheral implementation also features

programmable baud rate, clock phase, and polarities. The SPI-

compatible port uses open-drain drivers to support a multimas-

ter configuration and to avoid data contention.

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

I/O Processor Features

Automotive versions of the ADSP-21469 I/O processor provide

67 channels of DMA, while standard versions provide 36 chan-

nels of DMA, as well as an extensive set of peripherals that are

described in the following sections.

DMA Controller

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the ADSP-21469’s internal memory and its serial ports,

the SPI-compatible (serial peripheral interface) ports, the IDP

(input data port), the parallel data acquisition port (PDAP), or

the UART.

Up to 67 channels of DMA are available on the ADSP-21469

processors as shown in Table 7. Programs can be downloaded to

the ADSP-21469 using DMA transfers. Other DMA features

include interrupt generation upon completion of DMA trans-

fers, and DMA chaining for automatic linked DMA transfers.

UART Port

The processors provide a full-duplex Universal Asynchronous

Receiver/Transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface

standard. The UART port also includes support for 5 to 8 data

bits, 1 or 2 stop bits, and none, even, or odd parity. The UART

port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

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ADSP-21469

Delay Line DMA

Table 8. Boot Mode Selection

The ADSP-21469 processor provides delay line DMA function-

ality. This allows processor reads and writes to external delay

line buffers (and hence to external memory) with limited core

interaction.

BOOTCFG2–0

Booting Mode

000

001

010

011

SPI Slave Boot

SPI Master Boot

AMI Boot (for 8-bit Flash boot)

Scatter/Gather DMA

No boot occurs, processor executes from

internal ROM after reset

The ADSP-21469 processor provides scatter/gather DMA func-

tionality. This allows processor DMA reads/writes to/from non-

contiguous memory blocks.

100

101

Link Port 0 Boot

Reserved

Table 7. DMA Channels

Peripheral

SPORTs

DMA Channels

The Running Reset feature allows a user to perform a reset of

the processor core and peripherals, without resetting the PLL

and DDR2 DRAM controller or performing a Boot. The func-

tionality of the RESETOUT pin also acts as the input for

initiating a Running Reset. For more information, see the

ADSP-214xx SHARC Processor Hardware Reference.

16

8

IDP/PDAP

SPI

2

UART

2

External Port

Link Port

2

Power Supplies

2

The processors have separate power supply connections

for the internal (V_{DD_INT}), external (V_{DD_EXT}), and analog

(V_{DD_A}) power supplies. The internal and analog supplies must

meet the V_{DD_INT}specifications. The external supply must meet

the V_{DD_EXT}specification. All external supply pins must be con-

nected to the same power supply.

Accelerators

Memory-to-Memory

MLB¹

2

31

¹Automotive models only.

IIR Accelerator

Note that the analog supply pin (V_{DD_A}) powers the processor’s

internal clock generator PLL. To produce a stable clock, it is rec-

ommended that PCB designs use an external filter circuit for the

The IIR (infinite impulse response) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data, and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency.

V

_{DD_A}pin. Place the filter components as close as possible to

the V_{DD_A}/AGND pins. For an example circuit, see Figure 3. (A

recommended ferrite chip is the muRata BLM18AG102SN1D).

FFT Accelerator

ADSP-2146x

FFT accelerator implements radix-2 complex/real input, com-

plex output FFT with no core intervention. The FFT accelerator

runs at the peripheral clock frequency.

100nF

10nF

1nF

VDD_A

AGND

V

DD_INT

FIR Accelerator

HI Z FERRITE

BEAD CHIP

The FIR (finite impulse response) accelerator consists of a 1024

word coefficient memory, a 1024 word deep delay line for the

data, and four MAC units. A controller manages the accelerator.

The FIR accelerator runs at the peripheral clock frequency.

LOCATE ALL COMPONENTS

CLOSE TO VDD_A AND AGND PINS

Figure 3. Analog Power (V_{DD_A}) Filter Circuit

SYSTEM DESIGN

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V_{DD_INT}and GND. Use wide

traces to connect the bypass capacitors to the analog power

(V_{DD_A}) and ground (AGND) pins. Note that the V_{DD_A}and

AGND pins specified in Figure 3 are inputs to the processor and

not the analog ground plane on the board—the AGND pin

should connect directly to digital ground (GND) at the chip.

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

The internal memory of the ADSP-21469 boots at system

power-up from an 8-bit EPROM via the external port, link port,

an SPI master, or an SPI slave. Booting is determined by the

boot configuration (BOOTCFG2–0) pins in Table 8.

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ADSP-21469

Target Board JTAG Emulator Connector

Evaluation Kit

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21469 pro-

cessors to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processor stacks. The processor's JTAG interface ensures that

the emulator will not affect target system loading or timing.

Analog Devices offers a range of EZ-KIT Lite^®evaluation plat-

forms to use as a cost effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++^®development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate Emulator Hardware User's Guide.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

DEVELOPMENT TOOLS

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board Flash device to store

user-specific boot code, enabling the board to run as a stand-

alone unit without being connected to the PC.

The ADSP-21469 processor is supported with a complete set of

CROSSCORE^®software and hardware development tools,

including Analog Devices emulators and VisualDSP++^®devel-

opment environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-21469 processors.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom defined system. Connecting one of Analog Devices JTAG

emulators to the EZ-KIT Lite board enables high speed, non-

intrusive emulation.

EZ-KIT Lite Evaluation Board

For evaluation of the processors, use the EZ-KIT Lite^®board

being developed by Analog Devices. The board comes with on-

chip emulation capabilities and is equipped to enable software

development. Multiple daughter cards are available.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21469

architecture and functionality. For detailed information on the

ADSP-21469 family core architecture and instruction set, refer

to the SHARC Processor Programming Reference.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-

circuit emulation is assured by the use of the processor’s JTAG

interface—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the processor, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The processor must be halted to send data and com-

mands, but once an operation has been completed by the

emulator, the DSP system is set running at full speed with no

impact on system timing.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the "signal chain" entry in

Wikipedia or the Glossary of EE Terms on the Analog Devices

website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

The Application Signal Chains page in the Circuits from the

Lab^TMsite (http://www.analog.com/signalchains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

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ADSP-21469

PIN FUNCTION DESCRIPTIONS

UNUSED DDR2 PINS

When the DDR2 controller is not used:

• Leave the DDR2 signal pins floating.

• Internally, three-state the DDR2 I/O signals. This can be

done by setting the DIS_DDRCTL bit of DDR2CTL0

register.

• Power down the receive path by setting the PWD bits of the

DDR2PADCTLx register.

• Connect the V_{DD_DDR2}pins to the V_{DD_INT}supply.

• Leave V_REFfloating/unconnected.

Table 9. Pin Descriptions

State During/

Name

Type

After Reset

Description

AMI_ADDR_23–0

I/O/T (ipu)

High-Z/driven External Address. The processor outputs addresses for external memory and

low (boot)

High-Z

peripherals on these pins. The data pins can be multiplexed to support the PDAP (I)

and PWM (O). After reset, all AMI_ADDR_23–0pins are in external memory interface

mode and FLAG(0–3) pins are in FLAGS mode (default). When configured in the

IDP_PDAP_CTL register, IDPchannel0 scans the AMI_ADDR_23–0pins for parallel input

data. Unused AMI pins can be left unconnected.

AMI_DATA_7–0

AMI_ACK

I/O/T (ipu)

I (ipu)

External Data. The data pins can be multiplexed to support the external memory

interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset, all AMI_DATA

pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). Unused AMI

pins can be left unconnected.

Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK (low) to

add wait states to an external memory access. AMI_ACK is used by I/O devices,

memory controllers, or other peripherals to hold off completion of an external

memory access. Unused AMI pins can be left unconnected.

AMI_MS_0–1

O/T (ipu)

High-Z

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-

sponding banks of external memory on the AMI interface. The MS_1-0lines are

decoded memory address lines that change at the same time as the other address

lines. When no external memory access is occurring the MS_1-0lines are inactive; they

are active however when a conditional memory access instruction is executed,

whether or not the condition is true. Unused AMI pins can be left unconnected.

The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the

ADSP-214xx SHARC Processor Hardware Reference.

AMI_RD

AMI_WR

O/T (ipu)

High-Z

AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word

from external memory.

External Port Write Enable. AMI_WR is asserted when the processor writes a word

to external memory.

FLAG[0]/IRQ0

FLAG[1]/IRQ1

I/O (ipu)

FLAG[0] INPUT FLAG0/Interrupt Request0.

FLAG[1] INPUT FLAG1/Interrupt Request1.

FLAG[2]/IRQ2/

AMI_MS2

FLAG[2] INPUT FLAG2/Interrupt Request2/Async Memory Select2.

FLAG[3]/TMREXP/ I/O (ipu)

AMI_MS3

FLAG[3] INPUT FLAG3/Timer Expired/Async Memory Select3.

The following symbols appear in the Type column of Table 9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.

To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be

enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–63 k. The range

of an ipd resistor can be between 31 k–85 k.

In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

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ADSP-21469

Table 9. Pin Descriptions (Continued)

State During/

After Reset

Name

Type

Description

DDR2_ADDR_15–0O/T

High-Z/driven DDR2 Address. DDR2 address pins.

low

DDR2_BA_2-0

O/T

High-Z/driven DDR2 Bank Address Input. Defines which internal bank an ACTIVATE, READ, WRITE,

low

or PRECHARGE command is being applied to. BA_2–0define which mode registers,

including MR, EMR, EMR(2), and EMR(3) are loaded during the LOAD MODE REGISTER

command.

DDR2_CAS

DDR2_CKE

DDR2_CS_3-0

O/T

High-Z/driven DDR2 Column Address Strobe. Connect to DDR2_CAS pin; in conjunction with

high other DDR2 command pins, defines the operation for the DDR2 to perform.

High-Z/driven DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2 CKE

low signal.

High-Z/driven DDR2 Chip Select. All commands are masked when DDR2_CS_3-0is driven high.

high

DDR2_CS_3-0are decoded memory address lines. Each DDR2_CS_3-0line selects the

corresponding external bank.

DDR2_DATA_15-0I/O/T

High-Z

DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.

DDR2_DM_1-0

O/T

High-Z/driven DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled on

high

both edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA 7–0 and

DM1 corresponds to DDR2_DATA15–8.

DDR2_DQS_1-0

I/O/T (Differential) High-Z

Data Strobe. Output with Write Data. Input with Read Data. DQS0 corresponds to

DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8. Based on software

control via the DDR2CTL3 register, this pin can be single-ended or differential.

DDR2_RAS

DDR2_WE

O/T

High-Z/driven DDR2 Row Address Strobe. Connect to DDR2_RAS pin; in conjunction with other

high DDR2 command pins, defines the operation for the DDR2 to perform.

O/T

High-Z/driven DDR2 Write Enable. Connect to DDR2_WE pin; in conjunction with other DDR2

high command pins, defines the operation for the DDR2 to perform.

DDR2_CLK0,

DDR2_CLK1,

DDR2_CLK1

O/T (Differential)

High-Z/driven DDR2 Memory Clocks. Two differential outputs available via software control

low (DDR2CTL0register).Freerunning, minimumfrequencynotguaranteedduringreset.

DDR2_ODT

O/T

High-Z/driven DDR2 On Die Termination. ODT pin when driven high (along with other require-

low

ments) enables the DDR2 termination resistances. ODT is enabled/disabled

regardless of read or write commands.

The following symbols appear in the Type column of Table 9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.

To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be

enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–63 k. The range

of an ipd resistor can be between 31 k–85 k.

In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

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ADSP-21469

Table 9. Pin Descriptions (Continued)

State During/

After Reset

Name

Type

Description

DAI _P_20–1

I/O/T (ipu)

High-Z

Digital Applications Interface. These pins provide the physical interface to the DAI

SRU. The DAI SRU configuration registers define the combination of on-chip audio-

centric peripheral inputs or outputs connected to the pin and to the pin’s output

enable. The configuration registers of these peripherals then determine the exact

behavior of the pin. Any input or output signal present in the DAI SRU may be routed

to any of these pins. The DAI SRU provides the connection from the serial ports, the

S/PDIF module, input data ports (2), and the precision clock generators (4), to the

DAI_P20–1 pins.

DPI _P_14–1

I/O/T (ipu)

High-Z

Digital Peripheral Interface. These pins provide the physical interface to the DPI

SRU. The DPI SRU configuration registers define the combination of on-chip

peripheral inputs or outputs connected to the pin and to the pin’s output enable. The

configuration registers of these peripherals then determines the exact behavior of

the pin. Any input or output signal present in the DPI SRU may be routed to any of

these pins. The DPI SRU provides the connection from the timers (2), SPIs (2), UART

(1), flags (12), and general-purpose I/O (9) to the DPI_P14–1 pins.

LDAT0_7–0

LDAT1_7–0

I/O/T (ipd)

High-Z

Link Port Data (Link Ports 0–1). When configured as a transmitter, the port drives

both the data lines.

LCLK0

LCLK1

Link Port Clock (Link Ports 0–1). Allows asynchronous data transfers. When

configured as a transmitter, the port drives LCLKx lines. An external 25 k pull-down

resistor is required for the proper operation of this pin.

LACK0

LACK1

I/O/T (ipd)

High-Z

Link Port Acknowledge (Link Port 0–1). Provides handshaking. When the link ports

are configured as a receiver, the port drives the LACKx line. An external 25 k pull-

down resistor is required for the proper operation of this pin.

THD_P

I

Thermal Diode Anode. If unused, can be left floating.

Thermal Diode Cathode. If unused, can be left floating.

THD_M

MLBCLK¹

O

I (ipd)

Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-

nized to the MOST network and provides the timing for the entire MLB interface.

49.152 MHz at Fs = 48 kHz. If unused, can be left floating.

MLBDAT¹

MLBSIG¹

I/O/T (ipd) in 3 pin High-Z

mode. I/T (ipd) in 5

pin mode.

Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device

and is received by all other MLB devices including the MLB controller. The MLBDAT

line carries the actual data. In 5-pin MLB mode, this pin is an input only. If unused,

can be left floating.

I/O/T (ipd) in 3 pin High-Z

mode.

I/T(ipd) in 5 pin

mode.

Media Local Bus Signal. This is a multiplexed signal which carries the Channel/

Address generated by the MLB Controller, as well as the Command and RxStatus

bytes from MLB devices. In 5-pin mode, this pin is an input only. If unused, can be left

floating.

MLBDO¹

MLBSO¹

O/T (ipd)

High-Z

Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB

mode. This serves as the output data pin in 5-pin mode. If unused, can be left floating.

O/T (ipd)

Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB

mode. This serves as the output signal pin in 5-pin mode. If unused, can be left

floating.

The following symbols appear in the Type column of Table 9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.

To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be

enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–63 k. The range

of an ipd resistor can be between 31 k–85 k.

In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

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ADSP-21469

Table 9. Pin Descriptions (Continued)

State During/

After Reset

Name

TDI

Type

I (ipu)

O /T

I (ipu)

I

Description

Test Data Input (JTAG). Provides serial data for the boundary scan logic.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Mode Select (JTAG). Used to control the test state machine.

TDO

TMS

TCK

High-Z

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the device.

TRST

I (ipu)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the processor.

EMU

O/T (ipu)

I

High-Z

EmulationStatus. Must be connected to the ADSP-21469AnalogDevicesDSPTools

product line of JTAG emulators target board connector only.

CLK_CFG_1–0

Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that

the operating frequency can be changed by programming the PLL multiplier and

divider in the PMCTL register at any time after the core comes out of reset. The

allowed values are:

00 = 6:1

01 = 32:1

10 = 16:1

11 = reserved

CLKIN

I

Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures

the processors to use either its internal clock generator or an external clock source.

Connecting the necessary components to CLKIN and XTAL enables the internal clock

generator. Connecting the external clock to CLKIN while leaving XTAL unconnected

configures the processors to use the external clock source such as an external clock

oscillator. CLKIN may not be halted, changed, or operated below the specified

frequency.

XTAL

O

I

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

RESET

Processor Reset. Resets the processor to a known state. Upon deassertion, there is

a 4096 CLKIN cyclelatency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

RESETOUT/

RUNRSTIN

I/O (ipu)

Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also

has a second function as RUNRSTIN which is enabled by setting bit 0 of the

RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor

Hardware Reference.

BOOT_CFG_2–0

I

Boot Configuration Select. These pins select the boot mode for the processor. The

BOOT_CFG pins must be valid before RESET (hardware and software) is de-asserted.

The following symbols appear in the Type column of Table 9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.

To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be

enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–63 k. The range

of an ipd resistor can be between 31 k–85 k.

In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

¹The MLB pins are only available on automotive models of the ADSP-21469 processors. These pins are NC (no connect) on the standard models. For more information, see

CSP_BGA Ball Assignment—Automotive Models on Page 63, and CSP_BGA Ball Assignment—Standard Models on Page 66.

Rev. 0

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Page 15 of 72

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June 2010

ADSP-21469

Table 10. Pin List, Power and Ground

Name

Type

Description

V_DD

P

G

Internal Power

_

INT

EXT

A

External Power

Analog Power for PLL

Thermal Diode Power

DDR2 Interface Power

DDR2 Input Voltage Reference

Ground

THD

DDR

1

2

V_REF

GND

AGND

Analog Ground

¹Applies to DDR2 signals.

Rev. 0

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Page 16 of 72

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June 2010

ADSP-21469

SPECIFICATIONS

OPERATING CONDITIONS

450 MHz

Nom

400 MHz

Nom

Parameter¹

Description

Min

Max

Min

Max

Unit

V_DD

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

Analog Power Supply Voltage

DDR2 Controller Supply Voltage 1.7

Thermal Diode Supply Voltage

DDR2 Reference Voltage

1.05

3.13

1.05

1.1

3.3

1.1

1.8

3.3

0.9

1.15

3.47

1.15

1.9

3.47

0.96

1.0

3.13

1.0

1.05

3.3

1.05

1.8

3.3

0.9

1.1

3.47

1.1

1.9

3.47

0.96

V

_

INT

EXT

_A2

3, 4

1.7

DDR

THD

2

3.13

0.84

2.0

3.13

0.84

2.0

V_REF

5

V_IH

High Level Input Voltage @

V_{DD EXT}= Max

Low Level Input Voltage @ V_DD

= Min

_

5

V_IL

0.8

V

_

EXT

_CLKIN6

V_IH

_

High Level Input Voltage @

2.0

V_{DD EXT}= Max

Low Level Input Voltage @ V_DD

= Min

_

_CLKIN6

V_IL

_

1.32

_

V_{IL 2}(DC)

DC Low Level Input Voltage

DC High Level Input Voltage

AC Low Level Input Voltage

AC High Level Input Voltage

V_REF– 0.125

V_REF– 0.25

115

V_REF– 0.125

V_REF– 0.25

110

V

_DDR

V_IH₂(DC)

V_REF+ 0.125

_DDR

V_{IL 2}(AC)

_DDR

V_{IH 2}(AC)

V_REF+ 0.25

0

V_REF+ 0.25

0

_DDR

T_J

Junction Temperature 324-Lead

CSP_BGA @ T_AMBIENT0°C to +70°C

°C

T_J

Junction Temperature 324-Lead N/A

CSP_BGA @ T_AMBIENT–40°C to

+85°C

N/A

–40

125

°C

¹Specifications subject to change without notice.

²See Figure 3 on Page 10 for an example filter circuit.

³Applies to DDR2 signals.

4

If unused, see Unused DDR2 Pins on Page 12.

⁵Applies to input and bidirectional pins: AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0, DAI_Px, DPI_Px, BOOTCFGx, CLKCFGx, (RUNRSTIN), RESET, TCK, TMS, TDI,

TRST.

⁶Applies to input pin CLKIN.

Rev. 0

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Page 17 of 72

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June 2010

ADSP-21469

ELECTRICAL CHARACTERISTICS

450 MHz

Max

400 MHz

Max

Parameter¹

Description

Test Conditions

Min

Unit

2

V_OH

High Level Output @ V_{DD EXT}= Min, I_OH= –1.0 mA³2.4

2.4

V

_

Voltage

2

V_OL

Low Level Output

Voltage

@ V_{DD EXT}= Min, I_OL= 1.0 mA³

0.4

V

_

V_OH

High Level Output @ V_{DD DDR}= Min, IOH = –13.4

1.4

V

_DDR

2

_

Voltage for DDR2

mA

V_OL

Low Level Output

Voltage for DDR2

@ V_{DD DDR}= Min, IOL = 13.4 mA

0.29

10

0.29

10

V

_

DDR

2

_

4, 5

I_IH

High Level Input

Current

@ V_{DD EXT}= Max, V_IN= V_DD

μA

mA

pF

_

_EXT

Max

4, 6

I_IL

Low Level Input

Current

@ V_{DD EXT}= Max, V_IN= 0 V

10

_

5

I_ILPU

Low Level Input

Current Pull-up

@ V_{DD EXT}= Max, V_IN= 0 V

200

10

200

10

_

6

I_IHPD

High Level Input

Current Pull-down Max

@ V_{DD EXT}= Max, V_IN= V_DD

_

_EXT

7, 8

I_OZH

Three-StateLeakage @ V_{DD EXT}/V_{DD DDR}= Max,

Current

_

V_IN= V_{DD EXT}/V_DD

Max

_DDR

_

7, 9

I_OZL

Three-StateLeakage @ V_{DD EXT}/V_DD

Current

= Max,

10

_

_DDR

V_IN= 0 V

8

I_OZLPU

Three-StateLeakage @ V_{DD EXT}= Max, V_IN= 0 V

Current Pull-up

200

_

9

I_OZHPD

Three-StateLeakage @ V_{DD EXT}= Max,

_

Current Pull-down V_IN= V_DD

Max

_EXT

_INTYP10, 11

I_DD

-

Supply Current

(Internal)

f_CCLK> 0 MHz

Table 12 +

Table 13 × ASF

Table 12 +

Table 13 × ASF

_A12

I_DD

_

Supply Current

(Analog)

V_{DD A}= Max

10

_

13, 14

C_IN

Input Capacitance T_CASE= 25°C

5

¹Specifications subject to change without notice.

²Applies to output and bidirectional pins: AMI_ADDR23-0, AMI_DATA7-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO.

³See Output Drive Currents on Page 58 for typical drive current capabilities.

⁴Applies to input pins: BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

⁵Applies to input pins with internal pull-ups: TRST, TMS, TDI.

⁶Applies to input pins with internal pull-downs: MLBCLK

⁷Applies to three-statable pins: all DDR2 pins.

⁸Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

⁹Applies to three-statable pins with pull-downs: MLBDAT, MLBSIG, MLBDO, MLBSO, LDAT07-0, LDAT17-0, LCLK0, LCLK1, LACK0, LACK1.

¹⁰Typical internal current data reflects nominal operating conditions.

¹¹See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2146x SHARC Processors” for further information.

¹²Characterized but not tested.

¹³Applies to all signal pins.

¹⁴Guaranteed, but not tested.

Rev. 0

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Page 18 of 72

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June 2010

ADSP-21469

Total Power Dissipation

Total power dissipation has two components:

1. Internal power consumption

2. External power consumption

The ASF is combined with the CCLK frequency and V_{DD_INT}

dependent data in Table 13 to calculate this part. The second

part is due to transistor switching in the peripheral clock

(PCLK) domain, which is included in the I_{DD_INT}specification

equation.

Internal power consumption also comprises two components:

1. Static, due to leakage current. Table 12 shows the static cur-

rent consumption (I_DD-STATIC) as a function of junction

temperature (T_J) and core voltage (V_{DD_INT}).

Table 11. Activity Scaling Factors (ASF)¹

Activity

Scaling Factor (ASF)

2. Dynamic (I_DD-DYNAMC), due to transistor switching char-

acteristics and activity level of the processor. The activity

level is reflected by the Activity Scaling Factor (ASF), which

represents application code running on the processor core

and having various levels of peripheral and external port

activity (Table 11). Dynamic current consumption is calcu-

lated by scaling the specific application by the ASF and

using baseline dynamic current consumption as a

reference.

Idle

0.38

0.58

1.23

1.35

0.87

0.94

1.00

Low

High

Peak

Peak-typical (50:50)²

Peak-typical (60:40)

Peak-typical (70:30)

¹See Estimating Power for SHARC Processors (EE-348) for more information on

External power consumption is due to the switching activity of

the external pins.

the explanation of the power vectors specific to the ASF table.

²Ratio of continuous instruction loop (core) to DDR2 control code reads:writes.

Table 12. I_DD-STATIC(mA)

V_{DD_INT}(V)¹

T_J(°C)¹

0.95 V

72

1.0 V

91

1.05 V

110

119

131

145

166

192

223

260

302

354

413

484

566

660

768

896

1036

1198

1.10 V

140

149

163

182

206

237

273

318

367

428

497

578

674

783

912

1054

1220

1404

1.15 V

167

–45

–35

–25

–15

–5

79

99

181

89

109

122

140

162

189

222

259

305

359

421

496

580

683

794

921

1070

198

101

115

134

158

186

218

258

305

360

424

502

586

692

806

939

220

249

5

284

15

326

25

377

35

434

45

503

55

582

65

675

75

781

85

904

95

1048

1212

1394

1601

105

115

125

¹Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 17.

Rev. 0

|

Page 19 of 72

|

June 2010

ADSP-21469

Table 13. Baseline Dynamic Current in CCLK Domain (mA, with ASF = 1.0)¹

2

f_CCLK

Voltage (V_{DD_INT}

1.05 V

)

(MHz)²

0.95 V

78

1.0 V

82

1.10 V

91

1.15 V

98

100

150

200

250

300

350

400

450

86

115

150

186

222

259

293

N/A

121

159

197

236

275

309

N/A

130

169

208

249

288

328

366

136

177

219

261

304

344

385

142

188

231

276

319

361

406

¹The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 18.

²Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 17.

ABSOLUTE MAXIMUM RATINGS

PACKAGE INFORMATION

Stresses greater than those listed in Table 14 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

The information presented in Figure 4 provides details about

the package branding for the ADSP-21469 processors. For a

complete listing of product availability, see Ordering Guide on

Page 70.

a

Table 14. Absolute Maximum Ratings

ADSP-2146x

tppZ-cc

Parameter

Rating

vvvvvv.x n.n

Internal (Core) Supply Voltage (V_{DD INT}) –0.3 V to +1.32 V

_

yyww country_of_origin

Analog (PLL) Supply Voltage (V_DD

)

A

–0.3 V to +1.15 V

) –0.3 V to +3.6 V

_

S

External (I/O) Supply Voltage (V_DD

_EXT

Thermal Diode Supply Voltage (V_{DD THD}) –0.3 V to +3.6 V

_

DDR2 Controller Supply Voltage

(V_DD

–0.3 V to +1.9 V

Figure 4. Typical Package Brand

_

DDR2)

Table 15. Package Brand Information¹

DDR2 Input Voltage

–0.3 V to +1.9 V

–0.3 V to +3.6 V

–0.3 V to V_{DD_EXT}+0.5 V

–65C to +150C

125C

Input Voltage

Brand Key

Field Description

Temperature Range

Package Type

Output Voltage Swing

Storage Temperature Range

Junction Temperature While Biased

t

pp

Z

RoHS Compliant Option

See Ordering Guide

Assembly Lot Code

Silicon Revision

cc

ESD SENSITIVITY

vvvvvv.x

n.n

#

RoHS Compliant Designation

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

yyww

Date Code

¹Non-Automotive only. For branding information specific to Automotive

products, contact Analog Devices Inc.

Rev. 0

|

Page 20 of 72

|

June 2010

ADSP-21469

PLLD = Divider value 2, 4, 8, or 16 based on the PLLD value

programmed on the PMCTL register. During reset this value

is 2.

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 45 on Page 58 under Test Conditions for voltage refer-

ence levels.

In the following sections, Switching Characteristics specify how

the processor changes its signals. Circuitry external to the pro-

cessor must be designed for compatibility with these signal

characteristics. Switching characteristics describe what the pro-

cessor will do in a given circumstance. Use switching

characteristics to ensure that any timing requirement of a device

connected to the processor (such as memory) is satisfied.

f

_INPUT= input frequency to the PLL

_INPUT= CLKIN when the input divider is disabled, or

_INPUT= CLKIN  2 when the input divider is enabled

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in and

Table 16. All of the timing specifications for the ADSP-21469

peripherals are defined in relation to t_PCLK. See the peripheral

specific section for each peripheral’s timing information.

Table 16. Clock Periods

Timing

Requirements

Description

In the following sections, Timing Requirements apply to signals

that are controlled by circuitry external to the processor, such as

the data input for a read operation. Timing requirements guar-

antee that the processor operates correctly with other devices.

t_CK

CLKIN Clock Period

t_CCLK

t_PCLK

Processor Core Clock Period

Peripheral Clock Period = 2 × t_CCLK

Figure 5 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the ADSP-214xx SHARC Processor Hard-

ware Reference.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 5). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Voltage Controlled Oscillator

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

f

_VCOspecified in Table 18.

• The product of CLKIN and PLLM must never exceed 1/2 of

f_VCO(max) in Table 18 if the input divider is not enabled

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed

f_VCO(max) in Table 18 if the input divider is enabled

(INDIV = 1).

The VCO frequency is calculated as follows:

f

_VCO= 2 × PLLM × f_INPUT

_CCLK= (2 × PLLM × f_INPUT) ÷ (PLLD)

where:

_VCO= VCO output

f

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

Rev. 0

|

Page 21 of 72

|

June 2010

ADSP-21469

PMCTL

(LCLKR)

PMCTL

(PLLBP)

LINK PORT

CLOCK

DIVIDER

PLL

PLLI

CLK

LCLK

CLKIN

LOOP

FILTER

PLL

DIVIDER

VCO

DIVIDER

f_INPUT

PMCTL

XTAL

BUF

(DDR2CKR)

PMCTL

(PLLD)

CLK_CFGx/

PMCTL

(INDIV)

PLL

MULTIPLIER

f_CCLK

DDR2

DIVIDER

PMCTL

(PLLBP)

CCLK

DDR2_CLK

CLK_CFGx/PMCTL (2xPLLM)

PCLK

DIVIDE

BY 2

PCLK

CCLK

CLKOUT (TEST ONLY)

DELAY OF

4096 CLKIN

CYCLES

RESETOUT

BUF

RESETOUT

CORERST

RESET

Figure 5. Core Clock and System Clock Relationship to CLKIN

Rev. 0

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Page 22 of 72

|

June 2010

ADSP-21469

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 17. While no specific power-up sequencing is required

sharing these signals on the board must determine if there

are any issues that need to be addressed based on this

behavior.

between V_{DD EXT}, V_DD

₂, and V_{DD INT}, there are some consider-

_

ations that the system^Dd^De^Rsigns shou^_ld take into account.

Note that during power-up, when the V_{DD INT}power supply

_

• No power supply should be powered up for an extended

period of time (> 200 ms) before another supply starts to

ramp up.

comes up after V_{DD EXT}, a leakage current of the order of three-

_

state leakage current pull-up, pull-down may be observed on

any pin, even if that pin is an input only (for example the RESET

pin) until the V_{DD INT}rail has powered up.

_

• If V_{DD INT}power supply comes up after V_{DD EXT}, any pin,

_

such as RESETOUT and RESET, may actually drive

momentarily until the V_{DD INT}rail has powered up. Systems

_

Table 17. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

t_IVDD

RESET Low Before V_{DD INT}or V_{DD EXT}or V_{DD 2}On

0

ms

_

_DDR

V_{DD INT}On Before V_DD

–200

0

10²

20³

+200

200

-

EVDD

_

_EXT

t_EVDD

V_{DD EXT}On Before V_DD

_ _DDR

_

DDR

1

2

VDD

2

t_CLKVDD

t_CLKRST

t_PLLRST

CLKIN Valid After V_{DD INT}or V_{DD EXT}or V_{DD 2}Valid

_ _ _DDR

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

Switching Characteristic

4, 5

t_CORERST

Core Reset Deasserted After RESET Deasserted

4096 × t_CK+ 2 × t_CCLK

ms

¹Valid V_{DD INT}assumes that the supply is fully ramped to its nominal value. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the

design of^_the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles.

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4096 cycle count depends on t_SRSTspecification in Table 19. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

t_RSTVDD

RESET

V

DDINT

t_IVDDEVDD

V

DDEXT

t_CLKVDD

CLKIN

t_CLKRST

CLK_CFG1–0

RESETOUT

t_PLLRST

t_CORERST

Figure 6. Power-Up Sequencing

Rev. 0

|

Page 23 of 72

|

June 2010

ADSP-21469

Clock Input

Table 18. Clock Input

400 MHz¹

Max

450 MHz²

Max

Parameter

Min

Unit

Timing Requirements

t_CK

CLKIN Period

15³

7.5

100

45

13.26

6.63

100

45

ns

t_CKL

t_CKH

t_CKRF

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK Period

ns

45

3⁴

45

3⁴

ns

5

t_CCLK

2.5

10

2.22

200

10

ns

6

f_VCO

VCO Frequency

200

–250

900

+250

900

+250

MHz

ps

7, 8

t_CKJ

CLKIN Jitter Tolerance

–250

¹Applies to all 400 MHz models. See Ordering Guide on Page 70.

²Applies to all 450 MHz models. See Ordering Guide on Page 70.

³Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.

⁴Guaranteed by simulation but not tested on silicon.

⁵Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

⁶See Figure 5 on Page 22 for VCO diagram.

.

⁷Actual input jitter should be combined with ac specifications for accurate timing analysis.

⁸Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

t_CKJ

t_CK

CLKIN

t_CKH

t_CKL

Figure 7. Clock Input

Clock Signals

The ADSP-21469 can use an external clock or a crystal. See the

CLKIN pin description in Table 9. Programs can configure the

processor to use its internal clock generator by connecting the

necessary components to CLKIN and XTAL. Figure 8 shows the

component connections used for a crystal operating in funda-

mental mode. Note that the clock rate is achieved using a

25 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN

achieves a clock speed of 400 MHz).

ADSP-2146x

R1

XTAL

R2

CLKIN

1Mꢀ*

47ꢀ*

C1

22pF

C2

22pF

Y1

To achieve the full core clock rate, programs need to configure

the multiplier bits in the PMCTL register.

25.000 MHz

*TYPICAL VALUES

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’S SPECIFICATIONS

Figure 8. Recommended Circuit for

Fundamental Mode Crystal Operation

Rev. 0

|

Page 24 of 72

|

June 2010

ADSP-21469

Reset

Table 19. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

RESET Pulse Width Low

4 × t_CK

8

ns

t_SRST

RESET Setup Before CLKIN Low

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 ms while RESET is low, assuming stable

V_DDand CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_WRST

t_SRST

RESET

Figure 9. Reset

Running Reset

The following timing specification applies to

RESETOUT/RUNRSTIN pin when it is configured as

RUNRSTIN.

Table 20. Running Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRUNRST

t_SRUNRST

Running RESET Pulse Width Low

4 × t_CK

8

ns

Running RESET Setup Before CLKIN High

CLKIN

t_WRUNRST

t_SRUNRST

RUNRSTIN

Figure 10. Running Reset

Rev. 0

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June 2010

ADSP-21469

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts as well as the DAI_P20–1 and

DPI_P14–1 pins when they are configured as interrupts.

Table 21. Interrupts

Parameter

Min

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

2 × t_PCLK+ 2

ns

INTERRUPT

INPUTS

t_IPW

Figure 11. Interrupts

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP).

Table 22. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_WCTIM

TMREXP Pulse Width

4 × t_PCLK– 1

ns

t_WCTIM

FLAG3

(TMREXP)

Figure 12. Core Timer

Rev. 0

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June 2010

ADSP-21469

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0 and

Timer1 in PWM_OUT (pulse-width modulation) mode. Timer

signals are routed to the DPI_P14–1 pins through the DPI SRU.

Therefore, the timing specifications provided below are valid at

the DPI_P14–1 pins.

Table 23. Timer PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

t_PWMO

Timer Pulse Width Output

2 × t_PCLK– 1.2

2 × (2³¹– 1) × t_PCLK

ns

t_PWMO

PWM

OUTPUTS

Figure 13. Timer PWM_OUT Timing

Timer WDTH_CAP Timing

The following timing specification applies to Timer0 and

Timer1 in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DPI_P14–1 pins.

Table 24. Timer Width Capture Timing

Parameter

Min

Max

Unit

Timing Requirement

t_PWI

Timer Pulse Width

2 × t_PCLK

2 × (2³¹– 1) × t_PCLK

ns

t_PWI

TIMER

CAPTURE

INPUTS

Figure 14. Timer Width Capture Timing

Rev. 0

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June 2010

ADSP-21469

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to

DAI_PB02_O).

Table 25. DAI and DPI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid

1.5

12

ns

DAI_Pn

DPI_Pn

t_DPIO

DAI_Pm

DPI_Pm

Figure 15. DAI and DPI Pin to Pin Direct Routing

Rev. 0

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June 2010

ADSP-21469

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 26. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIW

t_STRIG

Input Clock Period

t_PCLK× 4

ns

PCG Trigger Setup Before Falling Edge of PCG Input 4.5

Clock

t_HTRIG

PCG Trigger Hold After Falling Edge of PCG Input

Clock

3

ns

Switching Characteristics

t_DPCGIO

PCGOutputClockandFrameSyncActiveEdgeDelay 2.5

After PCG Input Clock

10

ns

t_DTRIGCLK

PCG Output Clock Delay After PCG Trigger

PCG Frame Sync Delay After PCG Trigger

Output Clock Period

2.5 + (2.5 × t_PCGIP

)

2.5 + ((2.5 + D – PH) × t_PCGIP

2 × t_PCGIP– 1

10 + (2.5 × t_PCGIP)

t_DTRIGFS

)

10 + ((2.5 + D – PH) × t_PCGIP)

1

t_PCGOW

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators”

chapter.

¹Normal mode of operation.

t_STRIG

t_HTRIG

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

t_PCGIW

DAI_Py

DPI_Py

PCK_CLKx_O

t_DTRIGCLK

t_PCGOW

t_DPCGIO

DAI_Pz

DPI_Pz

PCG_FSx_O

t_DTRIGFS

Figure 16. Precision Clock Generator (Direct Pin Routing)

Rev. 0

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June 2010

ADSP-21469

Flags

The timing specifications provided below apply to

AMI_ADDR23–0 and AMI_DATA7–0 when configured as

FLAGS. See Table 9 on Page 12 for more information on flag

use.

Table 27. Flags

Parameter

Min

Max

Unit

ns

Timing Requirement

t_FIPW

DPI_P14–1, AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0 IN Pulse Width

2 × t_PCLK+ 3

2 × t_PCLK– 3

Switching Characteristic

t_FOPW

DPI_P14–1, AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0 OUT Pulse Width

ns

FLAG

INPUTS

t_FIPW

FLAG

OUTPUTS

t_FOPW

Figure 17. Flags

Rev. 0

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June 2010

ADSP-21469

DDR2 SDRAM Read Cycle Timing

Table 28. DDR2 SDRAM Read Cycle Timing, V_DD-DDR2Nominal 1.8 V

200 MHz¹

Max

225 MHz¹

Max

Parameter

Min

Unit

Timing Requirements

t_AC

DQ Output Access Time From CK/CK

–1.0

0.7

–1.0

0.7

ns

t_DQSCK

t_DQSQ

t_QH

DQS Output Access Time From CK/CK

DQS-DQ Skew for DQS and Associated DQ Signals

DQ, DQS Output Hold Time From DQS

Read Preamble

0.7

0.450

ns

t_CK

1.9

1.71

0.6

t_RPRE

t_RPST

0.6

Read Postamble

0.25

Switching Characteristics

t_CK

t_CH

t_CL

t_AS

t_AH

Clock Cycle Time

4.8

4.22

2.05

1.65

0.9

ns

Minimum Clock Pulse Width

Maximum Clock Pulse Width

Address Setup Time

2.35

1.85

1.0

2.75

2.45

Address Hold Time

¹In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed (see Engineer-to-Engineer Note EE-349).

t_CK

t_CH

t_CL

DDR2_CLKx

t_AS

t_AH

DDR2_ADDR

DDR2_CTL

t_AC

t_DQSCK

t_RPRE

DDR2_DQSn

t_DQSQ

t_RPST

t_QH

t_DQSQ

t_QH

DDR2_DATA

Figure 18. DDR2 SDRAM Controller Input AC Timing

Rev. 0

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June 2010

ADSP-21469

DDR2 SDRAM Write Cycle Timing

Table 29. DDR2 SDRAM Write Cycle Timing, V_DD-DDR2Nominal 1.8 V

200 MHz¹

Max

225 MHz¹

Max

Parameter

Min

Unit

Switching Characteristics

t_CK

Clock Cycle Time

4.8

4.22

2.05

–0.45

ns

t_CH

Minimum Clock Pulse Width

Maximum Clock Pulse Width

2.35

2.75

0.4

2.45

0.45

t_CL

2

t_DQSS

DQS Latching Rising Transitions to Associated Clock –0.4

Edges

t_DS

Last Data Valid to DQS Delay

0.6

0.5

ns

t_CK

ns

t_DH

t_DSS

t_DSH

DQS to First Data Invalid Delay

DQS Falling Edge to Clock Setup Time

DQS Falling Edge Hold Time From CK

DQS Input HIGH Pulse Width

0.65

1.95

2.05

2.0

0.55

1.65

1.8

t_DQSH

t_DQSL

t_WPRE

t_WPST

t_AS

1.65

0.8

DQS Input LOW Pulse Width

Write Preamble

0.8

Write Postamble

0.5

Control/address Maximum Delay From DDCK Rise

Control/Address Minimum Delay From DDCK Rise

1.85

1.0

1.65

0.9

t_AH

¹In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed (see Engineer-to-Engineer Note No: EE-349).

²Write command to first DQS delay = WL × t_CK+ t_DQSS

.

t_CK

t_CH

t_CL

DDR2_CLKx

t_AS

t_AH

DDR2_ADDR

DDR2_CTL

t_DSH

t_DSS

t_DQSS

DDR2_DQSn

t_DQSL

t_DQSH

t_WPST

t_WPRE

t_DS

t_DH

DDR2_DATA/DM

Figure 19. DDR2 SDRAM Controller Output AC Timing

Rev. 0

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June 2010

ADSP-21469

AMI Read

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 30. Memory Read

Parameter

Min

Max

Unit

Timing Requirements

t_DAD

Address, Selects Delay to Data Valid^{1, 2}

AMI_RD Low to Data Valid¹

W + t_{DDR CLK}–5.4

ns

2_

t_DRLD

t_SDS

W – 3.2

Data Setup to AMI_RD High

2.5

0

t_HDRH

t_DAAK

t_DSAK

Data Hold from AMI_RD High^{3, 4}

AMI_ACK Delay from Address, Selects^{2, 5}

AMI_ACK Delay from AMI_RD Low⁴

t_DDR

–9.5 + W

2_CLK

W – 7.0

Switching Characteristics

t_DRHA

t_DARL

t_RW

Address Selects Hold After AMI_RD High

RH + 0.20

ns

Address Selects to AMI_RD Low²

t_DDR

– 3.8

2_CLK

AMI_RD Pulse Width

W – 1.4

HI + t_DDR

t_RWR

AMI_RD High to AMI_RD Low

– 1

2_CLK

W = (number of wait states specified in AMICTLx register) × t_DDR

.

2_CLK

RHC = (number of Read Hold Cycles specified in AMICTLx register) × t_DDR

Where PREDIS = 0

2_CLK

HI = RHC: Read to Read from same bank

HI = RHC + IC: Read to Read from different bank

HI = RHC + Max (IC, (4 × t_{DDR2_CLK})): Read to Write from same or different bank

Where PREDIS = 1

HI = RHC + Max(IC, (4 × t_{DDR2_CLK})): Read to Write from same or different bank

HI = RHC + (3 × tDDR2_CLK): Read to Read from same bank

HI = RHC + Max(IC, (3 × t_{DDR2_CLK})): Read to Read from different bank

IC = (number of idle cycles specified in AMICTLx register) × t_{DDR2_CLK}

H = (number of hold cycles specified in AMICTLx register) × t_{DDR2_CLK}

¹Data delay/setup: System must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of AMI_MSx, is referenced.

³Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.

⁴Data hold: User must meet t_HDRHin asynchronous access mode. See Test Conditions on Page 58 for the calculation of hold times given capacitive and dc loads.

⁵AMI_ACK delay/setup: User must meet t_DAAK, or t_DSAK, for deassertion of AMI_ACK (low).

Rev. 0

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Page 33 of 72

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June 2010

ADSP-21469

AMI_ADDR

AMI_MSx

t_DARL

t_RW

t_DRHA

AMI_RD

t_DRLD

t_SDS

t_DAD

t_HDRH

AMI_DATA

t_DSAK

t_RWR

t_DAAK

AMI_ACK

AMI_WR

Figure 20. AMI Read

Rev. 0

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Page 34 of 72

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June 2010

ADSP-21469

AMI Write

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 31. Memory Write

Parameter

Min

Max

Unit

Timing Requirements

t_DAAK

t_DSAK

AMI_ACK Delay from Address, Selects^{1, 2}

AMI_ACK Delay from AMI_WR Low ^{1, 3}

t_{DDR CLK}– 9.7 + W

ns

2_

W – 6

Switching Characteristics

t_DAWH

t_DAWL

t_WW

Address, Selects to AMI_WR Deasserted²

t_{DDR CLK}– 3.1+ W

ns

2_

Address, Selects to AMI_WR Low²

t_{DDR CLK}– 3

2_

AMI_WR Pulse Width

W – 1.3

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

t_WWR

Data Setup Before AMI_WR High

Address Hold After AMI_WR Deasserted

Data Hold After AMI_WR Deasserted

Data Disable After AMI_WR Deasserted⁴

AMI_WR High to AMI_WR Low⁵

Data Disable Before AMI_RD Low

AMI_WR Low to Data Enabled

t_{DDR CLK}– 3.0+ W

2_

H + 0.15

H

t_DDR

– 1.37 + H

t_DDR

+ 4.9 + H

2_CLK

t_{DDR CLK}– 1.5+ H

2_

t_DDWR

t_WDE

2t_{DDR CLK}– 6

2_

t_{DDR CLK}– 3.5

2_

W = (number of wait states specified in AMICTLx register) × t_{SDDR CLK}H = (number of hold cycles specified in AMICTLx register) × t_DDR

2_

2_CLK

¹AMI_ACK delay/setup: System must meet t_DAAK, or t_DSAK, for deassertion of AMI_ACK (low).

²The falling edge of AMI_MSx is referenced.

³Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.

⁴See Test Conditions on Page 58 for calculation of hold times given capacitive and dc loads.

⁵For Write to Write: t_{DDR2_CLK}+ H, for both same bank and different bank. For Write to Read: (3 × t_{DDR2_CLK}) + H, for the same bank and different banks.

AMI_ADDR

AMI_MSx

t_DAWH

t_DWHA

t_DAWL

t_WW

AMI_WR

t_WWR

t_WDE

t_DATRWH

t_DDWH

t_DDWR

AMI_DATA

t_DSAK

t_DWHD

t_DAAK

AMI_ACK

AMI_RD

Figure 21. AMI Write

Rev. 0

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Page 35 of 72

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June 2010

ADSP-21469

Link Ports

Calculation of link receiver data setup and hold relative to link

clock is required to determine the maximum allowable skew

that can be introduced in the transmission path length differ-

ence between LDATA and LCLK. Setup skew is the maximum

delay that can be introduced in LDATA relative to LCLK:

(setup skew = t_LCLKTWHmin – t_DLDCH– t_SLDCL). Hold skew is

the maximum delay that can be introduced in LCLK relative to

LDATA: (hold skew = t_LCLKTWLmin – t_HLDCH– t_HLDCL).

Table 32. Link Ports—Receive

Parameter

Min

Max

Unit

Timing Requirements

t_SLDCL

Data Setup Before LCLK Low

Data Hold After LCLK Low

LCLK Period

0.5

ns

t_HLDCL

1.5

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

t_LCLK(6 ns)

2.6

LCLK Width Low

LCLK Width High

2.6

Switching Characteristics

t_DLALC

LACK Low Delay After LCLK Low¹

5

12

ns

¹LACK goes low with t_DLALCrelative to rise of LCLK after first byte, but does not go low if the receiver's link buffer is not about to fill.

t_LCLKIW

t_LCLKRWH

t_LCLKRWL

LCLK

t_HLDCL

t_SLDCL

LDAT7–0

IN

t_DLALC

LACK (OUT)

Figure 22. Link Ports—Receive

Rev. 0

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Page 36 of 72

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June 2010

ADSP-21469

Table 33. Link Ports—Transmit

Parameter

Min

Max

Unit

Timing Requirements

t_SLACH

t_HLACH

Switching Characteristics

LACK Setup Before LCLK Low

8.5

0

ns

LACK Hold After LCLK Low

t_DLDCH

Data Delay After LCLK High

1

ns

t_HLDCH

Data Hold After LCLK High

LCLK Width Low

–1

t_LCLKTWL

t_LCLKTWH

t_DLACLK

0.5 × t_LCLK– 0.4

0.4 × t_LCLK– 0.4¹

t_LCLK– 2

0.6 × t_LCLK+ 0.4¹

0.5 × t_LCLK+ 0.4

t_LCLK+ 8

ns

LCLK Width High

LCLK Low Delay After LACK High

¹For 1:2.5 ratio. For other ratios this specification is 0.5 × t_LCLK– 1.

LAST BYTE

FIRST BYTE

1

t_LCLKTWHt_LCLKTWL

TRANSMITTED

LCLK

t_DLDCH

t_HLDCH

LDAT7–0

LACK (IN)

OUT

t_SLACH

t_HLACH

t_DLACLK

NOTES

The t_SLACHand t_HLACHspecifications apply only to the LACK falling edge. If these specifications are met,

LCLK would extend and the dotted LCLK falling edge would not occur as shown. The position of the

dotted falling edge can be calculated using the t_LCLKTWHspecification. t_LCLKTWHMin should be used for t _SLACH

and t_LCLKTWHMax for t_HLACH

.

Figure 23. Link Ports—Transmit

Rev. 0

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Page 37 of 72

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June 2010

ADSP-21469

Serial Ports

In slave transmitter mode and master receiver mode the maxi-

mum serial port frequency is f_PCLK/8. To determine whether

communication is possible between two devices at clock speed

n, the following specifications must be confirmed: 1) frame sync

delay and frame sync setup and hold, 2) data delay and data

setup and hold, and 3) serial clock (SCLK) width.

Serial port signals are routed to the DAI_P20–1 pins using the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins. In Figure 24 either the rising edge

or the falling edge of SCLK (external or internal) can be used as

the active sampling edge.

Table 34. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSE

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode)

2.5

ns

1

t_HFSE

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode)

ns

t_SDRE

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

SCLK Width

1.9

1

t_HDRE

t_SCLKW

t_SCLK

2.5

(t_PCLK× 4) ÷ 2 – 0.5

t_PCLK× 4

SCLK Period

Switching Characteristics

2

t_DFSE

Frame Sync Delay After SCLK

(Internally Generated Frame Sync in either Transmit or Receive Mode)

10.25

8.5

ns

2

t_HOFSE

Frame Sync Hold After SCLK

(Internally Generated Frame Sync in either Transmit or Receive Mode)

2

ns

2

t_DDTE

Transmit Data Delay After Transmit SCLK

Transmit Data Hold After Transmit SCLK

2

t_HDTE

¹Referenced to sample edge.

²Referenced to drive edge.

Table 35. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSI

Frame Sync Setup Before SCLK

7

(Externally Generated Frame Sync in either Transmit or Receive Mode)

ns

1

t_HFSI

Frame Sync Hold After SCLK

2.5

(Externally Generated Frame Sync in either Transmit or Receive Mode)

ns

1

t_SDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

7

1

t_HDRI

2.5

Switching Characteristics

2

t_DFSI

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)

4

ns

2

t_HOFSI

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1.0

Transmit Data Delay After SCLK

2

t_DFSIR

9.75

3.25

2

t_HOFSIR

2

t_DDTI

2

t_HDTI

Transmit Data Hold After SCLK

Transmit or Receive SCLK Width

–1.25

t_SCLKIW

2 × t_PCLK– 1.5

2 × t_PCLK+ 1.5 ns

¹Referenced to the sample edge.

²Referenced to drive edge.

Rev. 0

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Page 38 of 72

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June 2010

ADSP-21469

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSIR

t_DFSE

t_HOFSIR

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_SDRI

t_HDRI

t_SDRE

t_HDRE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 24. Serial Ports

Rev. 0

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Page 39 of 72

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June 2010

ADSP-21469

Table 36. Serial Ports—Enable and Three-State

Parameter

Min

2

Max

Unit

Switching Characteristics

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

ns

1

t_DDTTE

11.5

1

t_DDTIN

–1

¹Referenced to drive edge.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

t_DDTEN

t_DDTTE

DAI_P20–1

(FRAME SYNC)

DRIVE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

t_DDTIN

Figure 25. Serial Ports—Enable and Three-State

Rev. 0

|

Page 40 of 72

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June 2010

ADSP-21469

The SPORTx_TDV_O output signal (routing unit) becomes

active in SPORT multichannel mode. During transmit slots

(enabled with active channel selection registers) the

SPORTx_TDV_O is asserted for communication with external

devices.

Table 37. Serial Ports—TDV (Transmit Data Valid)

Parameter

Switching Characteristics¹

Min

3

Max

Unit

t_DRDVEN

t_DFDVEN

t_DRDVIN

t_DFDVIN

Data-Valid Enable Delay from Drive Edge of External Clock

Data-Valid Disable Delay from Drive Edge of External Clock

Data-Valid Enable Delay from Drive Edge of Internal Clock

Data-Valid Disable Delay from Drive Edge of Internal Clock

ns

8

2

–0.1

¹Referenced to drive edge.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

TDVx

DAI_P20-1

t_DFDVEN

t_DRDVEN

DRIVE EDGE

DAI_P20–1

(SCLK, INT)

TDVx

DAI_P20-1

t_DFDVIN

t_DRDVIN

Figure 26. Serial Ports—Transmit Data Valid Internal and External Clock

Rev. 0

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Page 41 of 72

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June 2010

ADSP-21469

Table 38. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit Frame Sync or External

7.75

Receive Frame Sync with MCE = 1, MFD = 0

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

SAMPLE DRIVE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

Figure 27. External Late Frame Sync

Rev. 0

|

Page 42 of 72

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June 2010

ADSP-21469

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 39. IDP

signals are routed to the DAI_P20–1 pins using the SRU. There-

fore, the timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 39. Input Data Port (IDP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Clock Width

3.8

ns

1

t_SIHFS

2.5

1

t_SISD

t_SIHD

2.5

1

2.5

t_IDPCLKW

t_IDPCLK

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can

be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IPDCLK

t_IPDCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 28. IDP Master Timing

Rev. 0

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Page 43 of 72

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June 2010

ADSP-21469

PDAP chapter of the ADSP-214xx SHARC Processor Hardware

Reference. Note that the 20 bits of external PDAP data can be

provided through the AMI_ADDR23–4 pins or over the DAI

pins.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 40. PDAP is the parallel mode operation of channel 0 of

the IDP. For details on the operation of the PDAP, see the

Table 40. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SPHOLD

PDAP_HOLD Setup Before PDAP_CLK Sample Edge

PDAP_HOLD Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge

PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge

Clock Width

2.5

ns

1

t_HPHOLD

2.5

1

t_PDSD

3.85

1

t_PDHD

2.5

t_PDCLKW

t_PDCLK

(t_PCLK× 4) ÷ 2 – 3

t_PCLK× 4

Clock Period

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

2 × t_PCLK+ 3

2 × t_PCLK– 1

ns

1

Data source pins are AMI_ADDR23–4 or DAI pins. Source pins for serial clock and frame sync are 1) AMI_ADDR3–2 pins, 2) DAI pins.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20–1

(PDAP_CLK)

t_HPHOLD

t_SPHOLD

DAI_P20–1

(PDAP_HOLD)

t_PDHD

t_PDSD

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

t_PDHLDD

t_PDSTRB

DAI_P20–1

(PDAP_STROBE)

Figure 29. PDAP Timing

Rev. 0

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Page 44 of 72

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June 2010

ADSP-21469

Sample Rate Converter—Serial Input Port

The ASRC input signals are routed from the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided in

Table 41 are valid at the DAI_P20–1 pins.

Table 41. ASRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Clock Width

4

ns

1

t_SRCHFS

5.5

1

t_SRCSD

4

1

t_SRCHD

t_SRCCLKW

t_SRCCLK

5.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCSD

t_SRCHD

DAI_P20–1

(SDATA)

Figure 30. ASRC Serial Input Port Timing

Rev. 0

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Page 45 of 72

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June 2010

ADSP-21469

Sample Rate Converter—Serial Output Port

For the serial output port, the frame sync is an input and it

should meet setup and hold times with regard to the serial clock

on the output port. The serial data output has a hold time and

delay specification with regard to serial clock. Note that the

serial clock rising edge is the sampling edge, and the falling edge

is the drive edge.

Table 42. ASRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Clock Width

4

ns

1

t_SRCHFS

t_SRCCLKW

t_SRCCLK

5.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

Switching Characteristics

1

t_SRCTDD

Transmit Data Delay After Serial Clock Falling Edge

Transmit Data Hold After Serial Clock Falling Edge

9.9

ns

1

t_SRCTDH

1

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCTDD

t_SRCTDH

DAI_P20–1

(SDATA)

Figure 31. ASRC Serial Output Port Timing

Rev. 0

|

Page 46 of 72

|

June 2010

ADSP-21469

Pulse-Width Modulation (PWM) Generators

The following timing specifications apply when the

AMI_ADDR23–8 pins are configured as PWM.

Table 43. Pulse-Width Modulation (PWM) Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_PWMW

t_PWMP

PWM Output Pulse Width

PWM Output Period

t_PCLK– 2

(2¹⁶– 2) × t_PCLK– 2

(2¹⁶– 1) × t_PCLK– 1.5

ns

2 × t_PCLK– 1.5

t_PWMW

PWM

OUTPUTS

t_PWMP

Figure 32. PWM Timing

Rev. 0

|

Page 47 of 72

|

June 2010

ADSP-21469

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left-justified, I²S, or right-justified with word widths of 16, 18,

20, or 24 bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 33 shows the right-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the

rising edge of serial clock. The MSB is delayed minimum in

24-bit output mode or maximum in 16-bit output mode from

an LRCLK transition, so that when there are 64 serial clock peri-

ods per LRCLK period, the LSB of the data will be right-justified

to the next LRCLK transition.

Figure 34 shows the default I²S-justified mode. LRCLK is low

for the left channel and HI for the right channel. Data is valid on

the rising edge of serial clock. The MSB is left-justified to an

LRCLK transition but with a delay.

Figure 35 shows the left-justified mode. LRCLK is high for the

left channel and LO for the right channel. Data is valid on the

rising edge of serial clock. The MSB is left-justified to an LRCLK

transition with no delay.

Table 44. S/PDIF Transmitter Right-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

t_RJD

LRCLK to MSB Delay in Right-Justified Mode

16-Bit Word Mode

16

14

12

8

SCLK

18-Bit Word Mode

20-Bit Word Mode

24-Bit Word Mode

LEFT/RIGHT CHANNEL

DAI_P20–1

LRCLK

DAI_P20–1

SCLK

t_RJD

DAI_P20–1

SDATA

LSB

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 33. Right-Justified Mode

Table 45. S/PDIF Transmitter I²S Mode

Parameter

Nominal

Unit

Timing Requirement

t_I2

LRCLK to MSB Delay in I²S Mode

1

SCLK

SD

LEFT/RIGHT CHANNEL

DAI_P20–1

LRCLK

DAI_P20–1

SCLK

t_I2SD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 34. I²S-Justified Mode

Rev. 0

|

Page 48 of 72

|

June 2010

ADSP-21469

Table 46. S/PDIF Transmitter Left-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

t_LJD

LRCLK to MSB Delay in Left-Justified Mode

0

SCLK

DAI_P20–1

LRCLK

LEFT/RIGHT CHANNEL

DAI_P20–1

SCLK

t_LJD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 35. Left-Justified Mode

Rev. 0

|

Page 49 of 72

|

June 2010

ADSP-21469

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 47. Input signals are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 47. S/PDIF Transmitter Input Data Timing

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Transmit Clock Width

3

ns

1

t_SIHFS

3

1

t_SISD

t_SIHD

3

1

3

t_SITXCLKW

t_SITXCLK

t_SISCLKW

t_SISCLK

9

Transmit Clock Period

20

36

80

Clock Width

Clock Period

¹The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SITXCLKW

t_SITXCLK

DAI_P20–1

(TxCLK)

t_SISCLK

t_SISCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 36. S/PDIF Transmitter Input Timing

Oversampling Clock (HFCLK) Switching Characteristics

The S/PDIF transmitter has an oversampling clock. This

HFCLK input is divided down to generate the biphase clock.

Table 48. Oversampling Clock (HFCLK) Switching Characteristics

Parameter

Max

Unit

MHz

kHz

HFCLK Frequency for HFCLK = 384 × Frame Sync

HFCLK Frequency for HFCLK = 256 × Frame Sync

Frame Rate (Fs)

Oversampling Ratio × Frame Sync <= 1/t_SIHFCLK

49.2

192.0

Rev. 0

|

Page 50 of 72

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June 2010

ADSP-21469

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 49. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

LRCLK Delay After Serial Clock

LRCLK Hold After Serial Clock

5

ns

t_HOFSI

t_DDTI

–2

Transmit Data Delay After Serial Clock

Transmit Data Hold After Serial Clock

Transmit Serial Clock Width

t_HDTI

–2

1

t_SCLKIW

8 × t_PCLK– 2

¹Serial clock frequency is 64 × Frame Sync, where FS = the frequency of LRCLK.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20–1

(SCLK)

t_DFSI

t_HOFSI

DAI_P20–1

(FS)

t_DDTI

t_HDTI

DAI_P20–1

(DATA CHANNEL

A/B)

Figure 37. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. 0

|

Page 51 of 72

|

June 2010

ADSP-21469

SPI Interface—Master

The ADSP-21469 contains two SPI ports. Both primary and sec-

ondary are available through DPI only. The timing provided in

Table 50 and Table 51 applies to both.

Table 50. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid to SPICLK Edge (Data Input Setup Time)

8.2

2

ns

SPICLK Last Sampling Edge to Data Input Not Valid

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × t_PCLK– 2

4 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

DPI Pin (SPI Device Select) Low to First SPICLK Edge

Last SPICLK Edge to DPI Pin (SPI Device Select) High

Sequential Transfer Delay

2.5

4 × t_PCLK– 2

4 × t_PCLK– 1

t_SPITDM

DPI

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

(INPUT)

t_DDSPIDM

t_HDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

CPHASE = 0

MISO

(INPUT)

Figure 38. SPI Master Timing

Rev. 0

|

Page 52 of 72

|

June 2010

ADSP-21469

SPI Interface—Slave

Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

t_HDS

Serial Clock Cycle

4 × t_PCLK– 2

2 × t_PCLK– 2

2 × t_PCLK

2

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE = 0)

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_PCLK

Switching Characteristics

t_DSOESPIDS Assertion to Data Out Active

0

6.8

8

ns

1

t_DSOE

t_DSDHI

SPIDS Assertion to Data Out Active (SPI2)

SPIDS Deassertion to Data High Impedance

10.5

9.5

1

t_DSDHI

SPIDS Deassertion to Data High Impedance (SPI2)

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE = 0)

t_DDSPIDS

t_HDSPIDS

t_DSOV

2 × t_PCLK

5 × t_PCLK

ns

¹The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral

Interface Port” chapter.

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0,

CP = 1)

(INPUT)

t_SDSCO

t_DSOE

t_DSDHI

t_HDSPIDS

t_DDSPIDS

MISO

(OUTPUT)

t_SSPIDSt_HSPIDS

CPHASE = 1

t_SSPIDS

MOSI

(INPUT)

t_HDSPIDS

t_DDSPIDS

t_DSDHI

MISO

(OUTPUT)

t_DSOV

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

(INPUT)

Figure 39. SPI Slave Timing

Rev. 0

|

Page 53 of 72

|

June 2010

ADSP-21469

Media Local Bus

All the numbers given are applicable for all speed modes

(1024 Fs, 512 Fs, and 256 Fs for 3-pin; 512 Fs and 256 Fs for 5-

pin) unless otherwise specified. Please refer to MediaLB specifi-

cation document rev 3.0 for more details.

Table 52. MLB Interface, 3-Pin Specifications

Parameter

Min

Typ

Max

Unit

3-Pin Characteristics

t_MLBCLK

MLB Clock Period

1024 Fs

20.3

40

81

ns

512 Fs

256 Fs

t_MCKL

MLBCLK Low Time

1024 Fs

6.1

14

30

ns

512 Fs

256 Fs

t_MCKH

MLBCLK High Time

1024 Fs

9.3

14

30

ns

512 Fs

256 Fs

t_MCKR

MLBCLK Rise Time (V_ILto V_IH)

1024 Fs

1

3

ns

512 Fs/256 Fs

t_MCKF

MLBCLK Fall Time (V_IHto V_IL)

1024 Fs

1

3

ns

512 Fs/256 Fs

1

t_MPWV

MLBCLK Pulse Width Variation

1024 Fs

512 Fs/256 Fs

0.7

2.0

ns p-p

t_DSMCF

t_DHMCF

t_MCFDZ

t_MCDRV

DAT/SIG Input Setup Time

1

0

ns

DAT/SIG Input Hold Time

DAT/SIG Output Time to Three-state

DAT/SIG Output Data Delay From MLBCLK Rising Edge

15

8

2

t_MDZH

Bus Hold Time

1024 Fs

512 Fs/256 Fs

2

4

ns

C_MLB

DAT/SIG Pin Load

1024 Fs

40

60

pf

512 Fs/256 Fs

¹Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in nanoseconds peak-to-peak (ns p-p).

²The board must be designed to ensure that the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be

minimized while meeting the maximum capacitive load listed.

Rev. 0

|

Page 54 of 72

|

June 2010

ADSP-21469

MLBSIG/

MLBDAT

(Rx, Input)

VALID

t_DHMCF

t_DSMCF

t_MLBCLK

t_MCKH

t_MCKL

MLBCLK

t_MCKR

t_MCDRV

t_MCKF

t_MCFDZ

t_MDZH

MLBSIG/

MLBDAT

VALID

(Tx, Output)

Figure 40. MLB Timing (3-Pin Interface)

Table 53. MLB Interface, 5-Pin Specifications

Parameter

Min

Typ

Max

Unit

5-Pin Characteristics

t_MLBCLK

MLB Clock Period

512 Fs

40

81

ns

256 Fs

t_MCKL

MLBCLK Low Time

512 Fs

15

30

ns

256 Fs

t_MCKH

MLBCLK High Time

512 Fs

15

30

ns

256 Fs

t_MCKR

t_MCKF

MLBCLK Rise Time (V_ILto V_IH)

MLBCLK Fall Time (V_IHto V_IL)

MLBCLK Pulse Width Variation

DAT/SIG Input Setup Time

DAT/SIG Input Hold Time

6

2

ns

1

t_MPWV

ns p-p

ns

2

t_DSMCF

t_DHMCF

t_MCDRV

3

5

ns

DS/DO Output Data Delay From MLBCLK Rising Edge

8

ns

3

t_MCRDL

DO/SO Low From MLBCLK High

512 Fs

256 Fs

10

20

ns

C_MLB

DS/DO Pin Load

40

pf

¹Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in nanoseconds peak-to-peak (ns p-p).

²Gate delays due to OR'ing logic on the pins must be accounted for.

³When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,

external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.

Rev. 0

|

Page 55 of 72

|

June 2010

ADSP-21469

MLBSIG,

MLBDAT

(Rx, Input)

VALID

t_DHMCF

t_DSMCF

t_MLBCLK

t_MCKH

t_MCKL

MLBCLK

t_MCKR

t_MCDRV

t_MCKF

t_MCRDL

MLBSO,

MLBDO

VALID

(Tx, Output)

Figure 41. MLB Timing (5-Pin Interface)

MLBCLK

t_MPWV

Figure 42. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing

Rev. 0

|

Page 56 of 72

|

June 2010

ADSP-21469

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

For information on the UART port receive and transmit opera-

tions, see the ADSP-214xx SHARC Hardware Reference Manual.

2-Wire Interface (TWI)—Receive and Transmit Timing

For information on the TWI receive and transmit operations,

see the ADSP-214xx SHARC Hardware Reference Manual.

JTAG Test Access Port and Emulation

Table 54. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

20

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

5

6

1

t_SSYS

7

1

t_HSYS

t_TRSTW

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

18

4 × t_CK

10

ns

2

t_DSYS

t_CK÷ 2 + 7

¹System Inputs = AMI_DATA, DDR2_DATA, CLKCFG1-0, BOOTCFG2-0 RESET, DAI, DPI, FLAG3-0.

²System Outputs = AMI_ADDR/DATA, DDR2_ADDR/DATA, AMI_CTRL, DDR2_CTRL, DAI, DPI, FLAG3-0, EMU.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 43. IEEE 1149.1 JTAG Test Access Port

Rev. 0

|

Page 57 of 72

|

June 2010

ADSP-21469

TEST CONDITIONS

OUTPUT DRIVE CURRENTS

The ac signal specifications (timing parameters) appear in

Table 19 on Page 25 through Table 54 on Page 57. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 44.

Figure 46 and Figure 46 shows typical I-V characteristics for the

output drivers of the ADSP-21469, and Table 55 shows the pins

associated with each driver. The curves represent the current

drive capability of the output drivers as a function of output

voltage.

Timing is measured on signals when they cross the V_MEASlevel

as described in Figure 45. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches V_MEASand

the point that the second signal reaches V_MEAS. The value of

Table 55. Driver Types

Driver Type Associated Pins

A

LACK1–0,LDAT0[7:0],LDAT1[7:0],MLBCLK,MLBDAT,

MLBDO, MLBSIG, MLBSO, AMI_ACK,

AMI_ADDR23–0, AMI_DATA7–0, AMI_MS1–0,

AMI_RD, AMI_WR, DAI_P, DPI_P, EMU, FLAG3–0,

RESETOUT, TDO

V

_MEASis 1.5 V for non-DDR pins and 0.9 V for DDR pins.

TESTER PIN ELECTRONICS

50ꢀ

V

LOAD

B

C

LCLK1–0

T1

DUT

OUTPUT

DDR2_ADDR15–0, DDR2_BA2–0, DDR2_CAS,

DDR2_CKE, DDR2_CS3–0, DDR2_DATA15–0,

DDR2_DM1–0, DDR2_ODT, DDR2_RAS, DDR2_WE

45ꢀ

70ꢀ

ZO = 50ꢀꢁ(impedance)

TD = 4.04 ꢂ 1.18 ns

50ꢀ

0.5pF

D (TRUE)

D (COMP)

DDR2_CLK1–0, DDR2_DQS1–0

4pF

2pF

400ꢀ

200

150

100

NOTES:

THE WORST-CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

V_OH3.13 V, 125 °C

TYPE B

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

TYPE A

50

0

Figure 44. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

TYPE A

-

50

-

100

150

TYPE B

INPUT

OR

V_MEAS

-

OUTPUT

V_OL3.13 V, 125 °C

-200

0.5

1.0

1.5

2.0

2.5

3.5

0

3.0

Figure 45. Voltage Reference Levels for AC Measurements

SWEEP (V_DDEXT) VOLTAGE (V)

Figure 46. Output Buffer Characteristics (Worst-Case Non-DDR2)

Rev. 0

|

Page 58 of 72

|

June 2010

ADSP-21469

50

40

30

20

10

0

14

12

10

8

TYPE C & D, FULL DRIVE

TYPE A FALL

y = 0.0746x + 0.5146

V_OH3.13 V, 125 °C

TYPE A RISE

y = 0.0572x + 0.5571

TYPE C & D, HALF DRIVE

TYPE B FALL

y = 0.0278x + 0.3138

TYPE C & D, HALF DRIVE

6

-

10

20

30

40

50

4

TYPE B RISE

y = 0.0258x + 0.3684

V_OL3.13 V, 125 °C

TYPE C & D, FULL DRIVE

2

0

0.5

1.0

1.5

0

25

50

75

100

125

150

175

200

SWEEP (V_DDEXT) VOLTAGE (V)

LOAD CAPACITANCE (pF)

Figure 47. Output Buffer Characteristics (Worst-Case DDR2)

Figure 49. Typical Output Rise/Fall Time Non-DDR2

(20% to 80%, V_{DD_EXT}= Min)

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Table 55). Figure 52 through Figure 57

show graphically how output delays and holds vary with load

capacitance. The graphs of Figure 48 through Figure 57 may not

be linear outside the ranges shown for Typical Output Delay vs.

Load Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

TYPE C & D HALF DRIVE FALL

y = 0.0217x + 0.26

TYPE C & D HALF DRIVE RISE

y = 0.0198x + 0.2304

7

6

TYPE C & D FULL DRIVE RISE

y = 0.0061x + 0.207

TYPE A DRIVE FALL

TYPE A DRIVE RISE

y = 0.0413x + 0.2651

y = 0.0342x + 0.309

TYPE C & D FULL DRIVE FALL

y = 0.0058x + 0.2113

5

4

3

2

1

0

TYPE B DRIVE RISE

y = 0.0153x + 0.2131

0

5

10

15

20

25

30

35

40

LOAD CAPACITANCE (pF)

Figure 50. Typical Output Rise/Fall Time DDR2

(20% to 80%, V_{DD_EXT}= Max)

TYPE B DRIVE FALL

y = 0.0152x + 0.1882

0

25

50

75

100

125

150

175

200

LOAD CAPACITANCE (pF)

Figure 48. Typical Output Rise/Fall Time Non-DDR2

(20% to 80%, V_{DD_EXT}= Max)

Rev. 0

|

Page 59 of 72

|

June 2010

ADSP-21469

4

4.5

4

TYPE A FALL

y = 0.0196x + 1.2934

TYPE A RISE

3.5

y = 0.0152x + 1.7611

TYPE C & D HALF DRIVE FALL

y = 0.0841x + 0.8997

3.5

3

TYPE C & D HALF DRIVE RISE

y = 0.0617x + 0.7995

3

2.5

2

TYPE B RISE

y = 0.0060x + 1.7614

TYPE C & D FULL

DRIVE FALL

y = 0.0421x + 0.9257

2.5

2

TYPE B FALL

y = 0.0074x + 1.421

1.5

1

1.5

1

TYPE C & D FULL

DRIVE RISE

y = 0.0304x + 0.8204

0.5

0

0.5

0

25

50

75

100

125

150

175

200

0

5

10

15

20

25

30

35

40

LOAD CAPACITANCE (pF)

Figure 51. Typical Output Rise/Fall Time DDR2

(20% to 80%, V_{DD_EXT}= Min)

Figure 53. Typical Output Rise/Fall Delay No- DDR

(V_{DD_EXT}= Max)

10

9

3.0

2.8

TYPE A DRIVE FALL

y = 0.0359x + 2.9227

TYPE C HALF DRIVE (FALL)

8

y = 0.0122x + 2.0405

TYPE A DRIVE RISE

y = 0.0256x + 3.5876

TYPE C HALF DRIVE (RISE)

2.6

y = 0.0079x + 2.0476

7

6

TYPE B DRIVE RISE

y = 0.0116x + 3.5697

2.4

2.2

5

4

3

2.0

1.8

TYPE B DRIVE FALL

y = 0.0136x + 3.1135

TYPE C FULL DRIVE (RISE & FALL)

y = 0.0023x + 1.9472

2

1

0

1.6

1.4

0

25

50

75

100

125

150

175

200

0

5

10

15

20

25

30

35

LOAD CAPACITANCE (pF)

Figure 52. Typical Output Rise/Fall Delay Non-DDR

(V_{DD_EXT}= Min)

Figure 54. Typical Output Rise/Fall Delay DDR Pad C

(V_{DD_EXT}= Min)

Rev. 0

|

Page 60 of 72

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June 2010

ADSP-21469

3.0

2.8

1.4

1.3

1.2

1.1

1.0

0.9

0.8

TYPE D HALF DRIVE TRUE (RISE)

y = 0.003x + 1.1758

TYPE D HALF DRIVE TRUE (FALL)

TYPE D HALF DRIVE COMP (FALL)

y = 0.0047x + 1.1884

TYPE D HALF DRIVE TRUE (FALL)

TYPE D HALF DRIVE COMP (FALL)

y = 0.0123x + 2.3194

TYPE D HALF DRIVE TRUE (RISE)

y = 0.0077x + 2.2912

2.6

2.4

2.2

TYPE D HALF DRIVE COMP (RISE)

y = 0.0077x + 2.2398

2.0

1.8

TYPE D FULL DRIVE COMP (RISE)

y = 0.0022x + 2.1499

TYPE D FULL DRIVE COMP (RISE)

y = 0.0007x + 1.0964

TYPE D HALF DRIVE COMP (RISE)

y = 0.0031x + 1.1599

TYPE D FULL DRIVE TRUE (RISE & FALL)

TYPE D FULL DRIVE COMP (FALL)

y = 0.0008x + 1.1074

TYPE D FULL DRIVE TRUE (RISE & FALL)

TYPE D FULL DRIVE COMP (FALL )

y = 0.0022x + 2.2027

1.6

1.4

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

LOAD CAPACITANCE (pF)

Figure 55. Typical Output Rise/Fall Delay DDR Pad D

(V_{DD_EXT}= Min)

Figure 57. Typical Output Rise/Fall Delay DDR Pad D

(V_{DD_EXT}= Max)

THERMAL CHARACTERISTICS

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

The ADSP-21469 processor is rated for performance over the

temperature range specified in Operating Conditions on

Page 17.

Table 56 airflow measurements comply with JEDEC standards

JESD51-2 and JESD51-6, and the junction-to-board measure-

ment complies with JESD51-8. Test board design complies with

JEDEC standards JESD51-7 (CSP_BGA). The junction-to-case

measurement complies with MIL- STD-883. All measurements

use a 2S2P JEDEC test board.

TYPE C HALF DRIVE (FALL)

y = 0.0046x + 1.0577

TYPE C HALF DRIVE (RISE)

y = 0.0032x + 1.0622

To determine the junction temperature of the device while on

the application PCB use:

T_J= junction temperature (°C)

TYPE C FULL DRIVE (RISE & FALL)

y = 0.0007x + 0.9841

T

= T

+   P 

CASE JT

D

0

5

10

15

20

25

30

35

J

LOAD CAPACITANCE (pF)

where:

Figure 56. Typical Output Rise/Fall Delay DDR Pad C

(V_{DD_EXT}= Max)

T_CASE= case temperature (°C) measured at the top center of the

package

_JT= junction-to-top (of package) characterization parameter

is the typical value from Table 56.

P

_D= power dissipation

Values of _JAare provided for package comparison and PCB

design considerations. _JAcan be used for a first order approxi-

mation of T_Jby the equation:

T

= T +   P 

A JA D

J

where:

T_A= ambient temperature °C

Values of _JCare provided for package comparison and PCB

design considerations when an external heat sink is required.

Rev. 0

|

Page 61 of 72

|

June 2010

ADSP-21469

Values of _JBare provided for package comparison and PCB

design considerations. Note that the thermal characteristics val-

ues provided in Table 56 are modeled values.

Table 56. Thermal Characteristics for 324-Lead CSP_BGA

Parameter

_JA

_JMA

_JC

_JT

_JMT

Condition

Typical

22.7

20.4

19.5

6.6

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.11

0.19

0.24

Thermal Diode

The ADSP-21469 processors incorporate thermal diodes to

monitor the die temperature. The thermal diode of is a

grounded collector PNP bipolar junction transistor (BJT). The

THD_P pin is connected to the emitter and the THD_M pin is

connected to the base of the transistor. These pins can be used

by an external temperature sensor (such as ADM 1021A or

LM86, or others) to read the die temperature of the chip.

The technique used by the external temperature sensor is to

measure the change in V_BEwhen the thermal diode is operated

at two different currents. This is shown in the following

equation:

n = multiplication factor close to 1, depending on process

variations

k = Boltzmann’s constant

T = temperature (°C)

q = charge of the electron

N = ratio of the two currents

The two currents are usually in the range of 10 μA to 300 μA for

the common temperature sensor chips available.

Table 57 contains the thermal diode specifications using the

transistor model. Note that Measured Ideality Factor already

takes into effect variations in beta ().

kT

-----

V_BE= n 

 In(N)

q

where:

Table 57. Thermal Diode Parameters—Transistor Model¹

Symbol

Parameter

Min

10

Typ

Max

300

Unit

A

2

I_FW

Forward Bias Current

Emitter Current

Transistor Ideality

Series Resistance

I_E

10

300

3, 4

n_Q

1.012

0.12

1.015

0.2

1.017

0.28

4, 5

R_T



¹See the Engineer-to-Engineer Note EE-346.

²Analog Devices does not recommend operation of the thermal diode under reverse bias.

³Not 100% tested. Specified by design characterization.

⁴The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: I_C= I_S× (e ^qVBE/nqkT–1), where I_S= saturation current,

q = electronic charge, V_BE= voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).

⁵The series resistance (R_T) can be used for more accurate readings as needed.

Rev. 0

|

Page 62 of 72

|

June 2010

ADSP-21469

CSP_BGA BALL ASSIGNMENT—AUTOMOTIVE MODELS

Table 58 lists the automotive CSP_BGA ball assignments by

signal.

Table 58. CSP_BGA Ball Assignment (Alphabetical by Signal)

Signal

Ball No.

H02

R10

V16

U16

T16

R16

V15

U15

T15

R15

V14

U14

T14

R14

V13

U13

T13

R13

V12

U12

T12

R12

V11

U11

T11

R11

U18

T18

R18

P18

V17

U17

T17

R17

T10

U10

J04

Signal

Ball No.

G02

L01

R06

V05

R07

R03

U05

T05

V06

V02

R05

V04

U04

T04

U06

U02

R04

V03

U03

T03

T06

T02

D13

C13

D14

C14

B14

A14

D15

C15

B15

A15

D16

C16

B16

A16

B17

A17

C18

C17

B18

C07

Signal

Ball No.

E01

A07

B07

A13

B13

C01

D01

C02

D02

B02

A02

B03

A03

B05

A05

B06

A06

B08

A08

B09

A09

A11

B11

A12

B12

C03

C11

A04

B04

A10

B10

B01

C09

C10

R02

U01

T01

R01

P01

P02

P03

P04

Signal

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DPI_P14

EMU

Ball No.

N01

N02

N03

N04

M03

M04

K02

R08

V07

U07

T07

A01

A18

C04

C06

C08

D05

D07

D09

D10

D17

E03

AGND

CLK_CFG1

CLKIN

DDR2_CKE

AMI_ACK

DDR2_CLK0

DDR2_CLK1

DDR2_CS0

AMI_ADDR0

AMI_ADDR01

AMI_ADDR02

AMI_ADDR03

AMI_ADDR04

AMI_ADDR05

AMI_ADDR06

AMI_ADDR07

AMI_ADDR08

AMI_ADDR09

AMI_ADDR10

AMI_ADDR11

AMI_ADDR12

AMI_ADDR13

AMI_ADDR14

AMI_ADDR15

AMI_ADDR16

AMI_ADDR17

AMI_ADDR18

AMI_ADDR19

AMI_ADDR20

AMI_ADDR21

AMI_ADDR22

AMI_ADDR23

AMI_DATA0

AMI_DATA1

AMI_DATA2

AMI_DATA3

AMI_DATA4

AMI_DATA5

AMI_DATA6

AMI_DATA7

AMI_MS0

DAI_P01

DAI_P02

DAI_P03

DAI_P04

DAI_P05

DDR2_CS1

DAI_P06

DDR2_CS2

FLAG0

FLAG1

FLAG2

FLAG3

GND

DAI_P07

DDR2_CS3

DAI_P08

DDR2_DATA0

DDR2_DATA01

DDR2_DATA02

DDR2_DATA03

DDR2_DATA04

DDR2_DATA05

DDR2_DATA06

DDR2_DATA07

DDR2_DATA08

DDR2_DATA09

DDR2_DATA10

DDR2_DATA11

DDR2_DATA12

DDR2_DATA13

DDR2_DATA14

DDR2_DATA15

DDR2_DM0

DDR2_DM1

DDR2_DQS0

DDR2_DQS1

DDR2_ODT

DDR2_RAS

DAI_P09

DAI_P10

DAI_P11

GND

DAI_P12

GND

DAI_P13

GND

DAI_P14

GND

DAI_P15

GND

DAI_P16

GND

DAI_P17

GND

DAI_P18

GND

DAI_P19

GND

DAI_P20

GND

DDR2_ADDR0

DDR2_ADDR01

DDR2_ADDR02

DDR2_ADDR03

DDR2_ADDR04

DDR2_ADDR05

DDR2_ADDR06

DDR2_ADDR07

DDR2_ADDR08

DDR2_ADDR09

DDR2_ADDR10

DDR2_ADDR11

DDR2_ADDR12

DDR2_ADDR13

DDR2_ADDR14

DDR2_ADDR15

DDR2_BA0

DDR2_BA1

DDR2_BA2

DDR2_CAS

GND

E05

GND

E12

GND

E13

GND

E16

GND

F01

F02

GND

F04

GND

F14

GND

F16

GND

G03

G04

G05

G07

G08

G09

G10

G11

G12

G15

H04

GND

DDR2_WE

GND

DPI_P01

GND

AMI_MS1

DPI_P02

GND

AMI_RD

DPI_P03

GND

AMI_WR

V10

J02

DPI_P04

GND

BOOT_CFG0

BOOT_CFG1

BOOT_CFG2

CLK_CFG0

DPI_P05

GND

J03

DPI_P06

GND

Ho3

G01

DPI_P07

GND

DPI_P08

GND

Rev. 0

|

Page 63 of 72

|

June 2010

ADSP-21469

Table 58. CSP_BGA Ball Assignment (Alphabetical by Signal) (Continued)

Signal

GND

Ball No.

H07

H08

H09

H10

H11

H12

J01

Signal

Ball No.

V01

V18

K17

P17

J18

Signal

Ball No.

E04

E07

E10

E11

E17

F03

F05

F15

G14

G16

H15

H18

J05

Signal

Ball No.

F13

GND

V_DD

_

DDR

EXT

INT

2

_INT

_THD

GND

G06

G13

H05

H06

H13

H14

J06

LACK_0

LACK_1

LCLK_0

LCLK_1

LDAT0_0

LDAT0_1

LDAT0_2

LDAT0_3

LDAT0_4

LDAT0_5

LDAT0_6

LDAT0_7

LDAT1_0

LDAT1_1

LDAT1_2

LDAT1_3

LDAT1_4

LDAT1_5

LDAT1_6

LDAT1_7

MLBCLK

MLBDAT

MLBSIG

MLBSO

MLBDO

RESET

N18

E18

F17

F18

G17

G18

H16

H17

J16

J07

J08

J13

J09

K06

K13

L06

J10

J11

J12

L13

J14

J15

M06

M13

N06

N07

N08

N09

N13

N10

D04

D11

K01

J17

K18

L16

K14

L05

M14

M18

N05

P06

P08

P10

P12

P14

P15

T08

T09

U08

U09

V08

V09

D12

E06

E08

E09

E14

E15

F06

F07

F08

F09

F10

F11

F12

K05

K07

K08

K09

K10

K11

K12

L07

L08

L09

L10

L11

L12

L14

M05

M07

M08

M09

M10

M11

M12

N14

N17

P05

P07

P09

P11

P13

R09

L17

L18

M16

M17

N16

P16

K03

K04

L02

V_REF

XTAL

L03

L04

M01

M02

K15

L15

RESETOUT/RUNRSTIN

TCK

TDI

TDO

M15

N12

N11

K16

N15

H01

C05

C12

D03

D06

D08

D18

E02

THD_M

THD_P

INT

TMS

INT

TRST

INT

VDD_A

INT

V_DD

_DDR

2

INT

Rev. 0

|

Page 64 of 72

|

June 2010

ADSP-21469

A1 CORNER

INDEX AREA

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18

A

B

C

D

E

F

D

R

D

R

D

G

A

S

H

J

K

L

M

N

P

R

T

U

V

D

R

T

DD_INT

DD_EXT

DD_DDR2

REF

V

GND

DD_THD

DD_A

A

S

I/O SIGNALS

AGND

Figure 58. Ball Configuration, Automotive Model

Rev. 0

|

Page 65 of 72

|

June 2010

ADSP-21469

CSP_BGA BALL ASSIGNMENT—STANDARD MODELS

Table 59 lists the standard model CSP_BGA ball assignments by

signal.

Table 59. CSP_BGA Ball Assignment (Alphabetical by Signal)

Signal

Ball No.

H02

R10

V16

U16

T16

R16

V15

U15

T15

R15

V14

U14

T14

R14

V13

U13

T13

R13

V12

U12

T12

R12

V11

U11

T11

R11

U18

T18

R18

P18

V17

U17

T17

R17

T10

U10

J04

Signal

Ball No.

G02

L01

R06

V05

R07

R03

U05

T05

V06

V02

R05

V04

U04

T04

U06

U02

R04

V03

U03

T03

T06

T02

D13

C13

D14

C14

B14

A14

D15

C15

B15

A15

D16

C16

B16

A16

B17

A17

C18

C17

B18

C07

Signal

Ball No.

E01

A07

B07

A13

B13

C01

D01

C02

D02

B02

A02

B03

A03

B05

A05

B06

A06

B08

A08

B09

A09

A11

B11

A12

B12

C03

C11

A04

B04

A10

B10

B01

C09

C10

R02

U01

T01

R01

P01

P02

P03

P04

Signal

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DPI_P14

EMU

Ball No.

N01

N02

N03

N04

M03

M04

K02

R08

V07

U07

T07

A01

A18

C04

C06

C08

D05

D07

D09

D10

D17

E03

AGND

CLK_CFG1

CLKIN

DDR2_CKE

AMI_ACK

DDR2_CLK0

DDR2_CLK1

DDR2_CS0

AMI_ADDR0

AMI_ADDR01

AMI_ADDR02

AMI_ADDR03

AMI_ADDR04

AMI_ADDR05

AMI_ADDR06

AMI_ADDR07

AMI_ADDR08

AMI_ADDR09

AMI_ADDR10

AMI_ADDR11

AMI_ADDR12

AMI_ADDR13

AMI_ADDR14

AMI_ADDR15

AMI_ADDR16

AMI_ADDR17

AMI_ADDR18

AMI_ADDR19

AMI_ADDR20

AMI_ADDR21

AMI_ADDR22

AMI_ADDR23

AMI_DATA0

AMI_DATA1

AMI_DATA2

AMI_DATA3

AMI_DATA4

AMI_DATA5

AMI_DATA6

AMI_DATA7

AMI_MS0

DAI_P01

DAI_P02

DAI_P03

DAI_P04

DAI_P05

DDR2_CS1

DAI_P06

DDR2_CS2

FLAG0

FLAG1

FLAG2

FLAG3

GND

DAI_P07

DDR2_CS3

DAI_P08

DDR2_DATA0

DDR2_DATA01

DDR2_DATA02

DDR2_DATA03

DDR2_DATA04

DDR2_DATA05

DDR2_DATA06

DDR2_DATA07

DDR2_DATA08

DDR2_DATA09

DDR2_DATA10

DDR2_DATA11

DDR2_DATA12

DDR2_DATA13

DDR2_DATA14

DDR2_DATA15

DDR2_DM0

DDR2_DM1

DDR2_DQS0

DDR2_DQS1

DDR2_ODT

DDR2_RAS

DAI_P09

DAI_P10

DAI_P11

GND

DAI_P12

GND

DAI_P13

GND

DAI_P14

GND

DAI_P15

GND

DAI_P16

GND

DAI_P17

GND

DAI_P18

GND

DAI_P19

GND

DAI_P20

GND

DDR2_ADDR0

DDR2_ADDR01

DDR2_ADDR02

DDR2_ADDR03

DDR2_ADDR04

DDR2_ADDR05

DDR2_ADDR06

DDR2_ADDR07

DDR2_ADDR08

DDR2_ADDR09

DDR2_ADDR10

DDR2_ADDR11

DDR2_ADDR12

DDR2_ADDR13

DDR2_ADDR14

DDR2_ADDR15

DDR2_BA0

DDR2_BA1

DDR2_BA2

DDR2_CAS

GND

E05

GND

E12

GND

E13

GND

E16

GND

F01

F02

GND

F04

GND

F14

GND

F16

GND

G03

G04

G05

G07

G08

G09

G10

G11

G12

G15

H04

GND

DDR2_WE

GND

DPI_P01

GND

AMI_MS1

DPI_P02

GND

AMI_RD

DPI_P03

GND

AMI_WR

V10

J02

DPI_P04

GND

BOOT_CFG0

BOOT_CFG1

BOOT_CFG2

CLK_CFG0

DPI_P05

GND

J03

DPI_P06

GND

H03

G01

DPI_P07

GND

DPI_P08

GND

Rev. 0

|

Page 66 of 72

|

June 2010

ADSP-21469

Table 59. CSP_BGA Ball Assignment (Alphabetical by Signal) (Continued)

Signal

GND

Ball No.

H07

H08

H09

H10

H11

H12

J01

Signal

GND

Ball No.

V01

V18

K17

P17

J18

Signal

Ball No.

E04

E07

E10

E11

E17

F03

F05

F15

G14

G16

H15

H18

J05

Signal

Ball No.

F13

V_DD

_

DDR

EXT

INT

2

_INT

_THD

GND

G06

G13

H05

H06

H13

H14

J06

LACK_0

LACK_1

LCLK_0

LCLK_1

LDAT0_0

LDAT0_1

LDAT0_2

LDAT0_3

LDAT0_4

LDAT0_5

LDAT0_6

LDAT0_7

LDAT1_0

LDAT1_1

LDAT1_2

LDAT1_3

LDAT1_4

LDAT1_5

LDAT1_6

LDAT1_7

NC

N18

E18

F17

F18

G17

G18

H16

H17

J16

J07

J08

J13

J09

K06

K13

L06

J10

J11

J12

L13

J14

J15

M06

M13

N06

N07

N08

N09

N13

N10

D04

D11

K01

J17

K18

L16

K14

L05

M14

M18

N05

P06

P08

P10

P12

P14

P15

T08

T09

U08

U09

V08

V09

D12

E06

E08

E09

E14

E15

F06

F07

F08

F09

F10

F11

F12

K05

K07

K08

K09

K10

K11

K12

L07

L08

L09

L10

L11

L12

L14

M05

M07

M08

M09

M10

M11

M12

N14

N17

P05

P07

P09

P11

P13

R09

L17

L18

M16

M17

N16

P16

K03

K04

L02

V_REF

NC

XTAL

NC

L03

NC

L04

RESET

M01

M02

K15

L15

RESETOUT/RUNRSTIN

TCK

TDI

TDO

M15

N12

N11

K16

N15

H01

C05

C12

D03

D06

D08

D18

E02

THD_M

THD_P

TMS

INT

TRST

INT

VDD_A

INT

V_DD

_DDR

2

INT

Rev. 0

|

Page 67 of 72

|

June 2010

ADSP-21469

A1 CORNER

INDEX AREA

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18

A

B

C

D

E

F

D

R

D

R

D

G

A

S

H

J

K

L

M

N

P

R

T

U

V

D

R

T

DD_INT

DD_DDR2

REF

V

DD_EXT

GND

NC

DD_THD

DD_A

A

S

AGND

I/O SIGNALS

Figure 59. Ball Configuration, Standard Model

Rev. 0

|

Page 68 of 72

|

June 2010

ADSP-21469

OUTLINE DIMENSIONS

The ADSP-21469 processor is available in a 19 mm by 19 mm

CSP_BGA lead-free package.

19.10

19.00 SQ

18.90

A1 BALL

CORNER

18 16 14 12 10

17 15 13 11

8

6

4

2

A1 BALL

CORNER

9

7

5

3

1

A

C

E

G

J

B

D

F

17.00

BSC SQ

H

K

M

P

T

L

1.00

BSC

N

R

U

V

1.00

REF

TOP VIEW

DETAIL A

BOTTOM VIEW

*

1.80

1.71

1.56

1.31

1.21

1.11

DETAIL A

0.50 NOM

0.45 MIN

0.70

0.60

SEATING

PLANE

COPLANARITY

0.20

0.50

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-192-AAG-1 WITH

THE EXCEPTION TO PACKAGE HEIGHT.

Figure 60. 324-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]

(BC-324-1)

Dimensions shown in millimeters

SURFACE-MOUNT DESIGN

The following table is provided as an aid to PCB design. For

industry-standard design recommendations, refer to IPC-7351,

Generic Requirements for Surface-Mount Design and Land Pat-

tern Standard.

Package Solder Mask

Opening

Package

Package Ball Attach Type

Package Ball Pad Size

0.6 mm diameter

324-Ball CSP_BGA (BC-324-1)

Solder Mask Defined

0.43 mm diameter

Rev. 0

|

Page 69 of 72

|

June 2010

ADSP-21469

AUTOMOTIVE PRODUCTS

The ADSP-21469W model is available with controlled manu-

facturing to support the quality and reliability requirements of

automotive applications. Note that automotive models may

have specifications that differ from commercial models and

designers should review the Specifications section of this data

sheet carefully. Only the automotive grade products shown in

Table 60 are available for use in automotive applications. Con-

tact your local ADI account representative for specific product

ordering information and to obtain the specific Automotive

Reliability reports for these models.

Table 60. Automotive Products

Model ¹

AD21469WBBCZ3xx³

Temperature Range²On-Chip SRAM Package Description

–40°C to +85°C 5M bit 324-Ball Grid Array (CSP_BGA)

Package Option

BC-324-1

1

Z = RoHS compliant part.

²Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 17 for junction temperature (T_J)

specification, which is the only temperature specification.

³xx denotes silicon revision.

ORDERING GUIDE

Temperature

Range²

On-Chip

SRAM

Processor Instruction

Rate (Max)

Package

Option

Model ¹

Package Description

ADSP-21469KBCZ-3

ADSP-21469BBCZ-3

ADSP-21469KBCZ-4

¹Z = RoHS compliant part.

0C to +70C

5M bit

400 MHz

450 MHz

324-Ball Grid Array (CSP_BGA)

BC-324-1

–40C to +85C 5M bit

0C to +70C 5M bit

²Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 17 for junction temperature (T_J)

specification, which is the only temperature specification.

Rev. 0

|

Page 70 of 72

|

June 2010

ADSP-21469

Rev. 0

|

Page 71 of 72

|

June 2010

ADSP-21469

registered trademarks are the property of their respective owners.

D07900-0-6/10(0)

Rev. 0

|

Page 72 of 72

|

June 2010


型号：	ADSP-21469KBCZ-4
厂家：	ADI
描述：	SHARC Processor SHARC处理器微控制器和处理器外围集成电路数字信号处理器时钟
文件：	总72页 (文件大小：2169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21469KBCZ-4 [ADI]

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