ADSP-21478BSWZ-2AX_技术文档

SHARC Processor

Preliminary Technical Data

ADSP-21478/ADSP-21479

Qualified for Automotive Applications . See Automotive

Products on Page 69

SUMMARY

Note: This datasheet is preliminary. This document contains

material that is subject to change without notice.

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—5 Mbits of on-chip RAM, 4 Mbits of on-chip

ROM

Up to 300 MHz operating frequency

Code compatible with all other members of the SHARC family

The ADSP-2147x processors are available with unique audio-

centric peripherals such as the digital applications

interface, serial ports, precision clock generators, S/PDIF

transceiver, asynchronous sample rate converters, input

data port, and more.

For complete ordering information, see Ordering Guide on

Page 69.

Internal Memory

SIMD Core

Block 0

RAM/ROM

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

Instruction

Cache

5 Stage

Sequencer

B2D

64-BIT

B0D

64-BIT

B3D

64-BIT

B1D

64-BIT

Core

Timer

S

DAG1/2

PEx

DMD

64-BIT

DMD

64-BIT

PEy

Core Bus

Cross Bar

Internal Memory I/F

PMD

64-BIT

PMD 64-BIT

FLAGx/IRQx/

TMREXP

IOD0 32-BIT

THERMAL

DIODE

EPD BUS 64-BIT

JTAG

IOD1

32-BIT

PERIPHERAL BUS

32-BIT

IOD0 BUS

FFT

FIR

IIR

DTCP/

MTM

PERIPHERAL BUS

EP

SPEP BUS

CORE

PCG

PDAP/

IDP

7-0

S/PDIF PCG ASRC

SPORT

7-0

SDRAM

CTL

SHIFT

REG

CORE PWM

TIMER

1-0

AMI

FLAGS/

TWI SPI/B UART

RTC WDT MLB

Tx/Rx

A

-D

3

-0

FLAGS

3-0

C

-D

PWM3-1

DAI Routing/Pins

DPI Routing/Pins

External Port Pin MUX

External

Port

Peripherals

DAI Peripherals

DPI Peripherals

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.326.3113

www.analog.com

ADSP-21478/ADSP-21479

Preliminary Technical Data

TABLE OF CONTENTS

Summary ............................................................... 1

Revision History ...................................................... 2

General Description ................................................. 3

Family Core Architecture ........................................ 4

Family Peripheral Architecture ................................ 7

I/O Processor Features ......................................... 11

System Design .................................................... 12

Development Tools ............................................. 12

Additional Information ........................................ 13

Related Signal Chains .......................................... 13

Pin Function Descriptions ....................................... 14

Specifications ........................................................ 19

Operating Conditions .......................................... 19

Electrical Characteristics ....................................... 20

Package Information ........................................... 22

ESD Sensitivity ................................................... 22

Maximum Power Dissipation ................................. 22

Absolute Maximum Ratings ................................... 22

Timing Specifications ........................................... 23

Output Drive Currents ......................................... 61

Test Conditions .................................................. 61

Capacitive Loading .............................................. 61

Thermal Characteristics ........................................ 62

100-LQFP_EP Lead Assignment ................................ 64

196-Ball BGA Ball Assignment .................................. 66

Outline Dimensions ................................................ 67

Surface-Mount Design .......................................... 68

Automotive Products .............................................. 69

Ordering Guide ..................................................... 69

REVISION HISTORY

2/11—Rev. PrC to PrD

This version of the data sheet has replaced most of the TBDs

from the previous version. This version also has the following

revisions and or additions.

Added power numbers to Table 12, Table 13 and

Table 14 ................................................................ 21

Revised Automotive Products .................................... 69

Revised Ordering Guide ........................................... 69

Rev. PrD

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February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

GENERAL DESCRIPTION

The ADSP-21478/ADSP-21479 SHARC^®processors are mem-

bers of the SIMD SHARC family of DSPs that feature Analog

Devices' Super Harvard Architecture. The processors are source

code compatible with the ADSP-2126x, ADSP-2136x,

Table 2. ADSP-2147x Family Features (Continued)

Feature

ADSP-21478

ADSP-21479

DAI (SRU)/DPI (SRU2)

S/PDIF Transceiver

SPI

20/14 pins

ADSP-2137x, ADSP-2146x, and ADSP-2116x DSPs as well as

with first generation ADSP-2106x SHARC processors in SISD

(single-instruction, single-data) mode. These new processors

are 32-bit/40-bit floating point processors optimized for high

performance audio applications with its large on-chip SRAM,

multiple internal buses to eliminate I/O bottlenecks, and an

innovative digital applications interface (DAI).

Table 1 shows performance benchmarks for the ADSP-2147x

processors. Table 2 shows the features of the individual product

offerings.

1

2

TWI

1

SRC SNR Performance

Thermal Diode³

VISA Support

Package¹

–128 dB

Yes

196-Ball CSP_BGA

100-Lead LQFP

Table 1. Processor Benchmarks

¹The 100-lead packages of the ADSP-21478 and 21479 processors do not contain

an external port. The SDRAM controller pins must be disabled when using this

package. For more information, see Pin Function Descriptions on Page 15.

²Available on the 196-Ball CSP_BGA package only.

Speed

(at 300 MHz)

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, With Reversal) 30.59 μs

FIR Filter (per Tap)¹

IIR Filter (per Biquad)¹

³Available on the 100-lead package only.

1.66 ns

6.65 ns

The diagram on Page 1 shows the two clock domains that make

up the ADSP-2147x processors. The core clock domain contains

the following features.

• Two processing elements (PEx, PEy), each of which com-

prises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]

[4 × 4] × [4 × 1]

14.99 ns

26.66 ns

Divide (y/×)

11.61 ns

18.08 ns

Inverse Square Root

¹Assumes two files in multichannel SIMD mode.

• PM and DM buses capable of supporting 2x64-bit data

transfers between memory and the core at every core pro-

cessor cycle

• One periodic interval timer with pinout

• On-chip SRAM (up to 5M bit)

• JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points which allows flexible exception handling.

The block diagram of the ADSP-2147x on Page 1 also shows the

peripheral clock domain (also known as the I/O processor)

which contains the following features:

• IOD0 (peripheral DMA) and IOD1 (external port DMA)

buses for 32-bit data transfers

• Peripheral and external port buses for core connection

• External port with an AMI and SDRAM controller

• 4 units for PWM control

Table 2. ADSP-2147x Family Features

Feature

ADSP-21478

ADSP-21479

Frequency

Up to 300 MHz

3M bits 5M bits

RAM

N/A

ROM

Pulse-Width Modulation

4 Units (3 in 100-lead package)

Yes, 16-bit

External Port Interface

(SDRAM, AMI)¹

Serial Ports

8

Direct DMA from SPORTs to

External Memory

Yes

FIR, IIR, FFT Accelerator

MediaLB Interface

Watch Dog Timer²

Real-time Clock²

Shift Register²

IDP/PDAP

Yes

Automotive Models Only

Yes

1

• 1 MTM unit for internal-to-internal memory transfers

• Digital applications interface that includes four precision

clock generators (PCG), an input data port (IDP/PDAP)

for serial and parallel interconnect, an S/PDIF

UART

Rev. PrD

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February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

receiver/transmitter, four asynchronous sample rate con-

verters, eight serial ports, a shift register, and a flexible

signal routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, a 2-

wire interface, one UART, two serial peripheral interfaces

(SPI), 2 precision clock generators (PCG), three pulse

width modulation (PWM) units, and a flexible signal rout-

ing unit (DPI SRU).

Timer

The processor contains a core timer that can generate periodic

software interrupts. The core timer can be configured to use

FLAG3 as a timer expired signal.

As shown in the SHARC core block diagram on Page 5, the pro-

cessor uses two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. With its SIMD computational hard-

ware, the processors can perform 1.8 GFLOPS running at 300

MHz.

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register (16 primary, 16 secondary) register files,

combined with the processor’s enhanced Harvard architecture,

allow unconstrained data flow between computation units and

internal memory. The registers in PEX are referred to as

R0–R15 and in PEY as S0–S15.

FAMILY CORE ARCHITECTURE

The ADSP-2147x is code compatible at the assembly level with

the ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,

ADSP-21160, and ADSP-21161, and with the first generation

ADSP-2106x SHARC processors. The ADSP-2147x shares

architectural features with the ADSP-2126x, ADSP-2136x,

ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD SHARC

processors, as shown in Figure 2 and detailed in the following

sections.

Context Switch

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result registers all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

SIMD Computational Engine

Universal Registers

The ADSP-2147x contains two computational processing ele-

ments that operate as a single-instruction, multiple-data

(SIMD) engine. The processing elements are referred to as PEX

and PEY and each contains an ALU, multiplier, shifter, and reg-

ister file. PEX is always active, and PEY may be enabled by

setting the PEYEN mode bit in the MODE1 register. SIMD

mode allows the processor to execute the same instruction in

both processing elements, but each processing element operates

on different data. This architecture is efficient at executing math

intensive DSP algorithms.

Universal registers can be used for general-purpose tasks. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all peripheral control and status

registers.

The data bus exchange register (PX) permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM/DM data bus. These

registers contain hardware to handle the data width difference.

SIMD mode also affects the way data is transferred between

memory and the processing elements because twice the data

bandwidth is required to sustain computational operation in the

processing elements. Therefore, entering SIMD mode also dou-

bles the bandwidth between memory and the processing

elements. When using the DAGs to transfer data in SIMD

mode, two data values are transferred with each memory or reg-

ister file access.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-2147x features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 2). With its separate program and data memory

buses and on-chip instruction cache, the processor can simulta-

neously fetch four operands (two over each data bus) and one

instruction (from the cache), all in a single cycle.

SIMD mode is supported from external SDRAM but is not sup-

ported in the AMI.

Instruction Cache

The processor includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

Rev. PrD

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February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

S

JTAG

FLAG TIMER INTERRUPT CACHE

SIMD Core

PM ADDRESS 24

PM DATA 48

DMD/PMD 64

5 STAGE

PROGRAM SEQUENCER

DAG2

16x32

DAG1

16x32

PM ADDRESS 32

SYSTEM

I/F

DM ADDRESS 32

PM DATA 64

USTAT

4x32-BIT

PX

64-BIT

DM DATA 64

DATA

SWAP

RF

Rx/Fx

PEx

RF

Sx/SFx

PEy

ALU

SHIFTER

MULTIPLIER

ALU

SHIFTER MULTIPLIER

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MRF

80-BIT

MSF

80-BIT

ASTATy

STYKy

ASTATx

STYKx

Figure 2. SHARC Core Block Diagram

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from

previous SHARC processors, the ADSP-2147x supports new

instructions of 16 and 32 bits. This feature, called Variable

Instruction Set Architecture (VISA), drops redundant/unused

bits within the 48-bit instruction to create more efficient and

compact code. The program sequencer supports fetching these

16-bit and 32-bit instructions from both internal and external

SDRAM memory. This support is not extended to the asynchro-

nous memory interface (AMI). Source modules need to be built

using the VISA option, in order to allow code generation tools

to create these more efficient opcodes.

The ADSP-2147x’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs of the processors contain

sufficient registers to allow the creation of up to 32 circular buf-

fers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

On-Chip Memory

Flexible Instruction Set

The ADSP-21478 processor contains 3 Mbits of internal RAM

(Table 3) and the ADSP-21479 processor contains 5 Mbits of

internal RAM (Table 4). Each block can be configured for dif-

ferent combinations of code and data storage. Each memory

block supports single-cycle, independent accesses by the core

processor and I/O processor.

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-2147x can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

Rev. PrD

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February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

The processor’s SRAM can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data, 106.7k

words of 48-bit instructions (or 40-bit data), or combinations of

different word sizes up to 5 megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit

floating-point storage format is supported that effectively dou-

bles the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point

formats is performed in a single instruction. While each mem-

ory block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

The memory maps in Table 4 and Table 5 display the internal

memory address space of the processors. The 48-bit space sec-

tion describes what this address range looks like to an

instruction that retrieves 48-bit memory. The 32-bit section

describes what this address range looks like to an instruction

that retrieves 32-bit memory.

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming

there are no block conflicts). The total bandwidth is realized

using the DMD and PMD buses (2 x 64-bits, CCLK speed) and

the IOD0/1 buses (2 x 32-bit, PCLK speed).

Using the DM bus and PM buses, with one bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

Table 3. ADSP-21478 Internal Memory Space (3M Bit)¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Instruction Word (48 Bits)

Long Word (64 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

0x0008 0000–0x0008 AAA9

0x0008 0000–0x0008 FFFF

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

0x0008 AAAA–0x0008 BFFF

0x0009 0000–0x0009 1FFF

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 CFFF

0x0008 C000–0x0009 1554

0x0009 2000–0x0009 9FFF

0x0012 4000–0x0013 3FFF

Reserved

0x0004 D000–0x0004 FFFF

0x0009 1555–0x0009 FFFF

0x0009 A000–0x0009 FFFF

0x0013 4000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

0x000A 0000–0x000A AAA9

0x000A 0000–0x000A FFFF

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

0x000A AAAA–0x000A BFFF

0x000B 0000–0x000B 1FFF

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 CFFF

0x000A C000–0x000B 1554

0x000B 2000–0x000B 9FFF

0x0016 4000–0x0017 3FFF

Reserved

0x0005 D000–0x0005 FFFF

0x000B 1555–0x000B FFFF

0x000B A000–0x000B FFFF

0x0017 4000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 1FFF

0x000C 0000–0x000C 2AA9

0x000C 0000–0x000C 3FFF

0x0018 0000–0x0018 7FFF

Reserved

0x0006 2000– 0x0006 FFFF

0x000C 2AAA–0x000D FFFF

0x000C 4000–0x000D FFFF

0x0018 8000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 1FFF

0x000E 0000–0x000E 2AA9

0x000E 0000–0x000E 3FFF

0x001C 0000–0x001C 7FFF

Reserved

0x0007 2000–0x0007 FFFF

0x000E 2AAA–0x000F FFFF

0x000E 4000–0x000F FFFF

0x001C 8000–0x001F FFFF

¹Some ADSP-2147x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog

Devices sales representative for additional details.

Rev. PrD

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February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

Table 4. ADSP-21479 Internal Memory Space (5M Bit)¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Instruction Word (48 Bits)

Long Word (64 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

0x0008 0000–0x0008 AAA9

0x0008 0000–0x0008 FFFF

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

0x0008 AAAA–0x0008 BFFF

0x0009 0000–0x0009 1FFF

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 EFFF

0x0008 C000–0x0009 3FFF

0x0009 2000–0x0009 DFFF

0x0012 4000–0x0013 BFFF

Reserved

0x0004 F000–0x0004 FFFF

0x0009 4000–0x0009 FFFF

0x0009 E000–0x0009 FFFF

0x0013 C000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

0x000A 0000–0x000A AAA9

0x000A 0000–0x000AFFFF

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

0x000A AAAA–0x000A BFFF

0x000B 0000–0x000B 1FFF

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 EFFF

0x000A C000–0x000B 3FFF

0x000B 2000–0x000B DFFF

0x0016 4000–0x0017 BFFF

Reserved

0x0005 F000–0x0005 FFFF

0x000B 4000–0x000B FFFF

0x000B E000–0x000B FFFF

0x0017 C000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 3FFF

0x000C 0000–0x000C 5554

0x000C 0000–0x000C 7FFF

0x0018 0000–0x0018 FFFF

Reserved

0x0006 4000– 0x0006 FFFF

0x000C 5555–0x0000D FFFF

0x000C 8000–0x000D FFFF

0x0019 0000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 3FFF

0x000E 0000–0x000E 5554

0x000E 0000–0x000E 7FFF

0x001C 0000–0x001C FFFF

Reserved

0x0007 4000–0x0007 FFFF

0x000E 5555–0x0000F FFFF

0x000E 8000–0x000F FFFF

0x001D 0000–0x001F FFFF

¹Some ADSP-2147x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog

Devices sales representative for additional details.

scrambling system) is protected by this copy protection system.

For more information on this feature, contact your local ADI

sales office.

ROM Based Security

The ADSP-2147x has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the processor does not boot-load any

external code, executing exclusively from internal ROM. Addi-

tionally, the processor is not freely accessible via the JTAG port.

Instead, a unique 64-bit key, which must be scanned in through

the JTAG or Test Access Port is assigned to each customer. The

device ignores a wrong key. Emulation features are available

after the correct key is scanned.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-2147x family contains a rich set of peripherals that

support a wide variety of applications including high quality

audio, medical imaging, communications, military, test equip-

ment, 3D graphics, speech recognition, motor control, imaging,

and other applications.

External Port

Digital Transmission Content Protection

The external port is available in the 196-ball CSP_BGA package.

The interface supports access to the external memory through

core and DMA accesses. The external memory address space is

divided into four banks. Any bank can be programmed as either

asynchronous or synchronous memory. The external ports are

comprised of the following modules.

The DTCP specification defines a cryptographic protocol for

protecting audio entertainment content from illegal copying,

intercepting, and tampering as it traverses high performance

digital buses, such as the IEEE 1394 standard. Only legitimate

entertainment content delivered to a source device via another

approved copy protection system (such as the DVD content

Rev. PrD

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February 2011

ADSP-21478/ADSP-21479

• An Asynchronous Memory Interface which communicates

with SRAM, FLASH, and other devices that meet the stan-

dard asynchronous SRAM access protocol. The AMI

supports 6M words of external memory in bank 0 and 8M

words of external memory in bank 1, bank 2, and bank 3.

• An SDRAM controller that supports a glueless interface

with any of the standard SDRAMs. The SDC supports 62M

words of external memory in bank 0, and 64M words of

external memory in bank 1, bank 2, and bank 3.

Preliminary Technical Data

Table 6. External Bank 0 Instruction Fetch

Size in

Access Type Words

Address Range

ISA (NW)

4M

0x0020 0000 - 0x005F FFFF

0x0060 0000 – 0x00FF FFFF

VISA (SW)

10M

SDRAM Controller

• Arbitration logic to coordinate core and DMA transfers

between internal and external memory over the external

port.

The SDRAM controller, available on the ADSP-21479 in the

196-ball CSP_BGA package, provides an interface of up to four

separate banks of industry-standard SDRAM devices or

DIMMs, at speeds up to f_SDCLK. Fully compliant with the

SDRAM standard, each bank has its own memory select line

(MS0–MS3), and can be configured to contain between

4M bytes and 256M bytes of memory. SDRAM external mem-

ory address space is shown in Table 7.

External Port

The external port provides a high performance, glueless inter-

face to a wide variety of industry-standard memory devices. The

external port, available on the 196-ball CSP_BGA, may be used

to interface to synchronous and/or asynchronous memory

devices through the use of its separate internal memory control-

lers. The first is an SDRAM controller for connection of

industry-standard synchronous DRAM devices while the sec-

ond is an asynchronous memory controller intended to

interface to a variety of memory devices. Four memory select

pins enable up to four separate devices to coexist, supporting

any desired combination of synchronous and asynchronous

device types. Non-SDRAM external memory address space is

shown in Table 5.

Table 7. External Memory for SDRAM Addresses

Size in

Words

Bank

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

62M

0x0020 0000–0x03FF FFFF

0x0400 0000–0x07FF FFFF

0x0800 0000–0x0BFF FFFF

0x0C00 0000–0x0FFF FFFF

64M

Table 5. External Memory for Non-SDRAM Addresses

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. Note

that 32-bit wide devices are not supported on SDRAM and the

AMI interface.

The SDRAM controller address, data, clock, and control pins

can drive loads up to distributed 30 pF. For larger memory sys-

tems, the SDRAM controller external buffer timing should be

selected and external buffering should be provided so that the

load on the SDRAM controller pins does not exceed 30 pF.

Size in

Words

6M

Bank

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

0x0020 0000–0x007F FFFF

0x0400 0000–0x047F FFFF

0x0800 0000–0x087F FFFF

0x0C00 0000–0x0C7F FFFF

8M

SIMD Access to External Memory

The SDRAM controller on the processor supports SIMD access

on the 64-bit EPD (external port data bus) which allows to

access the complementary registers on the PEy unit in the nor-

mal word space (NW). This improves performance since there

is no need to explicitly load the complimentary registers as in

SISD mode.

Note that the external memory bank addresses shown are for

normal-word (32-bit) accesses. If 48-bit instructions as well as

32-bit data are both placed in the same external memory bank,

care must be taken while mapping them to avoid overlap.

Asynchronous Memory Controller

The asynchronous memory controller, available on the

ADSP-21479 in the 196-ball CSP_BGA package, provides a con-

figurable interface for up to four separate banks of memory or

I/O devices. Each bank can be independently programmed with

different timing parameters, enabling connection to a wide vari-

ety of memory devices including SRAM, flash, and EPROM, as

well as I/O devices that interface with standard memory control

lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3

occupy a 8M word window in the processor’s address space but,

if not fully populated, these windows are not made contiguous

by the memory controller logic.

VISA and ISA Access to External Memory

The SDRAM controller on the ADSP-2147x processors sup-

ports VISA code operation which reduces the memory load

since the VISA instructions are compressed. Moreover, bus

fetching is reduced because, in the best case, one 48-bit fetch

contains three valid instructions. Code execution from the tra-

ditional ISA operation is also supported. Note that code

execution is only supported from bank 0 regardless of

VISA/ISA. Table 6 shows the address ranges for instruction

fetch in each mode.

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Preliminary Technical Data

ADSP-21478/ADSP-21479

path to the SHARC core, configurable as either eight channels

of serial data, or a single 20-bit wide synchronous parallel data

acquisition port. Each data channel has its own DMA channel

that is independent from the processor’s serial ports.

External Port Throughput

The throughput for the external port, based on 133 MHz clock

and 16-bit data bus, is 88 M bytes/s for the AMI and 266 M

bytes/s for SDRAM.

Serial Ports (SPORTs)

MediaLB

The ADSP-2147x features eight synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports can support up to 16 transmit or 16 receive DMA

channels of audio data when all eight SPORTs are enabled, or

four full duplex TDM streams of 128 channels per frame.

The automotive models of the ADSP-2147x processors have an

MLB interface which allows the processor to function as a

media local bus device. It includes support for both 3-pin as well

as 5-pin media local bus protocols. It supports speeds up to 1024

FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical

channels, with up to 124 bytes of data per media local bus frame.

For a list of automotive products, see Automotive Products on

Page 69.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. One SPORT pro-

vides two transmit signals while the other SPORT provides the

two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard serial mode

• Multichannel (TDM) mode

• I²S mode

The entire PWM module has four groups of four PWM outputs

generating 16 PWM outputs in total. Each PWM group pro-

duces two pairs of PWM signals on the four PWM outputs.

• Packed I²S mode

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

midpoint of the PWM period. In double update mode, a second

updating of the PWM registers is implemented at the midpoint

of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

• Left-justified mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the

receiver/transmitter can be formatted as left justified, I²S or

right-justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources, such as the

SPORTs, external pins, the precision clock generators (PCGs),

and are controlled by the SRU control registers.

PWM signals can be mapped to the external port address lines

or to the DPI pins.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the DAI pins

(DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

Asynchronous Sample Rate Converter (SRC)

The sample rate converter contains four blocks and is the same

core as that used in the AD1896 192 kHz stereo asynchronous

sample rate converter and provides up to 128 dB SNR. The SRC

block is used to perform synchronous or asynchronous sample

rate conversion across independent stereo channels, without

using internal processor resources. The four SRC blocks can

also be configured to operate together to convert multichannel

audio data without phase mismatches. Finally, the SRC can be

used to clean up audio data from jittery clock sources such as

the S/PDIF receiver.

The DAI also includes eight serial ports, four precision clock

generators (PCG), S/PDIF transceiver, four ASRCs, and an

input data port (IDP). The IDP provides an additional input

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ADSP-21478/ADSP-21479

Preliminary Technical Data

Input Data Port

standard. The UART port also includes support for 5 to 8 data

bits, 1 or 2 stop bits, and none, even, or odd parity. The UART

port supports two modes of operation:

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

audio channels in I²S, left-justified sample pair, or right-justified

mode.

The IDP also provides a parallel data acquisition port (PDAP)

which can be used for receiving parallel data. The PDAP port

has a clock input and a hold input. The data for the PDAP can

be received from DAI pins or from the external port pins. The

PDAP supports a maximum of 20-bit data and four different

packing modes to receive the incoming data.

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

Precision Clock Generators

• Support for bit rates ranging from (f_PCLK/1,048,576) to

(f_PCLK/16) bits per second.

• Support for data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The precision clock generators (PCG) consist of four units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A B, C, and D, are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

The outputs of PCG A and B can be routed through the DAI

pins and the outputs of PCG C and D can be driven on to the

DAI as well as the DPI pins.

Timers

The ADSP-2147x has a total of three timers: a core timer that

can generate periodic software interrupts and two general-pur-

pose timers that can generate periodic interrupts and be

independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watch dog mode

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two

serial peripheral interface ports (SPI), one universal asynchro-

nous receiver-transmitter (UART), 12 flags, a 2-wire interface

(TWI), three PWM modules (PWM3–1), and two general-pur-

pose timers.

Serial Peripheral (Compatible) Interface (SPI)

The core timer can be configured to use FLAG3 as a timer

expired signal, and the general-purpose timers have one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables the general-

purpose timer.

The SPI is an industry-standard synchronous serial link,

enabling the SPI-compatible port to communicate with other

SPI compatible devices. The SPI consists of two data pins, one

device select pin, and one clock pin. It is a full-duplex synchro-

nous serial interface, supporting both master and slave modes.

The SPI port can operate in a multimaster environment by

interfacing with up to four other SPI-compatible devices, either

acting as a master or slave device. The SPI-compatible periph-

eral implementation also features programmable baud rate and

clock phase and polarities. The SPI-compatible port uses open

drain drivers to support a multimaster configuration and to

avoid data contention.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I²C bus protocol.

The TWI master incorporates the following features:

• 7-bit addressing

UART Port

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

The processors provide a full-duplex Universal Asynchronous

Receiver/Transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface

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Preliminary Technical Data

Shift Register

ADSP-21478/ADSP-21479

Table 8. DMA Channels (Continued)

The shift register can be used as a serial to parallel data con-

verter. The shift register module consists of an 18-stage serial

shift register, 18-bit latch, and three-state output buffers. The

shift register and latch have separate clocks. Data is shifted into

the serial shift register on the positive-going transitions of the

shift register serial clock (SR_SCLK) input. The data in each

flip-flop is transferred to the respective latch on a positive-going

transition of the shift register latch clock (SR_LAT) input.

Peripheral

UART

DMA Channels

2

External Port

Accelerators

Memory-to-Memory

MLB¹

2

31

¹Automotive models only.

The shift register’s signals can be configured as follows.

• The SR_SCLK can come from any of the SPORT0–7 SCLK

outputs, PCGA/B clock, any of the DAI pins (1–8), and one

dedicated pin (SR_SCLK).

• The SR_LAT can come from any of SPORT0–7 Frame sync

outputs, PCGA/B frame sync, any of the DAI pins (1–8),

and one dedicated pin (SR_LAT).

• The SR_SDI input can from any of SPORT0–7 serial data

outputs, any of the DAI pins (1–8), and one dedicated pin

(SR_SDI).

Delay Line DMA

The processor provides delay line DMA functionality. This

allows processor reads and writes to external delay line buffers

(and hence to external memory) with limited core interaction.

Scatter/Gather DMA

The processor provides scatter/gather DMA functionality. This

allows processor DMA reads/writes to/from non-contingeous

memory blocks.

FFT Accelerator

Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must

come from same source except in the case of where SR_SCLK

comes from PCGA/B or SR_SCLK and SR_LAT come from

PCGA/B.

FFT accelerator implements radix-2 complex/real input, com-

plex output FFT with no core intervention. The FFT accelerator

runs at the peripheral clock frequency.

If SR_SCLK comes from PCGA/B, then SPORT0–7 generates

the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT

come from PCGA/B, then SPORT0–7 generates the SR_SDI

signal.

FIR Accelerator

The FIR (finite impulse response) accelerator consists of a 1024

word coefficient memory, a 1024 word deep delay line for the

data, and four MAC units. A controller manages the accelerator.

The FIR accelerator runs at the peripheral clock frequency.

I/O PROCESSOR FEATURES

The I/O processor provides up to 65 channels of DMA as well as

an extensive set of peripherals.

IIR Accelerator

The IIR (infinite impulse response) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency.

DMA Controller

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the ADSP-2147x’s internal memory and its serial ports,

the SPI-compatible (serial peripheral interface) ports, the IDP

(input data port), the parallel data acquisition port (PDAP) or

the UART.

Up to 65 channels of DMA are available on the ADSP-2147x

processors as shown in Table 8.

Programs can be downloaded to the ADSP-2147x using DMA

transfers. Other DMA features include interrupt generation

upon completion of DMA transfers, and DMA chaining for

automatic linked DMA transfers.

Watch Dog Timer

The watch dog timer is used to supervise stability of the system

software. When used in this way, software reloads the watch dog

timer in a regular manner so that the downward counting timer

never expires. An expiring timer then indicates that system soft-

ware might be out of control.

The ADSP-2147x processors include a 32-bit watch dog timer

that can be used to implement a software watch dog function. A

software watch dog can improve system reliability by forcing the

processor to a known state through generation of a system reset,

if the timer expires before being reloaded by software. Software

initializes the count value of the timer, and then enables the

timer.

Table 8. DMA Channels

The watch dog timer resets both the core and the internal

peripherals. Software must be able to determine if the watch dog

was the source of the hardware reset by interrogating a status bit

in the watch dog timer control register.

Peripheral

SPORTs

PDAP

DMA Channels

16

8

SPI

2

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ADSP-21478/ADSP-21479

Preliminary Technical Data

The WDT contains a software programmable Trip Counter reg-

ister that sets the number of times that the WDT can expire

before the WDTRSTO pin is continually asserted until the next

time hardware reset is applied. The trip counter is not cleared by

the WDT generated reset. This gives software the ability to

count the number of WDT generated resets using the CUR-

TRIPVAL field in the trip counter register.

Program Booting

The internal memory of the ADSP-2147x boots at system

power-up from an 8-bit EPROM via the external port, an SPI

master, or an SPI slave. Booting is determined by the boot con-

figuration (BOOT_CFG2–0) pins in Table 9.

Table 9. Boot Mode Selection

Real-Time Clock

BOOT_CFG2–0¹Booting Mode

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the SHARC

processor. Connect RTC pins RTXI and RTXO with external

components as shown in Figure 3.

The RTC peripheral has dedicated power supply pins so that it

can remain powered up and clocked even when the rest of the

processor is in a low power state. The RTC provides several pro-

grammable interrupt options, including interrupt per second,

minute, hour, or day clock ticks, interrupt on programmable

stopwatch countdown, or interrupt at a programmed alarm

time. An RTCLKOUT signal that operates at 1Hz is also pro-

vided for calibration.

000

001

010

011

SPI Slave Boot

SPI Master Boot (from flash and other slaves)

AMI User Boot (for 8-bit Flash Boot)

No Boot (processor executes from internal

ROM after reset)

100

1xx

Reserved

¹The BOOT_CFG2 pin is not available on the 100-lead package.

The “Running Reset” feature is used to reset the processor core

and peripherals, but without resetting the PLL and SDRAM

controller, or performing a boot. The functionality of the RESE-

TOUT/RUNRSTIN pin has now been extended to also act as the

input for initiating a Running Reset. For more information, see

the ADSP-214xx SHARC Processor Hardware Reference.

RTXI

RTXO

R1

X1

Power Supplies

The processors have separate power supply connections for the

internal (V_{DD_INT}) and external (V_{DD_EXT}), power supplies. The

internal and analog supplies must meet the V_{DD_INT}specifica-

tions. The external supply must meet the V_{DD_EXT}specification.

All external supply pins must be connected to the same power

supply.

C1

C2

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V_{DD_INT}and GND.

Figure 3. External Components for RTC

Target Board JTAG Emulator Connector

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter. When the alarm

interrupt is enabled, the alarm function generates an interrupt

when the output of the timer matches the programmed value in

the alarm control register. There are two alarms: The first alarm

is for a time of day. The second alarm is for a day and time of

that day.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch inter-

rupt is enabled and the counter underflows, an interrupt is

generated.

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-2147x pro-

cessors to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processor stacks. The processor's JTAG interface ensures that

the emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User's Guide”.

DEVELOPMENT TOOLS

The ADSP-2147x processors are supported with a complete set

of CROSSCORE^®software and hardware development tools,

including Analog Devices emulators and VisualDSP++^®devel-

opment environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-2147x processors.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

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Preliminary Technical Data

EZ-KIT Lite Evaluation Board

ADSP-21478/ADSP-21479

ADDITIONAL INFORMATION

For evaluation of the processors, use the EZ-KIT Lite^®board

being developed by Analog Devices. The board comes with on-

chip emulation capabilities and is equipped to enable software

development. Multiple daughter cards are available.

This data sheet provides a general overview of the ADSP-2147x

architecture and functionality. For detailed information on the

ADSP-2147x family core architecture and instruction set, refer

to the SHARC Processor Programming Reference.

Designing an Emulator-Compatible DSP Board (Target)

RELATED SIGNAL CHAINS

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-

circuit emulation is assured by the use of the processor’s JTAG

interface—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the processor, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The processor must be halted to send data and

commands, but once an operation has been completed by the

emulator, the DSP system is set running at full speed with no

impact on system timing.

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

TM

The Circuits from the Lab site

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

(http://www.analog.com/signalchains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation plat-

forms to use as a cost effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++^®development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board Flash device to store

user-specific boot code, enabling the board to run as a stand-

alone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom defined system. Connecting one of Analog Devices JTAG

emulators to the EZ-KIT Lite board enables high speed, non-

intrusive emulation.

Rev. PrD

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ADSP-21478/ADSP-21479

Preliminary Technical Data

PIN FUNCTION DESCRIPTIONS

Table 10. Pin Descriptions

State During/

After Reset

Name

Type

Description

ADDR_23–0

I/O/T (ipu)

High-Z/driven External Address. The processor outputs addresses for external memory and

low (boot)

High-Z

peripherals on these pins. The ADDR pins can be multiplexed to support the

external memory interface address, FLAGS15–8 (I/O) and PWM (O). After reset, all

ADDR pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default).

When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the

ADDR_23–4pins for parallel input data.

DATA_15–0

AMI_ACK

I/O/T (ipu)

I (ipu)

External Data. The data pins can be multiplexed to support the external memory

interface data (I/O), and FLAGS_7–0(I/O).

MemoryAcknowledge. ExternaldevicescandeassertAMI_ACK(low) toaddwait

states to an external memory access. AMI_ACK is used by I/O devices, memory

controllers, or other peripherals to hold off completion of an external memory

access.

MS_0–1

O/T (ipu)

High-Z

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the

corresponding banks of external memory. The MS_1-0lines are decoded memory

address lines that change at the same time as the other address lines. When no

external memory access is occurring the MS_1-0lines are inactive; they are active

however when a conditional memory access instruction is executed, whether or

not the condition is true.

The MS1 pin can be used in EPORT/FLASH boot mode. For more information on

processor booting, see the ADSP-214xx SHARC Processor Hardware Reference.

AMI_RD

AMI_WR

O/T (ipu)

High-Z

AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word

from external memory.

AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to

external memory.

FLAG0/IRQ0

I/O (ipu)

FLAG[0] INPUT FLAG0/Interrupt Request0.

FLAG[1] INPUT FLAG1/Interrupt Request1.

FLAG1/IRQ1

FLAG2/IRQ2/MS2

FLAG[2] INPUT FLAG2/Interrupt Request2/Memory Select2. This pin is multiplexed with MS2

in the 196 BGA package only.

FLAG3/TMREXP/MS3 I/O (ipu)

FLAG[3] INPUT FLAG3/Timer Expired/Memory Select3. This pin is multiplexed with MS3 in the

196 BGA package only.

The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63kΩ.

The range of an ipd resistor can be between 31k–85kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.

Rev. PrD

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Page 14 of 70

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February 2011

Preliminary Technical Data

Table 10. Pin Descriptions (Continued)

ADSP-21478/ADSP-21479

State During/

After Reset

Name

Type

Description

SDRAS

O/T (ipu)

High-Z/

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with

driven high

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS

O/T (ipu)

High-Z/

driven high

SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction

with other SDRAM command pins, defines the operation for the SDRAM to

perform.

SDWE

SDCKE

SDA10

O/T (ipu)

High-Z/

driven high

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

High-Z/

driven high

SDRAMClock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

High-Z/

driven high

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-

SDRAM accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM

accesses.

SDDQM

O/T (ipu)

High-Z/

DQM Data Mask. SDRAM Input mask signal for write accesses and

driven high

ADSP-2147x output enable signal for read accesses. Input data is masked when

DQM is sampled high during a write cycle. The SDRAM output buffers are placed

in a High-Z state when DQM is sampled high during a read cycle. SDDQM is driven

high from reset de-assertion until SDRAM initialization completes. Afterwards, it

is driven low irrespective of whether any SDRAM accesses occur or not.

SDCLK

O/T (ipd)

High-Z/

driving

SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers.

See Figure 47 on page 61. For models in the 100-lead package, the SDRAM

interface should be disabled to avoid unnecessary power switching by setting the

DSDCTL bit in SDCTL register. For more information, see the ADSP-214xx SHARC

Processor Hardware Reference.

DAI _P_20–1

I/O/T (ipu)

High-Z

Digital Applications Interface. These pins provide the physical interface to the

DAI SRU. The DAI SRU configuration registers define the combination of on-chip

audiocentric peripheral inputs or outputs connected to the pin and to the pin’s

output enable. The configuration registers of these peripherals then determines

the exact behavior of the pin. Any input or output signal present in the DAI SRU

may be routed to any of these pins.

DPI _P_14–1

I/O/T (ipu)

Digital Peripheral Interface. These pins provide the physical interface to the DPI

SRU. The DPI SRU configuration registers define the combination of on-chip

peripheral inputs or outputs connected to the pin and to the pin's output enable.

The configuration registers of these peripherals then determines the exact

behavior of the pin. Any input or output signal present in the DPI SRU may be

routed to any of these pins.

WDT_CLKIN

WDT_CLKO

WDTRSTO

THD_P

I

Watch Dog Timer Clock Input. This pin should be pulled low when not used.

Watch Dog Resonator Pad Output.

O

O (ipu)

Watch Dog Timer Reset Out.

I

Thermal Diode Anode. When not used, this pin can be left floating.

Thermal Diode Cathode. When not used, this pin can be left floating.

THD_M

O

The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63kΩ.

The range of an ipd resistor can be between 31k–85kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.

Rev. PrD

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Page 15 of 70

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February 2011

ADSP-21478/ADSP-21479

Table 10. Pin Descriptions (Continued)

Preliminary Technical Data

State During/

After Reset

Name

Type

Description

MLBCLK

I

Media Local Bus Clock. This clock is generated by the MLB controller that is

synchronized to the MOST network and provides the timing for the entire MLB

interface at 49.152 MHz at FS=48 kHz. When the MLB controller is not used, this

pin should be grounded.

MLBDAT

MLBSIG

I/O/T in 3 pin

mode. I in 5 pin

mode.

High-Z

Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device

and is received by all other MLB devices including the MLB controller. The

MLBDAT line carries the actual data. In 5-pin MLB mode, this pin is an input only.

When the MLB controller is not used, this pin should be grounded.

I/O/T in 3 pin

mode. I in 5 pin

mode

Media Local Bus Signal. This is a multiplexed signal which carries the

Channel/Address generated by the MLB Controller, as well as the Command and

RxStatus bytes from MLB devices. In 5-pin mode, this pin is input only. When the

MLB controller is not used, this pin should be grounded.

MLBDO

MLBSO

O/T

High-Z

Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB

mode. This serves as the output data pin in 5-pin mode. When the MLB controller

is not used, this pin should be grounded.

Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin

MLB mode. This serves as the output signal pin in 5-pin mode. When the MLB

controller is not used, this pin should be grounded.

SR_SCLK

SR_CLR

SR_SDI

I (ipu)

O (ipu)

I (ipu)

O/T (ipu)

I

Shift Register Serial Clock. (Active high, rising edge sensitive)

Shift Register Reset. (Active LOW)

Shift Register Serial Data Input.

SR_SDO

SR_LAT

SR_LDO_17–0

RTXI

Shift Register Serial Data Output.

Shift Register Latch Clock Input. (Active high, rising edge sensitive)

Shift Register Parallel Data Output.

RTC Crystal Input. If RTC is not used then the bits RTCPDN and RTC_READENB of

RTC_INIT register must be set to ONE.

RTXO

RTCLKOUT

TDI

O

RTC Crystal Output.

O (ipd)

I (ipu)

O/T

I (ipu)

I

RTC Clock Output. For calibration purposes. The clock runs at 1 Hz.

Test Data Input (JTAG). Provides serial data for the boundary scan logic.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Mode Select (JTAG). Used to control the test state machine.

TDO

High-Z

TMS

TCK

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the device.

TRST

EMU

I (ipu)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed

low) after power-up or held low for proper operation of the processor.

O/T (ipu)

Emulation Status. Must be connected to the ADSP-2147x Analog Devices DSP

Tools product line of JTAG emulators target board connector only.

The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63kΩ.

The range of an ipd resistor can be between 31k–85kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.

Rev. PrD

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Page 16 of 70

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February 2011

Preliminary Technical Data

Table 10. Pin Descriptions (Continued)

ADSP-21478/ADSP-21479

State During/

After Reset

Name

Type

Description

CLK_CFG_1–0

I

Core to CLKIN Ratio Control. These pins set the start up clock frequency.

Note that the operating frequency can be changed by programming the PLL

multiplier and divider in the PMCTL register at any time after the core comes out

of reset. The allowed values are:

00 = 8:1

01 = 32:1

10 = 16:1

11 = reserved

CLKIN

I

Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It

configures the processors to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables

the internal clock generator. Connecting the external clock to CLKIN while leaving

XTAL unconnected configures the processors to use the external clock source

such as an external clock oscillator. CLKIN may not be halted, changed, or

operated below the specified frequency.

XTAL

O

I

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

RESET

Processor Reset. Resets the processor to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from thehardware resetvector address. The RESET input must

be asserted (low) at power-up.

RESETOUT/RUNRSTIN I/O (ipu)

Reset Out/Running Reset In. The default setting on this pin is reset out. This pin

also has a second function as RUNRSTIN which is enabled by setting bit 0 of the

RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor

Hardware Reference.

BOOT_CFG_2–0

I

Boot Configuration Select. These pins select the boot mode for the processor.

The BOOT_CFG pins must be valid before RESET (hardware and software) is de-

asserted.

Note that the BOOT_CFG2 pin is not available on the 100-lead LQFP package.

The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63kΩ.

The range of an ipd resistor can be between 31k–85kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.

Rev. PrD

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February 2011

ADSP-21478/ADSP-21479

Table 11. Pin List, Power and Ground

Preliminary Technical Data

Name

Type

Description

V_{DD_INT}

V_{DD_EXT}

V_{DD_RTC}

GND¹

P

G

P

Internal Power Supply.

I/O Power Supply.

Real Time Clock Power Supply.

Ground.

V_{DD_THD}

Thermal Diode Power Supply. When not used, this pin can be left floating.

¹The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the

exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided

in the package. See also 100-LQFP_EP Lead Assignment on Page 64.

Rev. PrD

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Page 18 of 70

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February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

SPECIFICATIONS

OPERATING CONDITIONS

100 MHz

266 MHz

300 MHz

Paramet

er¹

Description

Min

Nom

Max

Min

Nom

Max

Min

Nom

Max

Unit

V_{DD_INT}

Internal (Core) Supply

Voltage

1.05

1.1

1.15

1.14

1.2

1.26

1.25

1.3

1.35

V

V_{DD_EXT}

External (I/O) Supply

Voltage

3.13

TBD

3.3

3.47

TBD

3.13

TBD

2.0

3.3

3.47

TBD

3.13

TBD

2.0

3.3

3.47

TBD

V

°C

V_{DD_THD}Thermal Diode Supply

3.3

Voltage

Real-Time Clock Power

Supply Voltage

2

V_{DD_RTC}

TBD

3

V_IH

High Level Input Voltage @ 2.0

_{DD_EXT}= Max

V

4

V_IL

Low Level Input Voltage @

V_{DD_EXT}= Min

0.8

4

V_{IH_CLKIN}High Level Input Voltage @ 2.2

V_{DD_EXT}= Max

V_{IL_CLKIN}Low Level Input Voltage @ –0.3

V_{DD_EXT}= Max

V_DDEXT2.2

V_DDEXT

0.8

–0.3

0.8

–0.3

T_J

Junction Temperature 100-

Lead LQFP_EP @ T_AMBIENT

0°C to +70°C

Junction Temperature 100- –40

Lead LQFP_EP @ T_AMBIENT

–40°C to +85°C

Junction Temperature 196-

Ball CSP_BGA @ T_AMBIENT

0°C to +70°C

Junction Temperature 196- –40

Ball CSP_BGA @ T_AMBIENT

–40°C to +85°C

0

TBD

0

TBD

0

TBD

5

TBD

–40

0

+125

TBD

N/A

0

N/A

TBD

°C

0

–40

¹Specifications subject to change without notice.

²The expected voltage is = to V_{DD_EXT}

.

³Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST ,SDA10,

AMI_ACK, MLBCLK, MLBDAT, MLBSIG.

⁴Applies to input pin CLKIN, WDT_CLKIN.

⁵Applies to automotive models only. See Automotive Products on Page 69

Rev. PrD

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February 2011

ADSP-21478/ADSP-21479

ELECTRICAL CHARACTERISTICS

Preliminary Technical Data

100 MHz

Max

266 MHz

Max

300 MHz

Max

Parameter¹Description

Test Conditions

Min

Unit

2

V_OH

High Level Output

Voltage

Low Level Output Voltage @ V_{DD_EXT}= Min,

@ V_{DD_EXT}= Min,

2.4

V

I_oh= –1.0 mA³

2

V_OL

0.4

V

I_ol= 1.0 mA³

4, 5

I_IH

High Level Input Current @ V_{DD_EXT}= Max,

V_in= V_{DD_EXT}Max

Low Level Input Current

10

ꢀA

mA

4

I_IL

@ V_{DD_EXT}= Max,

V_IN= 0 V

@ V_{DD_EXT}= Max,

V_IN= 0 V

@ V_{DD_EXT}= Max,

V_IN= V_{DD_EXT}Max

@ V_{DD_EXT}= Max,

V_IN= 0 V

@ V_{DD_EXT}= Max,

V_IN= 0 V

–10

200

10

–10

200

10

–10

200

10

5

I_ILPU

Low Level Input Current

Pull-up

Three-State Leakage

Current

Three-State Leakage

Current

Three-State Leakage

Current Pull-up

Three-State Leakage

Current Pull-down

6, 7

I_OZH

6

I_OZL

I_OZLPU

–10

200

–10

200

–10

200

7

8

I_OZHPD

@ V_{DD_EXT}= Max,

V_IN= V_{DD_EXT}Max

9

I_DD-INTYP

Supply Current (Internal) f_CCLK> 0 MHz

Table 13 +

Table 14 ×

ASF

TBD

Table 14 ×

ASF

5

Table 14 ×

ASF

5

10, 11

C_IN

Input Capacitance

TBD

pF

¹Specifications subject to change without notice.

²Applies to output and bidirectional pins: ADDR23-0, DATA15-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT ,MLBSIG, MLBDAT, MLBDO,

MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1.

³See Output Drive Currents on Page 61 for typical drive current capabilities.

⁴Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

⁵Applies to input pins with internal pull-ups: TRST, TMS, TDI.

⁶Applies to three-statable pins: TDO, MLBDAT, MLBSIG, MLBDO, and MLBSO.

⁷Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

⁸Applies to three-statable pin with pull-down: SDCLK.

⁹See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2147x SHARC Processors” for further information.

¹⁰Applies to all signal pins.

¹¹Guaranteed, but not tested.

Rev. PrD

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Page 20 of 70

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February 2011

Preliminary Technical Data

Total Power Dissipation

ADSP-21478/ADSP-21479

Total power dissipation has two components:

1. Internal power consumption

External power consumption is due to the switching activity of

the external pins.

Table 12. Activity Scaling Factors (ASF)¹

2. External power consumption

Internal power consumption also comprises two components:

Activity

Idle

Scaling Factor (ASF)

1. Static, due to leakage current. Table 13 shows the static cur-

rent consumption (I_DD-STATIC) as a function of junction

temperature (T_J) and core voltage (V_{DD_INT}).

0.31

0.53

0.62

0.78

0.85

0.93

1.00

1.18

1.28

1.34

Low

Medium Low

Medium High

Peak-typical (50:50)²

Peak-typical (60:40)²

Peak-typical (70:30)²

High Typical

High

2. Dynamic (I_DD-DYNAMC), due to transistor switching char-

acteristics and activity level of the processor. The activity

level is reflected by the Activity Scaling Factor (ASF) which

represents application code running on the processor core

and having various levels of peripheral and external port

activity (Table 12). Dynamic current consumption is calcu-

lated by scaling the specific application by the ASF and

using baseline dynamic current consumption as a refer-

ence. The ASF is combined with the CCLK Frequency and

Peak

¹See Estimating Power for ADSP-214xx SHARC Processors (EE-348) for more

information on the explanation of the power vectors specific to the ASF table.

²Ratio of continuous instruction loop (core) to SDRAM control code reads and

writes.

V

_{DD_INT}dependent data in Table 14 to calculate this part.

Table 13. Static Current—I_DD-STATIC(mA)¹

V_{DD_INT}(V)

T_J(°C)

–45

1.05 V

< 0.1

0.2

1.10 V

< 0.1

0.2

1.15 V

0.4

1.20 V

0.8

1.25 V

1.3

1.30 V

2.1

1.35 V

3.3

–35

0.4

0.7

1.1

1.7

2.9

–25

0.4

0.8

1.2

1.7

2.9

–15

0.4

0.6

1.0

1.4

1.9

3.2

–5

0.6

0.9

1.3

1.8

2.3

3.7

+5

0.5

0.9

1.3

1.8

2.3

3.0

4.4

+15

+25

+35

+45

+55

+65

+75

+85

+95

+100

+105

+115

+125

0.8

1.4

1.8

2.3

3.0

3.7

5.1

1.3

1.9

2.5

3.1

3.9

4.7

6.2

2.0

2.8

3.4

4.2

5.1

6.0

8.0

3.0

3.9

4.7

5.7

6.7

7.8

10.1

12.9

16.4

21.2

27.1

34.6

39.2

N/A

4.3

5.4

6.3

7.6

8.8

10.3

13.5

17.4

22.6

29.4

33.0

N/A

6.0

7.3

8.6

10.1

13.3

17.5

22.9

25.9

29.5

38.2

48.8

11.7

15.3

19.9

26.1

29.4

33.4

42.9

54.8

8.3

9.9

11.5

15.3

20.1

22.9

26.1

33.9

43.6

11.2

15.2

17.4

20.0

26.3

34.4

13.2

17.6

20.2

23.0

30.0

38.9

¹Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 19.

Rev. PrD

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February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

Table 14. Baseline Dynamic Current in CCLK Domain (mA, with ASF = 1.0)^{1, 2}

f_CCLK

Voltage (V_{DD_INT})

(MHz)

1.05 V

75

1.10 V

78

1.15 V

82

1.20 V

86

1.25 V

90

1.30 V

95

1.35 V

98

100

150

200

266

300

111

N/A

117

122

162

215

N/A

128

170

225

N/A

134

178

234

264

141

186

246

279

146

194

256

291

N/A

¹The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 20.

²Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 19.

PACKAGE INFORMATION

ESD SENSITIVITY

The information presented in Figure 4 provides details about

the package branding for the ADSP-2147x processors. For a

complete listing of product availability, see Ordering Guide on

Page 69.

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

a

ADSP-2147x

tppZ-cc

vvvvvv.x n.n

MAXIMUM POWER DISSIPATION

#yyww country_of_origin

See Engineer-to-Engineer Note “Estimating Power Dissipation

for ADSP-2147x SHARC Processors” for detailed thermal and

power information regarding maximum power dissipation. For

information on package thermal specifications, see Thermal

Characteristics on Page 62.

S

Figure 4. Typical Package Brand

Table 15. Package Brand Information¹

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 16 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Brand Key

t

Field Description

Temperature Range

Package Type

pp

Z

RoHS Compliant Option

See Ordering Guide

Assembly Lot Code

Silicon Revision

cc

vvvvvv.x

n.n

Table 16. Absolute Maximum Ratings

#

RoHS Compliant Designation

Parameter

Rating

yyww

Date Code

¹Non Automotive only. For branding information specific to Automotive

products, contact Analog Devices Inc.

Internal (Core) Supply Voltage (V_{DD_INT}) –0.3 V to +1.35V

External (I/O) Supply Voltage (V_{DD_EXT}) –0.3 V to +4.6V

Real Time Clock Voltage (V_{DD_RTC}

)

–0.3 V to +4.6V

–0.3 V to +4.6 V

Thermal Diode Supply Voltage

(V_{DD_THD}

)

Input Voltage

–0.5 V to +3.8V

–0.5 V to V_{DD_EXT}+0.5V

–65°C to +150°C

125°C

Output Voltage Swing

Storage Temperature Range

Junction Temperature While Biased

Rev. PrD

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Page 22 of 70

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February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

f

_INPUT= is the input frequency to the PLL.

TIMING SPECIFICATIONS

_INPUT= CLKIN when the input divider is disabled or

_INPUT= CLKIN ÷ 2 when the input divider is enabled

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in and

Table 17. All of the timing specifications for the ADSP-2147x

peripherals are defined in relation to t_PCLK. See the peripheral

specific section for each peripheral’s timing information.

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 49 on page 61 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Table 17. Clock Periods

Timing

Requirements

Description

t_CK

CLKIN Clock Period

t_CCLK

t_PCLK

t_SDCLK

Processor Core Clock Period

Peripheral Clock Period = 2 × t_CCLK

SDRAM Clock Period = (t_CCLK) × SDCKR

Figure 5 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the ADSP-214xx SHARC Processor Hard-

ware Reference.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 5). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Voltage Controlled Oscillator

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

f

_VCOspecified in Table 19.

• The product of CLKIN and PLLM must never exceed 1/2 of

f

_VCO(max) in Table 19 if the input divider is not enabled

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed f_VCO

(max) in Table 19 if the input divider is enabled

(INDIV = 1).

The VCO frequency is calculated as follows:

f

_VCO= 2 × PLLM × f_INPUT

_CCLK= (2 × PLLM × f_INPUT) ÷ PLLD

where:

_VCO= VCO output

f

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

PLLD = 2, 4, 8, or 16 based on the divider value programmed on

the PMCTL register. During reset this value is 2.

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ADSP-21478/ADSP-21479

Preliminary Technical Data

PMCTL

(SDCKR)

PMCTL

(PLLBP)

PLL

f

CCLK

f_VCO

INPUT

SDRAM

DIVIDER

CLKIN

DIVIDER

LOOP

FILTER

PLL

DIVIDER

VCO

f_CCLK

SDCLK

XTAL

BUF

CLK_CFGx/

PMCTL (2 × PLLM)

PMCTL

(PLLD)

PMCTL

(INDIV)

PCLK

DIVIDE

BY 2

PMCTL

(PLLBP)

f_VCO÷ (2 × PLLM)

PCLK

CCLK

CLKOUT (TEST ONLY)*

DELAY OF

4096 CLKIN

CYCLES

BUF

RESETOUT

CORESRST

RESETOUT

RESET

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f_INPUT.

THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

Figure 5. Core Clock and System Clock Relationship to CLKIN

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Preliminary Technical Data

ADSP-21478/ADSP-21479

Systems sharing these signals on the board must determine

if there are any issues that need to be addressed based on

this behavior.

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 18. While no specific power-up sequencing is required

between V_{DD_EXT}and V_{DD_INT}, there are some considerations

that the system designs should take into account.

• No power supply should be powered up for an extended

period of time (> 200 ms) before another supply starts to

ramp up.

Note that during power-up, when the V_{DD_INT}power supply

comes up after V_{DD_EXT}, a leakage current of the order of three-

state leakage current pull-up, pull-down, may be observed on

any pin, even if that is an input only (for example the RESET

pin) until the V_{DD_INT}rail has powered up.

• If the V_{DD_INT}power supply comes up after V_{DD_EXT}, any

pin, such as RESETOUT and RESET may actually drive

momentarily until the V_{DD_INT}rail has powered up.

Table 18. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_{DD_EXT}or V_{DD_INT}On

V_{DD_INT}On Before V_{DD_EXT}

0

ms

t_IVDDEVDD

–200

0

10²

20³

+200

200

1

t_CLKVDD

CLKIN Valid After V_{DD_INT}and V_{DD_EXT}Valid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

t_CLKRST

t_PLLRST

Switching Characteristic

t_CORERST

4, 5

Core Reset Deasserted After RESET Deasserted

4096 × t_CK+ 2 × t_CCLK

ms

¹Valid V_{DD_INT}and V_{DD_EXT}assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary

from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles.

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4096 cycle count depends on t_SRSTspecification in Table 20. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

t_RSTVDD

RESET

V

DDINT

t_IVDDEVDD

V

DDEXT

t_CLKVDD

CLKIN

t_CLKRST

CLK_CFG1–0

RESETOUT

t_PLLRST

t_CORERST

Figure 6. Power-Up Sequencing

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ADSP-21478/ADSP-21479

Clock Input

Preliminary Technical Data

Table 19. Clock Input

100 MHz

Max

266 MHz

Max

300 MHz

Max

Unit

Parameter

Min

Timing Requirements

t_CK

CLKIN Period

TBD¹

TBD

TBD²

TBD

200

22.5¹

11.25

100²

45

TBD¹

TBD

TBD²

TBD

+250

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low

ns

CLKIN Width High

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK Period

45

ns

6

ns

3

10

3.75

200

10

TBD

–250

ns

4

f_VCO

VCO Frequency

TBD

533

+250

MHz

ps

5, 6

t_CKJ

CLKIN Jitter Tolerance

–250

+250

–250

¹Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

²Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.

³Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_cclk

⁴See Figure 5 on page 24 for VCO diagram.

.

⁵Actual input jitter should be combined with ac specifications for accurate timing analysis.

⁶Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

t_CKJ

t_CK

CLKIN

t_CKH

t_CKL

Figure 7. Clock Input

mental mode. Note that the clock rate is achieved using a 16.67

MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN

achieves a clock speed of 266 MHz). To achieve the full core

clock rate, programs need to configure the multiplier bits in the

PMCTL register.

Clock Signals

The ADSP-2147x can use an external clock or a crystal. See the

CLKIN pin description in Table 10. Programs can configure the

processor to use its internal clock generator by connecting the

necessary components to CLKIN and XTAL. Figure 8 shows the

component connections used for a crystal operating in funda-

ADSP-2147x

R1

1MΩ *

XTAL

R2

CLKIN

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’S SPECIFICATIONS

47Ω*

C1

22pF

C2

22pF

Y1

16.67

*TYPICAL VALUES

Figure 8. 266 MHz Operation (Fundamental Mode Crystal)

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February 2011

Preliminary Technical Data

Reset

ADSP-21478/ADSP-21479

Table 20. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

RESET Pulse Width Low

4 × t_ck

8

ns

t_SRST

RESET Setup Before CLKIN Low

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

V_ddand CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_WRST

t_SRST

RESET

Figure 9. Reset

Running Reset

The following timing specification applies to RESET-

OUT/RUNRSTIN pin when it is configured as RUNRSTIN.

Table 21. Running Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRUNRST

t_SRUNRST

Running RESET Pulse Width Low

4 × t_CK

8

ns

Running RESET Setup Before CLKIN High

CLKIN

t_WRUNRST

t_SRUNRST

RUNRSTIN

Figure 10. Running Reset

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ADSP-21478/ADSP-21479

Interrupts

Preliminary Technical Data

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts as well as the DAI_P20-1 and

DPI_P14-1 pins when they are configured as interrupts.

Table 22. Interrupts

Parameter

Min

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

2 × t_PCLK+ 2

ns

INTERRUPT

INPUTS

t_IPW

Figure 11. Interrupts

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP).

Table 23. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_WCTIM

TMREXP Pulse Width

4 × t_PCLK– 1

ns

t_WCTIM

FLAG3

(TMREXP)

Figure 12. Core Timer

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February 2011

Preliminary Technical Data

Timer PWM_OUT Cycle Timing

ADSP-21478/ADSP-21479

The following timing specification applies to timer0 and timer1

in PWM_OUT (pulse-width modulation) mode. Timer signals

are routed to the DPI_P14–1 pins through the DPI SRU. There-

fore, the timing specifications provided below are valid at the

DPI_P14–1 pins.

Table 24. Timer PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

t_PWMO

Timer Pulse Width Output

2 × t_PCLK– 1.2

2 × (2³¹– 1) × t_PCLK

ns

t_PWMO

PWM

OUTPUTS

Figure 13. Timer PWM_OUT Timing

Timer WDTH_CAP Timing

The following timing specification applies to timer0 and timer1,

and in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the timing specification provided below is valid

at the DPI_P14–1 pins.

Table 25. Timer Width Capture Timing

Parameter

Timing Requirement

Min

Max

2 × (2³¹– 1) × t_PCLK

Unit

t_PWI

Timer Pulse Width

2 × t_PCLK

ns

t_PWI

TIMER

CAPTURE

INPUTS

Figure 14. Timer Width Capture Timing

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February 2011

ADSP-21478/ADSP-21479

Watch Dog Timer Timing

Preliminary Technical Data

Table 26. Watch Dog Timer Timing

Parameter

Timing Requirement

t_WDTCLKPER

Min

Max

1000

6.4

Unit

100

ns

Switching Characteristics

t_RST

WDT Clock Rising Edge to Watch Dog Timer

RESET Falling Edge

3

ns

t_RSTPW

Reset Pulse Width

64 × t_WDTCLKPER

t_WDTCLKPER

WDT_CLKIN

t_RST

t_RSTPW

WDTRSTO

Figure 15. Watch Dog Timer Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to

DAI_PB02_O).

Table 27. DAI/DPI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid

1.5

10

ns

DAI_Pn

DPI_Pn

t_DPIO

DAI_Pm

DPI_Pm

Figure 16. DAI Pin to Pin Direct Routing

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Preliminary Technical Data

ADSP-21478/ADSP-21479

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 28. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIW

t_STRIG

Input Clock Period

t_PCLK× 4

ns

PCG Trigger Setup Before Falling Edge of PCG Input 4.5

Clock

t_HTRIG

PCG Trigger Hold After Falling Edge of PCG Input

Clock

3

ns

Switching Characteristics

t_DPCGIO

PCGOutputClockandFrameSyncActiveEdgeDelay

After PCG Input Clock

2.5

10

ns

t_DTRIGCLK

PCG Output Clock Delay After PCG Trigger

PCG Frame Sync Delay After PCG Trigger

Output Clock Period

2.5 + (2.5 × t_PCGIP

)

10 + (2.5 × t_PCGIP)

t_DTRIGFS

2.5 + ((2.5 + D – PH) × t_PCGIP

2 × t_PCGIP– 1

)

10 + ((2.5 + D – PH) × t_PCGIP)

1

t_PCGOW

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators”

chapter.

¹Normal mode of operation.

t_STRIG

t_HTRIG

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

t_PCGIW

DAI_Py

DPI_Py

PCK_CLKx_O

t_DTRIGCLK

t_PCGOW

t_DPCGIO

DAI_Pz

DPI_Pz

PCG_FSx_O

t_DTRIGFS

Figure 17. Precision Clock Generator (Direct Pin Routing)

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February 2011

ADSP-21478/ADSP-21479

Flags

Preliminary Technical Data

The timing specifications provided below apply to ADDR23–0

and DATA7–0 when configured as FLAGS. See Table 10 on

Page 14 for more information on flag use.

Table 29. Flags

Parameter

Timing Requirement

Min

Max

Unit

ns

t_FIPW

Switching Characteristic

FLAGs IN Pulse Width¹

2 × t_PCLK+ 3

2 × t_PCLK– 1.5

t_FOPW

FLAGs OUT Pulse Width¹

ns

¹This is applicable when the Flags are connected to DPI_P14–1, ADDR23–0, DATA7–0 and FLAG3–0 pins.

FLAG

INPUTS

t_FIPW

FLAG

OUTPUTS

t_FOPW

Figure 18. Flags

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Preliminary Technical Data

SDRAM Interface Timing (133 MHz SDCLK)

ADSP-21478/ADSP-21479

Table 30. SDRAM Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSDAT

t_HSDAT

DATA Setup Before SDCLK

DATA Hold After SDCLK

0.7

ns

1.23

Switching Characteristics

1

t_SDCLK

SDCLK Period

6

ns

t_SDCLKH

SDCLK Width High

2.2

t_SDCLKL

SDCLK Width Low

2

t_DCAD

Command, ADDR, Data Delay After SDCLK

Command, ADDR, Data Hold After SDCLK

Data Disable After SDCLK

4

2

t_HCAD

1

t_DSDAT

5.3

t_ENSDAT

Data Enable After SDCLK

0.3

¹Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 133 MHz the

SDRAM model with a speed grade of 143 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM memory to SHARC processors (EE-286)” for

more information on hardware design guidelines for the SDRAM interface.

²Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDQM, SDCKE.

t_SDCLKH

t_SDCLK

SDCLK

t_SSDAT

t_HSDAT

t_SDCLKL

DATA (IN)

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

DATA (OUT)

t_DCAD

t_HCAD

CMND ADDR

(OUT)

Figure 19. SDRAM Interface Timing

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ADSP-21478/ADSP-21479

AMI Read

Preliminary Technical Data

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 31. AMI Read

Parameter

Min

Max

Unit

Timing Requirements

1, 2, 3

t_DAD

Address Selects Delay to Data Valid

AMI_RD Low to Data Valid

W + t_SDCLK– 5.12

W – 3

ns

1, 3

t_DRLD

4, 5

t_SDS

Data Setup to AMI_RD High

2.2

0

t_HDRH

Data Hold from AMI_RD High

AMI_ACK Delay from Address Selects

AMI_ACK Delay from AMI_RD Low

2, 6

t_DAAK

t_SDCLK– 10. + W

W – 7.0

4

t_DSAK

Switching Characteristics

t_DRHAAddress Selects Hold After AMI_RD High

RHC+ 0.38

t_SDCLK– 3.3

W – 1.4

ns

2

t_DARL

t_RW

Address Selects to AMI_RD Low

AMI_RD Pulse Width

t_RWR

AMI_RD High to AMI_RD Low

HI + t_SDCLK– 0.8

W = (number of wait states specified in AMICTLx register) × t_SDCLK

.

RHC = (number of Read Hold Cycles specified in AMICTLx register) × t_SDCLK

Where PREDIS = 0

HI = RHC: Read to Read from same bank

HI = RHC + IC: Read to Read from different bank

HI = RHC + Max (IC, (4 × t_SDCLK)) : Read to Write from same or different bank

Where PREDIS = 1

HI = RHC + Max (IC, (4 × t_SDCLK)) : Read to Write from same or different bank

HI = RHC + (3 × t_SDCLK): Read to Read from same bank

HI = RHC + Max(IC, (3 × t_SDCLK)) : Read to Read from different bank

IC = (number of idle cycles specified in AMICTLx register) × t_SDCLK

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

.

¹Data delay/setup: System must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of MSx, is referenced.

³The maximum limit of timing requirement values for t_DADand t_DRLDparameters are applicable for the case where AMI_ACK is always high.

⁴Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.

⁵Data hold: User must meet t_HDRHin asynchronous access mode. See Test Conditions on Page 61 for the calculation of hold times given capacitive and dc loads.

⁶AMI_ACK delay/setup: User must meet t_daak, or t_dsak, for deassertion of AMI_ACK (low).

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Preliminary Technical Data

ADSP-21478/ADSP-21479

AMI_ADDR

AMI_MSx

t_DARL

t_RW

t_DRHA

AMI_RD

t_DRLD

t_SDS

t_DAD

t_HDRH

AMI_DATA

t_DSAK

t_RWR

t_DAAK

AMI_ACK

AMI_WR

Figure 20. AMI Read

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February 2011

ADSP-21478/ADSP-21479

AMI Write

Preliminary Technical Data

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 32. AMI Write

Parameter

Min

Max

Unit

Timing Requirements

t_DAAK

t_DSAK

AMI_ACK Delay from Address Selects^{1, 2}

AMI_ACK Delay from AMI_WR Low^{1, 3}

t_SDCLK– 10.1 + W

W – 7.1

ns

Switching Characteristics

t_DAWH

t_DAWL

t_WW

Address Selects to AMI_WR Deasserted²

t_SDCLK– 3.6 + W

t_SDCLK– 2.7

ns

Address Selects to AMI_WR Low²

AMI_WR Pulse Width

W – 1.3

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

t_WWR

Data Setup Before AMI_WR High

Address Hold After AMI_WR Deasserted

Data Hold After AMI_WR Deasserted

Data Disable After AMI_WR Deasserted⁴

AMI_WR High to AMI_WR Low⁵

Data Disable Before AMI_RD Low

AMI_WR Low to Data Enabled

t_SDCLK– 3.0 + W

H + 0.15

H + 0.02

t_SDCLK– 1.37 + H

t_SDCLK– 1.5+ H

2 × t_SDCLK– 5.1

t_SDCLK– 4.1

t_SDCLK+ 4.9+ H

t_DDWR

t_WDE

W = (number of wait states specified in AMICTLx register) × t_SDCLK

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

¹AMI_ACK delay/setup: System must meet t_DAAK, or t_DSAK, for deassertion of AMI_ACK (low).

²The falling edge of AMI_MSx is referenced.

³Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.

⁴See Test Conditions on Page 61 for calculation of hold times given capacitive and dc loads.

⁵For Write to Write: t_SDCLK+ H, for both same bank and different bank. For Write to Read: 3 × t_SDCLK+ H , for the same bank and different banks.

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February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

AMI_ADDR

AMI_MSx

t_DAWH

t_DWHA

t_DAWL

t_WW

AMI_WR

t_WWR

t_WDE

t_DATRWH

t_DDWH

t_DDWR

AMI_DATA

t_DSAK

t_DWHD

t_DAAK

AMI_ACK

AMI_RD

Figure 21. AMI Write

Rev. PrD

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February 2011

ADSP-21478/ADSP-21479

Serial Ports

Preliminary Technical Data

In slave transmitter mode and master receiver mode the maxi-

mum serial port frequency is f_PCLK/8. In master transmitter

mode and slave receiver mode the maximum serial port clock

frequency is f_PCLK/4.

Serial port signals (SCLK, FS, Data Channel A, Data Channel B)

are routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 33. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSE

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode)

2.5

ns

1

t_HFSE

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode)

2.5

ns

1

t_SDRE

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

SCLK Width

2.5

1

t_HDRE

t_SCLKW

t_SCLK

2.5

(t_PCLK× 4) ÷ 2 – 0.5

t_PCLK× 4

SCLK Period

Switching Characteristics

2

t_DFSE

Frame Sync Delay After SCLK

(Internally Generated Frame Sync in either Transmit or Receive Mode)

10.5

11

ns

2

t_HOFSE

Frame Sync Hold After SCLK

(Internally Generated Frame Sync in either Transmit or Receive Mode)

2

ns

2

t_DDTE

Transmit Data Delay After Transmit SCLK

2

t_HDTE

Transmit Data Hold After Transmit SCLK

¹Referenced to sample edge.

²Referenced to drive edge.

Table 34. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSI

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode)

7

ns

1

t_HFSI

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode)

2.5

7

ns

1

t_SDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

1

t_HDRI

2.5

Switching Characteristics

2

t_DFSI

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)

4

ns

2

t_HOFSI

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode)

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)

Transmit Data Delay After SCLK

–1.0

2

t_DFSIR

10.7

3.6

2

t_HOFSIR

2

t_DDTI

2

t_HDTI

Transmit Data Hold After SCLK

t_SCKLIW

Transmit or Receive SCLK Width

2 × t_PCLK– 1.5 2 × t_PCLK+ 1.5 ns

¹Referenced to the sample edge.

²Referenced to drive edge.

Rev. PrD

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Page 38 of 70

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February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

DATA RECEIVE—INTERNAL CLOCK

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSIR

t_DFSE

t_HOFSIR

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_SDRI

t_HDRI

t_SDRE

t_HDRE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 22. Serial Ports

Rev. PrD

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Page 39 of 70

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February 2011

ADSP-21478/ADSP-21479

Table 35. Serial Ports—External Late Frame Sync

Preliminary Technical Data

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTLFSE

DataDelay fromLateExternal TransmitFrameSyncorExternal Receive

10

Frame Sync with MCE = 1, MFD = 0

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

SAMPLE DRIVE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

Figure 23. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified mode.

Rev. PrD

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Page 40 of 70

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February 2011

Preliminary Technical Data

Table 36. Serial Ports—Enable and Three-State

ADSP-21478/ADSP-21479

Parameter

Switching Characteristics

Min

2

Max

Unit

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

ns

1

t_DDTTE

10

1

t_DDTIN

–1

¹Referenced to drive edge.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

t_DDTEN

t_DDTTE

DAI_P20–1

(DATA

CHANNEL A/B)

DRIVE EDGE

DAI_P20–1

(SCLK, INT)

t_DDTIN

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 24. Enable and Three-State

Rev. PrD

|

Page 41 of 70

|

February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

The SPORTx_TDV_O output signal (routing unit) becomes

active in SPORT multichannel/packed mode. During transmit

slots (enabled with active channel selection registers) the

SPORTx_TDV_O is asserted for communication with external

devices.

Table 37. Serial Ports—TDV (Transmit Data Valid)

Parameter

Min

TBD

Max

Unit

Switching Characteristics¹

t_DRDVEN

t_DFDVEN

t_DRDVIN

t_DFDVIN

TDV Assertion Delay from Drive Edge of External Clock

TDV Deassertion Delay from Drive Edge of External Clock

TDV Assertion Delay from Drive Edge of Internal Clock

TDV Deassertion Delay from Drive Edge of Internal Clock

ns

TBD

¹Referenced to drive edge.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

TDVx

DAI_P20-1

t_DFDVEN

t_DRDVEN

DRIVE EDGE

DAI_P20–1

(SCLK, INT)

TDVx

DAI_P20-1

t_DFDVIN

t_DRDVIN

Figure 25. Serial Ports—TDM Internal and External Clock

Rev. PrD

|

Page 42 of 70

|

February 2011

Preliminary Technical Data

Input Data Port (IDP)

ADSP-21478/ADSP-21479

The timing requirements for the IDP are given in Table 38. IDP

signals are routed to the DAI_P20–1 pins using the SRU. There-

fore, the timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 38. Input Data Port (IDP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Clock Width

3.8

ns

1

t_SIHFS

2.5

1

t_SISD

2.5

1

t_SIHD

t_IDPCLKW

t_IDPCLK

2.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's

input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IPDCLK

t_IPDCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 26. IDP Master Timing

Rev. PrD

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Page 43 of 70

|

February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

PDAP chapter of the ADSP-214xx SHARC Processor Hardware

Reference. Note that the 20-bits of external PDAP data can be

provided through the ADDR23–0 pins or over the DAI pins.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 39. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the PDAP, see the

Table 39. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SPHOLD

PDAP_HOLD Setup Before PDAP_CLK Sample Edge

PDAP_HOLD Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

Clock Width

2.5

ns

1

t_HPHOLD

2.5

1

t_PDSD

3.85

1

t_PDHD

2.5

t_PDCLKW

t_PDCLK

(t_PCLK× 4) ÷ 2 – 3

t_PCLK× 4

Clock Period

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

2 × t_PCLK+ 3

2 × t_PCLK– 1

ns

1

Source pins of DATA and control are ADDR23–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20–1

(PDAP_CLK)

t_HPHOLD

t_SPHOLD

DAI_P20–1

(PDAP_HOLD)

t_PDHD

t_PDSD

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

t_PDHLDD

t_PDSTRB

DAI_P20–1

(PDAP_STROBE)

Figure 27. PDAP Timing

Rev. PrD

|

Page 44 of 70

|

February 2011

Preliminary Technical Data

Sample Rate Converter—Serial Input Port

ADSP-21478/ADSP-21479

The ASRC input signals are routed from the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided in

Table 40 are valid at the DAI_P20–1 pins.

Table 40. ASRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Clock Width

TBD

ns

1

t_SRCHFS

TBD

1

t_SRCSD

TBD

1

t_SRCHD

t_SRCCLKW

t_SRCCLK

TBD

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCSD

t_SRCHD

DAI_P20–1

(SDATA)

Figure 28. ASRC Serial Input Port Timing

Rev. PrD

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Page 45 of 70

|

February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

delay specification with regard to serial clock. Note that serial

clock rising edge is the sampling edge and the falling edge is the

drive edge.

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it

should meet setup and hold times with regard to the serial clock

on the output port. The serial data output has a hold time and

Table 41. ASRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Clock Width

TBD

ns

1

t_SRCHFS

t_SRCCLKW

t_SRCCLK

TBD

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

Switching Characteristics

1

t_SRCTDD

Transmit Data Delay After Serial Clock Falling Edge

Transmit Data Hold After Serial Clock Falling Edge

TBD

ns

1

t_SRCTDH

TBD

1

The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCTDD

t_SRCTDH

DAI_P20–1

(SDATA)

Figure 29. ASRC Serial Output Port Timing

Rev. PrD

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Page 46 of 70

|

February 2011

Preliminary Technical Data

Pulse-Width Modulation Generators (PWM)

ADSP-21478/ADSP-21479

The following timing specifications apply when the

ADDR23–8/DPI_14–1 pins are configured as PWM.

Table 42. Pulse-Width Modulation (PWM) Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_PWMW

t_PWMP

PWM Output Pulse Width

PWM Output Period

t_PCLK– 2

(2¹⁶– 2) × t_PCLK– 2

(2¹⁶– 1) × t_PCLK– 1.5

ns

2 × t_PCLK– 1.5

t_PWMW

PWM

OUTPUTS

t_PWMP

Figure 30. PWM Timing

Rev. PrD

|

Page 47 of 70

|

February 2011

ADSP-21478/ADSP-21479

S/PDIF Transmitter

Preliminary Technical Data

Serial data input to the S/PDIF transmitter can be formatted as

left justified, I²S, or right justified with word widths of 16-, 18-,

20-, or 24-bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 31 shows the right-justified mode. Frame sync is high for

the left channel and low for the right channel. Data is valid on

the rising edge of serial clock. The MSB is delayed the minimum

in 24-bit output mode or the maximum in 16-bit output mode

from a frame sync transition, so that when there are 64 serial

clock periods per frame sync period, the LSB of the data is right-

justified to the next frame sync transition.

Table 43. S/PDIF Transmitter Right-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

t_RJD

FS to MSB Delay in Right-Justified Mode

16-Bit Word Mode

16

14

12

8

SCLK

18-Bit Word Mode

20-Bit Word Mode

24-Bit Word Mode

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_RJD

DAI_P20–1

SDATA

LSB

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 31. Right-Justified Mode

Rev. PrD

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Page 48 of 70

|

February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

Figure 32 shows the default I²S-justified mode. The frame sync

is low for the left channel and high for the right channel. Data is

valid on the rising edge of serial clock. The MSB is left-justified

to the frame sync transition but with a delay.

Table 44. S/PDIF Transmitter I²S Mode

Parameter

Nominal

Unit

Timing Requirement

t_I2SD

FS to MSB Delay in I²S Mode

1

SCLK

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_I2SD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 32. I²S-Justified Mode

Figure 33 shows the left-justified mode. The frame sync is high

for the left channel and low for the right channel. Data is valid

on the rising edge of serial clock. The MSB is left-justified to the

frame sync transition with no delay.

Table 45. S/PDIF Transmitter Left-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

t_LJD

FS to MSB Delay in Left-Justified Mode

0

SCLK

DAI_P20–1

FS

LEFT/RIGHT CHANNEL

DAI_P20–1

SCLK

t_LJD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 33. Left-Justified Mode

Rev. PrD

|

Page 49 of 70

|

February 2011

ADSP-21478/ADSP-21479

S/PDIF Transmitter Input Data Timing

Preliminary Technical Data

The timing requirements for the S/PDIF transmitter are given

in Table 46. Input signals are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 46. S/PDIF Transmitter Input Data Timing

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Transmit Clock Width

3

ns

1

t_SIHFS

3

1

t_SISD

3

1

t_SIHD

3

t_SITXCLKW

t_SITXCLK

t_SISCLKW

t_SISCLK

9

Transmit Clock Period

20

36

80

Clock Width

Clock Period

1

The serial clock, data and frame sync signals can come from any of the DAI pins.The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SITXCLKW

t_SITXCLK

DAI_P20–1

(TxCLK)

t_SISCLK

t_SISCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 34. S/PDIF Transmitter Input Timing

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter requires an oversampling clock input.

This high frequency clock (TxCLK) input is divided down to

generate the internal biphase clock.

Table 47. Oversampling Clock (TxCLK) Switching Characteristics

Parameter

Max

Unit

Frequency for TxCLK = 384 × Frame Sync

Frequency for TxCLK = 256 × Frame Sync

Frame Rate (FS)

Oversampling Ratio × Frame Sync <= 1/t_SITXCLKMHz

49.2

MHz

kHz

192.0

Rev. PrD

|

Page 50 of 70

|

February 2011

Preliminary Technical Data

S/PDIF Receiver

ADSP-21478/ADSP-21479

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the TBD × FS clock.

Table 48. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

FS Delay After Serial Clock

5

ns

t_HOFSI

t_DDTI

FS Hold After Serial Clock

–2

Transmit Data Delay After Serial Clock

Transmit Data Hold After Serial Clock

Transmit Serial Clock Width

t_HDTI

–2

1

t_SCLKIW

38.5

¹Serial clock frequency is TBD x frame sync where FS = the frequency of LRCLK.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20–1

(SCLK)

t_DFSI

t_HOFSI

DAI_P20–1

(FS)

t_DDTI

t_HDTI

DAI_P20–1

(DATA CHANNEL

A/B)

Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. PrD

|

Page 51 of 70

|

February 2011

ADSP-21478/ADSP-21479

SPI Interface—Master

Preliminary Technical Data

The ADSP-2147x contains two SPI ports. Both primary and sec-

ondary are available through DPI only. The timing provided in

Table 49 and Table 50 applies to both.

Table 49. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid to SPICLK Edge (Data Input Setup Time)

8.2

2

ns

SPICLK Last Sampling Edge to Data Input Not Valid

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × t_PCLK– 2

4 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay time)

SPICLK Edge to Data Out Not Valid (Data Out Hold time)

DPI Pin (SPI Device Select) Low to First SPICLK Edge

Last SPICLK Edge to DPI Pin (SPI Device Select) High

Sequential Transfer Delay

2.5

4 × t_PCLK– 2

4 × t_PCLK– 1

ns

t_SPITDM

DPI

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

(INPUT)

t_DDSPIDM

t_HDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

CPHASE = 0

MISO

(INPUT)

Figure 36. SPI Master Timing

Rev. PrD

|

Page 52 of 70

|

February 2011

Preliminary Technical Data

SPI Interface—Slave

ADSP-21478/ADSP-21479

Table 50. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

t_HDS

Serial Clock Cycle

4 × t_PCLK– 2

2 × t_PCLK– 2

2 × t_PCLK

2

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE = 0)

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_PCLK

Switching Characteristics

t_DSOESPIDS Assertion to Data Out Active

0

6.8

8

ns

1

t_DSOE

t_DSDHI

SPIDS Assertion to Data Out Active (SPI2)

SPIDS Deassertion to Data High Impedance

6.8

8.6

9.5

1

t_DSDHI

SPIDS Deassertion to Data High Impedance (SPI2)

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE = 0)

t_DDSPIDS

t_HDSPIDS

t_DSOV

2 × t_PCLK

5 × t_PCLK

¹The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral

Interface Port” chapter.

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0,

CP = 1)

(INPUT)

t_SDSCO

t_DSOE

t_DSDHI

t_HDSPIDS

t_DDSPIDS

MISO

(OUTPUT)

t_SSPIDSt_HSPIDS

CPHASE = 1

MOSI

(INPUT)

t_HDSPIDS

t_DDSPIDS

t_DSDHI

MISO

(OUTPUT)

t_DSOV

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

(INPUT)

Figure 37. SPI Slave Timing

Rev. PrD

|

Page 53 of 70

|

February 2011

ADSP-21478/ADSP-21479

Media Local Bus

Preliminary Technical Data

All the numbers given are applicable for all speed modes (1024

FS, 512 FS and 256 FS for 3-pin; 512 FS and 256 FS for 5-pin)

unless otherwise specified. Please refer to MediaLB specification

document rev 3.0 for more details.

Table 51. MLB Interface, 3-pin Specifications

Parameter

Min

Typ

Max

Unit

Three-Pin Characteristics

t_MLBCLK

MLB Clock Period

1024 FS

20.3

40

81

ns

512 FS

256 FS

t_MCKL

MLBCLK Low Time

1024 FS

6.1

14

30

ns

512 FS

256 FS

t_MCKH

MLBCLK High Time

1024 FS

9.3

14

30

ns

512 FS

256 FS

t_MCKR

MLBCLK Rise Time (V_ILto V_IH)

1024 FS

1

3

ns

512 FS/256 FS

t_MCKF

MLBCLK Fall Time (V_IHto V_IL)

1024 FS

1

3

ns

512 FS/256 FS

1

t_MPWV

MLBCLK Pulse Width Variation

1024 FS

512 FS/256

0.7

2.0

nspp

t_DSMCF

t_DHMCF

t_MCFDZ

t_MCDRV

DAT/SIG Input Setup Time

1

0

ns

DAT/SIG Input Hold Time

DAT/SIG Output Time to Three-state

DAT/SIG Output Data Delay From MLBCLK Rising Edge

15

8

2

t_MDZH

Bus Hold Time

1024 FS

512 FS/256

2

4

ns

C_MLB

DAT/SIG Pin Load

1024 FS

40

60

pf

512 FS/256

¹Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).

²The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be

minimized while meeting the maximum capacitive load listed.

Rev. PrD

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Page 54 of 70

|

February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

MLBSIG/

MLBDAT

(Rx, Input)

VALID

t_DHMCF

t_DSMCF

t_MCKH

t_MCKL

MLBCLK

t_MCKR

t_MCKF

t_MLBCLK

t_MCFDZ

t_MCDRV

t_MDZH

MLBSIG/

MLBDAT

VALID

(Tx, Output)

Figure 38. MLB Timing (3-Pin Interface)

Table 52. MLB Interface, 5-pin Specifications

Parameter

Min

Typ

Max

Unit

Five-Pin Characteristics

t_MLBCLK

MLB Clock Period

512 FS

40

81

ns

256 FS

t_MCKL

MLBCLK Low Time

512 FS

15

30

ns

256 FS

t_MCKH

MLBCLK High Time

512 FS

15

30

ns

256 FS

t_MCKR

t_MCKF

MLBCLK Rise Time (V_ILto V_IH)

MLBCLK Fall Time (V_IHto V_IL)

MLBCLK Pulse Width Variation

DAT/SIG Input Setup Time

DAT/SIG Input Hold Time

6

2

ns

1

t_MPWV

nspp

ns

2

t_DSMCF

3

5

t_DHMCF

t_MCDRV

ns

DS/DO Output Data Delay From MLBCLK Rising Edge

8

ns

3

t_MCRDL

DO/SO Low From MLBCLK High

512 FS

256 FS

10

20

ns

C_mlb

DS/DO Pin Load

40

pf

¹Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).

²Gate Delays due to OR’ing logic on the pins must be accounted for.

³When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,

external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.

Rev. PrD

|

Page 55 of 70

|

February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

MLBSIG/

MLBDAT

(Rx, Input)

VALID

t_DHMCF

t_DSMCF

t_MCKH

t_MCKL

MLBCLK

t_MCKR

t_MCKF

t_MLBCLK

t_MCRDL

t_MCDRV

VALID

MLBSO/

MLBDO

(Tx, Output)

Figure 39. MLB Timing (5-Pin Interface)

MLBCLK

t_MPWV

Figure 40. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing

Rev. PrD

|

Page 56 of 70

|

February 2011

Preliminary Technical Data

Shift Register

ADSP-21478/ADSP-21479

Table 53. Shift Register

Parameter

Timing Requirements

Min

TBD

Max

Unit

t_SSDI

SR_SDI Setup Before SR_SCLK Rising Edge

SR_SDI Hold After SR_SCLK Rising Edge

DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge

DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge

SR_SCLK to SR_LAT Setup

ns

MHz

ns

t_HSDI

TBD

1

t_SSDIDAI

1

t_HSDIDAI

2

t_SSCK2LCK

TBD

1, 2

t_SSCK2LCKDAI

t_CLRREM2SCK

t_CLRREM2LCK

t_CLRW

DAI_P08–01 (SR_SCLK) to DAI_P08–01 (SR_LAT) Setup

Removal Time SR_CLR to SR_SDCLK

Removal Time SR_CLR to SR_LAT

SR_CLR Pulse Width

t_SCKW

SR_SDCLK Clock Pulse Width

t_LCKW

SR_LAT Clock Pulse Width

f_MAX

Maximum Clock Frequency SR_SDCLK or SR_LAT

f_CCLK÷ 8

Switching Characteristics

3

t_DSDO1

SR_SDO Hold After SR_SCLK Rising Edge

TBD

3

t_DSDO2

t_DSDODAI1

t_DSDODAI2

SR_SDO Max. Delay After SR_SCLK Rising Edge

SR_SDO Hold After DAI_P08–01 (SR_SCLK) Rising Edge

SR_SDO Max. Delay After DAI_P08–01 (SR_SCLK) Rising Edge

SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge

SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge

SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge

SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge

SR_CLR to SR_SDO Min. Delay

TBD

1, 3

3, 4

t_DSDOSP1

t_DSDOSP2

t_DSDOPCG1

t_DSDOPCG2

3, 4

3, 5, 6

3

t_DSDOCLR1

3

t_DSDOCLR2

SR_CLR to SR_SDO Max. Delay

3

t_DLDO1

SR_LDO Hold After SR_LAT Rising Edge

3

t_DLDO2

SR_LDO Max. Delay After SR_LAT Rising Edge

SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge

SR_LDO Max. Delay After DAI_P08–01 (SR_LAT) Rising Edge

SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge

SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge

SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge

SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge

SR_CLR to SR_LDO Min. Delay

3

t_DLDODAI1

t_DLDODAI2

3, 4

t_DLDOSP1

t_DLDOSP2

3, 5, 6

t_DLDOPCG1

t_DLDOPCG2

3

t_DLDOCLR1

3

t_DLDOCLR2

SR_CLR to SR_LDO Max. Delay

¹DAI_P08–01 are selected as shift register clock, latch clock and serial data input.

²Both clocks can be connected to the same clock source. If both clocks are connected to same clock source, then data in the 18-stage shift register is always one cycle ahead of

latch register data.

³For setup/hold timing requirements of off-chip shift register interfacing devices.

⁴SPORTx serial clock out, frame sync out, and serial data outputs are routed to shift register block internally and are also routed onto DAI_P20–01.

⁵PCG serial clock output is routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SR_LAT and SDI internally.

⁶PCG Serial clock and frame sync outputs are routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SDI internally.

Rev. PrD

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Page 57 of 70

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February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

t_SSDI,t_SSDIDAI

DAI_P08

OR

-01

SR_SCLK

t_HSDI,t_HSDIDAI

DAI_P08

OR

-01

SR_SDI

SR_SDO

Figure 41. SR_SDI Setup, Hold

SR_SCLK OR

DAI_P08-01 OR

DAI_P20-01(SPx_CLK_O) OR

DAI_P20-01(PCG_CLKx_O)

t_DSDO1,t_DSDODAI1,t_DSDOSP1

t_DSDO2,t_DSDODAI2,t_DSDOSP2

SR_SDO

Figure 42. SR_ SDO Delay

SR_LAT OR

DAI_P08-01 OR

DAI_P20-01

(SPx_FS_O)

OR

DAI_P20-01

(PCG_FSx_O)

t_DLDO1

t_DLDO2

SR_LDO

THE TIMING PARAMETERS SHOWN FOR t_DLDO1AND t_DLDO2ARE ALSO VALID FOR t_DLDODAI1

t_DLDODAI2, t_DLDOSP1, t_DLDOSP2, t_DLDOPCG1, AND t_DLDOPCG2

,

.

Figure 43. SR_LDO Delay

Rev. PrD

|

Page 58 of 70

|

February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

SR_SCLK

OR

DAI_P08-01

t_SSCK2LCK

t_SSCK2LCKDAI

SR_LAT

OR

DAI_P08

-01

SR_SDI

OR

DAI_P08

-01

SR_LDO

Figure 44. SR_SDCLK to SR_LAT Setup, Clocks Pulse Width and Maximum Frequency

t_CLRW

SR_CLR

t_CLRREM2SCK

SR_SDCLK

OR

DAI_P08-01

t_CLRREM2LCK

SR_LAT

OR

DAI_P08-01

t_DSDOCLR2

t_DSDOCLR1

SR_SDO

SR_LDO

t_DLDOCLR2

t_DLDOCLR1

Figure 45. SR_CLR Timing

Rev. PrD

|

Page 59 of 70

|

February 2011

ADSP-21478/ADSP-21479

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

Preliminary Technical Data

For information on the UART port receive and transmit opera-

tions, see the ADSP-214xx SHARC Hardware Reference Manual.

2-Wire Interface (TWI)—Receive and Transmit Timing

For information on the TWI receive and transmit operations,

see the ADSP-214xx SHARC Hardware Reference Manual.

JTAG Test Access Port and Emulation

Table 54. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

t_ck

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

5

6

1

t_SSYS

7

1

t_HSYS

t_TRSTW

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

18

4 × t_CK

7

ns

2

t_DSYS

t_CK÷ 2 + 7

¹System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG1–0, DAI_Px, DPI_Px, FLAG3–0, MLBCLK, MLBDAT, MLBSIG, SR_SCLK, SR_CLR, SR_SDI, and

SR_LAT.

²System Outputs = DAI_Px, DPI_Px, ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK, MLBDAT, MLBSIG, MLBDO,

MLBSO, SR_SDO, SR_LDO and EMU.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 46. IEEE 1149.1 JTAG Test Access Port

Rev. PrD

|

Page 60 of 70

|

February 2011

Preliminary Technical Data

OUTPUT DRIVE CURRENTS

ADSP-21478/ADSP-21479

TESTER PIN ELECTRONICS

Figure 47 shows typical I-V characteristics for the output driv-

ers of the ADSP-2147x, and Table 55 shows the pins associated

with each driver. The curves represent the current drive capabil-

ity of the output drivers as a function of output voltage.

50ꢀ

V

LOAD

T1

DUT

OUTPUT

45ꢀ

70ꢀ

ZO = 50ꢀꢁ(impedance)

TD = 4.04 ꢂ 1.18 ns

50ꢀ

Table 55. Driver Types

0.5pF

2pF

4pF

Driver Type Associated Pins

400ꢀ

A

FLAG[0–3], AMI_ADDR[23–0], DATA[15–0],

AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,

SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU,

TDO,RESETOUT, DPI[1–14], DAI[1–20], WDTRSTO,

MLBDAT, MLBSIG, MLBSO, MLBDO, MLBCLK,

SR_CLR, SR_LAT, SR_LDO[17–0], SR_SCLK, SR_SDI

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

B

SDCLK, RTCLKOUT

Figure 48. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

200

150

100

V_OH3.13 V, 125 °C

TYPE B

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 48). Figure 52 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 50, Figure 51, and Figure 52 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

TYPE A

50

0

TYPE A

-

50

100

150

-

TYPE B

V_OL3.13 V, 125 °C

7

-200

0.5

1.0

1.5

2.0

2.5

3.5

0

3.0

SWEEP (V_DDEXT) VOLTAGE (V)

6

TYPE A DRIVE FALL

TYPE A DRIVE RISE

y = 0.0331x + 0.2662

y = 0.0421x + 0.2418

Figure 47. Typical Drive at Junction Temperature

5

4

3

2

1

0

TYPE B DRIVE FALL

y = 0.0206x + 0.2271

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 20 on Page 27 through Table 54 on Page 60. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 48.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 49. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

TYPE B DRIVE RISE

y = 0.0184x + 0.3065

0

25

50

75

100

125

150

175

200

LOAD CAPACITANCE (pF)

Figure 50. Typical Output Rise/Fall Time (20% to 80%,

V_{DD_EXT}= Max)

INPUT

OR

1.5V

OUTPUT

Figure 49. Voltage Reference Levels for AC Measurements

Rev. PrD

|

Page 61 of 70

|

February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

T = T

+ (Ψ × P )

JT

D

J

CASE

14

where:

T_J= junction temperature °C

TYPE A DRIVE FALL

y = 0.0748x + 0.4601

12

10

8

TYPE A DRIVE RISE

y = 0.0567x + 0.482

T

_CASE= case temperature (°C) measured at the top center of the

package

TYPE B DRIVE FALL

y = 0.0367x + 0.4502

Ψ_JT= junction-to-top (of package) characterization parameter

is the Typical value from Table 56.

6

P

_D= power dissipation

TYPE B DRIVE RISE

y = 0.0314x + 0.5729

4

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first order approxi-

mation of T_Jby the equation:

2

0

T = T + (θ × P )

J

A

JA

D

0

25

50

75

100

125

150

175

200

where:

T_A= ambient temperature °C

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heatsink is required.

LOAD CAPACITANCE (pF)

Figure 51. Typical Output Rise/Fall Time (20% to 80%,

V_{DD_EXT}= Min)

Values of θ_JBare provided for package comparison and PCB

design considerations. Note that the thermal characteristics val-

ues provided in Table 56 are modeled values.

4.5

4

TYPE A DRIVE FALL

y = 0.0199x + 1.1083

TYPE A DRIVE RISE

y = 0.015x + 1.4889

Table 56. Thermal Characteristics for 100-Lead LQFP_EP

3.5

3

Parameter

θ_JA

Condition

Typical

17.8

15.4

14.6

2.4

Unit

°C/W

TYPE B DRIVE RISE

y = 0.0088x + 1.6008

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

2.5

2

θ_JMA

θ_JC

TYPE B DRIVE FALL

y = 0.0102x + 1.2726

1.5

1

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.24

0.37

0.51

Ψ_JMT

0.5

0

Table 57. Thermal Characteristics for 196-Ball CSP_BGA

0

25

50

75

100

125

150

175

200

LOAD CAPACITANCE (pF)

Parameter

θ_JA

Condition

Typical

28.9

26.0

25.1

TBD

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

Figure 52. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

θ_JMA

θ_JC

THERMAL CHARACTERISTICS

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.26

0.48

0.58

The ADSP-2147x processor is rated for performance over the

temperature range specified in Operating Conditions on

Page 19.

Ψ_JMT

Table 56 airflow measurements comply with JEDEC standards

JESD51-2 and JESD51-6 and the junction-to-board measure-

ment complies with JESD51-8. Test board design complies with

JEDEC standards JESD51-7 (PBGA). The junction-to-case mea-

surement complies with MIL- STD-883. All measurements use a

2S2P JEDEC test board.

To determine the junction temperature of the device while on

the application PCB, use:

Rev. PrD

|

Page 62 of 70

|

February 2011

Preliminary Technical Data

Thermal Diode

ADSP-21478/ADSP-21479

where:

n = multiplication factor close to 1, depending on process

The ADSP-2147x processors incorporate thermal diode/s to

monitor the die temperature. The thermal diode of is a

grounded collector, PNP Bipolar Junction Transistor (BJT). The

THD_P pin is connected to the emitter and the THD_M pin is

connected to the base of the transistor. These pins can be used

by an external temperature sensor (such as ADM 1021A or

LM86 or others) to read the die temperature of the chip.

variations

k = Boltzmann’s constant

T = temperature (°C)

q = charge of the electron

N = ratio of the two currents

The technique used by the external temperature sensor is to

measure the change in VBE when the thermal diode is operated

at two different currents. This is shown in the following

equation:

The two currents are usually in the range of 10 micro Amperes

to 300 micro Amperes for the common temperature sensor

chips available.

Table 58 contains the thermal diode specifications using the

transistor model.

kT

-----

ΔV_BE= n ×

× In(N)

q

Table 58. Thermal Diode Parameters – Transistor Model

Symbol

I_FW

Parameter

Min

TBD

Typ

Max

TBD

Unit

μA

Forward Bias Current

Emitter Current

Transistor Ideality

I_E

n_Q

TBD

Beta

R_T

Series Resistance

Ω

Rev. PrD

|

Page 63 of 70

|

February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

100-LQFP_EP LEAD ASSIGNMENT

Table 59 lists the lead names and their default function after

reset (in parentheses).

Table 59. 100-Lead LQFP_EP Lead Assignments (Numerical by Lead Number)

Lead Name

V_{DD_INT}

CLK_CFG1

BOOT_CFG0

V_{DD_EXT}

V_{DD_INT}

BOOT_CFG1

GND

Lead No.

1

Lead Name

V_{DD_EXT}

Lead No.

26

Lead Name

DAI_P10

V_{DD_INT}

Lead No.

51

Lead Name

V_{DD_INT}

FLAG0

V_{DD_INT}

FLAG1

FLAG2

FLAG3

MLBCLK

MLBDAT

MLBDO

V_{DD_EXT}

MLBSIG

V_{DD_INT}

MLBSO

TRST

Lead No.

76

2

DPI_P08

DPI_P07

V_{DD_INT}

27

52

77

3

28

V_{DD_EXT}

DAI_P20

V_{DD_INT}

53

78

4

29

54

79

5

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DAI_P03

DPI_P14

V_{DD_INT}

30

55

80

6

31

DAI_P08

DAI_P04

DAI_P14

DAI_P18

DAI_P17

DAI_P16

DAI_P15

DAI_P12

V_{DD_INT}

56

81

7

32

57

82

NC

8

33

58

83

NC

9

34

59

84

CLK_CFG0

V_{DD_INT}

CLKIN

10

11

12

13

14

15

16

35

60

85

36

61

86

37

62

87

XTAL

V_{DD_INT}

38

63

88

V_{DD_EXT}

V_{DD_INT}

39

64

89

DAI_P13

DAI_P07

DAI_P19

DAI_P01

DAI_P02

V_{DD_INT}

40

DAI_P11

V_{DD_INT}

65

90

41

66

EMU

91

RESETOUT/RUNRSTIN 17

42

V_{DD_INT}

67

TDO

92

V_{DD_INT}

18

19

20

21

22

23

24

25

43

GND

68

V_{DD_EXT}

V_{DD_INT}

TDI

93

DPI_P01

DPI_P02

DPI_P03

V_{DD_INT}

44

THD_M

THD_P

69

94

45

70

95

V_{DD_EXT}

46

V_{DD_THD}

V_{DD_INT}

71

TCK

96

V_{DD_INT}

47

72

V_{DD_INT}

RESET

TMS

97

DPI_P05

DPI_P04

DPI_P06

DAI_P06

DAI_P05

DAI_P09

48

V_{DD_INT}

73

98

49

V_{DD_INT}

74

99

50

V_{DD_INT}

75

V_{DD_INT}

GND

100

101*

* Lead no. 101 is the GND supply (see Figure 53 and Figure 54) for the processor; this pad must be robustly connected to GND.

MLB pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. For non-automotive models, these pins should be connected

to ground (GND).

Rev. PrD

|

Page 64 of 70

|

February 2011

Preliminary Technical Data

Figure 53 shows the top view of the 100-lead LQFP_EP pin con-

figuration. Figure 54 shows the bottom view of the 100-lead

LQFP_EP lead configuration.

ADSP-21478/ADSP-21479

LEAD 100

LEAD 1

LEAD 76

LEAD 75

LEAD 1 INDICATOR

ADSP-2147x

100-LEAD LQFP_EP

TOP VIEW

LEAD 25

LEAD 51

LEAD 26

LEAD 50

Figure 53. 100-Lead LQFP_EP Lead Configuration (Top View)

LEAD 76

LEAD 100

LEAD 75

LEAD 1

ADSP-2147x

100-LEAD LQFP_EP

GND PAD

LEAD 1 INDICATOR

(LEAD 101)

BOTTOM VIEW

LEAD 51

LEAD 25

LEAD 50

LEAD 26

Figure 54. 100-Lead LQFP_EP Lead Configuration (Bottom View)

Rev. PrD

|

Page 65 of 70

|

February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

196-BALL BGA BALL ASSIGNMENT

Table 60. 196-Ball CSP_BGA Ball Assignment (Numerical by Ball No.)

Ball No. Signal

A1

GND

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

E1

ADDR6

ADDR4

ADDR1

CLK_CFG0

V_{DD_EXT}

ADDR14

ADDR20

WDT_CLKO

ADDR8

ADDR7

ADDR5

V_{DD_EXT}

V_{DD_INT}

V_{DD_EXT}

AMI_RD

ADDR22

FLAG2

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

J1

XTAL

K1

DPI_P02

DPI_P04

DPI_P05

DPI_P09

V_{DD_INT}

N1

DPI_P14

SR_LDO1

SR_LDO4

SR_LDO8

SR_LDO10

DAI_P01

SR_LDO9

DAI_P02

SR_LDO13

SR_SCLK

DAI_P09

SR_SDI

A2

SDCKE

SDDQM

SDRAS

SDWE

SDA10

ADDR11

GND

K2

N2

A3

K3

N3

A4

K4

N4

A5

V_{DD_INT}

GND

K5

N5

A6

DATA12

DATA13

DATA10

DATA9

DATA7

DATA3

DATA1

DATA2

GND

K6

GND

N6

A7

GND

K7

GND

N7

A8

GND

K8

GND

N8

A9

GND

K9

GND

N9

A10

A11

A12

A13

A14

B1

V_{DD_INT}

V_{DD_EXT}

ADDR21

ADDR19

RTXO

K10

K11

K12

K13

K14

L1

V_{DD_INT}

N10

N11

N12

N13

N14

P1

GND

DAI_P16

DAI_P18

DAI_P15

DAI_P03

DPI_P10

DPI_P08

DPI_P06

V_{DD_INT}

SR_LDO17

DAI_P14

GND

ADDR0

CLK_CFG1

BOOT_CFG0

TMS

ADDR13

ADDR12

ADDR10

ADDR17

V_{DD_INT}

GND

B2

E2

L2

P2

SR_LDO3

SR_LDO2

SR_LDO6

WDTRSTO

DAI_P19

DAI_P13

SR_LDO11

SR_LDO15

SR_CLR

B3

E3

L3

P3

B4

E4

L4

P4

B5

RESET

E5

L5

P5

B6

DATA14

DATA11

DATA4

DATA8

DATA6

DATA5

TRST

E6

L6

V_{DD_INT}

P6

B7

E7

GND

L7

V_{DD_INT}

P7

B8

E8

GND

L8

V_{DD_INT}

P8

B9

E9

GND

L9

V_{DD_INT}

P9

B10

B11

B12

B13

B14

C1

E10

E11

E12

E13

E14

F1

V_{DD_INT}

V_{DD_EXT}

BOOT_CFG2

ADDR23

RTXI

L10

L11

L12

L13

L14

M1

M2

M3

V_{DD_INT}

P10

P11

P12

P13

P14

DAI_P10

DAI_P20

DAI_P17

DAI_P04

DPI_P13

DPI_P12

SR_LDO0

DPI_P07

DPI_P11

SR_LDO5

SR_LDO7

DAI_P07

SR_LDO16

SR_SDO

DAI_P06

DAI_P05

DAI_P08

DAI_P12

SR_LAT

SR_LDO14

SR_LDO12

GND

FLAG1

DATA0

ADDR2

ADDR3

RTCLKOUT

MS0

CLKIN

DPI_P01

DPI_P03

ADDR18

C2

F2

ADDR9

BOOT_CFG1

NC

J2

C3

F3

J3

C4

F4

J4

RESETOUT/RUNRSTIN M4

C5

SDCAS

DATA15

TCK

F5

NC

J5

V_{DD_INT}

GND

M5

C6

F6

GND

J6

M6

C7

F7

GND

J7

GND

M7

C8

TDI

F8

GND

J8

GND

M8

C9

SDCLK0

EMU

F9

GND

J9

GND

M9

C10

C11

C12

C13

C14

F10

F11

F12

F13

F14

V_{DD_INT}

V_{DD_EXT}

ADDR15

FLAG0

J10

J11

J12

J13

J14

V_{SS_RTC}

V_{DD_RTC}

DAI_P11

AMI_ACK

MS1

M10

M11

M12

M13

M14

TDO

FLAG3

ADDR16

WDT_CLKIN

AMI_WR

Rev. PrD

|

Page 66 of 70

|

February 2011

Preliminary Technical Data

ADSP-21478/ADSP-21479

OUTLINE DIMENSIONS

The ADSP-2147x processors are available in a 100-lead

LQFP_EP and 196-ball CSP_BGA RoHS compliant packages.

For package assignment by model, see Ordering Guide on

Page 69.

16.20

16.00 SQ

15.80

1.60

14.20

14.00 SQ

13.80

MAX

0.75

0.60

0.45

100

1

76

100

1

75

SEATING

PLANE

PIN 1

EXPOSED

PAD

6.00

REF

1.45

1.40

1.35

0.20

0.15

0.09

TOP VIEW

BOTTOM VIEW

(PINS UP)

(PINS DOWN)

0.15

0.10

0.05

7°

3.5°

0°

51

25

51

25

26

50

26

50

0.08

0.27

0.22

0.17

COPLANARITY

VIEW A

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.50

BSC

VIEW A

LEAD PITCH

ROTATED 90° CCW

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD

Figure 55. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]

(SW-100-2)

Dimensions shown in millimeters

Rev. PrD

|

Page 67 of 70

|

February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

12.10

12.00 SQ

11.90

A1 BALL

CORNER

A1 BALL

CORNER

14 13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

10.40

BSC SQ

0.80

BSC

K

L

M

N

P

0.80

REF

TOP VIEW

DETAIL A

BOTTOM VIEW

1.50

1.41

1.29

1.13

1.06

0.99

DETAIL A

0.35 NOM

0.30 MIN

*

0.50

0.45

0.40

SEATING

PLANE

COPLANARITY

0.12

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-205-AE

WITH EXCEPTION TO BALL DIAMETER.

Figure 56. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]

(BG-196-7)

Dimensions shown in millimeters

SURFACE-MOUNT DESIGN

For industry standard design recommendations, refer to

IPC-7351, Generic Requirements for Surface-Mount Design

and Land Pattern Standard.

Rev. PrD

|

Page 68 of 70

|

February 2011

Preliminary Technical Data

AUTOMOTIVE PRODUCTS

ADSP-21478/ADSP-21479

The ADSP-21478 and ADSP-21479 models are available with

controlled manufacturing to support the quality and reliability

requirements of automotive applications. Note that these auto-

motive models may have specifications that differ from the

commercial models and designers should review the product

Specifications section of this datasheet carefully. Only the auto-

motive grade products shown in Table 61 are available for use in

Automotive applications. Contact your local ADI account rep-

resentative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these

models.

Table 61. Automotive Products

Processor Instruction

Package

Option

Model¹

Temperature Range²On-Chip SRAM Rate (Max)

Package Description

100-Lead LQFP_EP

AD21478WBSWZ2Axx

AD21478WBSWZ2Bxx^{3, 4}

AD21478WYSWZ2Axx

AD21478WYSWZ2Bxx^{3, 4}

AD21479WBSWZ2Axx

AD21479WBSWZ2Bxx^{3, 4}

AD21479WYSWZ2Axx

AD21479WYSWZ2Bxx^{3, 4}

¹Z =RoHS Compliant Part.

–40°C to +85°C

–40°C to +105°C

–40°C to +85°C

–40°C to +105°C

3 Mbit

5 Mbit

266 MHz

SW-100-2

²Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 19 for junction temperature (T_J)

specification which is the only temperature specification.

³Contains multichannel audio decoders from Dolby and DTS.

⁴Contains Digital Transmission Content Protection (DTCP) from DTLA. User must have current license from DTLA to order this product.

ORDERING GUIDE

Temperature

Range²

0°C to +70°C

ProcessorInstruction

On-Chip SRAM Rate (Max)

Package

Option

Model¹

Package Description

196-Ball CSP_BGA

100-Lead LQFP_EP

196-Ball CSP_BGA

100-Lead LQFP_EP

196-Ball CSP_BGA

ADSP-21478KBCZ-3AX

ADSP-21478BSWZ-2AX

ADSP-21478BSWZ-2BX^{3, 4}

ADSP-21478BBCZ-2AX

ADSP-21479KBCZ-3AX

ADSP-21479BSWZ-2AX

ADSP-21479BSWZ-2BX^{3, 4}

ADSP-21479BBCZ-2AX

¹Z =RoHS Compliant Part.

3 Mbit

5 Mbit

300 MHz

266 MHz

300 MHz

266 MHz

BC-196-7

SW-100-2

BC-196-7

SW-100-2

BC-196-7

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

²Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 19 for junction temperature (T_J)

specification which is the only temperature specification.

³Contains multichannel audio decoders from Dolby and DTS.

⁴Contains Digital Transmission Content Protection (DTCP) from DTLA. User must have current license from DTLA to order this product.

Rev. PrD

|

Page 69 of 70

|

February 2011

ADSP-21478/ADSP-21479

Preliminary Technical Data

registered trademarks are the property of their respective owners.

PR09017-0-2/11(PrD)

Rev. PrD

|

Page 70 of 70

|

February 2011


型号：	ADSP-21478BSWZ-2AX
厂家：	ADI
描述：	IC MIXED DSP, Digital Signal Processor 时钟外围集成电路
文件：	总70页 (文件大小：2169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21478BSWZ-2AX [ADI]

相关型号：

ADSP-21478BSWZ-2BX

ADSP-21478KBCZ-1A

ADSP-21478KBCZ-2A

ADSP-21478KBCZ-3A

ADSP-21478KBCZ-3AX

ADSP-21478KCPZ-1A

ADSP-21478KSWZ-1A

ADSP-21478KSWZ-2A

ADSP-21479

ADSP-21479BBCZ-2A

ADSP-21479BCPZ-1A

ADSP-21479BSWZ-2A