ADSP-21478KSWZ-1A_技术文档

SHARC Processor

ADSP-21477/ADSP-21478/ADSP-21479

The ADSP-2147x processors are available with unique

audio-centric peripherals, such as the digital applications

interface, serial ports, precision clock generators, S/PDIF

transceiver, asynchronous sample rate converters, input

data port, and more.

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—up to 5M bits of on-chip RAM, 4M bits of

on-chip ROM

Up to 300 MHz operating frequency

Qualified for automotive applications. See Automotive Prod-

ucts on Page 75

Factory programmed ROM versions containing latest audio

decoders from Dolby and DTS, available to IP licenses

For complete ordering information, see Ordering Guide on

Page 76.

Code compatible with all other members of the SHARC family

Internal Memory

SIMD Core

Block 0

RAM/ROM

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

Instruction

Cache

5 Stage

Sequencer

B2D

64-BIT

B0D

64-BIT

B3D

64-BIT

B1D

64-BIT

Core

Timer

S

DAG1/2

PEx

DMD

64-BIT

DMD

64-BIT

PEy

Core Bus

Cross Bar

Internal Memory I/F

PMD

64-BIT

PMD 64-BIT

FLAGx/IRQx/

TMREXP

IOD0 32-BIT

THERMAL

DIODE

EPD BUS 64-BIT

JTAG

IOD1

32-BIT

PERIPHERAL BUS 32-BIT

IOD0 BUS

FFT

FIR

IIR

DTCP/

MTM

PERIPHERAL BUS

EP

SPEP BUS

CORE

PCG

PDAP/

IDP

7-0

S/PDIF PCG ASRC

SPORT

7-0

SDRAM

CTL

SHIFT

REG

CORE PWM

TIMER

1-0

AMI

FLAGS/

TWI SPI/B UART

RTC WDT MLB

Tx/Rx

A

-D

3

-0

FLAGS

3-0

C

-D

PWM3-1

DAI Routing/Pins

DPI Routing/Pins

External Port Pin MUX

External

Port

Peripherals

DAI Peripherals

DPI Peripherals

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADSP-21477/ADSP-21478/ADSP-21479

TABLE OF CONTENTS

Summary ............................................................... 1

General Description ................................................. 3

Family Core Architecture ........................................ 4

Family Peripheral Architecture ................................ 8

I/O Processor Features ......................................... 12

System Design .................................................... 13

Development Tools ............................................. 13

Additional Information ........................................ 15

Related Signal Chains .......................................... 15

Pin Function Descriptions ....................................... 16

Specifications ........................................................ 21

Operating Conditions .......................................... 21

Electrical Characteristics ....................................... 22

Maximum Power Dissipation ................................ 24

Package Information ........................................... 24

ESD Sensitivity ................................................... 24

Absolute Maximum Ratings ................................... 24

Timing Specifications ........................................... 25

Output Drive Currents ......................................... 65

Test Conditions .................................................. 65

Capacitive Loading .............................................. 65

Thermal Characteristics ........................................ 66

88-LFCSP_VQ Lead Assignment ................................ 68

100-LQFP_EP Lead Assignment ................................ 70

196-BGA Ball Assignment ........................................ 72

Outline Dimensions ................................................ 73

Surface-Mount Design .......................................... 75

Automotive Products ........................................... 75

Ordering Guide ..................................................... 76

REVISION HISTORY

7/13—Rev. B to Rev. C

PRODUCT APPLICATION RESTRICTION

Updated Development Tools .................................... 13

Not for use in in-vivo applications for body fluid constituent

monitoring, including monitoring one or more of the compo-

nents that form, or may be a part of, or contaminate human

blood or other body fluids, such as, but not limited to, car-

boxyhemoglobin, methemoglobin total hemoglobin, oxygen

saturation, oxygen content, fractional arterial oxygen satura-

tion, bilirubin, glucose, drugs, lipids, water, protein, and pH.

Revised MS_1-0pin description and V_{DD_RTC}pin description in

Pin Function Descriptions ....................................... 16

Corrected parameter from I_DD-INTYPto I_{DD_INT}in

Electrical Characteristics .......................................... 22

Modified Total Power Dissipation .............................. 23

Added footnote 3 to Table 32 in AMI Read .................. 37

Changed Max values in Table 43 in Pulse-Width Modulation

Generators (PWM) ................................................ 51

Corrected the following lead names in Table 61 in

88-LFCSP_VQ Lead Assignment ............................... 68

• CLK_CFG_1 to CLK_CFG1

• BOOTCFG_0 to BOOT_CFG0

• BOOTCFG_1 to BOOT_CFG1

• CLK_CFG_0 to CLK_CFG0

• XTAL2 to XTAL

Updated package outline drawings for 88-Lead LFCSP and

100-Lead LQFP_EP packages in Outline Dimensions ..... 73

Added automotive model and corrected models in Table 64

(Automotive Product Models) in Automotive Products ... 75

To view product/process change notifications (PCNs) related to

this data sheet revision, please visit the processor’s product page

on the www.analog.com website and use the View PCN link.

Rev. C

|

Page 2 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

GENERAL DESCRIPTION

The ADSP-2147x SHARC^®processors are members of the

SIMD SHARC family of DSPs that feature Analog Devices’

Super Harvard Architecture. The processors are source code

Table 2. ADSP-2147x Family Features (Continued)

compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x,

ADSP-2146x, and ADSP-2116x DSPs as well as with first

generation ADSP-2106x SHARC processors in SISD (single-

instruction, single-data) mode. These processors are 32-bit/

40-bit floating-point processors optimized for high perfor-

mance audio applications with a large on-chip SRAM, multiple

internal buses to eliminate I/O bottlenecks, and an innovative

digital applications interface (DAI).

Feature

Watch Dog Timer²

Real-Time Clock^{2, 3}

Shift Register²

IDP/PDAP

No

Yes

Table 1 shows performance benchmarks for the ADSP-2147x

processors. Table 2 shows the features of the individual product

offerings.

Yes

1

UART

DAI (SRU)/DPI (SRU2)

S/PDIF Transceiver

SPI

20/14 Pins

Table 1. Processor Benchmarks

1

2

Speed

(at 200 MHz)

Benchmark Algorithm

(at 300 MHz)

TWI

1

1024 Point Complex FFT

(Radix 4, with Reversal)

FIR Filter (per Tap)¹

30.59 μs

45.885 μs

SRC SNR Performance

Thermal Diode⁴

VISA Support

–128 dB

Yes

1.66 ns

6.65 ns

2.49 ns

IIR Filter (per Biquad)¹

9.975 ns

Yes

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]

[4 × 4] × [4 × 1]

100-Lead

LQFP

196-Ball CSP_BGA

100-Lead LQFP

14.99 ns

26.66 ns

22.485 ns

39.99 ns

88-Lead

LFCSP_VQ

88-lead LFCSP_VQ

Divide (y/×)

11.61 ns

17.41 ns

27.12 ns

Package¹

Inverse Square Root

¹Assumes two files in multichannel SIMD mode.

18.08 ns

¹The 100-lead and 88-lead packages of the processors do not contain an external

port. The SDRAM controller pins must be disabled when using this package.

For more information, see Pin Function Descriptions on Page 17.

²Available on the 196-ball CSP_BGA package only.

Table 2. ADSP-2147x Family Features

³Real Time Clock (RTC) is supported only for products with a temperature range

of 0°C to +70°C and not supported for all other temperature grades.

⁴Available on the 88-lead and 100-lead packages only.

The diagram on Page 1 shows the two clock domains (core and

I/O processor) that make up the ADSP-2147x processors. The

core clock domain contains the following features.

Feature

Frequency

RAM

200 MHz

2M bits

N/A

Up to 300 MHz

• Two processing elements (PEx, PEy), each of which com-

prises an ALU, multiplier, shifter, and data register file

3M bits 5M bits

4M bits

ROM

• Two data address generators (DAG1, DAG2)

• A program sequencer with instruction cache

4 units (3 in 100-lead

package)

Pulse-Width Modulation

3

• PM and DM buses capable of supporting 2 × 64-bit data

transfers between memory and the core at every core pro-

cessor cycle

External Port Interface

(SDRAM, AMI)¹

No

Yes, 16-Bit

8

• One periodic interval timer with pinout

• On-chip SRAM (up to 5M bit)

Serial Ports

Direct DMA from SPORTs

to External Memory

No

Yes

• A JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points, which allows flexible exception handling.

FIR, IIR, FFT Accelerator

Automotive models

only

MediaLB Interface

Rev. C

|

Page 3 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

The block diagram of the ADSP-2147x on Page 1 also shows the

peripheral clock domain (also known as the I/O processor),

which contains the following features:

elements. When using the DAGs to transfer data in SIMD

mode, two data values are transferred with each memory or reg-

ister file access.

• IOD0 (peripheral DMA) and IOD1 (external port DMA)

buses for 32-bit data transfers

SIMD mode is supported from external SDRAM but is not sup-

ported in the AMI.

• Peripheral and external port buses for core connection

Independent, Parallel Computation Units

• External port with an asynchronous memory interface

(AMI) and SDRAM controller

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

• 4 units for pulse width modulation (PWM) control

• 1 memory-to-memory (MTM) unit for internal-to-internal

memory transfers

• Digital applications interface that includes four precision

clock generators (PCG), an input data port (IDP/PDAP)

for serial and parallel interconnect, an S/PDIF

receiver/transmitter, four asynchronous sample rate con-

verters, eight serial ports, a shift register, and a flexible

signal routing unit (DAI SRU).

Timer

• Digital peripheral interface that includes two timers, a 2-

wire interface, one UART, two serial peripheral interfaces

(SPI), two precision clock generators (PCG), three pulse

width modulation (PWM) units, and a flexible signal rout-

ing unit (DPI SRU).

The processor contains a core timer that can generate periodic

software interrupts. The core timer can be configured to use

FLAG3 as a timer expired signal.

Data Register File

As shown in the SHARC core block diagram on Page 5, the pro-

cessors use two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. With its SIMD computational hard-

ware, the processors can perform 1.8 GFLOPS running at

300 MHz.

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register (16 primary, 16 secondary) register files,

combined with the processor’s enhanced Harvard architecture,

allow unconstrained data flow between computation units and

internal memory. The registers in PEX are referred to as

R0–R15 and in PEY as S0–S15.

FAMILY CORE ARCHITECTURE

The processors are code compatible at the assembly level with

the ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,

ADSP-21160, and ADSP-21161, and with the first generation

ADSP-2106x SHARC processors. The ADSP-2147x share archi-

tectural features with the ADSP-2126x, ADSP-2136x, ADSP-

2137x, ADSP-2146x, and ADSP-2116x SIMD SHARC proces-

sors, as shown in Figure 2 and detailed in the following sections.

Context Switch

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result registers all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

SIMD Computational Engine

The processors contain two computational processing elements

that operate as a single-instruction, multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. SIMD mode allows

the processor to execute the same instruction in both processing

elements, but each processing element operates on different

data. This architecture is efficient at executing math intensive

DSP algorithms.

Universal Registers

Universal registers can be used for general-purpose tasks. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all peripheral control and status

registers.

The data bus exchange register (PX) permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM/DM data bus. These

registers contain hardware to handle the data width difference.

SIMD mode also affects the way data is transferred between

memory and the processing elements because twice the data

bandwidth is required to sustain computational operation in the

processing elements. Therefore, entering SIMD mode also dou-

bles the bandwidth between memory and the processing

Single-Cycle Fetch of Instruction and Four Operands

The processors feature an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 2). With its separate program and data memory

Rev. C

|

Page 4 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

buses and on-chip instruction cache, the processor can simulta-

neously fetch four operands (two over each data bus) and one

instruction (from the cache), all in a single cycle.

S

JTAG

FLAG TIMER INTERRUPT CACHE

SIMD Core

PM ADDRESS 24

PM DATA 48

DMD/PMD 64

5 STAGE

PROGRAM SEQUENCER

DAG2

16×32

DAG1

16×32

PM ADDRESS 32

SYSTEM

I/F

DM ADDRESS 32

PM DATA 64

USTAT

4×32-BIT

PX

64-BIT

DM DATA 64

DATA

SWAP

RF

Rx/Fx

PEx

RF

Sx/SFx

PEy

ALU

SHIFTER

MULTIPLIER

ALU

SHIFTER MULTIPLIER

16×40-BIT

MRB

80-BIT

MSB

80-BIT

MRF

80-BIT

MSF

80-BIT

ASTATy

STYKy

ASTATx

STYKx

Figure 2. SHARC Core Block Diagram

primary register sets, 16 secondary). The DAGs automatically

handle address pointer wraparound, reduce overhead, increase

performance, and simplify implementation. Circular buffers can

start and end at any memory location.

Instruction Cache

The processor includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full speed execution of core looped operations such

as digital filter multiply-accumulates, and FFT butterfly

processing.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

processors can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The processor’s two data address generators (DAGs) are used

for indirect addressing and implementing circular data buffers

in hardware. Circular buffers allow efficient programming of

delay lines and other data structures required in digital signal

processing, and are commonly used in digital filters and Fourier

transforms. The two DAGs of the processors contain sufficient

registers to allow the creation of up to 32 circular buffers (16

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from

previous SHARC processors, the processors support new

instructions of 16 and 32 bits. This feature, called Variable

Instruction Set Architecture (VISA), drops redundant/unused

Rev. C

|

Page 5 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

bits within the 48-bit instruction to create more efficient and

compact code. The program sequencer supports fetching these

16-bit and 32-bit instructions from both internal and external

SDRAM memory. This support is not extended to the asynchro-

nous memory interface (AMI). Source modules need to be built

using the VISA option, in order to allow code generation tools

to create these more efficient opcodes.

floating-point storage format is supported that effectively dou-

bles the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point

formats is performed in a single instruction. While each mem-

ory block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

On-Chip Memory

Using the DM bus and PM buses, with one bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

The processors contain varying amounts of internal RAM and

internal ROM which is shown in Table 3 through Table 5. Each

block can be configured for different combinations of code and

data storage. Each memory block supports single-cycle, inde-

pendent accesses by the core processor and I/O processor.

The memory maps in Table 3 through Table 5 display the inter-

nal memory address space of the processors. The 48-bit space

section describes what this address range looks like to an

instruction that retrieves 48-bit memory. The 32-bit section

describes what this address range looks like to an instruction

that retrieves 32-bit memory.

The processor’s SRAM can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data, 106.7k

words of 48-bit instructions (or 40-bit data), or combinations of

different word sizes up to 5M bits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit

Table 3. ADSP-21477 Internal Memory Space (2M bits)

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Instruction Word (48 Bits)

Block 0 ROM (Reserved)

0x0008 0000–0x0008 AAA9

Reserved

Normal Word (32 Bits)

Block 0 ROM (Reserved)

0x0008 0000–0x0008 FFFF

Reserved

Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0010 0000–0x0011 FFFF

Reserved

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

Reserved

0x0004 8000–0x0004 8FFF

0x0008 AAAA–0x0008 BFFF

Block 0 SRAM

0x0009 0000–0x0009 1FFF

Block 0 SRAM

0x0012 0000–0x0012 FFFF

Block 0 SRAM

0x0004 9000–0x0004 BFFF

Reserved

0x0008 C000–0x0008 FFFF

Reserved

0x0009 2000–0x0009 7FFF

Reserved

0x0012 4000–0x0012 FFFF

Reserved

0x0004 C000–0x0004 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

Reserved

0x0009 000–0x0009 5554

Block 1 ROM (Reserved)

0x000A 0000–0x000A AAA9

Reserved

0x0009 8000–0x0009 FFFF

Block 1 ROM (Reserved)

0x000A 0000–0x000AFFFF

Reserved

0x0013 0000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

Block 1 SRAM

0x000A AAAA–0x000A BFFF

Block 1 SRAM

0x000B 0000–0x000B 1FFF

Block 1 SRAM

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 BFFF

Reserved

0x000A C000–0x000A FFFF

Reserved

0x000B 2000–0x000B 7FFF

Reserved

0x0016 4000–0x0016 FFFF

Reserved

0x0005 C000–0x0005 FFFF

Block 2 SRAM

0x000B 0000–0x000B 5554

Block 2 SRAM

0x000B 8000–0x000B FFFF

Block 2 SRAM

0x0017 0000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 0FFF

Reserved

0x000C 0000–0x000C 1554

Reserved

0x000C 0000–0x000C 1FFF

Reserved

0x0018 0000–0x0018 3FFF

Reserved

0x0006 1000– 0x0006 FFFF

Block 3 SRAM

0x000C 1555–0x000D 5554

Block 3 SRAM

0x000C 2000–0x000D FFFF

Block 3 SRAM

0x0018 4000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 0FFF

Reserved

0x000E 0000–0x000E 1554

Reserved

0x000E 0000–0x000E 1FFF

Reserved

0x001C 0000–0x001C 3FFF

Reserved

0x0007 1000–0x0007 FFFF

0x000E 1555–0x000F 5554

0x000E 2000–0x000F FFFF

0x001C 4000–0x001F FFFF

Rev. C

|

Page 6 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 4. ADSP-21478 Internal Memory Space (3M bits)¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Instruction Word (48 Bits)

Long Word (64 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

0x0008 0000–0x0008 AAA9

0x0008 0000–0x0008 FFFF

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

0x0008 AAAA–0x0008 BFFF

0x0009 0000–0x0009 1FFF

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 CFFF

0x0008 C000–0x0009 1554

0x0009 2000–0x0009 9FFF

0x0012 4000–0x0013 3FFF

Reserved

0x0004 D000–0x0004 FFFF

0x0009 1555–0x0009 FFFF

0x0009 A000–0x0009 FFFF

0x0013 4000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

0x000A 0000–0x000A AAA9

0x000A 0000–0x000A FFFF

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

0x000A AAAA–0x000A BFFF

0x000B 0000–0x000B 1FFF

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 CFFF

0x000A C000–0x000B 1554

0x000B 2000–0x000B 9FFF

0x0016 4000–0x0017 3FFF

Reserved

0x0005 D000–0x0005 FFFF

0x000B 1555–0x000B FFFF

0x000B A000–0x000B FFFF

0x0017 4000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 1FFF

0x000C 0000–0x000C 2AA9

0x000C 0000–0x000C 3FFF

0x0018 0000–0x0018 7FFF

Reserved

0x0006 2000– 0x0006 FFFF

0x000C 2AAA–0x000D FFFF

0x000C 4000–0x000D FFFF

0x0018 8000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 1FFF

0x000E 0000–0x000E 2AA9

0x000E 0000–0x000E 3FFF

0x001C 0000–0x001C 7FFF

Reserved

0x0007 2000–0x0007 FFFF

0x000E 2AAA–0x000F FFFF

0x000E 4000–0x000F FFFF

0x001C 8000–0x001F FFFF

¹Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales

representative for additional details.

Rev. C

|

Page 7 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 5. ADSP-21479 Internal Memory Space (5M bits)¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Instruction Word (48 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

0x0008 0000–0x0008 AAA9

0x0008 0000–0x0008 FFFF

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

0x0008 AAAA–0x0008 BFFF

0x0009 0000–0x0009 1FFF

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 EFFF

0x0008 C000–0x0009 3FFF

0x0009 2000–0x0009 DFFF

0x0012 4000–0x0013 BFFF

Reserved

0x0004 F000–0x0004 FFFF

0x0009 4000–0x0009 FFFF

0x0009 E000–0x0009 FFFF

0x0013 C000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

0x000A 0000–0x000A AAA9

0x000A 0000–0x000AFFFF

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

0x000A AAAA–0x000A BFFF

0x000B 0000–0x000B 1FFF

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 EFFF

0x000A C000–0x000B 3FFF

0x000B 2000–0x000B DFFF

0x0016 4000–0x0017 BFFF

Reserved

0x0005 F000–0x0005 FFFF

0x000B 4000–0x000B FFFF

0x000B E000–0x000B FFFF

0x0017 C000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 3FFF

0x000C 0000–0x000C 5554

0x000C 0000–0x000C 7FFF

0x0018 0000–0x0018 FFFF

Reserved

0x0006 4000– 0x0006 FFFF

0x000C 5555–0x0000D FFFF

0x000C 8000–0x000D FFFF

0x0019 0000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 3FFF

0x000E 0000–0x000E 5554

0x000E 0000–0x000E 7FFF

0x001C 0000–0x001C FFFF

Reserved

0x0007 4000–0x0007 FFFF

0x000E 5555–0x0000F FFFF

0x000E 8000–0x000F FFFF

0x001D 0000–0x001F FFFF

¹Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales

representative for additional details.

On-Chip Memory Bandwidth

Digital Transmission Content Protection

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming

there are no block conflicts). The total bandwidth is realized

using the DMD and PMD buses (2 × 64-bit at CCLK speed) and

the IOD0/1 buses (2 × 32-bit at PCLK speed).

The DTCP specification defines a cryptographic protocol for

protecting audio entertainment content from illegal copying,

intercepting, and tampering as it traverses high performance

digital buses, such as the IEEE 1394 standard. Only legitimate

entertainment content delivered to a source device via another

approved copy protection system (such as the DVD content

scrambling system) is protected by this copy protection system.

For more information on this feature, contact your local ADI

sales office.

ROM Based Security

The processors have a ROM security feature that provides hard-

ware support for securing user software code by preventing

unauthorized reading from the internal code. When using this

feature, the processors do not boot-load any external code, exe-

cuting exclusively from internal ROM. Additionally, the

processor is not freely accessible via the JTAG port. Instead, a

unique 64-bit key, which must be scanned in through the JTAG

or Test Access Port, is assigned to each customer. The device

ignores an incorrect key. Emulation features are available after

the correct key is scanned.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-2147x family contains a rich set of peripherals that

support a wide variety of applications including high quality

audio, medical imaging, communications, military, test equip-

ment, 3D graphics, speech recognition, motor control, imaging,

and other applications.

Rev. C

|

Page 8 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Note that code execution is only supported from Bank 0 regard-

less of VISA/ISA. Table 7 shows the address ranges for

External Memory

The external memory interface supports access to the external

memory through core and DMA accesses. The external memory

address space is divided into four banks. Any bank can be pro-

grammed as either asynchronous or synchronous memory. The

external ports are comprised of the following modules.

instruction fetch in each mode.

Table 7. External Bank 0 Instruction Fetch

Size in

• An AMI which communicates with SRAM, FLASH, and

other devices that meet the standard asynchronous SRAM

access protocol. The AMI supports 6M words of external

memory in Bank 0 and 8M words of external memory in

Bank 1, Bank 2, and Bank 3.

Access Type Words

Address Range

ISA (NW)

4M

0x0020 0000–0x005F FFFF

0x0060 0000–0x00FF FFFF

VISA (SW)

10M

• An SDRAM controller that supports a glueless interface

with any of the standard SDRAMs. The SDC supports 62M

words of external memory in Bank 0, and 64M words of

external memory in Bank 1, Bank 2, and Bank 3.

SDRAM Controller

The SDRAM controller, available on the ADSP-2147x in the

196-ball CSP_BGA package, provides an interface of up to four

separate banks of industry-standard SDRAM devices or

DIMMs, at speeds up to f_SDCLK. Fully compliant with the

SDRAM standard, each bank has its own memory select line

(MS0–MS3), and can be configured to contain between

4 Mbytes and 256 Mbytes of memory. SDRAM external mem-

ory address space is shown in Table 8.

• Arbitration logic to coordinate core and DMA transfers

between internal and external memory over the

external port.

External Port

The external port provides a high performance, glueless inter-

face to a wide variety of industry-standard memory devices. The

external port, available on the 196-ball CSP_BGA, may be used

to interface to synchronous and/or asynchronous memory

devices through the use of its separate internal memory control-

lers. The first is an SDRAM controller for connection of

industry-standard synchronous DRAM devices while the sec-

ond is an asynchronous memory controller intended to

interface to a variety of memory devices. Four memory select

pins enable up to four separate devices to coexist, supporting

any desired combination of synchronous and asynchronous

device types. Non-SDRAM external memory address space is

shown in Table 6.

Table 8. External Memory for SDRAM Addresses

Size in

Bank

Words

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

62M

0x0020 0000–0x03FF FFFF

0x0400 0000–0x07FF FFFF

0x0800 0000–0x0BFF FFFF

0x0C00 0000–0x0FFF FFFF

64M

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

SDRAM and the AMI interface do not support 32-bit wide

devices.

Table 6. External Memory for Non-SDRAM Addresses

Size in

Bank

Words

Address Range

The SDRAM controller address, data, clock, and control pins

can drive loads up to distributed 30 pF. For larger memory sys-

tems, the SDRAM controller external buffer timing should be

selected and external buffering should be provided so that the

load on the SDRAM controller pins does not exceed 30 pF.

Bank 0

Bank 1

Bank 2

Bank 3

6M

0x0020 0000–0x007F FFFF

0x0400 0000–0x047F FFFF

0x0800 0000–0x087F FFFF

0x0C00 0000–0x0C7F FFFF

8M

Note that the external memory bank addresses shown are for

normal-word (32-bit) accesses. If 48-bit instructions as well as

32-bit data are both placed in the same external memory bank,

care must be taken while mapping them to avoid overlap.

SIMD Access to External Memory

The SDRAM controller supports SIMD access on the 64-bit

external port data bus (EPD) which allows access to the comple-

mentary registers on the PEy unit in the normal word space

(NW). This improves performance since there is no need to

explicitly load the complementary registers (as in SISD mode).

Asynchronous Memory Controller

The asynchronous memory controller, available on the

ADSP-2147x in the 196-ball CSP_BGA package, provides a con-

figurable interface for up to four separate banks of memory or

I/O devices. Each bank can be independently programmed with

different timing parameters, enabling connection to a wide vari-

ety of memory devices including SRAM, flash, and EPROM, as

well as I/O devices that interface with standard memory control

lines. Bank 0 occupies a 6M word window and Banks 1, 2, and 3

VISA and ISA Access to External Memory

The SDRAM controller supports VISA code operation which

reduces the memory load since the VISA instructions are com-

pressed. Moreover, bus fetching is reduced because, in the best

case, one 48-bit fetch contains three valid instructions. Code

execution from the traditional ISA operation is also supported.

Rev. C

|

Page 9 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

occupy a 8M word window in the processor’s address space but,

if not fully populated, these windows are not made contiguous

by the memory controller logic.

Serial ports operate in five modes:

• Standard serial mode

• Multichannel (TDM) mode

• I²S mode

External Port Throughput

The throughput for the external port, based on 133 MHz clock

and 16-bit data bus, is 88 Mbytes/sec for the AMI and

266 Mbytes/sec for SDRAM.

• Packed I²S mode

• Left-justified mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

MediaLB

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

bi phase encoded signal. The serial data input to the

The automotive models of the processors have an MLB interface

which allows the processor to function as a media local bus

device. It includes support for both 3-pin and 5-pin MLB proto-

cols. It supports speeds up to 1024 FS (49.25M bits/sec,

FS = 48.1 kHz) and up to 31 logical channels, with up to

124 bytes of data per media local bus frame. For a list of auto-

motive products, see Automotive Products on Page 75.

receiver/transmitter can be formatted as left justified, I²S or

right-justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources, such as the

SPORTs, external pins, the precision clock generators (PCGs),

and are controlled by the SRU control registers.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the DAI pins

(DAI_P20–1).

Asynchronous Sample Rate Converter (SRC)

The sample rate converter contains four blocks and is the same

core as that used in the AD1896 192 kHz stereo asynchronous

sample rate converter. The SRC block provides up to 128 dB

SNR and is used to perform synchronous or asynchronous sam-

ple rate conversion across independent stereo channels, without

using internal processor resources. The four SRC blocks can

also be configured to operate together to convert multichannel

audio data without phase mismatches. Finally, the SRC can be

used to clean up audio data from jittery clock sources such as

the S/PDIF receiver.

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with non con-

figurable signal paths.

The associated peripherals include eight serial ports, four preci-

sion clock generators (PCG), a S/PDIF transceiver, four ASRCs,

and an input data port (IDP). The IDP provides an additional

input path to the SHARC core, configurable as either eight

channels of serial data, or a single 20-bit wide synchronous par-

allel data acquisition port. Each data channel has its own DMA

channel that is independent from the processor’s serial ports.

Input Data Port

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

audio channels in I²S, left-justified sample pair, or right-justified

mode.

Serial Ports (SPORTs)

The processors feature eight synchronous serial ports that pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

The IDP also provides a parallel data acquisition port (PDAP)

which can be used for receiving parallel data. The PDAP port

has a clock input and a hold input. The data for the PDAP can

be received from DAI pins or from the external port pins. The

PDAP supports a maximum of 20-bit data and four different

packing modes to receive the incoming data.

Serial ports can support up to 16 transmit or 16 receive DMA

channels of audio data when all eight SPORTs are enabled, or

four full duplex TDM streams of 128 channels per frame.

Precision Clock Generators

The precision clock generators (PCG) consist of four units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A B, C, and D are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. One SPORT pro-

vides two transmit signals while the other SPORT provides the

two receive signals. The frame sync and clock are shared.

The outputs of PCG A and B can be routed through the DAI

pins and the outputs of PCG C and D can be driven on to the

DAI as well as the DPI pins.

Rev. C

|

Page 10 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Pulse-Width Modulation

Digital Peripheral Interface (DPI)

The PWM module is a flexible, programmable, PWM waveform

The digital peripheral interface provides connections to two

serial peripheral interface ports (SPI), one universal asynchro-

nous receiver-transmitter (UART), 12 flags, a 2-wire interface

(TWI), three PWM modules (PWM3–1), and two general-

purpose timers.

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

Serial Peripheral (Compatible) Interface (SPI)

The SPI is an industry-standard synchronous serial link,

enabling the SPI-compatible port to communicate with other

SPI compatible devices. The SPI consists of two data pins, one

device select pin, and one clock pin. It is a full-duplex synchro-

nous serial interface, supporting both master and slave modes.

The SPI port can operate in a multi-master environment by

interfacing with up to four other SPI-compatible devices, either

acting as a master or slave device. The SPI-compatible periph-

eral implementation also features programmable baud rate and

clock phase and polarities. The SPI-compatible port uses open

drain drivers to support a multi-master configuration and to

avoid data contention.

The entire PWM module has four groups of four PWM outputs

generating 16 PWM outputs in total. Each PWM group pro-

duces two pairs of PWM signals on the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

midpoint of the PWM period. In double update mode, a second

updating of the PWM registers is implemented at the midpoint

of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

UART Port

The processors provide a full-duplex Universal Asynchronous

Receiver/Transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface

standard. The UART port also includes support for 5 to 8 data

bits, 1 or 2 stop bits, and none, even, or odd parity. The UART

port supports two modes of operation:

PWM signals can be mapped to the external port address lines

or to the DPI pins.

Timers

The processors have a total of three timers: a core timer that can

generate periodic software interrupts and two general-purpose

timers that can generate periodic interrupts and be inde-

pendently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watch dog mode

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

The core timer can be configured to use FLAG3 as a timer

expired signal, and the general-purpose timers have one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables the general-

purpose timer.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire serial bus used to move 8-bit

data while maintaining compliance with the I²C bus protocol.

The TWI master incorporates the following features:

• Support for bit rates ranging from (f_PCLK/1,048,576) to

(f_PCLK/16) bits per second.

• Support for data formats from 7 to 12 bits per frame.

• 7-bit addressing

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

• Simultaneous master and slave operation on multiple

device systems with support for multi-master data

arbitration

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

Rev. C

|

Page 11 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 9. DMA Channels (Continued)

Shift Register

The shift register can be used as a serial to parallel data con-

verter. The shift register module consists of an 18-stage serial

shift register, 18-bit latch, and three-state output buffers. The

shift register and latch have separate clocks. Data is shifted into

the serial shift register on the positive-going transitions of the

shift register serial clock (SR_SCLK) input. The data in each

flip-flop is transferred to the respective latch on a positive-going

transition of the shift register latch clock (SR_LAT) input.

Peripheral

DMA Channels

External Port

2

Accelerators

2

Memory-to-Memory

MediaLB¹

¹Automotive models only.

2

31

The shift register’s signals can be configured as follows.

Delay Line DMA

• The SR_SCLK can come from any of the SPORT0–7 SCLK

outputs, PCGA/B clock, any of the DAI pins (1–8), and one

dedicated pin (SR_SCLK).

The processor provides delay line DMA functionality. This

allows processor reads and writes to external delay line buffers

(and therefore to external memory) with limited core

interaction.

• The SR_LAT can come from any of SPORT0–7 frame sync

outputs, PCGA/B frame sync, any of the DAI pins (1–8),

and one dedicated pin (SR_LAT).

Scatter/Gather DMA

The processor provides scatter/gather DMA functionality. This

allows processor DMA reads/writes to/from noncontiguous

memory blocks.

• The SR_SDI input can from any of SPORT0–7 serial data

outputs, any of the DAI pins (1–8), and one dedicated pin

(SR_SDI).

FFT Accelerator

Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must

come from same source except in the case of where SR_SCLK

comes from PCGA/B or SR_SCLK and SR_LAT come from

PCGA/B.

The FFT accelerator implements radix-2 complex/real input,

complex output FFTs with no core intervention. The FFT accel-

erator runs at the peripheral clock frequency.

If SR_SCLK comes from PCGA/B, then SPORT0–7 generates

the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT

come from PCGA/B, then SPORT0–7 generates the

SR_SDI signal.

FIR Accelerator

The FIR (finite impulse response) accelerator consists of a 1024

word coefficient memory, a 1024 word deep delay line for the

data, and four MAC units. A controller manages the accelerator.

The FIR accelerator runs at the peripheral clock frequency.

I/O PROCESSOR FEATURES

The I/O processor provides up to 65 channels of DMA as well as

an extensive set of peripherals.

IIR Accelerator

The IIR (infinite impulse response) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency.

DMA Controller

The DMA controller operates independently and invisibly to

the processor core, allowing DMA operations to occur while the

core is simultaneously executing its program instructions. DMA

transfers can occur between the processor’s internal memory

and its serial ports, the SPI-compatible (serial peripheral inter-

face) ports, the IDP (input data port), the parallel data

acquisition port (PDAP) or the UART.

Watchdog Timer (WDT)

The processors include a 32-bit watchdog timer that can be used

to implement a software watchdog function. A software watch-

dog can improve system reliability by forcing the processor to a

known state through generation of a system reset if the timer

expires before being reloaded by software. Software initializes

the count value of the timer, and then enables the timer.

Up to 65 channels of DMA are available on the processors as

shown in Table 9.

Programs can be downloaded using DMA transfers. Other

DMA features include interrupt generation upon completion of

DMA transfers, and DMA chaining for automatic linked DMA

transfers.

The WDT is used to supervise the stability of the system soft-

ware. When used in this way, software reloads the WDT in a

regular manner so that the downward counting timer never

expires. An expiring timer then indicates that system software

might be out of control.

Table 9. DMA Channels

Peripheral

SPORTs

PDAP

DMA Channels

The WDT resets both the core and the internal peripherals.

Software must be able to determine if the watch dog was the

source of the hardware reset by interrogating a status bit in the

watch dog timer control register.

16

8

SPI

2

UART

2

Rev. C

|

Page 12 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

The watch dog timer also has an internal RC oscillator that can

Table 10. Boot Mode Selection

be used as the clock source. The internal RC oscillator can be

used as an optional alternative to using an external clock applied

to the WDT_CLIN pin.

BOOT_CFG2–0¹Booting Mode

000

001

010

011

SPI Slave Boot

SPI Master Boot (from Flash and Other Slaves)

AMI User Boot (for 8-bit Flash Boot)

Real-Time Clock

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the SHARC

processor. Connect RTC pins RTXI and RTXO with external

components as shown in Figure 3.

No Boot (Processor Executes from Internal

ROM After Reset)

100

1xx

Reserved

¹The BOOT_CFG2 pin is not available on the 100-lead or 88-lead packages.

The RTC peripheral has dedicated power supply pins so that it

can remain powered up and clocked even when the rest of the

processor is in a low power state. The RTC provides several pro-

grammable interrupt options, including interrupt per second,

minute, hour, or day clock ticks, interrupt on programmable

stopwatch countdown, or interrupt at a programmed alarm

time. An RTCLKOUT signal that operates at 1 Hz is also pro-

vided for calibration.

A running reset feature is used to reset the processor core and

peripherals without resetting the PLL and SDRAM controller,

or performing a boot. The functionality of the RESETOUT

/RUNRSTIN pin has now been extended to also act as the input

for initiating a running reset. For more information, see the

ADSP-214xx SHARC Processor Hardware Reference.

Power Supplies

The processors have separate power supply connections for the

internal (V_{DD_INT}) and external (V_{DD_EXT}) power supplies. The

internal and analog supplies must meet the V_{DD_INT}specifica-

tions. The external supply must meet the V_{DD_EXT}specification.

All external supply pins must be connected to the same power

supply.

RTXI

RTXO

R1

X1

C1

C2

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V_{DD_INT}and GND.

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the processors to mon-

itor and control the target board processor during emulation.

Analog Devices DSP Tools product line of JTAG emulators pro-

vides emulation at full processor speed, allowing inspection and

modification of memory, registers, and processor stacks. The

processor's JTAG interface ensures that the emulator will not

affect target system loading or timing.

Figure 3. External Components for RTC

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and a 32,768-day counter. When the alarm

interrupt is enabled, the alarm function generates an interrupt

when the output of the timer matches the programmed value in

the alarm control register. There are two alarms: The first alarm

is for a time of day. The second alarm is for a day and time of

that day.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate emulator hardware user’s guide.

DEVELOPMENT TOOLS

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch inter-

rupt is enabled and the counter underflows, an interrupt is

generated.

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore^®Embed-

ded Studio and/or VisualDSP++^®), evaluation products,

emulators, and a wide variety of software add-ins.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

Program Booting

The internal memory boots at system power-up from an 8-bit

EPROM via the external port, an SPI master, or an SPI slave.

Booting is determined by the boot configuration

(BOOT_CFG2–0) pins in Table 10.

The newest IDE, CrossCore Embedded Studio, is based on the

TM

Eclipse framework. Supporting most Analog Devices proces-

sor families, it is the IDE of choice for future processors,

including multicore devices. CrossCore Embedded Studio

Rev. C

|

Page 13 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

seamlessly integrates available software add-ins to support real

time operating systems, file systems, TCP/IP stacks, USB stacks,

algorithmic software modules, and evaluation hardware board

support packages. For more information visit

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

Middleware Packages

www.analog.com/cces.

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

• www.analog.com/ucos3

• www.analog.com/ucfs

• www.analog.com/ucusbd

• www.analog.com/lwip

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite^®evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders^®, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com

and search on “Blackfin software modules” or “SHARC software

modules”.

EZ-KIT Lite Evaluation Kits

Designing an Emulator-Compatible DSP Board (Target)

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

Board Support Packages for Evaluation Hardware

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

Rev. C

|

Page 14 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2147x

architecture and functionality. For detailed information on the

family core architecture and instruction set, refer to the SHARC

Processor Programming Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

TM

The Circuits from the Lab site (www.analog.com/signal

chains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Rev. C

|

Page 15 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

PIN FUNCTION DESCRIPTIONS

Table 11. Pin Descriptions

State During/

Name

Type

After Reset

Description

ADDR_23–0

I/O/T (ipu)

High-Z/driven External Address. The processor outputs addresses for external memory and

low (boot)

High-Z

peripherals on these pins. The ADDR pins can be multiplexed to support the

external memory interface address, FLAGS15–8 (I/O) and PWM (O). After reset, all

ADDR pins are in EMIF mode, and FLAG(0–3) pins are in FLAGS mode (default).

When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR_23–4

pins for parallel input data.

DATA_15–0

I/O/T (ipu)

I (ipu)

External Data. The data pins can be multiplexed to support the external memory

interface data (I/O) and FLAGS_7–0(I/O).

AMI_ACK

MemoryAcknowledge. ExternaldevicescandeassertAMI_ACK(low) toaddwait

states to an external memory access. AMI_ACK is used by I/O devices, memory

controllers, or other peripherals to hold off completion of an external memory

access.

MS_0–1

O/T (ipu)

High-Z

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the

corresponding banks of external memory. The MS_1-0lines are decoded memory

address lines that change at the same time as the other address lines. When no

external memory access is occurring the MS_1-0lines are inactive; they are active

however when a conditional memory access instruction is executed, when the

condition evaluates as true.

The MS1 pin can be used in EPORT/FLASH boot mode. For more information on

processor booting, see the ADSP-214xx SHARC Processor Hardware Reference.

AMI_RD

AMI_WR

O/T (ipu)

High-Z

AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word

from external memory.

AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to

external memory.

FLAG0/IRQ0

I/O (ipu)

FLAG[0] INPUT FLAG0/Interrupt Request0.

FLAG[1] INPUT FLAG1/Interrupt Request1.

FLAG1/IRQ1

FLAG2/IRQ2/MS2

FLAG[2] INPUT FLAG2/Interrupt Request2/Memory Select2. This pin is multiplexed with MS2

in the 196-ball BGA package only.

FLAG3/TMREXP/MS3 I/O (ipu)

FLAG[3] INPUT FLAG3/Timer Expired/Memory Select3. This pin is multiplexed with MS3 in the

196-ball BGA package only.

The following symbols appear in the Type column of Table 11: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The

range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the V_{DD_EXT}level; at typical conditions

the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on

Page 70.

Rev. C

|

Page 16 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 11. Pin Descriptions (Continued)

State During/

Name

Type

After Reset

Description

SDRAS

O/T (ipu)

High-Z/

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with

driven high

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS

O/T (ipu)

High-Z/

driven high

SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction

with other SDRAM command pins, defines the operation for the SDRAM to

perform.

SDWE

SDCKE

SDA10

O/T (ipu)

High-Z/

driven high

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

High-Z/

driven high

SDRAMClock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

High-Z/

driven high

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-

SDRAM accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM

accesses.

SDDQM

O/T (ipu)

High-Z/

driven high

DQM Data Mask. SDRAM input mask signal for write accesses and output enable

signal for read accesses. Input data is masked when DQM is sampled high during

a write cycle. The SDRAM output buffers are placed in a High-Z state when DQM

is sampled high during a read cycle. SDDQM is driven high from reset de-assertion

until SDRAM initialization completes. Afterwards, it is driven low irrespective of

whether any SDRAM accesses occur or not.

SDCLK

O/T (ipd)

High-Z/

driving

SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers.

See Figure 47 on Page 65. For models in the 100-lead package, the SDRAM

interface should be disabled to avoid unnecessary power switching by setting the

DSDCTL bit in SDCTL register. For more information, see the ADSP-214xx SHARC

Processor Hardware Reference.

DAI _P_20–1

I/O/T (ipu)

High-Z

Digital Applications Interface. These pins provide the physical interface to the

DAI SRU. The DAI SRU configuration registers define the combination of on-chip

audio-centric peripheral inputs or outputs connected to the pin and to the pin’s

output enable. The configuration registers of these peripherals then determines

the exact behavior of the pin. Any input or output signal present in the DAI SRU

may be routed to any of these pins.

DPI _P_14–1

I/O/T (ipu)

Digital Peripheral Interface. These pins provide the physical interface to the DPI

SRU. The DPI SRU configuration registers define the combination of on-chip

peripheral inputs or outputs connected to the pin and to the pin's output enable.

The configuration registers of these peripherals then determine the exact

behavior of the pin. Any input or output signal present in the DPI SRU may be

routed to any of these pins.

WDT_CLKIN

WDT_CLKO

WDTRSTO

I

Watch Dog Timer Clock Input. This pin should be pulled low when not used.

Watch Dog Resonator Pad Output.

O

O (ipu)

Watch Dog Timer Reset Out.

The following symbols appear in the Type column of Table 11: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The

range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the V_{DD_EXT}level; at typical conditions

the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on

Page 70.

Rev. C

|

Page 17 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 11. Pin Descriptions (Continued)

State During/

Name

Type

After Reset

Description

THD_P

THD_M

MLBCLK

I

Thermal Diode Anode. When not used, this pin can be left floating.

Thermal Diode Cathode. When not used, this pin can be left floating.

O

I

Media Local Bus Clock. This clock is generated by the MLB controller that is

synchronized to the MOST network and provides the timing for the entire MLB

interface at 49.152 MHz at FS = 48 kHz. When the MLB controller is not used, this

pin should be grounded.

MLBDAT

MLBSIG

I/O/T in 3 pin

mode.

I in 5 pin mode.

High-Z

Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device

and is received by all other MLB devices including the MLB controller. The

MLBDAT line carries the actual data. In 5-pin MLB mode, this pin is an input only.

When the MLB controller is not used, this pin should be grounded.

I/O/T in 3 pin

mode.

I in 5 pin mode

Media Local Bus Signal. This is a multiplexed signal which carries the

Channel/Address generated by the MLB Controller, as well as the Command and

RxStatus bytes from MLB devices. In 5-pin mode, this pin is input only. When the

MLB controller is not used, this pin should be grounded.

MLBDO

MLBSO

O/T

High-Z

Media Local Bus Data Output (in 5 Pin Mode). This pin is used only in 5-pin MLB

mode and serves as the output data pin. When the MLB controller is not used, this

pin should be grounded.

Media Local Bus Signal Output (in 5 Pin Mode). This pin is used only in 5-pin

MLB mode and serves as the output signal pin. When the MLB controller is not

used, this pin should be grounded.

SR_SCLK

SR_CLR

SR_SDI

I (ipu)

O (ipu)

I (ipu)

O/T (ipu)

I

Shift Register Serial Clock. (Active high, rising edge sensitive)

Shift Register Reset. (Active low)

Shift Register Serial Data Input.

SR_SDO

SR_LAT

SR_LDO_17–0

RTXI

Driven Low

High-Z

Shift Register Serial Data Output.

Shift Register Latch Clock Input. (Active high, rising edge sensitive)

Shift Register Parallel Data Output.

RTC Crystal Input. If RTC is not used, then this pin needs to be NC (no connect)

and the RTC_PDN and RTC_BUSDIS bits of RTC_INIT register must be set to 1.

RTXO

O

RTC Crystal Output. If RTC is not used, then this pin needs to be NC (No Connect).

RTCLKOUT

O (ipd)

RTC Clock Output. For calibration purposes. The clock runs at 1 Hz. If RTC is not

used, then this pin needs to be NC (No Connect).

The following symbols appear in the Type column of Table 11: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The

range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the V_{DD_EXT}level; at typical conditions

the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on

Page 70.

Rev. C

|

Page 18 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 11. Pin Descriptions (Continued)

State During/

Name

Type

I (ipu)

O/T

After Reset

Description

TDI

Test Data Input (JTAG). Provides serial data for the boundary scan logic.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Mode Select (JTAG). Used to control the test state machine.

TDO

TMS

TCK

High-Z

I (ipu)

I

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the device.

TRST

I (ipu)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed

low) after power-up or held low for proper operation of the processor.

EMU

O (O/D, ipu)

I

High-Z

Emulation Status. Must be connected to the Analog Devices DSP Tools product

line of JTAG emulators target board connector only.

CLK_CFG_1–0

Core to CLKIN Ratio Control. These pins set the startup clock frequency.

Note that the operating frequency can be changed by programming the PLL

multiplier and divider in the PMCTL register at any time after the core comes out

of reset. The allowed values are:

00 = 8:1

01 = 32:1

10 = 16:1

11 = reserved

CLKIN

I

Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It

configures the processors to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables

the internal clock generator. Connecting the external clock to CLKIN while leaving

XTAL unconnected configures the processors to use the external clock source

such as an external clock oscillator. CLKIN may not be halted, changed, or

operated below the specified frequency.

XTAL

O

I

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

RESET

Processor Reset. Resets the processor to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from thehardware resetvector address. The RESETinput must

be asserted (low) at power-up.

RESETOUT/RUNRSTIN I/O (ipu)

Reset Out/Running Reset In. The default setting on this pin is reset out. This pin

also has a second function as RUNRSTIN which is enabled by setting bit 0 of the

RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor

Hardware Reference.

BOOT_CFG_2–0

I

Boot Configuration Select. These pins select the boot mode for the processor.

The BOOT_CFG pins must be valid before RESET (hardware and software) is de-

asserted.

The BOOT_CFG2 pin is only available on the 196-lead package.

The following symbols appear in the Type column of Table 11: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The

range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the V_{DD_EXT}level; at typical conditions

the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on

Page 70.

Rev. C

|

Page 19 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 12. Pin List, Power and Ground

Name

V_{DD_INT}

V_{DD_EXT}

V_{DD_RTC}

GND¹

Type

Description

P

G

P

Internal Power Supply.

I/O Power Supply.

Real-Time Clock Power Supply. When RTC is not used, this pin should be connected to V_{DD_EXT}

.

Ground.

V_{DD_THD}

Thermal Diode Power Supply. When not used, this pin can be left floating.

¹The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the

exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. See also 88-LFCSP_VQ Lead

Assignment on Page 68 and 100-LQFP_EP Lead Assignment on Page 70.

Rev. C

|

Page 20 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

SPECIFICATIONS

OPERATING CONDITIONS

200 MHz

266 MHz

300 MHz

Parameter¹

Description

Min Nom Max Min Nom Max

Min Nom Max

Unit

V_{DD_INT}

V_{DD_EXT}

V_{DD_THD}

V_{DD_RTC}

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

Thermal Diode Supply Voltage

1.14 1.2

3.13 3.3

1.26

3.47

3.6

1.14 1.2

3.13 3.3

2.0 3.0

2.0

1.26

3.47

3.6

1.25 1.3

3.13 3.3

1.35

3.47

3.6

V

°C

Real-Time Clock Power Supply Voltage

High Level Input Voltage @ V_{DD_EXT}= Max

Low Level Input Voltage @ V_{DD_EXT}= Min

High Level Input Voltage @ V_{DD_EXT}= Max

Low Level Input Voltage @ V_{DD_EXT}= Max

Junction Temperature 88-Lead LFCSP_VQ @

T_AMBIENT0C to +70C

Junction Temperature 88-Lead LFCSP_VQ @

T_AMBIENT–40C to +85C

Junction Temperature 88-Lead LFCSP_VQ @

T_AMBIENT–40C to +105C

Junction Temperature 100-Lead LQFP_EP @

T_AMBIENT0°C to +70°C

Junction Temperature 100-Lead LQFP_EP @

T_AMBIENT–40°C to +85°C

Junction Temperature 100-Lead LQFP_EP @

T_AMBIENT–40°C to +105°C

Junction Temperature 196-Ball CSP_BGA @

T_AMBIENT0°C to +70°C

2.0

3.0

2.0

3.0

2

V_IH

3

V_IL

0.8

V_{DD_EXT}2.2

+0.8 –0.3

105

0.8

V_{DD_EXT}2.2

+0.8

N/A

0.8

3

V_{IH_CLKIN}

V_{IL_CLKIN}

T_J

2.2

–0.3

0

V_{DD_EXT}

+0.8

N/A

–0.3

N/A

T_J

–40

0

+115 N/A

+125 N/A

N/A

105

N/A

100

N/A

°C

T_J⁴

T_J

105

N/A

0

T_J⁴

T_J⁵

N/A

–40

N/A

–40

+125 N/A

+125 –40

N/A

0

105

0

Junction Temperature 196-Ball CSP_BGA @

T_AMBIENT–40°C to +85°C

–40

+125 N/A

¹Specifications subject to change without notice.

²Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, SDA10,

AMI_ACK, MLBCLK, MLBDAT, MLBSIG.

³Applies to input pin CLKIN, WDT_CLKIN.

⁴Applies to automotive models only. See Automotive Products on Page 75.

⁵Real Time Clock (RTC) is supported only for products with a temperature range of 0°C to +70°C and not supported for all other temperature grades. For the status of unused RTC

pins please see Table 11 on Page 16.

Rev. C

|

Page 21 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

ELECTRICAL CHARACTERISTICS

200 MHz

266 MHz

Max

300 MHz

Max

Parameter¹Description

Test Conditions

Min

Max

Min

Unit

2

V_OH

High Level Output Voltage @ V_{DD_EXT}= Min,

I_OH= –1.0 mA³

Low Level Output Voltage @ V_{DD_EXT}= Min,

I_OL= 1.0 mA³

2.4

V

2

V_OL

0.4

10

0.4

10

0.4

10

V

4, 5

I_IH

High Level Input Current

@ V_{DD_EXT}= Max,

ꢀA

V_IN= V_{DD_EXT}Max

@ V_{DD_EXT}= Max, V_IN= 0 V

4

I_IL

Low Level Input Current

Pull-up

Three-State Leakage

Current

–10

200

–10

200

–10

200

ꢀA

5

I_ILPU

6, 7

I_OZH

@ V_{DD_EXT}= Max,

V_IN= V_{DD_EXT}Max

@ V_{DD_EXT}= Max, V_IN= 0 V

10

ꢀA

6

I_OZL

Three-State Leakage

Current

–10

200

0.76

–10

200

0.76

–10

200

0.76

7

I_OZLPU

Three-State Leakage

Current Pull-up

Three-State Leakage

Current Pull-down

V_{DD_RTC}Current

@ V_{DD_EXT}= Max, V_IN= 0 V

8

I_OZHPD

I_{DD_RTC}

@ V_{DD_EXT}= Max,

V_IN= V_{DD_EXT}Max

@ V_{DD_RTC}= 3.0,

T_J= 25°C

9

I_{DD_INT}

Supply Current (Internal)

f_CCLK> 0 MHz

Table 14

+

Table 14

+

Table 14 mA

+

Table 15

× ASF

5

Table 15

× ASF

5

Table 15

× ASF

5

10, 11

C_IN

Input Capacitance

T_CASE= 25°C

pF

¹Specifications subject to change without notice.

²Applies to output and bidirectional pins: ADDR23-0, DATA15-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT,MLBSIG, MLBDAT, MLBDO,

MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1.

³See Output Drive Currents on Page 65 for typical drive current capabilities.

⁴Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

⁵Applies to input pins with internal pull-ups: TRST, TMS, TDI.

⁶Applies to three-statable pins: TDO, MLBDAT, MLBSIG, MLBDO, and MLBSO.

⁷Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

⁸Applies to three-statable pin with pull-down: SDCLK.

⁹See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-214xx SHARC Processors” for further information.

¹⁰Applies to all signal pins.

¹¹Guaranteed, but not tested.

Rev. C

|

Page 22 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Total Power Dissipation

The information in this section should be augmented with

Table 13. Activity Scaling Factors (ASF)¹

Estimating Power for ADSP-214xx SHARC Processors (EE-348).

Activity

Scaling Factor (ASF)

Total power dissipation has two components:

Idle

0.31

0.53

0.62

0.78

0.85

0.93

1.00

1.18

1.28

1.34

1. Internal power consumption is additionally comprised of

two components:

Low

Medium Low

Medium High

Peak-Typical (50:50)²

Peak-Typical (60:40)²

Peak-Typical (70:30)²

High Typical

High

• Static current due to leakage. Table 14 shows the static

current consumption (I_{DD_INT_STATIC}) as a function of

junction temperature (T_J) and core voltage (V_{DD_INT}).

• Dynamic current (I_{DD_INT_DYNAMIC}), due to transistor

switching characteristics and activity level of the pro-

cessor. The activity level is reflected by the Activity

Scaling Factor (ASF), which represents the activity

level of the application code running on the processor

core and having various levels of peripheral and exter-

nal port activity (Table 13). Dynamic current

consumption is calculated by selecting the ASF that

corresponds most closely with the user application

and then multiplying that with the dynamic current

consumption (Table 15).

Peak

¹See Estimating Power for ADSP-214xx SHARC Processors (EE-348) for more

information on the explanation of the power vectors specific to the ASF table.

²Ratio of continuous instruction loop (core) to SDRAM control code reads and

writes.

2. External power consumption is due to the switching activ-

ity of the external pins.

Table 14. Static Current—I_{DD_INT_STATIC}(mA)¹

Voltage (V_{DD_INT}

)

T_J(°C)

–45

1.05 V

< 0.1

0.2

1.10 V

< 0.1

0.2

1.15 V

0.4

1.20 V

0.8

1.25 V

1.3

1.30 V

2.1

1.35 V

3.3

–35

0.4

0.7

1.1

1.7

2.9

–25

0.4

0.8

1.2

1.7

2.9

–15

0.4

0.6

1.0

1.4

1.9

3.2

–5

0.6

0.9

1.3

1.8

2.3

3.7

+5

0.5

0.9

1.3

1.8

2.3

3.0

4.4

+15

+25

+35

+45

+55

+65

+75

+85

+95

+100

+105

+115

+125

0.8

1.4

1.8

2.3

3.0

3.7

5.1

1.3

1.9

2.5

3.1

3.9

4.7

6.2

2.0

2.8

3.4

4.2

5.1

6.0

8.0

3.0

3.9

4.7

5.7

6.7

7.8

10.1

12.9

16.4

21.2

27.1

34.6

39.2

N/A

4.3

5.4

6.3

7.6

8.8

10.3

13.5

17.4

22.6

29.4

33.0

N/A

6.0

7.3

8.6

10.1

13.3

17.5

22.9

25.9

29.5

38.2

48.8

11.7

15.3

19.9

26.1

29.4

33.4

42.9

54.8

8.3

9.9

11.5

15.3

20.1

22.9

26.1

33.9

43.6

11.2

15.2

17.4

20.0

26.3

34.4

13.2

17.6

20.2

23.0

30.0

38.9

¹Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 21.

Rev. C

|

Page 23 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 15. Dynamic Current in CCLK Domain—I_{DD_INT_DYNAMIC}(mA, with ASF = 1.0)^{1, 2}

Voltage (V_{DD_INT}

)

f_CCLK(MHz)

100

1.05 V

75

1.10 V

78

1.15 V

82

1.20 V

86

1.25 V

90

1.30 V

95

1.35 V

98

150

111

N/A

117

122

162

215

N/A

128

170

225

N/A

134

178

234

264

141

186

246

279

146

194

256

291

200

N/A

266

300

¹The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 22.

²Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 21.

MAXIMUM POWER DISSIPATION

ESD SENSITIVITY

See Engineer-to-Engineer Note “Estimating Power Dissipation

for ADSP-2147x SHARC Processors” for detailed thermal and

power information regarding maximum power dissipation. For

information on package thermal specifications, see Thermal

Characteristics on Page 66.

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

PACKAGE INFORMATION

The information presented in Figure 4 provides details about

the package branding. For a complete listing of product avail-

ability, see Ordering Guide on Page 76.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 17 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in Operating Conditions on

Page 21 is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

a

ADSP-2147x

tppZ-cc

vvvvvv.x n.n

Table 17. Absolute Maximum Ratings

#yyww country_of_origin

Parameter

Rating

S

Internal (Core) Supply Voltage (V_{DD_INT}

)

–0.3 V to +1.35 V

–0.3 V to +4.6 V

–0.5 V to +3.8 V

–0.5 V to V_{DD_EXT}+0.5 V

–65°C to +150°C

125°C

External (I/O) Supply Voltage (V_{DD_EXT}

Real Time Clock Voltage (V_{DD_RTC}

)

Figure 4. Typical Package Brand

)

Table 16. Package Brand Information¹

Thermal Diode Supply Voltage (V_{DD_THD}

)

Input Voltage

Brand Key

Field Description

Temperature Range

Package Type

Output Voltage Swing

t

Storage Temperature Range

Junction Temperature While Biased

pp

Z

RoHS Compliant Option

See Ordering Guide

Assembly Lot Code

Silicon Revision

cc

vvvvvv.x

n.n

#

RoHS Compliant Designation

Date Code

yyww

¹Nonautomotiveonly. For brandinginformationspecific to automotiveproducts,

contact Analog Devices Inc.

Rev. C

|

Page 24 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

f

_INPUTis the input frequency to the PLL.

TIMING SPECIFICATIONS

f

_INPUT= CLKIN when the input divider is disabled, or

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 49 on Page 65 under Test Conditions for voltage refer-

ence levels.

CLKIN ÷ 2 when the input divider is enabled.

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in Table 20. All

of the timing specifications for the peripherals are defined in

relation to t_PCLK. See the peripheral specific section for each

peripheral’s timing information.

Table 18. Clock Periods

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing

Requirements

Description

t_CK

CLKIN Clock Period

t_CCLK

t_PCLK

t_SDCLK

Processor Core Clock Period

Peripheral Clock Period = 2 × t_CCLK

SDRAM Clock Period = (t_CCLK) × SDCKR

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Figure 5 shows core to CLKIN relationships with an external

oscillator or crystal. The shaded divider/multiplier blocks

denote where clock ratios can be set through hardware or soft-

ware using the power management control register (PMCTL).

For more information, see the ADSP-214xx SHARC Processor

Hardware Reference.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 5). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Voltage Controlled Oscillator (VCO)

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

f

_VCOspecified in Table 20.

• The product of CLKIN and PLLM must never exceed 1/2 of

f_VCO(max) in Table 20 if the input divider is not enabled

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed f_VCO

(max) in Table 20 if the input divider is enabled

(INDIV = 1).

The VCO frequency is calculated as follows:

f_VCO= 2 × PLLM × f_INPUT

f_CCLK= (2 × PLLM × f_INPUT) ÷ PLLD

where:

_VCO= VCO output

f

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

PLLD = 2, 4, 8, or 16 based on the divider value programmed on

the PMCTL register. During reset this value is 2.

Rev. C

|

Page 25 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

PMCTL

(SDCKR)

PMCTL

(PLLBP)

PLL

f

CCLK

f_VCO

INPUT

SDRAM

DIVIDER

CLKIN

DIVIDER

LOOP

FILTER

PLL

DIVIDER

VCO

f_CCLK

SDCLK

XTAL

BUF

CLK_CFGx/

PMCTL (2 × PLLM)

PMCTL

(PLLD)

PMCTL

(INDIV)

PCLK

DIVIDE

BY 2

PMCTL

(PLLBP)

f_VCO÷ (2 × PLLM)

PCLK

CCLK

CLKOUT (TEST ONLY)*

DELAY OF

4096 CLKIN

CYCLES

BUF

RESETOUT

CORESRST

RESETOUT

RESET

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f_INPUT.

THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

Figure 5. Core Clock and System Clock Relationship to CLKIN

Rev. C

|

Page 26 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

• If the V_{DD_INT}power supply comes up after V_{DD_EXT}, any

pin, such as RESETOUT and RESET, may actually drive

momentarily until the V_{DD_INT}rail has powered up. Systems

sharing these signals on the board must determine if there

are any issues that need to be addressed based on this

behavior.

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 19. While no specific power-up sequencing is required

between V_{DD_EXT}and V_{DD_INT}, there are some considerations

that the system designs should take into account.

• No power supply should be powered up for an extended

period of time (>200 ms) before another supply starts to

ramp up.

Note that during power-up, when the V_{DD_INT}power supply

comes up after V_{DD_EXT}, a leakage current of the order of three-

state leakage current pull-up, pull-down, may be observed on

any pin, even if that is an input only (for example, the RESET

pin), until the V_{DD_INT}rail has powered up.

Table 19. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_{DD_EXT}or V_{DD_INT}On

V_{DD_INT}On Before V_{DD_EXT}

0

ms

ꢀs

t_IVDDEVDD

–200

0

10²

20³

+200

200

1

t_CLKVDD

CLKIN Valid After V_{DD_INT}and V_{DD_EXT}Valid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

t_CLKRST

t_PLLRST

ꢀs

Switching Characteristic

4, 5

t_CORERST

Core Reset Deasserted After RESET Deasserted

4096 × t_CK+ 2 × t_CCLK

¹Valid V_{DD_INT}and V_{DD_EXT}assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary

from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles.

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4096 cycle count depends on t_SRSTspecification in Table 21. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

t_RSTVDD

RESET

V

DDINT

t_IVDDEVDD

V

DDEXT

t_CLKVDD

CLKIN

t_CLKRST

CLK_CFG1–0

RESETOUT

t_PLLRST

t_CORERST

Figure 6. Power-Up Sequencing

Rev. C

|

Page 27 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Clock Input

Table 20. Clock Input

200 MHz

266 MHz

Max

300 MHz

Max

Unit

Parameter

Min

Max

Min

Timing Requirements

t_CK

CLKIN Period

40

20

100

45

30¹

15

100

45

26.66¹

13.33

100

45

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low

ns

CLKIN Width High

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK Period

45

15

45

ns

3

ns

2

5

10

3.75

200

10

3.33

200

10

ns

3

f_VCO

VCO Frequency

200

600

+250

600

+250

MHz

ps

4, 5

t_CKJ

CLKIN Jitter Tolerance

–250

+250

–250

¹Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

²Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_cclk

³See Figure 5 on Page 26 for VCO diagram.

.

⁴Actual input jitter should be combined with ac specifications for accurate timing analysis.

⁵Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

t_CKJ

t_CK

CLKIN

t_CKH

t_CKL

Figure 7. Clock Input

Rev. C

|

Page 28 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

mental mode. Note that the clock rate is achieved using a

16.67 MHz crystal and a PLL multiplier ratio 16:1

Clock Signals

The processors can use an external clock or a crystal. See the

(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve

CLKIN pin description in Table 11. Programs can configure the

processor to use its internal clock generator by connecting the

necessary components to CLKIN and XTAL. Figure 8 shows the

component connections used for a crystal operating in funda-

the full core clock rate, programs need to configure the multi-

plier bits in the PMCTL register.

ADSP-2147x

R1

1MΩ *

XTAL

R2

CLKIN

CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1.

CHOOSE R2 TO LIMIT CRYSTAL DRIVE POWER.

REFER TO CRYSTAL MANUFACTURER'S SPECIFICATIONS

47Ω *

C1

22pF

C2

22pF

Y1

16.67

*TYPICAL VALUES

Figure 8. 266 MHz Operation (Fundamental Mode Crystal)

Reset

Table 21. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

t_SRST

RESET Pulse Width Low

RESET Setup Before CLKIN Low

4 × t_CK

ns

8

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable

V_DDand CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_WRST

t_SRST

RESET

Figure 9. Reset

Rev. C

|

Page 29 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Running Reset

The following timing specification applies to RESETOUT/

RUNRSTIN pin when it is configured as RUNRSTIN.

Table 22. Running Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRUNRST

t_SRUNRST

Running RESET Pulse Width Low

4 × t_CK

8

ns

Running RESET Setup Before CLKIN High

CLKIN

t_WRUNRST

t_SRUNRST

RUNRSTIN

Figure 10. Running Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts, as well as the DAI_P20–1 and

DPI_P14–1 pins when they are configured as interrupts.

Table 23. Interrupts

Parameter

Min

2 × t_PCLK+ 2

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

ns

INTERRUPT

INPUTS

t_IPW

Figure 11. Interrupts

Rev. C

|

Page 30 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP).

Table 24. Core Timer

88-Lead LFCSP Package

Max

All Other Packages

Max

Unit

Parameter

Min

Switching Characteristic

t_WCTIM

TMREXP Pulse Width

4 × t_PCLK– 1.55

4 × t_PCLK– 1.2

ns

t_WCTIM

FLAG3

(TMREXP)

Figure 12. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to timer0 and timer1

in PWM_OUT (pulse-width modulation) mode. Timer signals

are routed to the DPI_P14–1 pins through the DPI SRU. There-

fore, the timing specifications provided below are valid at the

DPI_P14–1 pins.

Table 25. Timer PWM_OUT Timing

88-Lead LFCSP Package

All Other Packages

Unit

ns

Parameter

Min

Max

Min

Max

Switching Characteristic

t_PWMO

Timer Pulse Width Output

2 × t_PCLK– 1.65

2 × (2³¹– 1) × t_PCLK

2 × t_PCLK– 1.2

2 × (2³¹– 1) × t_PCLK

t_PWMO

PWM

OUTPUTS

Figure 13. Timer PWM_OUT Timing

Rev. C

|

Page 31 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Timer WDTH_CAP Timing

The following timing specification applies to timer0 and timer1,

and in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the timing specification provided below is valid

at the DPI_P14–1 pins.

Table 26. Timer Width Capture Timing

Parameter

Min

Max

Unit

Timing Requirement

t_PWI

Timer Pulse Width

2 × t_PCLK

2 × (2³¹– 1) × t_PCLK

ns

t_PWI

TIMER

CAPTURE

INPUTS

Figure 14. Timer Width Capture Timing

Watchdog Timer Timing

Table 27. Watchdog Timer Timing

Parameter

Min

Max

1000

7.6

Unit

Timing Requirement

t_WDTCLKPER

100

ns

Switching Characteristics

t_RST

WDT Clock Rising Edge to Watchdog Timer

RESET Falling Edge

3

ns

1

t_RSTPW

Reset Pulse Width

64 × t_WDTCLKPER

¹When the internal oscillator is used, the 1/t_WDTCLKPERvaries from 1.5 MHz to 2.5 MHz and the WDT_CLKIN pin should be pulled low.

t_WDTCLKPER

WDT_CLKIN

t_RST

t_RSTPW

WDTRSTO

Figure 15. Watchdog Timer Timing

Rev. C

|

Page 32 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 28. DAI/DPI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid

1.5

10

ns

DAI_Pn

DPI_Pn

t_DPIO

DAI_Pm

DPI_Pm

Figure 16. DAI Pin to Pin Direct Routing

Rev. C

|

Page 33 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

inputs and outputs are not directly routed to/from DAI pins (via

Precision Clock Generator (Direct Pin Routing)

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 29. Precision Clock Generator (Direct Pin Routing)

88-Lead LFCSP Package

All Other Packages

Max

Unit

Parameter

Min

Max

Min

Timing Requirements

t_PCGIP

t_STRIG

Input Clock Period

t_PCLK× 4

4.5

t_PCLK× 4

4.5

ns

PCG Trigger Setup Before

Falling Edge of PCGInput Clock

t_HTRIG

PCG Trigger Hold After Falling 3

Edge of PCG Input Clock

3

ns

Switching Characteristics

t_DPCGIOPCG Output Clock and Frame

2 × t_PCLK

12.5

Sync Active Edge Delay After 2.5

PCG Input Clock

2.5

ns

t_DTRIGCLKPCG Output Clock Delay After 2.5 + (2.5 × t_PCGIP

PCG Trigger

)

2 × t_PCLK+ (2.5 × t_PCGIP) 2.5 + (2.5 × t_PCGIP

)

12.5 + (2.5 × t_PCGIP)

t_DTRIGFSPCG Frame Sync Delay After 2.5 + ((2.5 + D – PH) × 2 × t_PCLK+ ((2.5 + D – 2.5 + ((2.5 + D – PH) × 12.5 + ((2.5 + D – PH) ns

PCG Trigger

t_PCGIP

)

PH) × t_PCGIP

)

t_PCGIP

)

× t_PCGIP)

1

t_PCGOW

Output Clock Period

2 × t_PCGIP– 1

ns

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators”

chapter.

¹Normal mode of operation.

t_STRIG

t_HTRIG

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

t_PCGIP

DAI_Py

DPI_Py

PCK_CLKx_O

t_DTRIGCLK

t_PCGOW

t_DPCGIO

DAI_Pz

DPI_Pz

PCG_FSx_O

t_DTRIGFS

Figure 17. Precision Clock Generator (Direct Pin Routing)

Rev. C

|

Page 34 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Flags

The timing specifications provided below apply to ADDR23–0

and DATA7–0 when configured as FLAGS. See Table 11 on

Page 16 for more information on flag use.

Table 30. Flags

Parameter

Min

Max

Unit

ns

Timing Requirement

t_FIPW

Switching Characteristic

FLAGs IN Pulse Width¹

2 × t_PCLK+ 3

2 × t_PCLK– 3.5

t_FOPW

FLAGs OUT Pulse Width¹

ns

¹This is applicable when the Flags are connected to DPI_P14–1, ADDR23–0, DATA7–0 and FLAG3–0 pins.

FLAG

INPUTS

t_FIPW

FLAG

OUTPUTS

t_FOPW

Figure 18. Flags

Rev. C

|

Page 35 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

SDRAM Interface Timing

Table 31. SDRAM Interface Timing

133 MHz

150 MHz

Max

Parameter

Min

Max

Min

Unit

Timing Requirements

t_SSDAT

t_HSDAT

DATA Setup Before SDCLK

DATA Hold After SDCLK

0.7

1.5

ns

1.66

Switching Characteristics

1

t_SDCLK

SDCLK Period

7.5

2.5

6.66

2.2

ns

t_SDCLKH

SDCLK Width High

t_SDCLKL

SDCLK Width Low

2.2

2

t_DCAD

Command, ADDR, Data Delay After SDCLK

Command, ADDR, Data Hold After SDCLK

Data Disable After SDCLK

Data Enable After SDCLK

5

4.75

5.3

2

t_HCAD

1

t_DSDAT

6.2

t_ENSDAT

0.3

¹Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 133 MHz the

SDRAM model with a speed grade of 143 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM memory to SHARC processors (EE-286)” for

more information on hardware design guidelines for the SDRAM interface.

²Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDQM, SDCKE.

t_SDCLKH

t_SDCLK

SDCLK

t_SSDAT

t_HSDAT

t_SDCLKL

DATA (IN)

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

DATA (OUT)

t_DCAD

t_HCAD

COMMAND/ADDR

(OUT)

Figure 19. SDRAM Interface Timing

Rev. C

|

Page 36 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

AMI Read

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 32. AMI Read

Parameter

Min

Max

Unit

Timing Requirements

1, 2, 3

t_DAD

Address Selects Delay to Data Valid

AMI_RD Low to Data Valid

W + t_SDCLK– 6.32

W – 3

ns

1, 3

t_DRLD

4, 5

t_SDS

t_HDRH

Data Setup to AMI_RD High

2.6

0.4

Data Hold from AMI_RD High

AMI_ACK Delay from Address Selects

AMI_ACK Delay from AMI_RD Low

2, 6

t_DAAK

t_SDCLK– 10 + W

W – 7.0

4

t_DSAK

Switching Characteristics

t_DRHAAddress Selects Hold After AMI_RD High

RHC + 0.38

t_SDCLK– 5

ns

2

t_DARL

t_RW

Address Selects to AMI_RD Low

AMI_RD Pulse Width

W – 1.4

t_RWR

AMI_RD High to AMI_RD Low

HI + t_SDCLK– 1.2

W = (number of wait states specified in AMICTLx register) × t_SDCLK

.

RHC = (number of Read Hold Cycles specified in AMICTLx register) × t_SDCLK

Where PREDIS = 0

HI = RHC: Read to Read from same bank

HI = RHC + IC: Read to Read from different bank

HI = RHC + Max (IC, (4 × t_SDCLK)) : Read to Write from same or different bank

Where PREDIS = 1

HI = RHC + Max (IC, (4 × t_SDCLK)) : Read to Write from same or different bank

HI = RHC + (3 × t_SDCLK): Read to Read from same bank

HI = RHC + Max (IC, (3 × t_SDCLK)) : Read to Read from different bank

IC = (number of idle cycles specified in AMICTLx register) × t_SDCLK

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

.

¹Data delay/setup: System must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of AMI_MSx, is referenced.

³The maximum limit of timing requirement values for t_DADand t_DRLDparameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not used.

⁴Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.

⁵Data hold: User must meet t_HDRHin asynchronous access mode. See Test Conditions on Page 65 for the calculation of hold times given capacitive and dc loads.

⁶AMI_ACK delay/setup: User must meet t_daak, or t_dsak, for deassertion of AMI_ACK (low).

Rev. C

|

Page 37 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

ADDR

MSx

t_DARL

t_RW

t_DRHA

RD

t_DRLD

t_SDS

t_DAD

t_HDRH

DATA

t_DSAK

t_RWR

t_DAAK

ACK

WR

Figure 20. AMI Read

Rev. C

|

Page 38 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

AMI Write

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 33. AMI Write

Parameter

Min

Max

Unit

Timing Requirements

t_DAAK

t_DSAK

AMI_ACK Delay from Address Selects^{1, 2}

AMI_ACK Delay from AMI_WR Low^{1, 3}

t_SDCLK– 10.1 + W

W – 7.1

ns

Switching Characteristics

t_DAWH

t_DAWL

t_WW

Address Selects to AMI_WR Deasserted²

Address Selects to AMI_WR Low²

t_SDCLK– 4.4 + W

t_SDCLK– 4.5

W – 1.3

ns

AMI_WR Pulse Width

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

t_WWR

Data Setup Before AMI_WR High

Address Hold After AMI_WR Deasserted

Data Hold After AMI_WR Deasserted

Data Disable After AMI_WR Deasserted⁴

AMI_WR High to AMI_WR Low⁵

Data Disable Before AMI_RD Low

AMI_WR Low to Data Enabled

t_SDCLK– 4.3 + W

H

t_SDCLK– 1.37 + H

t_SDCLK– 1.5+ H

2 × t_SDCLK– 7.1

t_SDCLK– 4.5

t_SDCLK+ 6.75+ H

t_DDWR

t_WDE

W = (number of wait states specified in AMICTLx register) × t_SDCLK

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

¹AMI_ACK delay/setup: System must meet t_DAAK, or t_DSAK, for deassertion of AMI_ACK (low).

²The falling edge of AMI_MSx is referenced.

³Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.

⁴See Test Conditions on Page 65 for calculation of hold times given capacitive and dc loads.

⁵For Write to Write: t_SDCLK+ H, for both same bank and different bank. For Write to Read: 3 × t_SDCLK+ H, for the same bank and different banks.

Rev. C

|

Page 39 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

ADDR

MSx

t_DAWH

t_DWHA

t_DAWL

t_WW

WR

t_WWR

t_WDE

t_DATRWH

t_DDWH

t_DDWR

DATA

t_DSAK

t_DWHD

t_DAAK

ACK

RD

Figure 21. AMI Write

Rev. C

|

Page 40 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Serial Ports

In slave transmitter mode and master receiver mode, the maxi-

mum serial port frequency is f_PCLK/8. In master transmitter

mode and slave receiver mode, the maximum serial port clock

frequency is f_PCLK/4.

Serial port signals (SCLK, FS, Data Channel A, Data Channel B)

are routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

To determine whether communication is possible between two

devices at clock speed, n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Table 34. Serial Ports—External Clock

88-Lead LFCSP Package

All Other Packages

Max

Unit

Parameter

Min

Max

Min

Timing Requirements

1

t_SFSE

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in Either Transmit or

Receive Mode)

4

2.5

ns

1

t_HFSE

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in Either Transmit or

Receive Mode)

1

t_SDRE

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

4

2.5

ns

1

t_HDRE

4

t_SCLKWSCLK Width

t_SCLKSCLK Period

(t_PCLK× 4) ÷ 2 – 1.5

t_PCLK× 4

(t_PCLK× 4) ÷ 2 – 1.5

t_PCLK× 4

Switching Characteristics

2

t_DFSE

Frame Sync Delay After SCLK

(Internally Generated Frame Sync in Either Transmit or

Receive Mode)

15

ns

2

t_HOFSEFrame Sync Hold After SCLK

(Internally Generated Frame Sync in Either Transmit or

Receive Mode)

2

t_DDTE

Transmit Data Delay After Transmit SCLK

ns

2

t_HDTE

Transmit Data Hold After Transmit SCLK

¹Referenced to sample edge.

²Referenced to drive edge.

Rev. C

|

Page 41 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 35. Serial Ports—Internal Clock

88-Lead LFCSP Package

All Other Packages

Max

Unit

Parameter

Min

Max

Min

Timing Requirements

1

t_SFSI

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in Either Transmit 13

10.5

2.5

ns

or Receive Mode)

1

t_HFSI

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in Either Transmit 2.5

or Receive Mode)

1

t_SDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

13

10.5

2.5

ns

1

t_HDRI

2.5

Switching Characteristics

2

t_DFSI

Frame Sync Delay After SCLK (Internally Generated

Frame Sync in Transmit Mode)

5

ns

2

t_HOFSIFrame Sync Hold After SCLK (Internally Generated –1.0

–1.0

Frame Sync in Transmit Mode)

2

t_DFSIR

Frame Sync Delay After SCLK (Internally Generated

Frame Sync in Receive Mode)

10.7

2

t_HOFSIRFrame Sync Hold After SCLK (Internally Generated –1.0

–1.0

Frame Sync in Receive Mode)

2

t_DDTI

Transmit Data Delay After SCLK

Transmit Data Hold After SCLK

4

ns

2

t_HDTI

–1.0

t_SCKLIWTransmit or Receive SCLK Width

2 × t_PCLK– 1.5

2 × t_PCLK+ 1.5 2 × t_PCLK– 1.5

2 × t_PCLK+ 1.5 ns

¹Referenced to the sample edge.

²Referenced to drive edge.

Rev. C

|

Page 42 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSIR

t_DFSE

t_HOFSIR

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_SDRI

t_HDRI

t_SDRE

t_HDRE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 22. Serial Ports

Rev. C

|

Page 43 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 36. Serial Ports—External Late Frame Sync

88-Lead LFCSP Package

All Other Packages

Unit

Parameter

Min

Max

Min

Max

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit Frame Sync or

2 × t_PCLK

13.5

External Receive Frame Sync with MCE = 1, MFD = 0

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

SAMPLE DRIVE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

Figure 23. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified mode.

Rev. C

|

Page 44 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 37. Serial Ports—Enable and Three-State

88-Lead LFCSP Package

All Other Packages

Max

Unit

Parameter

Min

Max

Min

2

Switching Characteristics

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

2

ns

1

t_DDTTE

23

20

1

t_DDTIN

–1

¹Referenced to drive edge.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

t_DDTEN

t_DDTTE

DAI_P20–1

(DATA

CHANNEL A/B)

DRIVE EDGE

DAI_P20–1

(SCLK, INT)

t_DDTIN

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 24. Enable and Three-State

Rev. C

|

Page 45 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

The SPORTx_TDV_O output signal (routing unit) becomes

active in SPORT multichannel/packed mode. During transmit

slots (enabled with active channel selection registers), the

SPORTx_TDV_O is asserted for communication with external

devices.

Table 38. Serial Ports—TDV (Transmit Data Valid)

88-Lead LFCSP Package

All Other Packages

Unit

Parameter

Min

Max

Min

Max

Switching Characteristics¹

t_DRDVEN

t_DFDVEN

t_DRDVIN

t_DFDVIN

TDV Assertion Delay from Drive Edge of External Clock

3

ns

TDV Deassertion Delay from Drive Edge of External Clock

TDV Assertion Delay from Drive Edge of Internal Clock

TDV Deassertion Delay from Drive Edge of Internal Clock

2 × t_PCLK

3.5

13.25

3.5

–0.1

¹Referenced to drive edge.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

TDVx

DAI_P20-1

t_DFDVEN

t_DRDVEN

DRIVE EDGE

DAI_P20–1

(SCLK, INT)

TDVx

DAI_P20-1

t_DFDVIN

t_DRDVIN

Figure 25. Serial Ports—TDV Internal and External Clock

Rev. C

|

Page 46 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 39. IDP

signals are routed to the DAI_P20–1 pins using the SRU. There-

fore, the timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 39. Input Data Port (IDP)

88-Lead LFCSP Package

Min Max

All Other Packages

Max

Unit

Parameter

Min

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge 4.5

3.8

2.5

ns

1

t_SIHFS

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Clock Width

3

1

t_SISD

4

1

t_SIHD

t_IDPCLKW

t_IDPCLK

3

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The PCG’s input

can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IPDCLK

t_IPDCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 26. IDP Master Timing

Rev. C

|

Page 47 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

PDAP chapter of the ADSP-214xx SHARC Processor Hardware

Parallel Data Acquisition Port (PDAP)

Reference. Note that the 20 bits of external PDAP data can be

The timing requirements for the PDAP are provided in

Table 40. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the PDAP, see the

provided through the ADDR23–0 pins or over the DAI pins.

Table 40. Parallel Data Acquisition Port (PDAP)

88-Lead LFCSP Package

All Other Packages

Min Max

Unit

Parameter

Min

Max

Timing Requirements

1

t_SPHOLD

PDAP_HOLD Setup Before PDAP_CLK Sample Edge

PDAP_HOLD Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

Clock Width

4

2.5

ns

1

t_HPHOLD

4

2.5

1

t_PDSD

5

3.85

1

t_PDHD

4

2.5

t_PDCLKW

t_PDCLK

(t_PCLK× 4) ÷ 2 – 3

t_PCLK× 4

(t_PCLK× 4) ÷ 2 – 3

t_PCLK× 4

Clock Period

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK

2 × t_PCLK+ 3

ns

Capture Edge for a Word

PDAP Strobe Pulse Width

t_PDSTRB

2 × t_PCLK– 1.5

1

Source pins of DATA and control are ADDR23–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20–1

(PDAP_CLK)

t_HPHOLD

t_SPHOLD

DAI_P20–1

(PDAP_HOLD)

t_PDHD

t_PDSD

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

t_PDHLDD

t_PDSTRB

DAI_P20–1

(PDAP_STROBE)

Figure 27. PDAP Timing

Rev. C

|

Page 48 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Sample Rate Converter—Serial Input Port

The ASRC input signals are routed from the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided in

Table 41 are valid at the DAI_P20–1 pins.

Table 41. ASRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Clock Width

4

ns

1

t_SRCHFS

5.5

1

t_SRCSD

4

1

t_SRCHD

t_SRCCLKW

t_SRCCLK

5.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCSD

t_SRCHD

DAI_P20–1

(SDATA)

Figure 28. ASRC Serial Input Port Timing

Rev. C

|

Page 49 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

delay specification with regard to serial clock. Note that serial

Sample Rate Converter—Serial Output Port

clock rising edge is the sampling edge and the falling edge is the

drive edge.

For the serial output port, the frame sync is an input, and it

should meet setup and hold times with regard to the serial clock

on the output port. The serial data output has a hold time and

Table 42. ASRC, Serial Output Port

88-Lead LFCSP Package

All Other Packages

Max

Unit

Parameter

Min

Max

Min

Timing Requirements

1

t_SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Clock Width

4

ns

1

t_SRCHFS

t_SRCCLKW

t_SRCCLK

5.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

Switching Characteristics

1

t_SRCTDD

Transmit Data Delay After Serial Clock Falling Edge

Transmit Data Hold After Serial Clock Falling Edge

2 × t_PCLK

13

ns

1

t_SRCTDH

1

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCTDD

t_SRCTDH

DAI_P20–1

(SDATA)

Figure 29. ASRC Serial Output Port Timing

Rev. C

|

Page 50 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Pulse-Width Modulation Generators (PWM)

The following timing specifications apply when the

ADDR23–8/DPI_14–1 pins are configured as PWM.

Table 43. Pulse-Width Modulation (PWM) Timing

88-Lead LFCSP Package

Max

All Other Packages

Max

Unit

Parameter

Min

Switching Characteristics

t_PWMW

t_PWMP

PWM Output Pulse Width

t_PCLK– 2

(2¹⁶– 2) × t_PCLK

(2¹⁶– 1) × t_PCLK

t_PCLK– 2

(2¹⁶– 2) × t_PCLK

(2¹⁶– 1) × t_PCLK

ns

PWM Output Period

2 × t_PCLK– 2

2 × t_PCLK– 1.5

t_PWMW

PWM

OUTPUTS

t_PWMP

Figure 30. PWM Timing

Rev. C

|

Page 51 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left-justified, I²S, or right-justified with word widths of 16, 18,

20, or 24 bits. The following sections provide timing for the

transmitter.

in 24-bit output mode or the maximum in 16-bit output mode

from a frame sync transition, so that when there are 64 serial

clock periods per frame sync period, the LSB of the data is right-

justified to the next frame sync transition.

Figure 32 shows the default I²S-justified mode. The frame sync

is low for the left channel and high for the right channel. Data is

valid on the rising edge of serial clock. The MSB is left-justified

to the frame sync transition but with a delay.

S/PDIF Transmitter-Serial Input Waveforms

Figure 31 shows the right-justified mode. Frame sync is high for

the left channel and low for the right channel. Data is valid on

the rising edge of serial clock. The MSB is delayed the minimum

Table 44. S/PDIF Transmitter Right-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

t_RJD

FS to MSB Delay in Right-Justified Mode

16-Bit Word Mode

16

14

12

8

SCLK

18-Bit Word Mode

20-Bit Word Mode

24-Bit Word Mode

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_RJD

DAI_P20–1

SDATA

LSB

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 31. Right-Justified Mode

Table 45. S/PDIF Transmitter I²S Mode

Parameter

Nominal

Unit

Timing Requirement

t_I2SD

FS to MSB Delay in I²S Mode

1

SCLK

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_I2SD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 32. I²S-Justified Mode

Figure 33 shows the left-justified mode. The frame sync is high

for the left channel and low for the right channel. Data is valid

on the rising edge of serial clock. The MSB is left-justified to the

frame sync transition with no delay.

Rev. C

|

Page 52 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Table 46. S/PDIF Transmitter Left-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

t_LJD

FS to MSB Delay in Left-Justified Mode

0

SCLK

DAI_P20–1

FS

LEFT/RIGHT CHANNEL

DAI_P20–1

SCLK

t_LJD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 33. Left-Justified Mode

Rev. C

|

Page 53 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 47. Input signals are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 47. S/PDIF Transmitter Input Data Timing

88-Lead LFCSP Package

All Other Packages

Min Max

Unit

Parameter

Min

Max

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge

4.5

3

ns

1

t_SIHFS

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Transmit Clock Width

3

1

t_SISD

4.5

3

1

t_SIHD

3

t_SITXCLKW

t_SITXCLK

t_SISCLKW

t_SISCLK

9

Transmit Clock Period

20

36

80

20

36

80

Clock Width

Clock Period

1

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SITXCLKW

t_SITXCLK

DAI_P20–1

(TxCLK)

t_SISCLK

t_SISCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 34. S/PDIF Transmitter Input Timing

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter requires an oversampling clock input.

This high frequency clock (TxCLK) input is divided down to

generate the internal biphase clock.

Table 48. Oversampling Clock (TxCLK) Switching Characteristics

Parameter

Max

Unit

MHz

kHz

Frequency for TxCLK = 384 × Frame Sync

Frequency for TxCLK = 256 × Frame Sync

Frame Rate (FS)

Oversampling Ratio × Frame Sync ≤ 1/t_SITXCLK

49.2

192.0

Rev. C

|

Page 54 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 49. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

FS Delay After Serial Clock

5

ns

t_HOFSI

t_DDTI

FS Hold After Serial Clock

–2

Transmit Data Delay After Serial Clock

Transmit Data Hold After Serial Clock

Transmit Serial Clock Width

t_HDTI

–2

1

t_SCLKIW

38.5

¹The serial clock frequency is 64 × frame sync (FS) where FS = the frequency of LRCLK.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20–1

(SCLK)

t_DFSI

t_HOFSI

DAI_P20–1

(FS)

t_DDTI

t_HDTI

DAI_P20–1

(DATA CHANNEL

A/B)

Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. C

|

Page 55 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

SPI Interface—Master

Both the primary and secondary SPIs are available through DPI

only. The timing provided in Table 50 and Table 51 applies

to both.

Table 50. SPI Interface Protocol—Master Switching and Timing Specifications

88-Lead LFCSP Package

All Other Packages

Unit

Parameter

Min

Max

Min

Max

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid to SPICLK Edge (Data Input Setup Time) 10

8.6

2

ns

SPICLK Last Sampling Edge to Data Input Not Valid

2

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × t_PCLK– 2

4 × t_PCLK– 2

8 × t_PCLK– 2

4 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay time)

2.5

SPICLK Edge to Data Out Not Valid (Data Out Hold time) 4 × t_PCLK– 2

4 × t_PCLK– 2

4 × t_PCLK– 1.4

ns

DPI Pin (SPI Device Select) Low to First SPICLK Edge

Last SPICLK Edge to DPI Pin (SPI Device Select) High

Sequential Transfer Delay

4 × t_PCLK– 2

t_SPITDM

DPI

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

(INPUT)

t_DDSPIDM

t_HDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

CPHASE = 0

MISO

(INPUT)

Figure 36. SPI Master Timing

Rev. C

|

Page 56 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

SPI Interface—Slave

Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications

88-Lead LFCSP Package

All Other Packages

Unit

Parameter

Min

Max

Min

Max

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

t_HDS

Serial Clock Cycle

4 × t_PCLK– 2

2 × t_PCLK– 2

4 × t_PCLK– 2

2 × t_PCLK– 2

2 × t_PCLK

2

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 2 × t_PCLK

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE = 0)

2 × t_PCLK

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_PCLK

Switching Characteristics

t_DSOESPIDS Assertion to Data Out Active

0

13

0

10.25

13.25

11.5

ns

1

t_DSOE

t_DSDHI

SPIDS Assertion to Data Out Active (SPI2)

13

SPIDS Deassertion to Data High Impedance

2 × t_PCLK

13

1

t_DSDHI

SPIDS Deassertion to Data High Impedance (SPI2)

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE = 0)

t_DDSPIDS

t_HDSPIDS

t_DSOV

2 × t_PCLK

5 × t_PCLK

¹The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral

Interface Port (SPI)” chapter.

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0,

CP = 1)

(INPUT)

t_SDSCO

t_DSOE

t_DSDHI

t_HDSPIDS

t_DDSPIDS

MISO

(OUTPUT)

t_SSPIDSt_HSPIDS

CPHASE = 1

MOSI

(INPUT)

t_HDSPIDS

t_DSDHI

MISO

(OUTPUT)

t_DSOV

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

(INPUT)

Figure 37. SPI Slave Timing

Rev. C

|

Page 57 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Media Local Bus

All the numbers given are applicable for all speed modes

(1024 FS, 512 FS, and 256 FS for 3-pin; 512 FS and 256 FS for

5-pin) unless otherwise specified. Please refer to MediaLB speci-

fication document rev 3.0 for more details.

Table 52. MLB Interface, 3-Pin Specifications

Parameter

Min

Typ

Max

Unit

3-Pin Characteristics

t_MLBCLK

MLB Clock Period

1024 FS

512 FS

256 FS

20.3

40

81

ns

t_MCKL

MLBCLK Low Time

1024 FS

6.1

14

30

ns

512 FS

256 FS

t_MCKH

MLBCLK High Time

1024 FS

9.3

14

30

ns

512 FS

256 FS

t_MCKR

MLBCLK Rise Time (V_ILto V_IH)

1024 FS

1

3

ns

512 FS/256 FS

t_MCKF

MLBCLK Fall Time (V_IHto V_IL)

1024 FS

1

3

ns

512 FS/256 FS

1

t_MPWV

MLBCLK Pulse Width Variation

1024 FS

0.7

2.0

ns p-p

512 FS/256

t_DSMCF

t_DHMCF

t_MCFDZ

t_MCDRV

DAT/SIG Input Setup Time

1

ns

DAT/SIG Input Hold Time

1.2

0

DAT/SIG Output Time to Three-State

DAT/SIG Output Data Delay From MLBCLK Rising Edge

15

8

2

t_MDZH

Bus Hold Time

1024 FS

512 FS/256

2

4

ns

C_MLB

DAT/SIG Pin Load

1024 FS

40

60

pf

512 FS/256

¹Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (p-p).

²The board must be designed to ensure that the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be

minimized while meeting the maximum capacitive load listed.

Rev. C

|

Page 58 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

MLBSIG/

MLBDAT

(Rx, Input)

VALID

t_DHMCF

t_DSMCF

t_MCKH

t_MCKL

MLBCLK

t_MCKR

t_MCKF

t_MLBCLK

t_MCFDZ

t_MCDRV

t_MDZH

VALID

MLBSIG/

MLBDAT

(Tx, Output)

Figure 38. MLB Timing (3-Pin Interface)

Table 53. MLB Interface, 5-Pin Specifications

Parameter

Min

Typ

Max

Unit

5-Pin Characteristics

t_MLBCLK

MLB Clock Period

512 FS

40

81

ns

256 FS

t_MCKL

MLBCLK Low Time

512 FS

15

30

ns

256 FS

t_MCKH

MLBCLK High Time

512 FS

15

30

ns

256 FS

t_MCKR

t_MCKF

MLBCLK Rise Time (V_ILto V_IH)

MLBCLK Fall Time (V_IHto V_IL)

MLBCLK Pulse Width Variation

DAT/SIG Input Setup Time

DAT/SIG Input Hold Time

6

2

ns

1

t_MPWV

ns p-p

ns

2

t_DSMCF

3

5

t_DHMCF

t_MCDRV

ns

DS/DO Output Data Delay From MLBCLK Rising Edge

8

ns

3

t_MCRDL

DO/SO Low From MLBCLK High

512 FS

256 FS

10

20

ns

C_mlb

DS/DO Pin Load

40

pf

¹Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (p-p).

²Gate delays due to OR’ing logic on the pins must be accounted for.

³When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,

external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.

Rev. C

|

Page 59 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

MLBSIG/

MLBDAT

VALID

(Rx, Input)

t_DHMCF

t_DSMCF

t_MCKH

t_MCKL

MLBCLK

t_MCKR

t_MCKF

t_MLBCLK

t_MCRDL

t_MCDRV

VALID

MLBSO/

MLBDO

(Tx, Output)

Figure 39. MLB Timing (5-Pin Interface)

MLBCLK

t_MPWV

Figure 40. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing

Rev. C

|

Page 60 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Shift Register

Table 54. Shift Register

Parameter

Min

Max

Unit

Timing Requirements

t_SSDI

SR_SDI Setup Before SR_SCLK Rising Edge

7

ns

MHz

ns

t_HSDI

SR_SDI Hold After SR_SCLK Rising Edge

DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge

DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge

SR_SCLK to SR_LAT Setup

2

1

t_SSDIDAI

7

1

t_HSDIDAI

2

t_SSCK2LCK

2

1, 2

t_SSCK2LCKDAI

t_CLRREM2SCK

t_CLRREM2LCK

t_CLRW

DAI_P08–01 (SR_SCLK) to DAI_P08–01 (SR_LAT) Setup

Removal Time SR_CLR to SR_SCLK

2

3 × t_PCLK– 5

2 × t_PCLK– 5

4 × t_PCLK– 5

2 × t_PCLK– 2

2 × t_PCLK– 5

Removal Time SR_CLR to SR_LAT

SR_CLR Pulse Width

t_SCKW

SR_SCLK Clock Pulse Width

t_LCKW

SR_LAT Clock Pulse Width

f_MAX

Maximum Clock Frequency SR_SCLK or SR_LAT

f_PCLK 4

Switching Characteristics

3

t_DSDO1

SR_SDO Hold After SR_SCLK Rising Edge

3

t_DSDO2

t_DSDODAI1

t_DSDODAI2

SR_SDO Max. Delay After SR_SCLK Rising Edge

SR_SDO Hold After DAI_P08–01 (SR_SCLK) Rising Edge

SR_SDO Max. Delay After DAI_P08–01 (SR_SCLK) Rising Edge

SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge

SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge

SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge

SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge

SR_CLR to SR_SDO Min. Delay

13

5

1, 3

3

3, 4

t_DSDOSP1

t_DSDOSP2

t_DSDOPCG1

t_DSDOPCG2

–2

4

3, 4

3, 5, 6

5

3

t_DSDOCLR1

3

t_DSDOCLR2

SR_CLR to SR_SDO Max. Delay

13

5

3

t_DLDO1

SR_LDO Hold After SR_LAT Rising Edge

3

t_DLDO2

SR_LDO Max. Delay After SR_LAT Rising Edge

SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge

SR_LDO Max. Delay After DAI_P08–01 (SR_LAT) Rising Edge

SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge

SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge

SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge

SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge

SR_CLR to SR_LDO Min. Delay

3

t_DLDODAI1

3

t_DLDODAI2

3, 4

t_DLDOSP1

t_DLDOSP2

–2

4

3, 5, 6

t_DLDOPCG1

t_DLDOPCG2

5

3

t_DLDOCLR1

3

t_DLDOCLR2

SR_CLR to SR_LDO Max. Delay

14

¹Any of the DAI_P08–01 pins can be routed to the shift register clock, latch clock and serial data input via the SRU.

²Both clocks can be connected to the same clock source. If both clocks are connected to same clock source, then data in the 18-stage shift register is always one cycle ahead of

latch register data.

³For setup/hold timing requirements of off-chip shift register interfacing devices.

⁴SPORTx serial clock out, frame sync out, and serial data outputs are routed to shift register block internally and are also routed onto DAI_P20–01.

⁵PCG serial clock output is routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SR_LAT and SDI internally.

⁶PCG Serial clock and frame sync outputs are routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SDI internally.

Rev. C

|

Page 61 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

t_SSDI,t_SSDIDAI

DAI_P08

OR

-01

SR_SCLK

t_HSDI,t_HSDIDAI

DAI_P08

OR

-01

SR_SDI

SR_SDO

Figure 41. SR_SDI Setup, Hold

SR_SCLK OR

DAI_P08-01 OR

DAI_P20-01(SPx_CLK_O) OR

DAI_P20-01(PCG_CLKx_O)

t_DSDO2

t_DSDO1

SR_SDO

THE TIMING PARAMETERS SHOWN FOR t_{DSDO1 AND}t_DSDO2ARE VALID FOR t

DSDOSP1, DSDOPCG1,

,

DSDODAI1

t

t_DSDODAI2, t_{DSDOSP2, AND}t_DSDOPCG2

Figure 42. SR_ SDO Delay

SR_LAT OR

DAI_P08 01 OR

01

-

DAI_P20

-

(SPx_FS_O)

OR

DAI_P20-01

(PCG_FSx_O)

t_DLDO1

t_DLDO2

SR_LDO

THE TIMING PARAMETERS SHOWN FOR t_DLDO1AND t_DLDO2ARE ALSO VALID FOR t_DLDODAI1

t_DLDODAI2, t_DLDOSP1, t_DLDOSP2, t_DLDOPCG1, AND t_DLDOPCG2

,

.

Figure 43. SR_LDO Delay

Rev. C

|

Page 62 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

SR_SCLK

OR

DAI_P08-01

t_SSCK2LCK

t_SSCK2LCKDAI

SR_LAT

OR

DAI_P08

-01

SR_SDI

OR

DAI_P08

-01

SR_LDO

Figure 44. SR_SCLK to SR_LAT Setup, Clocks Pulse Width and Maximum Frequency

t_CLRW

SR_CLR

t_CLRREM2SCK

SR_SDCLK

OR

DAI_P08-01

t_CLRREM2LCK

SR_LAT

OR

DAI_P08-01

t_DSDOCLR2

t_DSDOCLR1

SR_SDO

SR_LDO

t_DLDOCLR2

t_DLDOCLR1

Figure 45. Shift Register Reset Timing

Rev. C

|

Page 63 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

For information on the UART port receive and transmit opera-

tions, see the ADSP-214xx SHARC Hardware Reference Manual.

2-Wire Interface (TWI)—Receive and Transmit Timing

For information on the TWI receive and transmit operations,

see the ADSP-214xx SHARC Hardware Reference Manual.

JTAG Test Access Port and Emulation

Table 55. JTAG Test Access Port and Emulation

88-Lead LFCSP Package

All Other Packages

Max

Unit

Parameter

Min

Max

Min

Timing Requirements

t_TCK

TCK Period

20

5

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

5

6

1

t_SSYS

7

1

t_HSYS

t_TRSTW

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

18

4 × t_CK

11.5

10.5

ns

2

t_DSYS

t_CK÷ 2 + 7

¹System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG1–0, DAI_Px, DPI_Px, FLAG3–0, MLBCLK, MLBDAT, MLBSIG, SR_SCLK, SR_CLR, SR_SDI, and

SR_LAT.

²System Outputs = DAI_Px, DPI_Px, ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK, MLBDAT, MLBSIG, MLBDO,

MLBSO, SR_SDO, SR_LDO, and EMU.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 46. IEEE 1149.1 JTAG Test Access Port

Rev. C

|

Page 64 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

OUTPUT DRIVE CURRENTS

TESTER PIN ELECTRONICS

Table 56 shows the driver types and the pins associated with

50:

each driver. Figure 47 shows typical I-V characteristics for each

driver. The curves represent the current drive capability of the

output drivers as a function of output voltage.

V

LOAD

T1

DUT

OUTPUT

45:

70:

ZO = 50:ꢀ(impedance)

TD = 4.04 ꢀ 1.18 ns

50:

Table 56. Driver Types

0.5pF

4pF

2pF

Driver Type Associated Pins

400:

A

FLAG[0–3], AMI_ADDR[23–0], DATA[15–0],

AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,

SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU,

TDO, RESETOUT, DPI[1–14], DAI[1–20],

WDTRSTO, MLBDAT, MLBSIG, MLBSO, MLBDO,

MLBCLK, SR_CLR, SR_LAT, SR_LDO[17–0],

SR_SCLK, SR_SDI

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

B

SDCLK, RTCLKOUT

Figure 48. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

200

150

100

V_OH3.13 V, 125 °C

TYPE B

INPUT

OR

1.5V

TYPE A

OUTPUT

50

0

Figure 49. Voltage Reference Levels for AC Measurements

TYPE A

-

50

100

150

CAPACITIVE LOADING

-

TYPE B

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 48). Figure 52 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 50, Figure 51, and Figure 52 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

V_OL3.13 V, 125 °C

-

200

0.5

1.0

1.5

2.0

2.5

3.5

0

3.0

SWEEP (V_DDEXT) VOLTAGE (V)

Figure 47. Typical Drive at Junction Temperature

TEST CONDITIONS

7

The ac signal specifications (timing parameters) appear in

Table 21 on Page 29 through Table 55 on Page 64. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 48.

6

TYPE A DRIVE FALL

TYPE A DRIVE RISE

y = 0.0331x + 0.2662

y = 0.0421x + 0.2418

5

4

3

2

1

0

TYPE B DRIVE FALL

y = 0.0206x + 0.2271

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 49. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

TYPE B DRIVE RISE

y = 0.0184x + 0.3065

0

25

50

75

100

125

150

175

200

LOAD CAPACITANCE (pF)

Figure 50. Typical Output Rise/Fall Time (20% to 80%,

V_{DD_EXT}= Max)

Rev. C

|

Page 65 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

where:

14

T_J= junction temperature (°C)

TYPE A DRIVE FALL

y = 0.0748x + 0.4601

T_CASE= case temperature (°C) measured at the top center of the

package

12

10

8

TYPE A DRIVE RISE

y = 0.0567x + 0.482

_JT= junction-to-top (of package) characterization parameter is

the typical value from Table 58

TYPE B DRIVE FALL

y = 0.0367x + 0.4502

P_D= power dissipation

6

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first order approxi-

mation of T_Jby the equation:

TYPE B DRIVE RISE

y = 0.0314x + 0.5729

4

2

T

= T +   P 

A JA D

J

0

where:

T_A= ambient temperature °C

0

25

50

75

100

125

150

175

200

LOAD CAPACITANCE (pF)

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heatsink is required.

Figure 51. Typical Output Rise/Fall Time (20% to 80%,

V_{DD_EXT}= Min)

Note that the thermal characteristics values provided in

Table 58 are modeled values.

4.5

4

TYPE A DRIVE FALL

y = 0.0199x + 1.1083

Table 57. Thermal Characteristics for 88-Lead LFCSP_VQ

TYPE A DRIVE RISE

y = 0.015x + 1.4889

Parameter

_JA

Condition

Typical

22.6

18.2

17.3

7.9

Unit

°C/W

3.5

3

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

TYPE B DRIVE RISE

y = 0.0088x + 1.6008

_JMA

_JC

2.5

2

TYPE B DRIVE FALL

y = 0.0102x + 1.2726

_JT

_JMT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.22

0.36

0.44

1.5

1

0.5

0

Table 58. Thermal Characteristics for 100-Lead LQFP_EP

Parameter

θ_JA

Condition

Typical

18.1

15.5

14.6

2.4

Unit

°C/W

0

25

50

75

100

125

150

175

200

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

LOAD CAPACITANCE (pF)

θ_JMA

Figure 52. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

θ_JMA

θ_JC

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.22

0.36

0.50

THERMAL CHARACTERISTICS

Ψ_JMT

The processor is rated for performance over the temperature

range specified in Operating Conditions on Page 21.

Table 58 airflow measurements comply with JEDEC standards

JESD51-2 and JESD51-6 and the junction-to-board measure-

ment complies with JESD51-8. Test board design complies with

JEDEC standards JESD51-7 (PBGA). The junction-to-case mea-

surement complies with MIL- STD-883. All measurements use a

2S2P JEDEC test board.

Table 59. Thermal Characteristics for 196-Ball CSP_BGA

Parameter

θ_JA

Condition

Typical

29.0

26.1

25.1

8.8

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

θ_JMA

To determine the junction temperature of the device while on

the application PCB, use:

θ_JC

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.23

0.42

0.52

T

= T

+   P 

CASE JT

D

J

Ψ_JMT

Rev. C

|

Page 66 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

where:

Thermal Diode

n = multiplication factor close to 1, depending on process

The processors incorporate thermal diode/s to monitor the die

temperature. The thermal diode is a grounded collector, PNP

bipolar junction transistor (BJT). The THD_P pin is connected

to the emitter, and the THD_M pin is connected to the base of

the transistor. These pins can be used by an external tempera-

ture sensor (such as ADM1021A or LM86 or others) to read the

die temperature of the chip.

variations

k = Boltzmann constant

T = temperature (°C)

q = charge of the electron

N = ratio of the two currents

The technique used by the external temperature sensor is to

measure the change in VBE when the thermal diode is operated

at two different currents. This is shown in the following

equation:

The two currents are usually in the range of 10 μA to 300 μA for

the common temperature sensor chips available.

Table 60 contains the thermal diode specifications using the

transistor model.

kT

q

V = n 

 In(N)

-----

BE

Table 60. Thermal Diode Parameters—Transistor Model¹

Symbol

Parameter

Min

10

Typ

Max

300

Unit

μA

2

I_FW

Forward Bias Current

Emitter Current

Transistor Ideality

Series Resistance

I_E

10

300

μA

3, 4

n_Q

1.012

1.015

0.2

1.017

0.28

3, 5

R_T

0.12

Ω

¹Analog Devices does not recommend operation of the thermal diode under reverse bias.

²Analog Devices does not recommend operation of the thermal diode under reverse bias.

³Specified by design characterization.

⁴The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: I_C= I_S× (e ^qVBE/nqkT– 1) where I_S= saturation current,

q = electronic charge, V_BE= voltage across the diode, k = Boltzmann constant, and T = absolute temperature (Kelvin).

⁵The series resistance (R_T) can be used for more accurate readings as needed.

Rev. C

|

Page 67 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

88-LFCSP_VQ LEAD ASSIGNMENT

Table 61 lists the 88-Lead LFCSP_VQ package lead names.

Table 61. 88-Lead LFCSP_VQ Lead Assignments (Numerical by Lead Number)

Lead Name

CLK_CFG1

BOOT_CFG0

V_{DD_EXT}

Lead No.

Lead Name

V_{DD_EXT}

Lead No.

23

Lead Name

DAI_P10

V_{DD_INT}

Lead No.

45

Lead Name

V_{DD_INT}

FLAG0

V_{DD_INT}

FLAG1

FLAG2

FLAG3

GND

Lead No.

67

1

2

DPI_P08

DPI_P07

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DAI_P03

DPI_P14

V_{DD_INT}

24

46

68

3

25

V_{DD_EXT}

47

69

V_{DD_INT}

4

26

DAI_P20

V_{DD_INT}

48

70

BOOT_CFG1

GND

5

27

49

71

6

28

DAI_P08

DAI_P04

DAI_P14

DAI_P18

DAI_P17

DAI_P16

DAI_P15

DAI_P12

DAI_P11

V_{DD_INT}

50

72

CLK_CFG0

V_{DD_INT}

7

29

51

73

8

30

52

GND

74

CLKIN

9

31

53

V_{DD_EXT}

GND

75

XTAL

10

11

12

13

32

54

76

V_{DD_EXT}

33

55

V_{DD_INT}

TRST

77

V_{DD_INT}

DAI_P13

DAI_P07

DAI_P19

DAI_P01

DAI_P02

V_{DD_INT}

34

56

78

V_{DD_INT}

35

57

EMU

79

RESETOUT/RUNRSTIN 14

36

58

TDO

80

V_{DD_INT}

15

16

17

18

19

20

21

22

37

59

V_{DD_EXT}

V_{DD_INT}

TDI

81

DPI_P01

DPI_P02

DPI_P03

V_{DD_INT}

38

GND

60

82

39

THD_M

THD_P

61

83

V_{DD_EXT}

40

62

TCK

84

V_{DD_INT}

41

V_{DD_THD}

63

V_{DD_INT}

RESET

TMS

85

DPI_P05

DPI_P04

DPI_P06

DAI_P06

DAI_P05

DAI_P09

42

V_{DD_INT}

64

86

43

V_{DD_INT}

65

87

44

V_{DD_INT}

66

V_{DD_INT}

GND

88

89*

* Lead no. 89 is the GND supply (see Figure 53 and Figure 54) for the processor; this pad must be robustly connected to GND in order for the

processor to function.

Rev. C

|

Page 68 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Figure 53 shows the top view of the 88-lead LFCSP_VQ pin

configuration. Figure 54 shows the bottom view.

PIN 88

PIN 67

PIN 66

PIN 1

PIN 1 INDICATOR

ADSP-2147x

88-LEAD LFCSP_VQ

TOP VIEW

PIN 22

PIN 45

PIN 23

PIN 44

Figure 53. 88-Lead LFCSP_VQ Lead Configuration (Top View)

PIN 67

PIN 88

PIN 66

PIN 1

ADSP-2147x

88-LEAD LFCSP_VQ

GND PAD

PIN 1 INDICATOR

(PIN 89)

BOTTOM VIEW

PIN 45

PIN 22

PIN 44

PIN 23

Figure 54. 88-Lead LFCSP_VQ Lead Configuration (Bottom View)

Rev. C

|

Page 69 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

100-LQFP_EP LEAD ASSIGNMENT

Table 62 lists the 100-Lead LQFP_EP lead names.

Table 62. 100-Lead LQFP_EP Lead Assignments (Numerical by Lead Number)

Lead Name

V_{DD_INT}

Lead No.

Lead Name

V_{DD_EXT}

Lead No.

26

Lead Name

DAI_P10

V_{DD_INT}

Lead No.

51

Lead Name

V_{DD_INT}

FLAG0

V_{DD_INT}

FLAG1

FLAG2

FLAG3

MLBCLK

MLBDAT

MLBDO

V_{DD_EXT}

MLBSIG

V_{DD_INT}

MLBSO

TRST

Lead No.

76

1

CLK_CFG1

BOOT_CFG0

V_{DD_EXT}

2

DPI_P08

DPI_P07

V_{DD_INT}

27

52

77

3

28

V_{DD_EXT}

53

78

4

29

DAI_P20

V_{DD_INT}

54

79

V_{DD_INT}

5

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DAI_P03

DPI_P14

V_{DD_INT}

30

55

80

BOOT_CFG1

GND

6

31

DAI_P08

DAI_P04

DAI_P14

DAI_P18

DAI_P17

DAI_P16

DAI_P15

DAI_P12

V_{DD_INT}

56

81

7

32

57

82

NC

8

33

58

83

NC

9

34

59

84

CLK_CFG0

V_{DD_INT}

10

11

12

13

14

15

16

35

60

85

36

61

86

CLKIN

37

62

87

XTAL

V_{DD_INT}

38

63

88

V_{DD_EXT}

V_{DD_INT}

39

64

89

V_{DD_INT}

DAI_P13

DAI_P07

DAI_P19

DAI_P01

DAI_P02

V_{DD_INT}

40

DAI_P11

V_{DD_INT}

65

90

V_{DD_INT}

41

66

EMU

91

RESETOUT/RUNRSTIN 17

42

V_{DD_INT}

67

TDO

92

V_{DD_INT}

18

19

20

21

22

23

24

25

43

GND

68

V_{DD_EXT}

V_{DD_INT}

TDI

93

DPI_P01

DPI_P02

DPI_P03

V_{DD_INT}

44

THD_M

THD_P

V_{DD_THD}

V_{DD_INT}

69

94

45

70

95

V_{DD_EXT}

46

71

TCK

96

V_{DD_INT}

47

72

V_{DD_INT}

RESET

TMS

97

DPI_P05

DPI_P04

DPI_P06

DAI_P06

DAI_P05

DAI_P09

48

V_{DD_INT}

73

98

49

V_{DD_INT}

74

99

50

V_{DD_INT}

75

V_{DD_INT}

GND

100

101*

* Lead no. 101 is the GND supply (see Figure 55 and Figure 56) for the processor; this pad must be robustly connected to GND.

MLB pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. For non-automotive models, these pins should be connected

to ground (GND).

Rev. C

|

Page 70 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

Figure 55 shows the top view configuration of the 100-lead

LQFP_EP package. Figure 56 shows the bottom view configura-

tion of the 100-lead LQFP_EP package.

LEAD 100

LEAD 1

LEAD 76

LEAD 75

LEAD 1 INDICATOR

ADSP-2147x

100-LEAD LQFP_EP

TOP VIEW

LEAD 25

LEAD 51

LEAD 26

LEAD 50

Figure 55. 100-Lead LQFP_EP Lead Configuration (Top View)

LEAD 76

LEAD 100

LEAD 75

LEAD 1

ADSP-2147x

100-LEAD LQFP_EP

GND PAD

LEAD 1 INDICATOR

(LEAD 101)

BOTTOM VIEW

LEAD 51

LEAD 25

LEAD 50

LEAD 26

Figure 56. 100-Lead LQFP_EP Lead Configuration (Bottom View)

Rev. C

|

Page 71 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

196-BGA BALL ASSIGNMENT

Table 63. 196-Ball CSP_BGA Ball Assignment (Numerical by Ball No.)

Ball No. Signal

A1

GND

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

E1

ADDR6

ADDR4

ADDR1

CLK_CFG0

V_{DD_EXT}

ADDR14

ADDR20

WDT_CLKO

ADDR8

ADDR7

ADDR5

V_{DD_EXT}

V_{DD_INT}

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

J1

XTAL

K1

DPI_P02

DPI_P04

DPI_P05

DPI_P09

V_{DD_INT}

N1

DPI_P14

SR_LDO1

SR_LDO4

SR_LDO8

SR_LDO10

DAI_P01

SR_LDO9

DAI_P02

SR_LDO13

SR_SCLK

DAI_P09

SR_SDI

A2

SDCKE

SDDQM

SDRAS

SDWE

SDA10

ADDR11

GND

K2

N2

A3

K3

N3

A4

K4

N4

A5

V_{DD_INT}

GND

K5

N5

A6

DATA12

DATA13

DATA10

DATA9

DATA7

DATA3

DATA1

DATA2

GND

K6

GND

N6

A7

GND

K7

GND

N7

A8

GND

K8

GND

N8

A9

GND

K9

GND

N9

A10

A11

A12

A13

A14

B1

V_{DD_INT}

V_{DD_EXT}

ADDR21

ADDR19

RTXO

K10

K11

K12

K13

K14

L1

V_{DD_INT}

N10

N11

N12

N13

N14

P1

GND

DAI_P16

DAI_P18

DAI_P15

DAI_P03

DPI_P10

DPI_P08

DPI_P06

V_{DD_INT}

SR_LDO17

DAI_P14

GND

ADDR0

CLK_CFG1

BOOT_CFG0

TMS

ADDR13

ADDR12

ADDR10

ADDR17

V_{DD_INT}

GND

B2

E2

L2

P2

SR_LDO3

SR_LDO2

SR_LDO6

WDTRSTO

DAI_P19

DAI_P13

SR_LDO11

SR_LDO15

SR_CLR

B3

E3

L3

P3

B4

E4

L4

P4

B5

RESET

E5

L5

P5

B6

DATA14

DATA11

DATA4

DATA8

DATA6

DATA5

TRST

E6

V_{DD_INT}

L6

V_{DD_INT}

P6

B7

E7

V_{DD_INT}

GND

L7

V_{DD_INT}

P7

B8

E8

V_{DD_INT}

GND

L8

V_{DD_INT}

P8

B9

E9

V_{DD_INT}

GND

L9

V_{DD_INT}

P9

B10

B11

B12

B13

B14

C1

E10

E11

E12

E13

E14

F1

V_{DD_INT}

V_{DD_EXT}

BOOT_CFG2

ADDR23

RTXI

L10

L11

L12

L13

L14

M1

M2

M3

V_{DD_INT}

P10

P11

P12

P13

P14

V_{DD_EXT}

AMI_RD

ADDR22

FLAG2

CLKIN

DAI_P10

DAI_P20

DAI_P17

DAI_P04

DPI_P13

DPI_P12

SR_LDO0

DPI_P07

DPI_P11

SR_LDO5

SR_LDO7

DAI_P07

SR_LDO16

SR_SDO

DAI_P06

DAI_P05

DAI_P08

DAI_P12

SR_LAT

SR_LDO14

SR_LDO12

GND

FLAG1

DATA0

ADDR2

ADDR3

RTCLKOUT

MS0

DPI_P01

DPI_P03

ADDR18

C2

F2

ADDR9

BOOT_CFG1

NC

J2

C3

F3

J3

C4

F4

J4

RESETOUT/RUNRSTIN M4

C5

SDCAS

DATA15

TCK

F5

NC

J5

V_{DD_INT}

GND

M5

C6

F6

GND

J6

M6

C7

F7

GND

J7

GND

M7

C8

TDI

F8

GND

J8

GND

M8

C9

SDCLK

EMU

F9

GND

J9

GND

M9

C10

C11

C12

C13

C14

F10

F11

F12

F13

F14

V_{DD_INT}

J10

J11

J12

J13

J14

V_{SS_RTC}

V_{DD_RTC}

DAI_P11

AMI_ACK

MS1

M10

M11

M12

M13

M14

TDO

V_{DD_EXT}

ADDR15

FLAG0

AMI_WR

FLAG3

ADDR16

WDT_CLKIN

Rev. C

|

Page 72 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

OUTLINE DIMENSIONS

The processors are available in 88-lead LFCSP_VQ, 100-lead

LQFP_EP and 196-ball CSP_BGA RoHS compliant packages.

For package assignment by model, see Ordering Guide on

Page 76.

12.10

12.00 SQ

11.90

0.30

0.23

0.18

0.60 MAX

0.60

MAX

PIN 1

67

66

88

INDICATOR

1

PIN 1

INDICATOR

0.50

BSC

11.85

11.75 SQ

11.65

6.70

REF SQ

EXPOSED PAD

0.50

0.40

0.30

22

45

44

23

BOTTOM VIEW

TOP VIEW

0.70

10.50

REF

0.65

0.60

12° MAX

*

0.90

0.85

0.75

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.045

0.025

0.005

SECTION OF THIS DATA SHEET.

COPLANARITY

SEATING

PLANE

0.08

0.138~0.194 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-VRRD

EXCEPT FOR MINIMUM THICKNESS AND LEAD COUNT.

Figure 57. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ¹]

(CP-88-5)

Dimensions Shown in Millimeters

¹For information relating to the exposed pad on the CP-88-5 package, see the table endnote on Page 68.

Rev. C

|

Page 73 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

16.20

16.00 SQ

15.80

1.60

14.20

14.00 SQ

13.80

MAX

0.75

0.60

0.45

12.00 REF

100

76

100

1

75

1

1.00 REF

PIN 1

SEATING

PLANE

EXPOSED

PAD

6.00 BSC

SQ

TOP VIEW

BOTTOM VIEW

(PINS UP)

1.45

1.40

1.35

(PINS DOWN)

51

25

51

25

0.20

0.09

26

50

26

50

0.27

0.22

0.17

VIEW A

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.50

BSC

LEAD PITCH

0.15

0.05

7°

0°

0.08

COPLANARITY

SECTION OF THIS DATA SHEET.

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD

ROTATED 90° CCW

Figure 58. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP¹]

(SW-100-2)

Dimensions shown in millimeters

¹For information relating to the exposed pad on the SW-100-2 package, see the table endnote on Page 70.

12.10

12.00 SQ

11.90

A1 BALL

CORNER

A1 BALL

CORNER

14 13 12 11 10 9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

10.40

BSC SQ

0.80

BSC

K

L

M

N

P

0.80

REF

TOP VIEW

DETAIL A

BOTTOM VIEW

1.50

1.41

1.32

1.13

1.06

0.99

0.70

REF

DETAIL A

0.35 NOM

0.30 MIN

0.36

REF

0.50

0.45

0.40

COPLANARITY

0.12

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

Figure 59. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]

(BC-196-8)

Dimensions shown in millimeters

Rev. C

|

Page 74 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

SURFACE-MOUNT DESIGN

AUTOMOTIVE PRODUCTS

For industry-standard design recommendations, refer to

IPC-7351, Generic Requirements for Surface-Mount Design

and Land Pattern Standard.

The ADSP-21477, ADSP-21478, and ADSP-21479 are available

with controlled manufacturing to support the quality and reli-

ability requirements of automotive applications. Note that these

automotive models may have specifications that differ from the

commercial models, and designers should review the product

Specifications section of this data sheet carefully.

Only the automotive grade products shown in Table 64 are

available for use in automotive applications. Contact your local

ADI account representative for specific product ordering infor-

mation and to obtain the specific Automotive Reliability reports

for these models.

Table 64. Automotive Product Models

Processor

Temperature

Range²

On-Chip

SRAM

Instruction

Rate (Max)

Package

Package Description Option

Model¹

Notes

AD21477WYCPZ1Axx

AD21477WYSWZ1Axx

AD21478WYBCZ2Axx

AD21478WYCPZ1Axx

AD21478WYSWZ2Axx

AD21478WYSWZ2Bxx

AD21479WYCPZ1Axx

AD21479WYCPZ1Bxx

AD21479WYSWZ2Axx

AD21479WYSWZ2Bxx

¹Z = RoHS compliant part.

–40°C to +105°C

2M bits

3M bits

5M bits

200 MHz

266 MHz

200 MHz

200MHz

266 MHz

88-Lead LFCSP_VQ

100-Lead LQFP_EP

88-Lead LFCSP_VQ

100-Lead LQFP_EP

88-Lead LFCSP_VQ

100-Lead LQFP_EP

CP-88-5

SW-100-2

CP-88-5

SW-100-2

CP-88-5

3, 4

CP-88-5

SW-100-2

²Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 21 for junction temperature (T_J)

specification, which is the only temperature specification.

³Contains multichannel audio decoders from Dolby and DTS.

⁴Contains Digital Transmission Content Protection (DTCP) from DTLA. User must have current license from DTLA to order this product.

Rev. C

|

Page 75 of 76

|

July 2013

ADSP-21477/ADSP-21478/ADSP-21479

ORDERING GUIDE

ProcessorInstruction

Temperature Range²On-Chip SRAM Rate (Max)

Package

Option

Model¹

Package Description

88-Lead LFCSP_VQ

100-Lead LQFP_EP

88-Lead LFCSP_VQ

196-Ball CSP_BGA

100-Lead LQFP_EP

196-Ball CSP_BGA

100-Lead LQFP_EP

88-Lead LFCSP_VQ

196-Ball CSP_BGA

100-Lead LQFP_EP

196-Ball CSP_BGA

100-Lead LQFP_EP

ADSP-21477KCPZ-1A

ADSP-21477KSWZ-1A

ADSP-21477BCPZ-1A

ADSP-21478KCPZ-1A

ADSP-21478BCPZ-1A

ADSP-21478BBCZ-2A

ADSP-21478BSWZ-2A

ADSP-21478KBCZ-1A

ADSP-21478KBCZ-2A

ADSP-21478KBCZ-3A

ADSP-21478KSWZ-1A

ADSP-21478KSWZ-2A

ADSP-21479KCPZ-1A

ADSP-21479BCPZ-1A

ADSP-21479BBCZ-2A

ADSP-21479BSWZ-2A

ADSP-21479KBCZ-1A

ADSP-21479KBCZ-2A

ADSP-21479KBCZ-3A

ADSP-21479KSWZ-1A

ADSP-21479KSWZ-2A

¹Z =RoHS compliant part.

0°C to +70°C

–40C to +85C

0°C to +70°C

–40C to +85C

–40°C to +85°C

0°C to +70°C

–40C to +85C

–40°C to +85°C

0°C to +70°C

2M Bits

3M Bits

5M Bits

200 MHz

266 MHz

200 MHz

266 MHz

300 MHz

200 MHz

266 MHz

200 MHz

266 MHz

200 MHz

266 MHz

300 MHz

200 MHz

266 MHz

CP-88-5

SW-100-2

CP-88-5

BC-196-8

SW-100-2

BC-196-8

SW-100-2

CP-88-5

BC-196-8

SW-100-2

BC-196-8

SW-100-2

²Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 21 for junction temperature (T_J)

specification, which is the only temperature specification.

registered trademarks are the property of their respective owners.

D09017-0-7/13(C)

Rev. C

|

Page 76 of 76

|

July 2013


型号：	ADSP-21478KSWZ-1A
厂家：	ADI
描述：	SHARC Processor SHARC处理器微控制器和处理器外围集成电路微处理器 PC 时钟
文件：	总76页 (文件大小：1921K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21478KSWZ-1A [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E