ADSP-21483_技术文档

SHARC Processor

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

FEATURES

High performance 32-bit/40-bit floating-point processor

The ADSP-2148x processors are available with unique audio-

centric peripherals, such as the digital applications

interface, serial ports, precision clock generators, S/PDIF

transceiver, asynchronous sample rate converters, input

data port, and more

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip

ROM

For complete ordering information, see Ordering Guide on

Page 70

Up to 450 MHz operating frequency

AEC-Q100 qualified for automotive applications

Code compatible with all other members of the SHARC family

Internal Memory

SIMD Core

Block 0

RAM/ROM

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

Instruction

Cache

5 Stage

Sequencer

S

B2D

64-BIT

B0D

64-BIT

B3D

64-BIT

B1D

64-BIT

Core

Timer

DAG1/2

PEx

DMD

64-BIT

PEy

Core Bus

Cross Bar

Internal Memory I/F

PMD

64-BIT

PMD 64-BIT

FLAGx/IRQx/

TMREXP

IOD0 32-BIT

THERMAL

DIODE

EPD BUS 64-BIT

JTAG

PERIPHERAL BUS

32-BIT

IOD1

32-BIT

IOD0 BUS

FFT

DTCP/

FIR

MTM

IIR

PERIPHERAL BUS

EP

SPEP BUS

CORE

FLAGS/

PWM3

PDAP/

IDP

7-0

S/PDIF PCG ASRC

Tx/Rx

SPORT

7-0

CORE PWM

WDT

SDRAM

CTL

PCG

TIMER

1-0

TWI SPI/B UART

AMI

A

-

D

3

-

0

FLAGS

3-0

C-D

-

1

DPI Routing/Pins

DAI Routing/Pins

External Port Pin MUX

External

Port

DPI Peripherals

DAI Peripherals

Figure 1. Functional Block Diagram

Peripherals

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. H Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

TABLE OF CONTENTS

Features ................................................................. 1

Table of Contents ..................................................... 2

Revision History ...................................................... 2

General Description ................................................. 3

Family Core Architecture ........................................ 4

Family Peripheral Architecture ................................ 7

I/O Processor Features ......................................... 10

System Design .................................................... 11

Development Tools ............................................. 12

Additional Information ........................................ 13

Related Signal Chains .......................................... 13

Pin Function Descriptions ....................................... 14

Specifications ........................................................ 18

Operating Conditions .......................................... 18

Electrical Characteristics ....................................... 19

Absolute Maximum Ratings .................................. 21

ESD Sensitivity ................................................... 21

Maximum Power Dissipation ................................. 21

Timing Specifications ........................................... 22

Output Drive Currents ......................................... 55

Test Conditions .................................................. 55

Capacitive Loading .............................................. 55

Thermal Characteristics ........................................ 56

88-Lead LFCSP_VQ Lead Assignment ......................... 58

100-Lead LQFP_EP Lead Assignment ......................... 60

176-Lead LQFP_EP Lead Assignment ......................... 62

Outline Dimensions ................................................ 66

Surface-Mount Design .......................................... 68

Automotive Products .............................................. 69

Ordering Guide ..................................................... 70

REVISION HISTORY

2/2020—Rev. G to Rev. H

Changes to Pin List, Power, Ground and Other .............. 17

Changes to Operating Conditions ............................... 18

Changes to Electrical Characteristics ............................ 19

Changes to Thermal Characteristics ............................ 56

Changes to 88-Lead LFCSP_VQ Lead Assignment .......... 58

Changes to 100-Lead LQFP_EP Lead Assignment ........... 60

Changes to 176-Lead LQFP_EP Lead Assignment ........... 62

Changes to Automotive Products ................................ 69

Changes to Ordering Guide ....................................... 70

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

GENERAL DESCRIPTION

The ADSP-2148x SHARC^®processors are members of the

SIMD SHARC family of DSPs that feature Analog Devices’

Super Harvard Architecture. The processors are source code

compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x,

ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as

with first generation ADSP-2106x SHARC processors in SISD

(single-instruction, single-data) mode. The ADSP-2148x pro-

cessors are 32-bit/40-bit floating point processors optimized for

high performance audio applications with large on-chip SRAM,

multiple internal buses to eliminate I/O bottlenecks, and an

innovative digital applications interface (DAI).

Table 1. Processor Benchmarks

Speed

(at 400 MHz) (at 450 MHz)

Benchmark Algorithm

1024 Point Complex FFT

(Radix 4, with Reversal)

23 μs

20.44 μs

FIR Filter (per Tap)¹

IIR Filter (per Biquad)¹

1.25 ns

5 ns

1.1 ns

4.43 ns

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]

[4 × 4] × [4 × 1]

11.25 ns

20 ns

10.0 ns

17.78 ns

Table 1 shows performance benchmarks for the ADSP-2148x

processors. Table 2 shows the features of the individual product

offerings.

Divide (y/×)

7.5 ns

6.67 ns

10.0 ns

Inverse Square Root

¹Assumes two files in multichannel SIMD mode

11.25 ns

Table 2. ADSP-2148x Family Features

Feature

ADSP-21483 ADSP-21486

ADSP-21487

ADSP-21488

400 MHz

2/3 Mbits¹

ADSP-21489

450 MHz

Maximum Instruction Rate

RAM

400 MHz

3 Mbits

400 MHz

450 MHz

5 Mbits

ROM

4 Mbits

No

Audio Decoders in ROM²

Pulse-Width Modulation

DTCP Hardware Accelerator

Yes

4 Units (3 Units on 100-Lead Packages)

Contact Analog Devices

External Port Interface (SDRAM, AMI)³Yes (16-bit)

AMI Only

Yes (16-bit)

Serial Ports

8

Direct DMA from SPORTs to

Yes

External Port (External Memory)

FIR, IIR, FFT Accelerator

Watchdog Timer

MediaLB Interface

IDP/PDAP

Yes

Yes (176-Lead Package Only)

Automotive Models Only

Yes

1

UART

DAI (SRU)/DPI (SRU2)

S/PDIF Transceiver

SPI

Yes

TWI

1

SRC Performance⁴

Thermal Diode

VISA Support

–128 dB

Yes

Package³

176-Lead LQFP EPAD

100-Lead LQFP EPAD

176-Lead LQFP EPAD 176-Lead LQFP EPAD 176-Lead LQFP EPAD

88-Lead LFCSP⁵100-Lead LQFP EPAD 100-Lead LQFP EPAD⁵

88-Lead LFCSP⁵88-Lead LFCSP⁵

¹See Ordering Guide on Page 70.

²ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby^®Labs and DTS^®. Decoder/post-processor algorithm

combination support varies depending upon the chip version and the system configurations. Visit www.analog.com for complete information.

³The 100-lead and 88-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin

FunctionDescriptionsonPage 14. TheADSP-21486 processorin the176-leadpackagealso does notcontaina SDRAMcontroller. Formoreinformation, see176-LeadLQFP_EP

Lead Assignment on page 62.

⁴Some models have –140 dB performance. For more information, see Ordering Guide on page 70.

⁵Only available up to 400 MHz. See Ordering Guide on Page 70 for details.

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

The diagram on Page 1 shows the two clock domains that make

up the ADSP-2148x processors. The core clock domain contains

the following features:

SIMD Computational Engine

The ADSP-2148x contains two computational processing ele-

ments that operate as a single-instruction, multiple-data

(SIMD) engine. The processing elements are referred to as PEX

and PEY and each contains an ALU, multiplier, shifter, and reg-

ister file. PEx is always active, and PEy may be enabled by

setting the PEYEN mode bit in the MODE1 register. SIMD

mode allows the processor to execute the same instruction in

both processing elements, but each processing element operates

on different data. This architecture is efficient at executing math

intensive DSP algorithms.

• Two processing elements (PEx, PEy), each of which com-

prises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting 2x64-bit data

transfers between memory and the core at every core pro-

cessor cycle

• One periodic interval timer with pinout

SIMD mode also affects the way data is transferred between

memory and the processing elements because twice the data

bandwidth is required to sustain computational operation in the

processing elements. Therefore, entering SIMD mode also dou-

bles the bandwidth between memory and the processing

elements. When using the DAGs to transfer data in SIMD

mode, two data values are transferred with each memory or reg-

ister file access.

• On-chip SRAM (5 Mbit) and mask-programmable ROM

(4 Mbit)

• JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points which allows flexible exception handling.

The block diagram of the ADSP-2148x on Page 1 also shows the

peripheral clock domain (also known as the I/O processor)

which contains the following features:

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle and are arranged in parallel, maximizing

computational throughput. Single multifunction instructions

execute parallel ALU and multiplier operations. In SIMD mode,

the parallel ALU and multiplier operations occur in both pro-

cessing elements. These computation units support IEEE 32-bit

single-precision floating-point, 40-bit extended precision float-

ing-point, and 32-bit fixed-point data formats.

• IOD0 (peripheral DMA) and IOD1 (external port DMA)

buses for 32-bit data transfers

• Peripheral and external port buses for core connection

• External port with an AMI and SDRAM controller

• 4 units for PWM control

• 1 memory-to-memory (MTM) unit for internal-to-internal

memory transfers

• Digital applications interface that includes four precision

clock generators (PCG), an input data port (IDP/PDAP)

for serial and parallel interconnects, an S/PDIF

receiver/transmitter, four asynchronous sample rate con-

verters, eight serial ports, and a flexible signal routing unit

(DAI SRU).

Timer

The processor contains a core timer that can generate periodic

software interrupts. The core timer can be configured to use

FLAG3 as a timer expired signal.

• Digital peripheral interface that includes two timers, a

2-wire interface (TWI), one UART, two serial peripheral

interfaces (SPI), 2 precision clock generators (PCG), pulse

width modulation (PWM), and a flexible signal routing

unit (DPI SRU2).

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register (16 primary, 16 secondary) register files,

combined with the processor’s enhanced Harvard architecture,

allow unconstrained data flow between computation units and

internal memory. The registers in PEX are referred to as

R0–R15 and in PEY as S0–S15.

As shown in the SHARC core block diagram on Page 5, the

processor uses two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. With its SIMD computational hard-

ware, the processors can perform 2.7 GFLOPS running at

450 MHz.

Context Switch

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result registers all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

FAMILY CORE ARCHITECTURE

The ADSP-2148x is code compatible at the assembly level with

the ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x,

ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first

generation ADSP-2106x SHARC processors. The ADSP-2148x

shares architectural features with the ADSP-2126x, ADSP-

2136x, ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD

SHARC processors, as shown in Figure 2 and detailed in the fol-

lowing sections.

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

S

JTAG

FLAG TIMER INTERRUPT CACHE

SIMD Core

PM ADDRESS 24

PM DATA 48

DMD/PMD 64

5 STAGE

PROGRAM SEQUENCER

DAG2

16x32

DAG1

16x32

PM ADDRESS 32

SYSTEM

I/F

DM ADDRESS 32

PM DATA 64

USTAT

4x32-BIT

PX

64-BIT

DM DATA 64

DATA

SWAP

RF

Rx/Fx

PEx

RF

Sx/SFx

PEy

ALU

SHIFTER

MULTIPLIER

ALU

SHIFTER MULTIPLIER

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MRF

80-BIT

MSF

80-BIT

ASTATy

STYKy

ASTATx

STYKx

Figure 2. SHARC Core Block Diagram

fetches conflict with PM bus data accesses are cached. This

cache allows full speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Universal Registers

These registers can be used for general-purpose tasks. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all peripheral registers (control/status).

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

The data bus exchange register (PX) permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM/DM data bus. These

registers contain hardware to handle the data width difference.

The two data address generators (DAGs) are used for indirect

addressing and implementing circular data buffers in hardware.

Circular buffers allow efficient programming of delay lines and

other data structures required in digital signal processing, and

are commonly used in digital filters and Fourier transforms.

The two DAGs contain sufficient registers to allow the creation

of up to 32 circular buffers (16 primary register sets, 16 second-

ary). The DAGs automatically handle address pointer

wraparound, reduce overhead, increase performance, and sim-

plify implementation. Circular buffers can start and end at any

memory location.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-2148x features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data.

With the its separate program and data memory buses and on-

chip instruction cache, the processor can simultaneously fetch

four operands (two over each data bus) and one instruction

(from the cache), all in a single cycle.

Instruction Cache

Flexible Instruction Set

The processor includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

processor can conditionally execute a multiply, an add, and a

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subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory, all in a single

instruction.

SDRAM memory. This support is not extended to the

asynchronous memory interface (AMI). Source modules need

to be built using the VISA option, in order to allow code genera-

tion tools to create these more efficient opcodes.

Variable Instruction Set Architecture (VISA)

On-Chip Memory

In addition to supporting the standard 48-bit instructions from

previous SHARC processors, the ADSP-2148x supports new

instructions of 16 and 32 bits. This feature, called Variable

Instruction Set Architecture (VISA), drops redundant/unused

bits within the 48-bit instruction to create more efficient and

compact code. The program sequencer supports fetching these

16-bit and 32-bit instructions from both internal and external

The ADSP-21483 and the ADSP-21488 processors contain

3 Mbits of internal RAM (Table 3) and the ADSP-21486,

ADSP-21487, and ADSP-21489 processors contain 5 Mbits of

internal RAM (Table 4). Each memory block supports single-

cycle, independent accesses by the core processor and I/O

processor.

Table 3. Internal Memory Space (3 MBits—ADSP-21483/ADSP-21488)¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Instruction Word (48 Bits)

Long Word (64 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

0x0008 0000–0x0008 AAA9

0x0008 0000–0x0008 FFFF

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

0x0008 AAAA–0x0008 BFFF

0x0009 0000–0x0009 1FFF

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 CFFF

0x0008 C000–0x0009 1554

0x0009 2000–0x0009 9FFF

0x0012 4000–0x0013 3FFF

Reserved

0x0004 D000–0x0004 FFFF

0x0009 1555–0x0009 FFFF

0x0009 A000–0x0009 FFFF

0x0013 4000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

0x000A 0000–0x000A AAA9

0x000A 0000–0x000A FFFF

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

0x000A AAAA–0x000A BFFF

0x000B 0000–0x000B 1FFF

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 CFFF

0x000A C000–0x000B 1554

0x000B 2000–0x000B 9FFF

0x0016 4000–0x0017 3FFF

Reserved

0x0005 D000–0x0005 FFFF

0x000B 1555–0x000B FFFF

0x000B A000–0x000B FFFF

0x0017 4000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 1FFF

0x000C 0000–0x000C 2AA9

0x000C 0000–0x000C 3FFF

0x0018 0000–0x0018 7FFF

Reserved

0x0006 2000– 0x0006 FFFF

0x000C 2AAA–0x000D FFFF

0x000C 4000–0x000D FFFF

0x0018 8000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 1FFF

0x000E 0000–0x000E 2AA9

0x000E 0000–0x000E 3FFF

0x001C 0000–0x001C 7FFF

Reserved

0x0007 2000–0x0007 FFFF

0x000E 2AAA–0x000F FFFF

0x000E 4000–0x000F FFFF

0x001C 8000–0x001F FFFF

¹Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Contact your Analog Devices

sales representative for additional details.

The processor’s SRAM can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data, 106.7k

words of 48-bit instructions (or 40-bit data), or combinations of

different word sizes up to 5 megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit

floating-point storage format is supported that effectively dou-

bles the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point

formats is performed in a single instruction. While each mem-

ory block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

The memory maps in Table 3 and Table 4 display the internal

memory address space of the processors. The 48-bit space sec-

tion describes what this address range looks like to an

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Table 4. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Instruction Word (48 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

0x0008 0000–0x0008 AAA9

0x0008 0000–0x0008 FFFF

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

0x0008 AAAA–0x0008 BFFF

0x0009 0000–0x0009 1FFF

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 EFFF

0x0008 C000–0x0009 3FFF

0x0009 2000–0x0009 DFFF

0x0012 4000–0x0013 BFFF

Reserved

0x0004 F000–0x0004 FFFF

0x0009 4000–0x0009 FFFF

0x0009 E000–0x0009 FFFF

0x0013 C000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

0x000A 0000–0x000A AAA9

0x000A 0000–0x000A FFFF

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

0x000A AAAA–0x000A BFFF

0x000B 0000–0x000B 1FFF

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 EFFF

0x000A C000–0x000B 3FFF

0x000B 2000–0x000B DFFF

0x0016 4000–0x0017 BFFF

Reserved

0x0005 F000–0x0005 FFFF

0x000B 4000–0x000B FFFF

0x000B E000–0x000B FFFF

0x0017 C000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 3FFF

0x000C 0000–0x000C 5554

0x000C 0000–0x000C 7FFF

0x0018 0000–0x0018 FFFF

Reserved

0x0006 4000– 0x0006 FFFF

0x000C 5555–0x000D FFFF

0x000C 8000–0x000D FFFF

0x0019 0000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 3FFF

0x000E 0000–0x000E 5554

0x000E 0000–0x000E 7FFF

0x001C 0000–0x001C FFFF

Reserved

0x0007 4000–0x0007 FFFF

0x000E 5555–0x0000F FFFF

0x000E 8000–0x000F FFFF

0x001D 0000–0x001F FFFF

¹Some ADSP-2148x processors include a customer-definable ROM block and are not reserved as shown on this table. Contact your Analog Devices sales representative for

additional details.

instruction that retrieves 48-bit memory. The 32-bit section

describes what this address range looks like to an instruction

that retrieves 32-bit memory.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-2148x family contains a rich set of peripherals that

support a wide variety of applications including high quality

audio, medical imaging, communications, military, test equip-

ment, 3D graphics, speech recognition, motor control, imaging,

and other applications.

ROM Based Security

The ADSP-2148x has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code. When using this

feature, the processor does not boot-load any external code, exe-

cuting exclusively from internal ROM. Additionally, the

processor is not freely accessible via the JTAG port. Instead, a

unique 64-bit key, which must be scanned in through the JTAG

or Test Access Port will be assigned to each customer. The

device will ignore a wrong key. Emulation features are available

after the correct key is scanned.

External Memory

The external port interface supports access to the external mem-

ory through core and DMA accesses. The external memory

address space is divided into four banks. Any bank can be pro-

grammed as either asynchronous or synchronous memory. The

external ports are comprised of the following modules.

• An Asynchronous Memory Interface which communicates

with SRAM, FLASH, and other devices that meet the stan-

dard asynchronous SRAM access protocol. The AMI

supports 6M words of external memory in bank 0 and 8M

words of external memory in bank 1, bank 2, and bank 3.

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming

there are no block conflicts). The total bandwidth is realized

using the DMD and PMD buses (2 × 64-bits, CCLK speed) and

the IOD0/1 buses (2 × 32-bit, PCLK speed).

• A SDRAM controller that supports a glueless interface with

any of the standard SDRAMs. The SDC supports 62M

words of external memory in bank 0, and 64M words of

external memory in bank 1, bank 2, and bank 3. NOTE:

This feature is not available on the ADSP-21486 product.

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• Arbitration logic to coordinate core and DMA transfers

between internal and external memory over the external

port.

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. Note

that 32-bit wide devices are not supported on the SDRAM and

AMI interfaces.

Non-SDRAM external memory address space is shown in

Table 5.

The SDRAM controller address, data, clock, and control pins

can drive loads up to distributed 30 pF. For larger memory sys-

tems, the SDRAM controller external buffer timing should be

selected and external buffering should be provided so that the

load on the SDRAM controller pins does not exceed 30 pF.

Table 5. External Memory for Non-SDRAM Addresses

Size in

Bank

Words

Address Range

Note that the external memory bank addresses shown are for

normal-word (32-bit) accesses. If 48-bit instructions as well as

32-bit data are both placed in the same external memory bank,

care must be taken while mapping them to avoid overlap.

Bank 0

Bank 1

Bank 2

Bank 3

6M

0x0020 0000–0x007F FFFF

0x0400 0000–0x047F FFFF

0x0800 0000–0x087F FFFF

0x0C00 0000–0x0C7F FFFF

8M

SIMD Access to External Memory

The SDRAM controller on the processor supports SIMD access

on the 64-bit EPD (external port data bus) which allows access

to the complementary registers on the PEy unit in the normal

word space (NW). This removes the need to explicitly access the

complimentary registers when the data is in external SDRAM

memory.

External Port

The external port provides a high performance, glueless inter-

face to a wide variety of industry-standard memory devices. The

external port, available on the 176-lead LQFP, may be used to

interface to synchronous and/or asynchronous memory devices

through the use of its separate internal memory controllers. The

first is an SDRAM controller for connection of industry-stan-

dard synchronous DRAM devices while the second is an

asynchronous memory controller intended to interface to a

variety of memory devices. Four memory select pins enable up

to four separate devices to coexist, supporting any desired com-

bination of synchronous and asynchronous device types.

VISA and ISA Access to External Memory

The SDRAM controller on the ADSP-2148x processors sup-

ports VISA code operation which reduces the memory load

since the VISA instructions are compressed. Moreover, bus

fetching is reduced because, in the best case, one 48-bit fetch

contains three valid instructions. Code execution from the tra-

ditional ISA operation is also supported. Note that code

execution is only supported from bank 0 regardless of

VISA/ISA. Table 7 shows the address ranges for instruction

fetch in each mode.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, flash, and EPROM, as well

as I/O devices that interface with standard memory control

lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3

occupy a 8M word window in the processor’s address space but,

if not fully populated, these windows are not made contiguous

by the memory controller logic.

Table 7. External Bank 0 Instruction Fetch

Size in

Access Type Words

Address Range

ISA (NW)

4M

0x0020 0000–0x005F FFFF

0x0060 0000–0x00FF FFFF

VISA (SW)

10M

SDRAM Controller

The SDRAM controller provides an interface of up to four sepa-

rate banks of industry-standard SDRAM devices at speeds up to

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

f

_SDCLK. Fully compliant with the SDRAM standard, each bank has

its own memory select line (MS0–MS3), and can be configured

to contain between 4M bytes and 256M bytes of memory.

SDRAM external memory address space is shown in Table 6.

NOTE: this feature is not available on the ADSP-21486 model.

Table 6. External Memory for SDRAM Addresses

Size in

Bank

Words

Address Range

The entire PWM module has four groups of four PWM outputs

generating 16 PWM outputs in total. Each PWM group pro-

duces two pairs of PWM signals on the four PWM outputs.

Bank 0

Bank 1

Bank 2

Bank 3

62M

0x0020 0000–0x03FF FFFF

0x0400 0000–0x07FF FFFF

0x0800 0000–0x0BFF FFFF

0x0C00 0000–0x0FFF FFFF

64M

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The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms:

single-update mode or double-update mode. In single-update

mode the duty cycle values are programmable only once per

PWM period. This results in PWM patterns that are symmetri-

cal about the midpoint of the PWM period. In double-update

mode, a second updating of the PWM registers is implemented

at the midpoint of the PWM period. In this mode, it is possible

to produce asymmetrical PWM patterns that produce lower

harmonic distortion in three-phase PWM inverters.

another serial port to provide TDM support. One SPORT pro-

vides two transmit signals while the other SPORT provides the

two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard serial mode

• Multichannel (TDM) mode

• I²S mode

• Packed I²S mode

• Left-justified mode

PWM signals can be mapped to the external port address lines

or to the DPI pins.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

MediaLB

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it

into a biphase encoded signal. The serial data input to the

receiver/transmitter can be formatted as left-justified, I²S or

right-justified with word widths of 16, 18, 20, or 24 bits.

The automotive models of the ADSP-2148x processors have an

MLB interface which allows the processor to function as a

media local bus device. It includes support for both 3-pin as well

as 5-pin media local bus protocols. It supports speeds up to

1024 FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical

channels, with up to 124 bytes of data per media local bus frame.

For a list of automotive models, see Automotive Products on

Page 69.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources, such as the

SPORTs, external pins, or the precision clock generators

(PCGs), and are controlled by the SRU control registers.

Digital Applications Interface (DAI)

Asynchronous Sample Rate Converter (SRC)

The digital applications interface (DAI) allows the connection

of various peripherals to any of the DAI pins (DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU).

The asynchronous sample rate converter contains four SRC

blocks and is the same core as that used in the AD1896 192 kHz

stereo asynchronous sample rate converter and provides up to

128 dB SNR. The SRC block is used to perform synchronous or

asynchronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to

convert multichannel audio data without phase mismatches.

Finally, the SRC can be used to clean up audio data from jittery

clock sources such as the S/PDIF receiver.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The DAI includes eight serial ports, four precision clock genera-

tors (PCG), a S/PDIF transceiver, four ASRCs, and an input

data port (IDP). The IDP provides an additional input path to

the SHARC core, configurable as either eight channels of serial

data, or a single 20-bit wide synchronous parallel data acquisi-

tion port. Each data channel has its own DMA channel that is

independent from the processor’s serial ports.

Input Data Port

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

audio channels in I²S, left-justified sample pair, or right-justified

mode.

Serial Ports (SPORTs)

The ADSP-2148x features eight synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

The IDP also provides a parallel data acquisition port (PDAP),

which can be used for receiving parallel data. The PDAP port

has a clock input and a hold input. The data for the PDAP can

be received from DAI pins or from the external port pins. The

PDAP supports a maximum of 20-bit data and four different

packing modes to receive the incoming data.

Precision Clock Generators

Serial ports can support up to 16 transmit or 16 receive DMA

channels of audio data when all eight SPORTs are enabled, or

four full duplex TDM streams of 128 channels per frame.

The precision clock generators (PCG) consist of four units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A B, C, and D, are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels. Each of the serial ports can work in conjunction with

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The outputs of PCG A and B can be routed through the DAI

pins and the outputs of PCG C and D can be driven on to the

DAI as well as the DPI pins.

The core timer can be configured to use FLAG3 as a timer

expired signal, and the general-purpose timers have one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables the general-

purpose timer.

Digital Peripheral Interface (DPI)

The ADSP-2148x SHARC processors have a digital peripheral

interface that provides connections to two serial peripheral

interface ports (SPI), one universal asynchronous receiver-

transmitter (UART), 12 flags, a 2-wire interface (TWI), three

PWM modules (PWM3–1), and two general-purpose timers.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I²C bus protocol.

The TWI master incorporates the following features:

Serial Peripheral (Compatible) Interface (SPI)

The SPI is an industry-standard synchronous serial link,

enabling the SPI-compatible port to communicate with other

SPI compatible devices. The SPI consists of two data pins, one

device select pin, and one clock pin. It is a full-duplex synchro-

nous serial interface, supporting both master and slave modes.

The SPI port can operate in a multimaster environment by

interfacing with up to four other SPI-compatible devices, either

acting as a master or slave device. The SPI-compatible periph-

eral implementation also features programmable baud rate and

clock phase and polarities. The SPI-compatible port uses open

drain drivers to support a multimaster configuration and to

avoid data contention.

• 7-bit addressing

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

I/O PROCESSOR FEATURES

The I/O processors provide up to 65 channels of DMA, as well

as an extensive set of peripherals.

UART Port

DMA Controller

The processors provide a full-duplex Universal Asynchronous

Receiver/Transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface

standard. The UART port also includes support for 5 to 8 data

bits, 1 or 2 stop bits, and none, even, or odd parity. The UART

port supports two modes of operation:

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the ADSP-2148x’s internal memory and its serial ports,

the SPI-compatible (serial peripheral interface) ports, the IDP

(input data port), the PDAP, or the UART. The DMA channel

summary is shown in Table 8.

Programs can be downloaded to the ADSP-2148x using DMA

transfers. Other DMA features include interrupt generation

upon completion of DMA transfers and DMA chaining for

automatic linked DMA transfers.

• PIO (programmed I/O)—The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access)—The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

Table 8. DMA Channels

Peripheral

SPORTs

DMA Channels

16

8

IDP/PDAP

SPI

2

UART

2

Timers

External Port

Accelerators

Memory-to-Memory

MLB¹

2

The ADSP-2148x has a total of three timers: a core timer that

can generate periodic software interrupts and two general-

purpose timers that can generate periodic interrupts and be

independently set to operate in one of three modes:

2

31

¹Automotive models only.

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

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Delay Line DMA

Table 9. Boot Mode Selection, 176-Lead Package

The processor provides delay line DMA functionality. This

allows processor reads and writes to external delay line buffers

(and hence to external memory) with limited core interaction.

BOOT_CFG2–0 Booting Mode

000

001

010

011

SPI Slave Boot

SPI Master Boot

Scatter/Gather DMA

AMI User Boot (for 8-bit Flash Boot)

The processor provides scatter/gather DMA functionality. This

allows processor DMA reads/writes to/from non contiguous

memory blocks.

No boot (processor executes from internal

ROM after reset)

1xx

Reserved

FFT Accelerator

Table 10. Boot Mode Selection, 100-Lead Package

The FFT accelerator implements a radix-2 complex/real input,

complex output FFT with no core intervention. The FFT accel-

erator runs at the peripheral clock frequency.

BOOT_CFG1–0 Booting Mode

00

01

10

11

SPI Slave Boot

SPI Master Boot

Reserved

FIR Accelerator

The FIR (finite impulse response) accelerator consists of a 1024

word coefficient memory, a 1024 word deep delay line for the

data, and four MAC units. A controller manages the accelerator.

The FIR accelerator runs at the peripheral clock frequency.

No boot (processor executes from internal

ROM after reset)

The “Running Reset” feature allows a user to perform a reset of

the processor core and peripherals, but without resetting the

PLL and SDRAM controller, or performing a boot. The

functionality of the RESETOUT/RUNRSTIN pin has now been

extended to also act as the input for initiating a Running Reset.

For more information, see the hardware reference manual.

IIR Accelerator

The IIR (infinite impulse response) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data, and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency.

Power Supplies

Watchdog Timer

The processors have separate power supply connections for the

internal (V_{DD_INT}) and external (V_{DD_EXT}) power supplies. The

internal supply must meet the V_{DD_INT}specifications. The

external supply must meet the V_{DD_EXT}specification. All exter-

nal supply pins must be connected to the same power supply.

The watchdog timer is used to supervise the stability of the sys-

tem software. When used in this way, software reloads the

watchdog timer in a regular manner so that the downward

counting timer never expires. An expiring timer then indicates

that system software might be out of control.

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V_{DD_INT}and GND.

The 32-bit watchdog timer that can be used to implement a soft-

ware watchdog function. A software watchdog can improve

system reliability by forcing the processor to a known state

through generation of a system reset, if the timer expires before

being reloaded by software. Software initializes the count value

of the timer, and then enables the timer. The watchdog timer

resets both the core and the internal peripherals. Note that this

feature is available on the 176-lead package only.

Static Voltage Scaling (SVS)

Some models of the ADSP-2148x feature Static Voltage Scaling

(SVS) on the V_{DD_INT}power supply. (See the Ordering Guide

on Page 70 for model details.) This voltage specification tech-

nique can provide significant performance benefits including

450 MHz core frequency operation without a significant

increase in power.

SYSTEM DESIGN

SVS optimizes the required V_{DD_INT}voltage for each individual

device to enable enhanced operating frequency up to 450 MHz.

The optimized SVS voltage results in a reduction of maximum

The following sections provide an introduction to system design

options and power supply issues.

I

_{DD_INT}which enables 450 MHz operation at the same or lower

Program Booting

maximum power than 400 MHz operation at a fixed voltage

supply. Implementation of SVS requires a specific voltage regu-

lator circuit design and initialization code.

The internal memory of the ADSP-2148x boots at system

power-up from an 8-bit EPROM via the external port, an SPI

master, or an SPI slave. Booting is determined by the boot con-

figuration (BOOT_CFG2–0) pins in Table 9 for the 176-lead

package and Table 10 for the 100-lead package.

Refer to the Engineer-to-Engineer Note Static Voltage Scaling

for ADSP-2148x SHARC Processors (EE-357) for further infor-

mation. The EE-Note details the requirements and process to

implement a SVS power supply system to enable operation up

to 450 MHz. This applies only to specific products within the

ADSP-2148x family which are capable of supporting 450 MHz

operation.

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Details on power consumption and Static and Dynamic current

consumption can be found at Total Power Dissipation on

Page 20. Also see Operating Conditions on Page 18 for more

information.

systems, file systems, TCP/IP stacks, USB stacks, algorithmic

software modules, and evaluation hardware board support

packages. For more information visit www.analog.com/cces.

The other Analog Devices IDE, VisualDSP++, supports proces-

sor families introduced prior to the release of CrossCore

Embedded Studio. This IDE includes the Analog Devices VDK

real time operating system and an open source TCP/IP stack.

For more information visit www.analog.com/visualdsp. Note

that VisualDSP++ will not support future Analog Devices

processors.

The following are SVS features.

• SVS is applicable only to 450 MHz models (not applicable

to 400 MHz or lower frequency models).

• Each individual SVS device includes a register (SVS_DAT)

containing the unique SVS voltage set at the factory, known

as SVS_NOM

.

EZ-KIT Lite Evaluation Board

• The SVS_NOMvalue is the intended set voltage for the

V_{DD_INT}voltage regulator.

For processor evaluation, Analog Devices provides wide range

of EZ-KIT Lite^®evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Also available are various EZ-Extenders^®, which are

daughter cards delivering additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com and search on “ezkit” or “ezextender”.

• No dedicated pins are required for SVS. The TWI serial bus

is used to communicate SVS_NOMto the voltage regulator.

• Analog Devices recommends a specific voltage regulator

design and initialization code sequence that optimizes the

power-up sequence.

The Engineer-to-Engineer Note Static Voltage Scaling for

ADSP-2148x SHARC Processors (EE-357) contains the

details of the regulator design and the initialization

requirements.

EZ-KIT Lite Evaluation Kits

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user’s PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit. This permits

the customer to download, execute, and debug programs for the

EZ-KIT Lite system. It also supports in-circuit programming of

the on-board Flash device to store user-specific boot code,

enabling standalone operation. With the full version of Cross-

Core Embedded Studio or VisualDSP++ installed (sold

separately), engineers can develop software for supported EZ-

KITs or any custom system utilizing supported Analog Devices

processors.

• Any differences from the Analog Devices recommended

programmable regulator design must be reviewed by Ana-

log Devices to ensure that it meets the voltage accuracy and

range requirements.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-2148x pro-

cessors to monitor and control the target board processor

during emulation. Analog Devices DSP Tools product line of

JTAG emulators provides emulation at full processor speed,

allowing inspection and modification of memory, registers, and

processor stacks. The processor’s JTAG interface ensures that

the emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate emulator hardware user’s guide.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend its capabilities

and reduce development time. Add-ins include board support

packages for evaluation hardware, various middleware pack-

ages, and algorithmic modules. Documentation, help,

configuration dialogs, and coding examples present in these

add-ins are viewable through the CrossCore Embedded Studio

IDE once the add-in is installed.

DEVELOPMENT TOOLS

Analog Devices supports its processors with a complete line of

software and hardware development tools, including integrated

development environments (which include CrossCore^®Embed-

ded Studio and/or VisualDSP++^®), evaluation products,

emulators, and a wide variety of software add-ins.

Integrated Development Environments (IDEs)

Board Support Packages for Evaluation Hardware

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers two IDEs.

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

Board Support Packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product. The link is found in the Product Download

area of the product web page.

TM

CrossCore Embedded Studio is based on the Eclipse frame-

work. Supporting most Analog Devices processor families, it is

the IDE of choice for future processors, including multicore

devices. CrossCore Embedded Studio seamlessly integrates

available software add-ins to support real time operating

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Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The application signal chains page in the Circuits from the Lab^®

site (http:\\www.analog.com\circuits) provides:

Middleware Packages

Analog Devices separately offers middleware add-ins such as

real time operating systems, file systems, USB stacks, and

TCP/IP stacks. For more information see the following web

pages:

• www.analog.com/ucos3

• www.analog.com/ucfs

• www.analog.com/ucusbd

• www.analog.com/lwip

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

Algorithmic Modules

• Reference designs applying best practice design techniques

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with both CrossCore Embedded Studio and

VisualDSP++. For more information visit www.analog.com and

search on “Blackfin software modules” or “SHARC software

modules”.

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The emu-

lator accesses the processor’s internal features via the

processor’s TAP, allowing the developer to load code, set break-

points, and view variables, memory, and registers. The

processor must be halted to send data and commands, but once

an operation is completed by the emulator, the DSP system is set

to run at full speed with no impact on system timing. The emu-

lators require the target board to include a header that supports

connection of the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see Analog Devices JTAG

Emulation Technical Reference (EE-68). This document is

updated regularly to keep pace with improvements to emulator

support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2148x

architecture and functionality. For detailed information on the

ADSP-2148x family core architecture and instruction set, refer

to the programming reference manual.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena.

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PIN FUNCTION DESCRIPTIONS

Table 11. Pin Descriptions

State

During/

Name

Type

After Reset

Description

ADDR_23–0

I/O/T (ipu)

High-Z/

driven low

(boot)

External Address. The processor outputs addresses for external memory and periph-

erals on these pins. The ADDR pins can be multiplexed to support the external memory

interface address, and FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in

external memory interface mode and FLAG(0–3) pins are in FLAGS mode (default).

When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR_23–4pins

for parallel input data.

DATA_15–0

AMI_ACK

I/O/T (ipu)

I (ipu)

High-Z

External Data. The data pins can be multiplexed to support the external memory

interface data (I/O), and FLAGS_7–0(I/O).

Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait

states to an external memory access. AMI_ACK is used by I/O devices, memory

controllers, or other peripherals to hold off completion of an external memory access.

MS_0–1

O/T (ipu)

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-

spondingbanksofexternalmemory. TheMS_1-0linesaredecodedmemoryaddresslines

that change at the same time as the other address lines. When no external memory

access is occurring the MS_1-0lines are inactive; they are active however when a condi-

tional memory access instruction is executed, when the condition evaluates as true.

The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the

hardware reference manual.

AMI_RD

O/T (ipu)

I/O (ipu)

High-Z

AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word from

external memory.

AMI_WR

AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to

external memory.

FLAG0/IRQ0

FLAG1/IRQ1

FLAG2/IRQ2/MS2

FLAG[0]

INPUT

FLAG0/Interrupt Request0.

FLAG[1]

INPUT

FLAG1/Interrupt Request1.

FLAG[2]

INPUT

FLAG2/Interrupt Request2/Memory Select2.

FLAG3/Timer Expired/Memory Select3.

FLAG3/TMREXP/MS3 I/O (ipu)

FLAG[3]

INPUT

The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full V_{DD_EXT}level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

Rev. H

| Page 14 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 11. Pin Descriptions (Continued)

State

During/

Name

Type

After Reset

Description

SDRAS

O/T (ipu)

High-Z/

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other

driven high

SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS

SDWE

O/T (ipu)

High-Z/

driven high

SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

High-Z/

driven high

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDCKE

SDA10

SDDQM

High-Z/

driven high

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

High-Z/

driven high

SDRAMA10Pin. EnablesapplicationstorefreshanSDRAMinparallelwithnon-SDRAM

accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses.

High-Z/

driven high

DQM Data Mask. SDRAM Input mask signal for write accesses and output mask signal

for read accesses. Input data is masked when DQM is sampled high during a write cycle.

The SDRAM output buffers are placed in a High-Z state when DQM is sampled high

during a read cycle. SDDQM is driven high from reset de-assertion until SDRAM initial-

ization completes. Afterwards it is driven low irrespective of whether any SDRAM

accesses occur or not.

SDCLK

O/T (ipd)

High-Z/

driving

SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See

Figure 40 on Page 55. For models in the 100-lead package, the SDRAM interface should

be disabled to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL

register. For more information, see the hardware reference manual.

DAI _P_20–1

I/O/T (ipu)

High-Z

Digital Applications Interface. These pins provide the physical interface to the DAI

SRU. The DAI SRU configuration registers define the combination of on-chip audio-

centricperipheralinputsoroutputsconnectedtothepinandtothepin’soutputenable.

The configuration registers of these peripherals then determines the exact behavior of

the pin. Any input or output signal present in the DAI SRU may be routed to any of these

pins.

DPI _P_14–1

I/O/T (ipu)

High-Z

Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

The DPI SRU configuration registers define the combination of on-chip peripheral

inputs or outputs connected to the pin and to the pin’s output enable. The configu-

ration registers of these peripherals then determines the exact behavior of the pin. Any

input or output signal present in the DPI SRU may be routed to any of these pins.

WDT_CLKIN

WDT_CLKO

WDTRSTO

THD_P

I

Watchdog Timer Clock Input. This pin should be pulled low when not used.

Watchdog Resonator Pad Output.

O

O (ipu)

Watchdog Timer Reset Out.

I

Thermal Diode Anode. When not used, this pin can be left floating.

Thermal Diode Cathode. When not used, this pin can be left floating.

THD_M

O

The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full V_{DD_EXT}level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

Rev. H

| Page 15 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 11. Pin Descriptions (Continued)

State

During/

Name

Type

After Reset

Description

MLBCLK¹

I

Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-

nized to the MOST network and provides the timing for the entire MLB interface at

49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be

grounded.

MLBDAT¹

MLBSIG¹

I/O/T in 3

pin mode. I

in 5 pin

High-Z

Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and

is received by all other MLB devices including the MLB controller. The MLBDAT line

carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB

controller is not used, this pin should be grounded.

mode.

I/O/T in 3

pin mode. I

in 5 pin

MediaLocalBusSignal. ThisisamultiplexedsignalwhichcarriestheChannel/Address

generated by the MLB Controller, as well as the Command and RxStatus bytes from

MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used,

this pin should be grounded.

mode

MLBDO¹

MLBSO¹

O/T

High-Z

MediaLocalBusDataOutput(in5pinmode). Thispinisusedonlyin5-pinMLBmode.

This serves as the output data pin in 5-pin mode. When the MLB controller is not used,

this pin should be connected to ground.

O/T

Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB

mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is

not used, this pin should be connected to ground.

TDI

I (ipu)

O/T

I (ipu)

I

Test Data Input (JTAG). Provides serial data for the boundary scan logic.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Mode Select (JTAG). Used to control the test state machine.

TDO

TMS

TCK

High-Z

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the device.

TRST

EMU

I (ipu)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the processor.

O (O/D, ipu) High-Z

Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools

product line of JTAG emulators target board connector only.

The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full V_{DD_EXT}level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

Rev. H

| Page 16 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 11. Pin Descriptions (Continued)

State

During/

Name

Type

After Reset

Description

CLK_CFG_1–0

I

Core to CLKIN Ratio Control. These pins set the start up clock frequency.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset. The

allowed values are:

00 = 8:1

01 = 32:1

10 = 16:1

11 = reserved

CLKIN

I

Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures

the processors to use either its internal clock generator or an external clock source.

Connecting the necessary components to CLKIN and XTAL enables the internal clock

generator. Connecting the external clock to CLKIN while leaving XTAL unconnected

configures the processors to use the external clock source such as an external clock

oscillator. CLKIN may not be halted, changed, or operated below the specified

frequency.

XTAL

O

I

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

RESET

Processor Reset. Resets the processor to a known state. Upon deassertion, there is a

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

RESETOUT/

RUNRSTIN

I/O (ipu)

I

Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also

has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL

register. For more information, see the hardware reference manual.

BOOT_CFG_2–0

Boot Configuration Select. These pins select the boot mode for the processor (see

Table 9). The BOOT_CFG pins must be valid before RESET (hardware and software) is

asserted.

The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot

be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The

range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full V_{DD_EXT}level; at typical

conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

¹The MLB pins are only available on the automotive models.

Table 12. Pin List, Power, Ground and Other

Name

V_{DD_INT}

V_{DD_EXT}

GND¹

Type

Description

P

Internal Power Supply

P

I/O Power Supply

G

Ground

V_{DD_THD}

DNC

P

Thermal Diode Power Supply. When not used, this pin can be left floating.

Do Not Connect. Do not make any electrical connection to this pin.

DNC

¹The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the

exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided

in the package.

Rev. H

| Page 17 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SPECIFICATIONS

OPERATING CONDITIONS

266 MHz / 300 MHz / 350 MHz / 400 MHz

450 MHz

Parameter¹Description

Min

Nominal

Max

Min

Nominal Max

Unit

2

V_{DD_INT}

V_{DD_EXT}

V_{DD_THD}

Internal (Core) Supply Voltage 1.05

External (I/O) Supply Voltage 3.13

Thermal Diode Supply Voltage 3.13

1.10

1.15

3.47

3.6

SVS_NOM– 25 mV 1.00 – 1.15 SVS_NOM+ 25 mV

V

3.13

2.0

3.47

3.6

3

V_IH

High Level Input Voltage at

_{DD_EXT}= Max

2.0

V

3

V_IL

Low Level Input Voltage at

V_{DD_EXT}= Min

–0.3

2.2

+0.8

–0.3

2.2

+0.8

V

4

V_{IH_CLKIN}

V_{IL_CLKIN}

High Level Input Voltage at

V_{DD_EXT}= Max

V_{DD_EXT}

+0.8

V_{DD_EXT}

+0.8

Low Level Input Voltage at

V_{DD_EXT}= Min

–0.3

CONSUMER GRADE

T_J

Junction Temperature

88-Lead LFCSP_VQ

0

115

110

N/A⁵

0

N/A⁵

115

°C

Junction Temperature

100-Lead LQFP_EP

Junction Temperature

176-Lead LQFP_EP

INDUSTRIAL GRADE

T_J

Junction Temperature

100-Lead LQFP_EP

–40

+125

N/A⁵

°C

T_J

Junction Temperature

176-Lead LQFP_EP

AUTOMOTIVE GRADE⁶

T_J

Junction Temperature

88-Lead LFCSP_VQ

–40

+125

N/A⁵

°C

Junction Temperature

100-Lead LQFP_EP

Junction Temperature

176-Lead LQFP_EP

¹Specifications subject to change without notice.

²SVS_NOMrefers to the nominal SVS voltage which is set between 1.0 V and 1.15 V at the factory for each individual device. Only the unique SVS_NOMvalue in each chip may be used

for 401 MHz to 450 MHz operation of that chip. This spec lists the possible range of the SVS_NOMvalues for all devices. The initial VDD_INT voltage at power on is 1.1 V nominal

and it transitions to SVS programmed voltage as outlined in Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357).

³Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, AMI_ACK,

MLBCLK, MLBDAT, MLBSIG.

⁴Applies to input pins CLKIN, WDT_CLKIN.

⁵N/A means not applicable.

⁶Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information.

Rev. H

| Page 18 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

ELECTRICAL CHARACTERISTICS

266 MHz / 300 MHz / 350 MHz / 400 MHz / 450 MHz

Parameter¹Description

Conditions

Min

Typ

Max

Unit

2

V_OH

High Level Output

Voltage

@ V_{DD_EXT}= Min,

I

2.4

V

_OH= –1.0 mA³

2

V_OL

Low Level Output

Voltage

@ V_{DD_EXT}= Min,

_OL= 1.0 mA³

0.4

10

V

I

4, 5

I_IH

High Level Input Current @ V_{DD_EXT}= Max,

_IN= V_{DD_EXT}Max

ꢀA

V

4

I_IL

Low Level Input Current @ V_{DD_EXT}= Max, V_IN= 0 V

10

ꢀA

5

I_ILPU

Low Level Input Current @ V_{DD_EXT}= Max, V_IN= 0 V

Pull-up

200

6, 7

I_OZH

Three-State Leakage

Current

@ V_{DD_EXT}= Max,

_IN= V_{DD_EXT}Max

10

ꢀA

V

6

I_OZL

Three-State Leakage

Current

@ V_{DD_EXT}= Max, V_IN= 0 V

@ V_{DD_EXT}= Max,

10

7

I_OZLPU

Three-State Leakage

Current Pull-up

200

8

I_OZHPD

Three-State Leakage

Current Pull-down

V

_IN= V_{DD_EXT}Max

9

I_{DD_INT}

Supply Current (Internal) f_CCLK> 0 MHz

Table 14 + Table 15 mA

× ASF

Supply Current (Internal) V_DDINT= 1.1 V, ASF = 1,

T_J= 25°C

385 / 410 / 450 / 500 / 550

mA

10, 11

C_IN

Input Capacitance

T_J= 25°C

5

pF

1

Specifications subject to change without notice.

²Applies to output and bidirectional pins: ADDR23–0, DATA15–0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT MLBSIG, MLBDAT, MLBDO,

MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1.

³See Output Drive Currents on Page 55 for typical drive current capabilities.

⁴Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

⁵Applies to input pins with internal pull-ups: TRST, TMS, TDI.

⁶Applies to three-statable pin: TDO.

⁷Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

⁸Applies to three-statable pin with pull-down: SDCLK.

⁹See Engineer-to-Engineer Note Estimating Power for ADSP-214xx SHARC Processors (EE-348) for further information.

¹⁰Applies to all signal pins.

¹¹Guaranteed, but not tested.

Rev. H

| Page 19 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Total Power Dissipation

The information in this section should be augmented with the

Engineer-to-Engineer Note Estimating Power for ADSP-214xx

SHARC Processors (EE-348).

Table 13. Activity Scaling Factors (ASF)¹

Activity

Scaling Factor (ASF)

Idle

0.29

0.53

0.61

0.77

0.85

0.93

1.00

1.16

1.25

1.31

Total power dissipation has two components:

Low

1. Internal power consumption is additionally comprised of

two components:

Medium Low

Medium High

Peak Typical (50:50)²

Peak Typical (60:40)²

Peak Typical (70:30)²

High Typical

High

• Static current due to leakage. Table 14 shows the static

current consumption (I_{DD_INT_STATIC}) as a function of

junction temperature (T_J) and core voltage (V_{DD_INT}).

• Dynamic current (I_{DD_INT_DYNAMIC}), due to transistor

switching characteristics and activity level of the pro-

cessor. The activity level is reflected by the Activity

Scaling Factor (ASF), which represents the activity

level of the application code running on the processor

core and having various levels of peripheral and exter-

nal port activity (Table 13).

Peak

¹See the Engineer-to-Engineer Note Estimating Power for ADSP-214xx SHARC

Processors (EE-348) for more information on the explanation of the power

vectors specific to the ASF table.

²Ratio of continuous instruction loop (core) to SDRAM control code reads and

writes.

Dynamic current consumption is calculated by select-

ing the ASF that corresponds most closely with the

user application and then multiplying that with the

dynamic current consumption (Table 15).

2. External power consumption is due to the switching activ-

ity of the external pins.

Table 14. Static Current—I_{DD_INT_STATIC}(mA)¹

V_{DD_INT}(V)

T_J(°C)

–45

–35

–25

–15

–5

0.975 V

68

1.0 V

77

1.025 V

86

1.05 V

96

1.075 V

107

114

125

140

161

188

219

257

303

359

423

500

588

693

816

958

1119

1305

1.10 V

118

126

138

155

177

206

240

280

329

389

458

539

633

746

877

1026

1198

1397

1.125 V

131

1.15 V

144

1.175 V

159

74

83

92

103

113

127

147

171

201

237

279

331

391

464

547

645

761

897

1047

1219

140

154

170

82

92

101

115

133

156

183

216

256

305

361

429

506

599

707

833

975

1138

153

168

185

94

104

121

142

168

199

237

282

334

398

471

559

662

779

914

1067

171

187

205

109

129

152

182

217

259

309

369

437

519

615

727

853

997

194

212

233

+5

225

245

268

+15

+25

+35

+45

+55

+65

+75

+85

+95

+105

+115

+125

261

285

309

305

331

360

358

388

420

421

455

492

495

533

576

582

626

675

682

731

789

802

860

926

942

1007

1179

1372

1601

1083

1266

1473

1716

1103

1285

1498

¹Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 18.

Rev. H

| Page 20 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 15. Dynamic Current in CCLK Domain—I_{DD_INT_DYNAMIC}(mA, with ASF = 1.0)^{1, 2}

f_CCLK

(MHz)

V_{DD_INT}(V)

0.975 V

76

1.0 V

77

1.025 V

81

1.05 V

84

1.075 V

87

1.10 V

88

1.125 V

90

1.15 V

92

1.175 V

95

100

150

200

250

300

350

400

450

117

119

156

195

233

272

309

349

123

161

201

240

278

317

356

126

165

207

246

286

326

365

130

170

212

253

294

335

374

133

174

217

260

302

344

385

136

179

223

266

309

352

394

139

183

229

273

318

361

405

144

188

235

280

325

370

415

153

190

227

263

300

339

¹The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 19.

²Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 18.

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

Stresses at or above those listed in Table 16 may cause perma-

nent damage to the product. This is a stress rating only;

functional operation of the product at these or any other condi-

tions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum

operating conditions for extended periods may affect product

reliability.

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

Table 16. Absolute Maximum Ratings

MAXIMUM POWER DISSIPATION

Parameter

Rating

See Engineer-to-Engineer Note Estimating Power for ADSP-

214xx SHARC Processors (EE-348) for detailed thermal and

power information regarding maximum power dissipation. For

information on package thermal specifications, see Thermal

Characteristics on Page 56.

Internal (Core) Supply Voltage (V_{DD_INT}

)

–0.3 V to +1.32 V

–0.3 V to +3.6 V

External (I/O) Supply Voltage (V_{DD_EXT}

)

Thermal Diode Supply Voltage

(V_{DD_THD}

)

Input Voltage

–0.5 V to +3.6 V

–0.5 V to V_{DD_EXT}+0.5 V

–65°C to +150°C

125°C

Output Voltage Swing

Storage Temperature Range

Junction Temperature While Biased

Rev. H

|

Page 21 of 71

|

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 42 on Page 55 for voltage reference levels.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, the processor core,

and the serial ports. During reset, program the ratio between the

processor’s internal clock frequency and external (CLKIN)

clock frequency with the CLK_CFG1–0 pins.

Switching characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 3). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

PMCTL

(SDCKR)

PMCTL

(PLLBP)

PLL

f

CCLK

f_VCO

INPUT

SDRAM

DIVIDER

CLKIN

DIVIDER

PLL

DIVIDER

LOOP

FILTER

VCO

f_CCLK

SDCLK

XTAL

BUF

CLK_CFGx/

PMCTL (2 × PLLM)

PMCTL

(PLLD)

PMCTL

(INDIV)

PCLK

DIVIDE

BY 2

PMCTL

(PLLBP)

f_VCO÷ (2 × PLLM)

PCLK

CCLK

CLKOUT (TEST ONLY)*

DELAY OF

4096 CLKIN

CYCLES

BUF

RESETOUT

CORESRST

RESETOUT

RESET

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f_INPUT.

THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

Figure 3. Core Clock and System Clock Relationship to CLKIN

Voltage Controlled Oscillator (VCO)

where:

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

f_VCOspecified in Table 19.

f_VCO= VCO output

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

• The product of CLKIN and PLLM must never exceed 1/2 of

f_VCO(max) in Table 19 if the input divider is not enabled

(INDIV = 0).

PLLD = 2, 4, 8, or 16 based on the divider value programmed on

the PMCTL register. During reset this value is 2.

• The product of CLKIN and PLLM must never exceed f_VCO

(max) in Table 19 if the input divider is enabled

(INDIV = 1).

f

_INPUT= is the input frequency to the PLL.

_INPUT= CLKIN when the input divider is disabled or

_INPUT= CLKIN ÷ 2 when the input divider is enabled

The VCO frequency is calculated as follows:

f

_VCO= 2 × PLLM × f_INPUT

_CCLK= (2 × PLLM × f_INPUT) ÷ PLLD

Rev. H

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Page 22 of 71

|

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in Table 17. All

of the timing specifications for the ADSP-2148x peripherals are

defined in relation to t_PCLK. See the peripheral specific section

for each peripheral’s timing information.

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 18. While no specific power-up sequencing is required

between V_{DD_EXT}and V_{DD_INT}, there are some considerations

that system designs should take into account.

• No power supply should be powered up for an extended

period of time (> 200 ms) before another supply starts to

ramp up.

Table 17. Clock Periods

Timing

Requirements

Description

• If the V_{DD_INT}power supply comes up after V_{DD_EXT}, any

pin, such as RESETOUT and RESET, may actually drive

momentarily until the V_{DD_INT}rail has powered up.

Systems sharing these signals on the board must determine

if there are any issues that need to be addressed based on

this behavior.

t_CK

CLKIN Clock Period

t_CCLK

t_PCLK

t_SDCLK

Processor Core Clock Period

Peripheral Clock Period = 2 × t_CCLK

SDRAM Clock Period = (t_CCLK) × SDCKR

Note that during power-up, when the V_{DD_INT}power supply

comes up after V_{DD_EXT}, a leakage current of the order of three-

state leakage current pull-up, pull-down may be observed on

any pin, even if that is an input only (for example the RESET

pin) until the V_{DD_INT}rail has powered up.

Figure 3 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the hardware reference manual.

Table 18. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_{DD_EXT}or V_{DD_INT}On

V_{DD_INT}On Before V_{DD_EXT}

0

ms

ꢀs

t_IVDDEVDD

–200

+200

200

1

t_CLKVDD

CLKIN Valid After V_{DD_INT}and V_{DD_EXT}Valid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

0

t_CLKRST

10²

20³

t_PLLRST

ꢀs

Switching Characteristic

4, 5

t_CORERST

Core Reset Deasserted After RESET Deasserted

4096 × t_CK+ 2 × t_CCLK

¹Valid V_{DD_INT}and V_{DD_EXT}assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary

from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Based on CLKIN cycles.

⁴Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

⁵The 4096 cycle count depends on t_SRSTspecification in Table 20. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

t_RSTVDD

RESET

V

DDINT

t_IVDDEVDD

V

DDEXT

t_CLKVDD

CLKIN

t_CLKRST

CLK_CFG1–0

RESETOUT

t_PLLRST

t_CORERST

Figure 4. Power-Up Sequencing

Clock Input

Table 19. Clock Input

266 MHz

300 MHz

350 MHz

400 MHz

450 MHz

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Timing Requirements

t_CK

CLKIN Period

30¹

15

100²

45

26.66¹100²

22.8¹100²

20¹

10

100²

45

17.75¹100²

ns

t_CKL

t_CKH

t_CKRF

t_CCLK

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK Period

13

45

11

45

3

8.875

45

ns

15

45

10

45

ns

3

4

3

ns

3.75

200

10

3.33

200

10

2.85

200

10

800

2.5

10

2.22

200

10

ns

5

f_VCO

VCO Frequency

800

+250

800

+250

200

800

+250

900

+250

MHz

ps

6, 7

t_CKJ

CLKIN Jitter Tolerance

–250

–250 +250 –250

–250

¹Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.

²Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.

³Guaranteed by simulation but not tested on silicon.

⁴Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

⁵See Figure 3 on Page 22 for VCO diagram.

.

⁶Actual input jitter should be combined with ac specifications for accurate timing analysis.

⁷Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

t_CKJ

t_CK

CLKIN

t_CKH

t_CKL

Figure 5. Clock Input

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Clock Signals

The ADSP-2148x can use an external clock or a crystal. See the

operating in fundamental mode. Note that the clock rate is

achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1

(CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve

the full core clock rate, programs need to configure the multi-

plier bits in the PMCTL register.

CLKIN pin description in Table 11 on Page 14. Programs can

configure the processor to use its internal clock generator by

connecting the necessary components to CLKIN and XTAL.

Figure 6 shows the component connections used for a crystal

ADSP-2148x

R1

ꢀ0ȍꢁ

XTAL

CLKIN

R2

47ȍꢁ

CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1.

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE

POWER. REFER TO CRYSTAL MANUFACTURER’S

SPECIFICATIONS.

C1

22pF

C2

22pF

Y1

25MHz

ꢁTYPICAL VALUES

Figure 6. Recommended Circuit for

Fundamental Mode Crystal Operation

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Reset

Table 20. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

t_SRST

RESET Pulse Width Low

RESET Setup Before CLKIN Low

4 × t_CK

8

ns

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μ while RESET is low, assuming stable

V_DDand CLKIN (not including start-up time of external clock oscillator).

CLKIN

t_WRST

t_SRST

RESET

Figure 7. Reset

Running Reset

The following timing specification applies to

RESETOUT/RUNRSTIN pin when it is configured as

RUNRSTIN.

Table 21. Running Reset

Parameter

Min

Max

Unit

Timing Requirements

t_WRUNRST

t_SRUNRST

Running RESET Pulse Width Low

4 × t_CK

8

ns

Running RESET Setup Before CLKIN High

CLKIN

t_WRUNRST

t_SRUNRST

RUNRSTIN

Figure 8. Running Reset

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts, as well as the DAI_P20–1 and

DPI_P14–1 pins when they are configured as interrupts.

Table 22. Interrupts

Parameter

Min

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

2 × t_PCLK+2

ns

INTERRUPT

INPUTS

t_IPW

Figure 9. Interrupts

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP).

Table 23. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_WCTIM

TMREXP Pulse Width

4 × t_PCLK– 1

ns

t_WCTIM

FLAG3

(TMREXP)

Figure 10. Core Timer

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Timer PWM_OUT Cycle Timing

The following timing specification applies to timer0 and timer1

in PWM_OUT (pulse-width modulation) mode. Timer signals

are routed to the DPI_P14–1 pins through the DPI SRU. There-

fore, the timing specifications provided below are valid at the

DPI_P14–1 pins.

Table 24. Timer PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

t_PWMO

Timer Pulse Width Output

2 × t_PCLK– 1.2

2 × (2³¹– 1) × t_PCLK

ns

t_PWMO

PWM

OUTPUTS

Figure 11. Timer PWM_OUT Timing

Timer WDTH_CAP Timing

The following timing specification applies to timer0 and timer1,

and in WDTH_CAP (pulse-width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the timing specification provided below is valid

at the DPI_P14–1 pins.

Table 25. Timer Width Capture Timing

Parameter

Min

Max

2 × (2³¹– 1) × t_PCLK

Unit

Timing Requirement

t_PWI

Timer Pulse Width

2 × t_PCLK

ns

t_PWI

TIMER

CAPTURE

INPUTS

Figure 12. Timer Width Capture Timing

Rev. H

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Watchdog Timer Timing

Table 26. Watchdog Timer Timing

Parameter

Min

Max

1000

6.4

Unit

Timing Requirement

t_WDTCLKPER

100

ns

Switching Characteristics

t_RST

WDT Clock Rising Edge to Watchdog Timer

RESET Falling Edge

3

ns

t_RSTPW

Reset Pulse Width

64 × t_WDTCLKPER

t_WDTCLKPER

WDT_CLKIN

t_RST

t_RSTPW

WDTRSTO

Figure 13. Watchdog Timer Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to

DAI_PB02_O).

Table 27. DAI/DPI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid

1.5

12

ns

DAI_Pn

DPI_Pn

t_DPIO

DAI_Pm

DPI_Pm

Figure 14. DAI Pin to Pin Direct Routing

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers), there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 28. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIW

t_STRIG

Input Clock Period

t_PCLK× 4

ns

PCGTrigger Setup BeforeFallingEdgeof PCG Input 4.5

Clock

t_HTRIG

PCG Trigger Hold After Falling Edge of PCG Input

Clock

3

ns

Switching Characteristics

t_DPCGIO

PCG Output Clock and Frame Sync Active Edge

2.5

10

Delay After PCG Input Clock

t_DTRIGCLK

PCG Output Clock Delay After PCG Trigger

PCG Frame Sync Delay After PCG Trigger

Output Clock Period

2.5 + (2.5 × t_PCGIP

)

10 + (2.5 × t_PCGIP

)

ns

t_DTRIGFS

2.5 + ((2.5 + D – PH) × t_PCGIP

2 × t_PCGIP– 1

)

10 + ((2.5 + D – PH) × t_PCGIP)

1

t_PCGOW

D = FSxDIV, PH = FSxPHASE. For more information, see the “Precision Clock Generators” chapter in the hardware reference manual.

¹Normal mode of operation.

t_STRIG

t_HTRIG

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

t_PCGIP

DAI_Py

DPI_Py

PCG_CLKx_O

t_DTRIGCLK

t_PCGOW

t_DPCGIO

DAI_Pz

DPI_Pz

PCG_FSx_O

t_DTRIGFS

Figure 15. Precision Clock Generator (Direct Pin Routing)

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Flags

The timing specifications provided below apply to the

DPI_P14–1, ADDR7–0, ADDR23–8, DATA7–0, and FLAG3–0

pins when configured as FLAGS. See Table 11 on Page 14 for

more information on flag use.

Table 29. Flags

Parameter

Min

Max

Unit

ns

Timing Requirement

1

t_FIPW

FLAGs IN Pulse Width

2 × t_PCLK+ 3

Switching Characteristic

1

t_FOPW

FLAGs OUT Pulse Width

2 × t_PCLK– 3

ns

¹This is applicable when the Flags are connected to DPI_P14–1, ADDR7–0, ADDR23–8, DATA7–0 and FLAG3–0 pins.

FLAG

INPUTS

t_FIPW

FLAG

OUTPUTS

t_FOPW

Figure 16. Flags

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SDRAM Interface Timing (166 MHz SDCLK)

The maximum frequency for SDRAM is 166 MHz. For informa-

tion on SDRAM frequency and programming, see the hardware

reference manual, Engineer-to-Engineer Note Interfacing

SDRAM Memories to SHARC Processors (EE-286), and the

SDRAM vendor data sheet.

Table 30. SDRAM Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSDAT

t_HSDAT

DATA Setup Before SDCLK

DATA Hold After SDCLK

0.7

ns

1.23

Switching Characteristics

1

t_SDCLK

SDCLK Period

6

ns

t_SDCLKH

SDCLK Width High

2.2

t_SDCLKL

SDCLK Width Low

2

t_DCAD

Command, ADDR, Data Delay After SDCLK

Command, ADDR, Data Hold After SDCLK

Data Disable After SDCLK

4

2

t_HCAD

1

t_DSDAT

5.3

t_ENSDAT

Data Enable After SDCLK

0.3

¹Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 166 MHz the

SDRAM model with a speed grade of 183 MHz or above should be used. See Engineer-to-Engineer Note Interfacing SDRAM Memories to SHARC Processors (EE-286) for

more information on hardware design guidelines for the SDRAM interface.

²Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

t_SDCLKH

t_SDCLK

SDCLK

t_SSDAT

t_HSDAT

t_SDCLKL

DATA (IN)

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

DATA (OUT)

t_DCAD

t_HCAD

COMMAND/ADDR

(OUT)

Figure 17. SDRAM Interface Timing

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

AMI Read

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 31. AMI Read

Parameter

Min

Max

Unit

Timing Requirements

1, 2, 3

t_DAD

t_DRLD

t_SDS

Address Selects Delay to Data Valid

AMI_RD Low to Data Valid

W + t_SDCLK–5.4

W – 3.2

ns

1, 3

Data Setup to AMI_RD High

2.5

0

4, 5

t_HDRH

Data Hold from AMI_RD High

AMI_ACK Delay from Address, Selects

AMI_ACK Delay from AMI_RD Low

2, 6

t_DAAK

t_SDCLK–9.5 + W

W – 7

4

t_DSAK

Switching Characteristics

t_DRHAAddress Selects Hold After AMI_RD High

RHC + 0.20

t_SDCLK– 3.8

W – 1.4

ns

4

t_DARL

t_RW

Address Selects to AMI_RD Low

AMI_RD Pulse Width

t_RWR

AMI_RD High to AMI_RD Low

HI + t_SDCLK– 1

W = (number of wait states specified in AMICTLx register) × t_SDCLK

.

RHC = (number of Read Hold Cycles specified in AMICTLx register) × t_SDCLK

Where PREDIS = 0

HI = RHC (if IC=0): Read to Read from same bank

HI = RHC + t_SDCLK(if IC>0): Read to Read from same bank

HI = RHC + IC: Read to Read from different bank

HI = RHC + Max (IC, (4 × t_SDCLK)): Read to Write from same or different bank

Where PREDIS = 1

HI = RHC + Max (IC, (4 × t_SDCLK)): Read to Write from same or different bank

HI = RHC + (3 × t_SDCLK): Read to Read from same bank

HI = RHC + Max (IC, (3 × t_SDCLK): Read to Read from different bank

IC = (number of idle cycles specified in AMICTLx register) × t_SDCLK

H = (number of hold cycles specified in AMICTLx register) × tSDCLK

¹Data delay/setup: System must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of MSx, is referenced.

³The maximum limit of timing requirement values for t_DADand t_DRLDparameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not

used.

⁴Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.

⁵Data hold: User must meet t_HDRHin asynchronous access mode. See Test Conditions on Page 55 for the calculation of hold times given capacitive and dc loads.

⁶AMI_ACK delay/setup: User must meet t_DAAK, or t_DSAK, for deassertion of AMI_ACK (low).

Rev. H

| Page 33 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

AMI_ADDR

AMI_MSx

t_DARL

t_RW

t_DRHA

AMI_RD

t_DRLD

t_SDS

t_DAD

t_HDRH

AMI_DATA

t_DSAK

t_RWR

t_DAAK

AMI_ACK

AMI_WR

Figure 18. AMI Read

Rev. H

| Page 34 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

AMI Write

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 32. AMI Write

Parameter

Min

Max

Unit

Timing Requirements

1, 2

t_DAAK

AMI_ACK Delay from Address, Selects

AMI_ACK Delay from AMI_WR Low

t_SDCLK– 9.7 + W

W – 6

ns

1, 3

t_DSAK

Switching Characteristics

2

t_DAWH

Address Selects to AMI_WR Deasserted

t_SDCLK– 3.1+ W

t_SDCLK– 3

ns

2

t_DAWL

t_WW

Address Selects to AMI_WR Low

AMI_WR Pulse Width

W – 1.3

t_DDWH

t_DWHA

t_DWHD

t_DATRWH

Data Setup Before AMI_WR High

Address Hold After AMI_WR Deasserted

Data Hold After AMI_WR Deasserted

Data Disable After AMI_WR Deasserted

AMI_WR High to AMI_WR Low

Data Disable Before AMI_RD Low

Data Enabled to AMI_WR Low

t_SDCLK– 3.7+ W

H + 0.15

H

4

t_SDCLK– 4.3 + H

t_SDCLK– 1.5+ H

2 × t_SDCLK– 6

t_SDCLK– 3.7

t_SDCLK+ 4.9 + H

5

t_WWR

t_DDWR

t_WDE

W = (number of wait states specified in AMICTLx register) × t_SDCLK

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

¹AMI_ACK delay/setup: System must meet t_DAAK, or t_DSAK, for deassertion of AMI_ACK (low).

²The falling edge of MSx is referenced.

³Note that timing for AMI_ACK, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.

⁴See Test Conditions on Page 55 for calculation of hold times given capacitive and dc loads.

⁵For Write to Write: t_SDCLK+ H, for both same bank and different bank. For Write to Read: 3 × t_SDCLK+ H, for the same bank and different banks.

AMI_ADDR

AMI_MSx

t_DAWH

t_DWHA

t_DAWL

t_WW

AMI_WR

t_WWR

t_WDE

t_DATRWH

t_DDWH

t_DDWR

AMI_DATA

t_DSAK

t_DWHD

t_DAAK

AMI_ACK

AMI_RD

Figure 19. AMI Write

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Serial Ports

In slave transmitter mode and master receiver mode, the maxi-

mum serial port frequency is f_PCLK/8. In master transmitter

mode and slave receiver mode, the maximum serial port clock

frequency is f_PCLK/4. To determine whether communication is

possible between two devices at clock speed n, the following

specifications must be confirmed: 1) frame sync delay and frame

sync setup and hold; 2) data delay and data setup and hold; and

3) SCLK width.

Serial port signals (SCLK, frame sync, Data Channel A, Data

Channel B) are routed to the DAI_P20–1 pins using the SRU.

Therefore, the timing specifications provided below are valid at

the DAI_P20–1 pins.

Table 33. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSE

Frame Sync Setup Before SCLK

2.5

(Externally Generated Frame Sync in either Transmit or Receive

Mode)

ns

1

t_HFSE

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in either Transmit or Receive

Mode)

2.5

1

t_SDRE

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

SCLK Width

1.9

ns

1

t_HDRE

t_SCLKW

t_SCLK

2.5

(t_PCLK× 4) ÷ 2 – 1.5

t_PCLK× 4

SCLK Period

Switching Characteristics

2

t_DFSE

Frame Sync Delay After SCLK

(Internally Generated Frame Sync in either Transmit or Receive Mode)

10.25

9

ns

2

t_HOFSE

Frame Sync Hold After SCLK

(InternallyGeneratedFrameSyncineitherTransmitorReceiveMode)

2

ns

2

t_DDTE

Transmit Data Delay After Transmit SCLK

2

t_HDTE

Transmit Data Hold After Transmit SCLK

¹Referenced to sample edge.

²Referenced to drive edge.

Table 34. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSI

Frame Sync Setup Before SCLK

7

(Externally Generated Frame Sync in either Transmit or Receive Mode)

ns

1

t_HFSI

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in either Transmit or Receive Mode)

2.5

ns

t_SDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

7

1

t_HDRI

2.5

Switching Characteristics

2

t_DFSI

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode)

4

ns

2

t_HOFSI

–1

–2

2

t_DFSIR

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)

Transmit Data Delay After SCLK

9.75

3.25

2

t_HOFSIR

2

t_DDTI

2

t_HDTI

Transmit Data Hold After SCLK

t_SCKLIW

Transmit or Receive SCLK Width

2 × t_PCLK– 1.5 2 × t_PCLK+ 1.5 ns

¹Referenced to the sample edge.

²Referenced to drive edge.

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_SDRI

t_HDRI

t_SDRE

t_HDRE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20–1

(SCLK)

DAI_P20–1

(SCLK)

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20–1

(FS)

DAI_P20–1

(FS)

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 20. Serial Ports

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 35. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit Frame Sync or External

8.5

Receive Frame Sync with MCE = 1, MFD = 0

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified, as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

SAMPLE DRIVE

DRIVE

DAI_P20–1

(SCLK)

t_HFSE/I

t_SFSE/I

DAI_P20–1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

2ND BIT

t

Figure 21. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified mode.

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 36. Serial Ports—Enable and Three-State

Parameter

Min

2

Max

Unit

Switching Characteristics

1

t_DDTEN

Data Enable from External Transmit SCLK

ns

1

t_DDTTE

Data Disable from External Transmit SCLK

11.5

1

t_DDTIN

Data Enable from Internal Transmit SCLK

–1.5

¹Referenced to drive edge.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

t_DDTEN

t_DDTTE

DAI_P20–1

(DATA

CHANNEL A/B)

DRIVE EDGE

DAI_P20–1

(SCLK, INT)

t_DDTIN

DAI_P20–1

(DATA

CHANNEL A/B)

Figure 22. Serial Ports—Enable and Three-State

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

The SPORTx_TDV_O output signal (routing unit) becomes

active in SPORT multichannel mode. During transmit slots

(enabled with active channel selection registers) the SPORTx-

_TDV_O is asserted for communication with external devices.

Table 37. Serial Ports—TDV (Transmit Data Valid)

Parameter

Switching Characteristics¹

Min

3

Max

Unit

t_DRDVEN

t_DFDVEN

t_DRDVIN

t_DFDVIN

TDV Assertion Delay from Drive Edge of External Clock

ns

TDV Deassertion Delay from Drive Edge of External Clock

TDV Assertion Delay from Drive Edge of Internal Clock

TDV Deassertion Delay from Drive Edge of Internal Clock

8

2

–1

¹Referenced to drive edge.

DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

TDVx

DAI_P20-1

t_DFDVEN

t_DRDVEN

DRIVE EDGE

DAI_P20–1

(SCLK, INT)

TDVx

DAI_P20-1

t_DFDVIN

t_DRDVIN

Figure 23. Serial Ports—TDM Internal and External Clock

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 38. IDP

signals are routed to the DAI_P20–1 pins using the SRU. There-

fore, the timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 38. Input Data Port (IDP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge

3.8

ns

1

t_SIHFS

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Clock Width

2.5

1

t_SISD

2.5

1

t_SIHD

t_IDPCLKW

t_IDPCLK

2.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can

be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_IDPCLK

t_IDPCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 24. IDP Master Timing

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

PDAP chapter of the hardware reference manual. Note that the

20 bits of external PDAP data can be provided through the

ADDR23–4 pins or over the DAI pins.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 39. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the PDAP, see the

Table 39. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SPHOLD

PDAP_HOLD Setup Before PDAP_CLK Sample Edge

PDAP_HOLD Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before PDAP_CLK Sample Edge

PDAP_DAT Hold After PDAP_CLK Sample Edge

Clock Width

2.5

ns

1

t_HPHOLD

2.5

1

t_PDSD

3.85

1

t_PDHD

2.5

t_PDCLKW

t_PDCLK

(t_PCLK× 4) ÷ 2 – 3

t_PCLK× 4

Clock Period

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

2 × t_PCLK+ 3

ns

2 × t_PCLK– 1.5

1

Source pins of PDAP_DATA are ADDR23–4 or DAI pins. Source pins for PDAP_CLK and PDAP_HOLD are 1) DAI pins; 2) CLKIN through PCG; 3) DAI pins through

PCG; or 4) ADDR3–2 pins.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20–1

(PDAP_CLK)

t_HPHOLD

t_SPHOLD

DAI_P20–1

(PDAP_HOLD)

t_PDHD

t_PDSD

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

t_PDHLDD

t_PDSTRB

DAI_P20–1

(PDAP_STROBE)

Figure 25. PDAP Timing

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Sample Rate Converter—Serial Input Port

The ASRC input signals are routed from the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided in

Table 40 are valid at the DAI_P20–1 pins.

Table 40. ASRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

4

ns

1

t_SRCHFS

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Clock Width

5.5

1

t_SRCSD

4

1

t_SRCHD

t_SRCCLKW

t_SRCCLK

5.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

1

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCSD

t_SRCHD

DAI_P20–1

(SDATA)

Figure 26. ASRC Serial Input Port Timing

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

specification with regard to serial clock. Note that serial clock

rising edge is the sampling edge, and the falling edge is the

drive edge.

Sample Rate Converter—Serial Output Port

For the serial output port, the frame sync is an input, and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output has a hold time and delay

Table 41. ASRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

Frame Sync Hold After Serial Clock Rising Edge

Clock Width

4

ns

1

t_SRCHFS

t_SRCCLKW

t_SRCCLK

5.5

(t_PCLK× 4) ÷ 2 – 1

t_PCLK× 4

Clock Period

Switching Characteristics

1

t_SRCTDD

Transmit Data Delay After Serial Clock Falling Edge

Transmit Data Hold After Serial Clock Falling Edge

9.9

ns

1

t_SRCTDH

1

¹The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

DAI_P20–1

(SCLK)

t_SRCCLKW

t_SRCSFS

t_SRCHFS

DAI_P20–1

(FS)

t_SRCTDD

t_SRCTDH

DAI_P20–1

(SDATA)

Figure 27. ASRC Serial Output Port Timing

Rev. H

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Pulse-Width Modulation Generators (PWM)

The following timing specifications apply when the

ADDR23–8/DPI_14–1 pins are configured as PWM.

Table 42. Pulse-Width Modulation (PWM) Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_PWMW

t_PWMP

PWM Output Pulse Width

PWM Output Period

t_PCLK– 2

(2¹⁶– 2) × t_PCLK

(2¹⁶– 1) × t_PCLK

ns

2 × t_PCLK– 1.5

t_PWMW

PWM

OUTPUTS

t_PWMP

Figure 28. PWM Timing

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left-justified, I²S, or right-justified with word widths of 16, 18,

20, or 24 bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 29 shows the right-justified mode. Frame sync is high for

the left channel and low for the right channel. Data is valid on

the rising edge of serial clock. The MSB is delayed the minimum

in 24-bit output mode or the maximum in 16-bit output mode

from a frame sync transition, so that when there are 64 serial

clock periods per frame sync period, the LSB of the data is right-

justified to the next frame sync transition.

Table 43. S/PDIF Transmitter Right-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

t_RJD

Frame Sync to MSB Delay in Right-Justified Mode

16-Bit Word Mode

16

14

12

8

SCLK

18-Bit Word Mode

20-Bit Word Mode

24-Bit Word Mode

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_RJD

DAI_P20–1

SDATA

LSB

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 29. Right-Justified Mode

Rev. H

| Page 45 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Figure 30 shows the default I²S-justified mode. The frame sync

is low for the left channel and HI for the right channel. Data is

valid on the rising edge of serial clock. The MSB is left-justified

to the frame sync transition but with a delay.

Table 44. S/PDIF Transmitter I²S Mode

Parameter

Timing Requirement

t_I2SD

Nominal

Unit

Frame Sync to MSB Delay in I²S Mode

1

SCLK

LEFT/RIGHT CHANNEL

DAI_P20–1

FS

DAI_P20–1

SCLK

t_I2SD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 30. I²S-Justified Mode

Figure 31 shows the left-justified mode. The frame sync is high

for the left channel and low for the right channel. Data is valid

on the rising edge of serial clock. The MSB is left-justified to the

frame sync transition with no delay.

Table 45. S/PDIF Transmitter Left-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

t_LJD

Frame Sync to MSB Delay in Left-Justified Mode

0

SCLK

DAI_P20–1

FS

LEFT/RIGHT CHANNEL

DAI_P20–1

SCLK

t_LJD

DAI_P20–1

SDATA

MSB

MSB–1 MSB–2

LSB+2 LSB+1

LSB

Figure 31. Left-Justified Mode

Rev. H

| Page 46 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 46. Input signals are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 46. S/PDIF Transmitter Input Data Timing

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

Frame Sync Setup Before Serial Clock Rising Edge

3

ns

1

t_SIHFS

Frame Sync Hold After Serial Clock Rising Edge

Data Setup Before Serial Clock Rising Edge

Data Hold After Serial Clock Rising Edge

Transmit Clock Width

3

1

t_SISD

3

1

t_SIHD

3

t_SITXCLKW

t_SITXCLK

t_SISCLKW

t_SISCLK

9

Transmit Clock Period

20

36

80

Clock Width

Clock Period

¹The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SITXCLKW

t_SITXCLK

DAI_P20–1

(TxCLK)

t_SISCLK

t_SISCLKW

DAI_P20–1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20–1

(FS)

t_SISD

t_SIHD

DAI_P20–1

(SDATA)

Figure 32. S/PDIF Transmitter Input Timing

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter requires an oversampling clock input.

This high frequency clock (TxCLK) input is divided down to

generate the internal biphase clock.

Table 47. Oversampling Clock (TxCLK) Switching Characteristics

Parameter

Max

Unit

MHz

kHz

Frequency for TxCLK = 384 × Frame Sync

Frequency for TxCLK = 256 × Frame Sync

Frame Rate (FS)

Oversampling Ratio × Frame Sync ≤ 1/t_SITXCLK

49.2

192.0

Rev. H

|

Page 47 of 71

|

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 48. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

Frame Sync Delay After Serial Clock

Frame Sync Hold After Serial Clock

Transmit Data Delay After Serial Clock

Transmit Data Hold After Serial Clock

Transmit Serial Clock Width

5

ns

t_HOFSI

t_DDTI

t_HDTI

–2

1

t_SCLKIW

8 × t_PCLK– 2

¹SCLK frequency is 64 × FS where FS = the frequency of frame sync.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20–1

(SCLK)

t_DFSI

t_HOFSI

DAI_P20–1

(FS)

t_DDTI

t_HDTI

DAI_P20–1

(DATA CHANNEL

A/B)

Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SPI Interface—Master

The ADSP-2148x contains two SPI ports. Both primary and sec-

ondary are available through DPI only. The timing provided in

Table 49 and Table 50 applies to both.

Table 49. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

Timing Requirements

t_SSPIDM

Min

Max

Unit

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

8.2

2

ns

t_HSPIDM

Switching Characteristics

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × t_PCLK– 2

4 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

DPI Pin (SPI Device Select) Low to First SPICLK Edge

Last SPICLK Edge to DPI Pin (SPI Device Select) High

Sequential Transfer Delay

2.5

4 × t_PCLK– 2

4 × t_PCLK– 1.2

t_SPITDM

DPI

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

(INPUT)

t_DDSPIDM

t_HDSPIDM

MOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

CPHASE = 0

MISO

(INPUT)

Figure 34. SPI Master Timing

Rev. H

| Page 49 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SPI Interface—Slave

Table 50. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

Timing Requirements

t_SPICLKS

Min

Max

Unit

Serial Clock Cycle

4 × t_PCLK– 2

2 × t_PCLK– 2

2 × t_PCLK

ns

t_SPICHS

Serial Clock High Period

Serial Clock Low Period

t_SPICLS

t_SDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

t_HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

Data Input Valid to SPICLK edge (Data Input Set-up Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE=0)

2 × t_PCLK

ns

t_SSPIDS

2

t_HSPIDS

2

t_SDPPW

2 × t_PCLK

Switching Characteristics

t_DSOE

SPIDS Assertion to Data Out Active

0

7.5

ns

1

t_DSOE

SPIDS Assertion to Data Out Active (SPI2)

7.5

t_DSDHI

SPIDS Deassertion to Data High Impedance

SPIDS Deassertion to Data High Impedance (SPI2)

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE = 0)

10.5

9.5

1

t_DSDHI

t_DDSPIDS

t_HDSPIDS

t_DSOV

2 × t_PCLK

5 × t_PCLK

¹The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the “Serial Peripheral Interface Port” chapter of

the hardware reference manual.

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0,

CP = 1)

(INPUT)

t_SDSCO

t_DSOE

t_DSDHI

t_HDSPIDS

t_DDSPIDS

MISO

(OUTPUT)

t_SSPIDSt_HSPIDS

CPHASE = 1

MOSI

(INPUT)

t_HDSPIDS

t_DSDHI

MISO

(OUTPUT)

t_DSOV

t_HSPIDS

CPHASE = 0

t_SSPIDS

MOSI

(INPUT)

Figure 35. SPI Slave Timing

Rev. H

| Page 50 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Media Local Bus

All the numbers given are applicable for all speed modes

(1024 FS, 512 FS and 256 FS for 3-pin; 512 FS and 256 FS for

5-pin), unless otherwise specified. Refer to the MediaLB specifi-

cation document revision 3.0 for more details.

Table 51. MLB Interface, 3-Pin Specifications

Parameter

Min

Typ

Max

Unit

3-Pin Characteristics

t_MLBCLK

MLB Clock Period

1024 FS

20.3

40

81

ns

512 FS

256 FS

t_MCKL

MLBCLK Low Time

1024 FS

6.1

14

30

ns

512 FS

256 FS

t_MCKH

MLBCLK High Time

1024 FS

9.3

14

30

ns

512 FS

256 FS

t_MCKR

MLBCLK Rise Time (V_ILto V_IH)

1024 FS

1

3

ns

512 FS/256 FS

t_MCKF

MLBCLK Fall Time (V_IHto V_IL)

1024 FS

1

3

ns

512 FS/256 FS

1

t_MPWV

MLBCLK Pulse Width Variation

1024 FS

0.7

2.0

nspp

512 FS/256

t_DSMCF

t_DHMCF

t_MCFDZ

t_MCDRV

DAT/SIG Input Setup Time

1

2

0

ns

DAT/SIG Input Hold Time

DAT/SIG Output Time to Three-state

DAT/SIG Output Data Delay From MLBCLK Rising Edge

15

8

2

t_MDZH

Bus Hold Time

1024 FS

512 FS/256

2

4

ns

C_MLB

DAT/SIG Pin Load

1024 FS

40

60

pf

512 FS/256

¹Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).

²The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be

minimized while meeting the maximum capacitive load listed.

Rev. H

| Page 51 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

MLBSIG/

MLBDAT

VALID

(Rx, Input)

t_DHMCF

t_DSMCF

t_MCKH

t_MCKL

MLBCLK

t_MCKR

t_MCKF

t_MLBCLK

t_MCFDZ

t_MCDRV

t_MDZH

MLBSIG/

MLBDAT

VALID

(Tx, Output)

Figure 36. MLB Timing (3-Pin Interface)

Table 52. MLB Interface, 5-Pin Specifications

Parameter

Min

Typ

Max

Unit

5-Pin Characteristics

t_MLBCLK

MLB Clock Period

512 FS

40

81

ns

256 FS

t_MCKL

MLBCLK Low Time

512 FS

15

30

ns

256 FS

t_MCKH

MLBCLK High Time

512 FS

15

30

ns

256 FS

t_MCKR

t_MCKF

MLBCLK Rise Time (V_ILto V_IH)

MLBCLK Fall Time (V_IHto V_IL)

MLBCLK Pulse Width Variation

DAT/SIG Input Setup Time

DAT/SIG Input Hold Time

6

2

ns

1

t_MPWV

nspp

ns

2

t_DSMCF

3

5

t_DHMCF

t_MCDRV

ns

DS/DO Output Data Delay From MLBCLK Rising Edge

8

ns

3

t_MCRDL

DO/SO Low From MLBCLK High

512 FS

256 FS

10

20

ns

C_MLB

DS/DO Pin Load

40

pf

¹Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).

²Gate Delays due to OR'ing logic on the pins must be accounted for.

³When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,

external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.

Rev. H

| Page 52 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

MLBSIG/

MLBDAT

VALID

(Rx, Input)

t_DHMCF

t_DSMCF

t_MCKH

t_MCKL

MLBCLK

t_MCKR

t_MCKF

t_MLBCLK

t_MCRDL

t_MCDRV

VALID

MLBSO/

MLBDO

(Tx, Output)

Figure 37. MLB Timing (5-Pin Interface)

MLBCLK

t_MPWV

Figure 38. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

For information on the UART port receive and transmit opera-

tions, see the hardware reference manual.

2-Wire Interface (TWI)—Receive and Transmit Timing

For information on the TWI receive and transmit operations,

see the hardware reference manual.

Rev. H

| Page 53 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

JTAG Test Access Port and Emulation

Table 53. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

20

5

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

6

1

t_SSYS

7

1

t_HSYS

t_TRSTW

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

18

4t_CK

10

ns

2

t_DSYS

t_TCK÷ 2 + 7

¹System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG2–0, DAI_Px, DPI_Px, and FLAG3–0.

²System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK and EMU.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 39. IEEE 1149.1 JTAG Test Access Port

Rev. H

| Page 54 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

OUTPUT DRIVE CURRENTS

TESTER PIN ELECTRONICS

Figure 40 shows typical I-V characteristics for the output driv-

50:

V

ers of the ADSP-2148x, and Table 54 shows the pins associated

LOAD

T1

DUT

with each driver. The curves represent the current drive capabil-

ity of the output drivers as a function of output voltage.

OUTPUT

45:

70:

ZO = 50:ꢀ(impedance)

50:

TD = 4.04 ꢀ 1.18 ns

Table 54. Driver Types

0.5pF

4pF

2pF

Driver Type Associated Pins

400:

A

FLAG[0–3], AMI_ADDR[0–23], DATA[0–15],

AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,

SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU, TDO,

RESETOUT, DPI[1–14], DAI[1–20], WDTRSTO,

MLBDAT, MLBSIG, MLBSO, MLBDO, MLBCLK

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

B

SDCLK

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

200

150

100

Figure 41. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

V_OH3.13 V, 125 °C

TYPE B

CAPACITIVE LOADING

TYPE A

50

0

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 41). Figure 45 and Figure 46 show

graphically how output delays and holds vary with load capaci-

tance. The graphs of Figure 43 through Figure 46 may not be

linear outside the ranges shown for Typical Output Delay vs.

Load Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

TYPE A

-

50

100

150

-

TYPE B

V_OL3.13 V, 125 °C

-200

0.5

1.0

1.5

2.0

2.5

3.5

0

3.0

7

SWEEP (V_DDEXT) VOLTAGE (V)

6

TYPE A DRIVE FALL

Figure 40. Typical Drive at Junction Temperature

y = 0.0414x + 0.2661

TYPE A DRIVE RISE

y = 0.0341x + 0.3093

5

TEST CONDITIONS

4

The ac signal specifications (timing parameters) appear in

Table 20 on Page 26 through Table 53 on Page 54. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 41.

TYPE B DRIVE RISE

y = 0.0153x + 0.2131

3

2

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 42. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

TYPE B DRIVE FALL

y = 0.0152x + 0.1882

1

0

25

50

75

100

125

150

175

200

LOAD CAPACITANCE (pF)

Figure 43. Typical Output Rise/Fall Time (20% to 80%, V_{DD_EXT}= Max)

INPUT

OR

1.5V

OUTPUT

Figure 42. Voltage Reference Levels for AC Measurements

Rev. H

|

Page 55 of 71

|

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

THERMAL CHARACTERISTICS

14

The ADSP-2148x processor is rated for performance over the

temperature range specified in Operating Conditions on

12

10

8

TYPE A DRIVE FALL

y = 0.0747x + 0.5154

Page 18.

The JESD51 package thermal characteristics in this section are

provided for package comparison and estimation purposes only.

They are not intended for accurate system temperature calcula-

tion. System thermal simulation is required for accurate

temperature analysis that accounts for all specific 3D system

design features, including, but not limited to other heat sources,

use of heat-sinks, and the system enclosure. Contact Analog

Devices for package thermal models that are intended for use

with thermal simulation tools.

TYPE A DRIVE RISE

y = 0.0571x + 0.5558

TYPE B DRIVE FALL

y = 0.0278x + 0.3138

6

4

TYPE B DRIVE RISE

y = 0.0258x + 0.3684

2

0

25

50

75

100

125

150

175

200

In Table 55, Table 56, and Table 57, airflow measurements com-

ply with JEDEC standards JESD51-2 and JESD51-6, and the

junction-to-board measurement complies with JESD51-8. Test

board design complies with JEDEC standards JESD51-7 (LQF-

P_EP). The junction-to-case measurement complies with MIL-

STD-883. All measurements use a 2S2P JEDEC test board.

LOAD CAPACITANCE (pF)

Figure 44. Typical Output Rise/Fall Time (20% to 80%, V_{DD_EXT}= Min)

4.5

To estimate the junction temperature of a single device while on

a JEDEC 2S2P PCB, use:

TYPE A DRIVE FALL

y = 0.0196x + 1.2945

TYPE A DRIVE RISE

y = 0.0152x + 1.7607

4

3.5

3

T = T

+   P 

JT

D

J

CASE

TYPE B DRIVE RISE

y = 0.0068x + 1.7614

where:

T_J= junction temperature °C

2.5

2

TYPE B DRIVE FALL

y = 0.0074x + 1.421

T

_CASE= case temperature (°C) measured at the top center of the

package

1.5

1

_JT= junction-to-top (of package) characterization parameter

is the typical value from Table 55, Table 56, and Table 57.

0.5

0

P_D= power dissipation

0

25

50

75

100

125

150

175

200

Values of _JAare provided for package comparison and PCB

design considerations. _JAcan be used for a first-order approxi-

mation of T_Jby the equation:

LOAD CAPACITANCE (pF)

Figure 45. Typical Output Rise/Fall Delay (V_{DD_EXT}= Max)

T = T +   P 

J

A

JA

D

9

8

7

6

5

4

3

2

1

0

where:

T_A= ambient temperature °C

TYPE A DRIVE RISE

TYPE A DRIVE FALL

y = 0.0256x + 3.5859

y = 0.0359x + 2.924

TYPE B DRIVE RISE

y = 0.0116x + 3.5697

TYPE B DRIVE FALL

y = 0.0136x + 3.1135

0

25

50

75

100

125

150

175

200

LOAD CAPACITANCE (pF)

Figure 46. Typical Output Rise/Fall Delay (V_{DD_EXT}= Min)

Rev. H

|

Page 56 of 71

|

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Note that the thermal characteristics values provided in

Table 55, Table 56, and Table 57 are modeled values.

Thermal Diode

The ADSP-2148x processors incorporate thermal diode/s to

monitor the die temperature. The thermal diode of is a

grounded collector, PNP Bipolar Junction Transistor (BJT). The

THD_P pin is connected to the emitter and the THD_M pin is

connected to the base of the transistor. These pins can be used

by an external temperature sensor (such as ADM 1021A or

LM86 or others) to read the die temperature of the chip.

Table 55. Thermal Characteristics for 88-Lead LFCSP_VQ

Parameter

_JA

_JMA

_JC

_JT

_JMT

Condition

Typical

22.6

18.2

17.3

7.9

Unit

°C/W

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

The technique used by the external temperature sensor is to

measure the change in VBE when the thermal diode is operated

at two different currents. This is shown in the following

equation:

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.22

0.36

0.44

kT

q

V = n 

 In(N)

-----

Table 56. Thermal Characteristics for 100-Lead LQFP_EP

BE

Parameter

_JA

_JMA

_JC

_JT

_JMT

Condition

Typical

17.8

15.4

14.6

2.4

Unit

°C/W

where:

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

n = multiplication factor close to 1, depending on process

variations

k = Boltzmann’s constant

T = temperature (°C)

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.24

0.37

0.51

q = charge of the electron

N = ratio of the two currents

The two currents are usually in the range of 10 micro Amperes

to 300 micro Amperes for the common temperature sensor

chips available.

Table 57. Thermal Characteristics for 176-Lead LQFP_EP

Parameter

_JA

Condition

Typical

16.9

14.6

13.8

2.3

Unit

°C/W

Table 58 contains the thermal diode specifications using the

transistor model.

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

_JMA

_JC

_JT

_JMT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.21

0.32

0.41

Table 58. Thermal Diode Parameters – Transistor Model¹

Symbol

Parameter

Min

10

Typ

Max

300

Unit

μA

2

I_FW

Forward Bias Current

Emitter Current

Transistor Ideality

Series Resistance

I_E

10

300

μA

3, 4

n_Q

1.012

1.015

0.2

1.017

0.28

3, 5

R_T

0.12

Ω

¹See Engineer-to-Engineer Note Using the On-Chip Thermal Diode on Analog Devices Processors (EE-346).

²Analog Devices does not recommend operation of the thermal diode under reverse bias.

³Specified by design characterization.

⁴The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: I_C= I_S× (e ^qVBE/nqkT–1) where I_S= saturation current,

q = electronic charge, V_BE= voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).

⁵The series resistance (R_T) can be used for more accurate readings as needed.

Rev. H

| Page 57 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

88-LEAD LFCSP_VQ LEAD ASSIGNMENT

Table 59 lists the 88-Lead LFCSP_VQ package lead names.

Table 59. 88-Lead LFCSP_VQ Lead Assignments (Numerical by Lead Number)

Lead Name

CLK_CFG1

BOOT_CFG0

V_{DD_EXT}

Lead No.

Lead Name

V_{DD_EXT}

Lead No.

23

Lead Name

DAI_P10

V_{DD_INT}

Lead No.

45

Lead Name

V_{DD_INT}

FLAG0

V_{DD_INT}

FLAG1

FLAG2

FLAG3

GND

Lead No.

67

1

2

DPI_P08

DPI_P07

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DAI_P03

DPI_P14

V_{DD_INT}

24

46

68

3

25

V_{DD_EXT}

DAI_P20

V_{DD_INT}

47

69

V_{DD_INT}

4

26

48

70

BOOT_CFG1

GND

5

27

49

71

6

28

DAI_P08

DAI_P04

DAI_P14

DAI_P18

DAI_P17

DAI_P16

DAI_P15

DAI_P12

DAI_P11

V_{DD_INT}

50

72

CLK_CFG0

V_{DD_INT}

7

29

51

73

8

30

52

GND

74

CLKIN

9

31

53

V_{DD_EXT}

GND

75

XTAL

10

11

12

13

32

54

76

V_{DD_EXT}

33

55

V_{DD_INT}

TRST

77

V_{DD_INT}

DAI_P13

DAI_P07

DAI_P19

DAI_P01

DAI_P02

V_{DD_INT}

34

56

78

V_{DD_INT}

35

57

EMU

79

RESETOUT/RUNRSTIN 14

36

58

TDO

80

V_{DD_INT}

15

16

17

18

19

20

21

22

37

59

V_{DD_EXT}

V_{DD_INT}

TDI

81

DPI_P01

DPI_P02

DPI_P03

V_{DD_INT}

38

GND

60

82

39

THD_M

THD_P

61

83

V_{DD_EXT}

40

62

TCK

84

V_{DD_INT}

41

V_{DD_THD}

V_{DD_INT}

63

V_{DD_INT}

RESET

TMS

85

DPI_P05

DPI_P04

DPI_P06

DAI_P06

DAI_P05

DAI_P09

42

64

86

43

V_{DD_INT}

65

87

44

V_{DD_INT}

66

V_{DD_INT}

GND

88

89*

* Lead no. 89 is the GND supply (see Figure 47 and Figure 48) for the processor; this pad must be robustly connected to GND for the processor

to function.

Rev. H

| Page 58 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Figure 47 shows the top view of the 88-lead LFCSP_VQ pin

configuration. Figure 48 shows the bottom view.

LEAD 88

LEAD 67

LEAD 1

LEAD 66

LEAD 1 INDICATOR

ADSP-2148x

88-LEAD LFCSP_VQ

TOP VIEW

LEAD 22

LEAD 45

LEAD 23

LEAD 44

Figure 47. 88-Lead LFCSP_VQ Lead Configuration (Top View)

LEAD 67

LEAD 88

LEAD 66

LEAD 1

ADSP-2148x

88-LEAD LFCSP_VQ

GND PAD

LEAD 1 INDICATOR

(LEAD 89)

BOTTOM VIEW

LEAD 45

LEAD 22

LEAD 44

LEAD 23

Figure 48. 88-Lead LFCSP_VQ Lead Configuration (Bottom View)

Rev. H

| Page 59 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

100-LEAD LQFP_EP LEAD ASSIGNMENT

Table 60. 100-Lead LQFP_EP Lead Assignments (Numerical by Lead Number)

Lead Name

V_{DD_INT}

CLK_CFG1

BOOT_CFG0

V_{DD_EXT}

V_{DD_INT}

BOOT_CFG1

GND

Lead No.

Lead Name

V_{DD_EXT}

Lead No.

26

Lead Name

DAI_P10

V_{DD_INT}

Lead No.

51

Lead Name

V_{DD_INT}

FLAG0

V_{DD_INT}

FLAG1

FLAG2

FLAG3

MLBCLK

MLBDAT

MLBDO

V_{DD_EXT}

MLBSIG

V_{DD_INT}

MLBSO

TRST

Lead No.

76

1

2

DPI_P08

DPI_P07

V_{DD_INT}

27

52

77

3

28

V_{DD_EXT}

DAI_P20

V_{DD_INT}

53

78

4

29

54

79

5

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DAI_P03

DPI_P14

V_{DD_INT}

30

55

80

6

31

DAI_P08

DAI_P04

DAI_P14

DAI_P18

DAI_P17

DAI_P16

DAI_P15

DAI_P12

V_{DD_INT}

56

81

7

32

57

82

DNC

8*

9*

10

11

12

13

14

15

16

33

58

83

DNC

34

59

84

CLK_CFG0

V_{DD_INT}

CLKIN

35

60

85

36

61

86

37

62

87

XTAL

V_{DD_INT}

38

63

88

V_{DD_EXT}

V_{DD_INT}

39

64

89

DAI_P13

DAI_P07

DAI_P19

DAI_P01

DAI_P02

V_{DD_INT}

40

DAI_P11

V_{DD_INT}

65

90

41

66

EMU

91

RESETOUT/RUNRSTIN 17

42

V_{DD_INT}

67

TDO

92

V_{DD_INT}

18

19

20

21

22

23

24

25

43

GND

68

V_{DD_EXT}

V_{DD_INT}

TDI

93

DPI_P01

DPI_P02

DPI_P03

V_{DD_INT}

44

THD_M

THD_P

69

94

45

70

95

V_{DD_EXT}

46

V_{DD_THD}

V_{DD_INT}

71

TCK

96

V_{DD_INT}

47

72

V_{DD_INT}

RESET

TMS

97

DPI_P05

DPI_P04

DPI_P06

DAI_P06

DAI_P05

DAI_P09

48

V_{DD_INT}

73

98

49

V_{DD_INT}

74

99

50

V_{DD_INT}

75

V_{DD_INT}

GND

100

101**

MLB pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. For non-automotive models, these pins should be connected

to ground (GND).

* Do not make any electrical connection to this pin.

** Pin no. 101 (exposed pad) is the GND supply (see Figure 49 and Figure 50) for the processor; this pad must be robustly connected to GND.

Rev. H

| Page 60 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Figure 49 shows the top view of the 100-lead LQFP_EP lead

configuration. Figure 50 shows the bottom view of the 100-lead

LQFP_EP lead configuration.

LEAD 100

LEAD 76

LEAD 1

LEAD 75

LEAD 1 INDICATOR

ADSP-2148x

100-LEAD LQFP_EP

TOP VIEW

LEAD 25

LEAD 51

LEAD 26

LEAD 50

Figure 49. 100-Lead LQFP_EP Lead Configuration (Top View)

LEAD 76

LEAD 100

LEAD 75

LEAD 1

ADSP-2148x

100-LEAD LQFP_EP

GND PAD

LEAD 1 INDICATOR

(LEAD 101)

BOTTOM VIEW

LEAD 51

LEAD 25

LEAD 50

LEAD 26

Figure 50. 100-Lead LQFP_EP Lead Configuration (Bottom View)

Rev. H

| Page 61 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

176-LEAD LQFP_EP LEAD ASSIGNMENT

Table 61. ADSP-21486 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number)

Lead Name

DNC

MS0

Lead No.

1*

2

3*

4

5

6

7

8

Lead Name

V_{DD_EXT}

DPI_P08

DPI_P07

V_{DD_INT}

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DPI_P14

DAI_P03

DNC

V_{DD_EXT}

DNC

V_{DD_INT}

DNC

V_{DD_INT}

DNC

V_{DD_INT}

DNC

WDTRSTO

DNC

V_{DD_EXT}

DAI_P07

DAI_P13

DAI_P19

DAI_P01

DAI_P02

V_{DD_INT}

DNC

V_{DD_EXT}

V_{DD_INT}

DAI_P06

DAI_P05

DAI_P09

Lead No.

45

46

47

48

49

50

51

52

53

54

55

56*

57

58*

59*

60*

61*

62

63*

64*

65

66*

67*

68

69*

70

71*

72

73

74

75

76

77

78

Lead Name

DAI_P10

V_{DD_INT}

V_{DD_EXT}

DAI_P20

V_{DD_INT}

DAI_P08

DAI_P14

DAI_P04

DAI_P18

DAI_P17

DAI_P16

DAI_P12

DAI_P15

V_{DD_INT}

DAI_P11

V_{DD_EXT}

V_{DD_INT}

BOOT_CFG2

V_{DD_INT}

AMI_ACK

GND

THD_M

THD_P

Lead No.

89

90

91

92

93

94

95

96

Lead Name

V_{DD_INT}

FLAG0

FLAG1

FLAG2

GND

FLAG3

GND

V_{DD_EXT}

GND

V_{DD_INT}

TRST

GND

EMU

DATA0

DATA1

DATA2

DATA3

TDO

DATA4

V_{DD_EXT}

DATA5

DATA6

V_{DD_INT}

DATA7

TDI

Lead No.

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159*

160

161

162

163

164

165

166

167

168

169

170

171*

172*

173

174

175*

176

177**

DNC

V_{DD_INT}

CLK_CFG1

ADDR0

BOOT_CFG0

V_{DD_EXT}

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

BOOT_CFG1

GND

9

97

98

99

10

11

12

13

14

15

16

17

18*

19*

20

21

22

23

24

25

26

27*

28

29

30

31

32

33

34

35

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

ADDR6

ADDR7

DNC

ADDR8

ADDR9

CLK_CFG0

V_{DD_INT}

CLKIN

XTAL

ADDR10

DNC

V_{DD_EXT}

V_{DD_INT}

ADDR11

ADDR12

ADDR17

ADDR13

V_{DD_INT}

ADDR18

V_{DD_THD}

V_{DD_INT}

MS1

V_{DD_INT}

DNC

V_{DD_EXT}

DATA8

DATA9

DATA10

TCK

DATA11

DATA12

DATA14

DATA13

V_{DD_INT}

DATA15

DNC

RESET

TMS

DNC

V_{DD_INT}

GND

WDT_CLKO

WDT_CLKIN

V_{DD_EXT}

ADDR23

ADDR22

ADDR21

V_{DD_INT}

ADDR20

ADDR19

V_{DD_EXT}

ADDR16

ADDR15

V_{DD_INT}

79*

80*

81*

82*

83*

84

85

86

87

88

RESETOUT/RUNRSTIN 36

V_{DD_INT}

37

38

39

40

41

42

43

44

DPI_P01

DPI_P02

DPI_P03

V_{DD_INT}

DPI_P05

DPI_P04

DPI_P06

ADDR14

AMI_WR

AMI_RD

* Do not make any electrical connection to this pin.

**Leadno. 177(exposed pad) is the GND supply (seeFigure 51 and Figure 52) for theprocessor; thispadmustbe robustly connected toGND.

Rev. H

| Page 62 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 62. ADSP-21483, ADSP-21487, ADSP-21488, and ADSP-21489 176-Lead LQFP_EP Lead Assignment

(Numerical by Lead Number)

Lead Name

SDDQM

MS0

Lead No.

1

2

3

4

5

6

7

8

Lead Name

V_{DD_EXT}

DPI_P08

DPI_P07

V_{DD_INT}

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DPI_P14

DAI_P03

DNC

V_{DD_EXT}

DNC

V_{DD_INT}

DNC

V_{DD_INT}

DNC

V_{DD_INT}

DNC

WDTRSTO

DNC

V_{DD_EXT}

DAI_P07

DAI_P13

DAI_P19

DAI_P01

DAI_P02

V_{DD_INT}

DNC

V_{DD_EXT}

V_{DD_INT}

DAI_P06

DAI_P05

DAI_P09

Lead No.

45

46

47

48

49

50

51

52

53

54

55

56*

57

58*

59*

60*

61*

62

63*

64*

65

66*

67*

68

69*

70

71*

72

73

74

75

76

77

78

Lead Name

DAI_P10

V_{DD_INT}

V_{DD_EXT}

DAI_P20

V_{DD_INT}

DAI_P08

DAI_P14

DAI_P04

DAI_P18

DAI_P17

DAI_P16

DAI_P12

DAI_P15

V_{DD_INT}

DAI_P11

V_{DD_EXT}

V_{DD_INT}

BOOT_CFG2

V_{DD_INT}

AMI_ACK

GND

THD_M

THD_P

Lead No.

89

90

91

92

93

94

95

96

Lead Name

V_{DD_INT}

FLAG0

FLAG1

FLAG2

GND

FLAG3

GND

V_{DD_EXT}

GND

V_{DD_INT}

TRST

GND

EMU

DATA0

DATA1

DATA2

DATA3

TDO

DATA4

V_{DD_EXT}

DATA5

DATA6

V_{DD_INT}

DATA7

TDI

SDCLK

V_{DD_EXT}

DATA8

DATA9

DATA10

TCK

DATA11

DATA12

DATA14

DATA13

V_{DD_INT}

DATA15

SDWE

SDRAS

RESET

TMS

Lead No.

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177**

SDCKE

V_{DD_INT}

CLK_CFG1

ADDR0

BOOT_CFG0

V_{DD_EXT}

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

BOOT_CFG1

GND

9

97

98

99

10

11

12

13

14

15

16

17

18*

19*

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

ADDR6

ADDR7

DNC

ADDR8

ADDR9

CLK_CFG0

V_{DD_INT}

CLKIN

XTAL

ADDR10

SDA10

V_{DD_EXT}

V_{DD_INT}

ADDR11

ADDR12

ADDR17

ADDR13

V_{DD_INT}

ADDR18

V_{DD_THD}

V_{DD_INT}

MS1

V_{DD_INT}

WDT_CLKO

WDT_CLKIN

V_{DD_EXT}

ADDR23

ADDR22

ADDR21

V_{DD_INT}

ADDR20

ADDR19

V_{DD_EXT}

ADDR16

ADDR15

V_{DD_INT}

79*

80*

81*

82*

83*

84

85

86

87

88

RESETOUT/RUNRSTIN 36

V_{DD_INT}

37

38

39

40

41

42

43

44

DPI_P01

DPI_P02

DPI_P03

V_{DD_INT}

DPI_P05

DPI_P04

DPI_P06

ADDR14

AMI_WR

AMI_RD

SDCAS

V_{DD_INT}

GND

* Do not make any electrical connection to this pin.

**Lead no. 177(exposed pad) is the GND supply (seeFigure 51 and Figure 52) for theprocessor; thispadmustbe robustly connected toGND.

Rev. H

| Page 63 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 63. Automotive Models ADSP-21488, and ADSP-21489 176-Lead LQFP_EP Lead Assignment (Numerical by Lead Number)

Lead Name

SDDQM

MS0

Lead No.

1

2

3

4

5

6

7

8

Lead Name

V_{DD_EXT}

DPI_P08

DPI_P07

V_{DD_INT}

DPI_P09

DPI_P10

DPI_P11

DPI_P12

DPI_P13

DPI_P14

DAI_P03

DNC

V_{DD_EXT}

DNC

V_{DD_INT}

DNC

V_{DD_INT}

DNC

V_{DD_INT}

DNC

WDTRSTO

DNC

V_{DD_EXT}

DAI_P07

DAI_P13

DAI_P19

DAI_P01

DAI_P02

V_{DD_INT}

DNC

V_{DD_EXT}

V_{DD_INT}

DAI_P06

DAI_P05

DAI_P09

Lead No.

45

46

47

48

49

50

51

52

53

54

55

56*

57

58*

59*

60*

61*

62

63*

64*

65

66*

67*

68

69*

70

71*

72

73

74

75

76

77

78

Lead Name

DAI_P10

V_{DD_INT}

V_{DD_EXT}

DAI_P20

V_{DD_INT}

DAI_P08

DAI_P14

DAI_P04

DAI_P18

DAI_P17

DAI_P16

DAI_P12

DAI_P15

V_{DD_INT}

DAI_P11

V_{DD_EXT}

V_{DD_INT}

BOOT_CFG2

V_{DD_INT}

AMI_ACK

GND

THD_M

THD_P

Lead No.

89

90

91

92

93

94

95

96

Lead Name

V_{DD_INT}

FLAG0

FLAG1

FLAG2

MLBCLK

FLAG3

MLBDAT

MLBDO

V_{DD_EXT}

MLBSIG

V_{DD_INT}

TRST

Lead No.

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177**

SDCKE

V_{DD_INT}

CLK_CFG1

ADDR0

BOOT_CFG0

V_{DD_EXT}

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

BOOT_CFG1

GND

9

97

98

99

10

11

12

13

14

15

16

17

18*

19*

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

MLBSO

EMU

DATA0

DATA1

DATA2

DATA3

TDO

DATA4

V_{DD_EXT}

DATA5

DATA6

V_{DD_INT}

DATA7

TDI

SDCLK

V_{DD_EXT}

DATA8

DATA9

DATA10

TCK

DATA11

DATA12

DATA14

DATA13

V_{DD_INT}

DATA15

SDWE

ADDR6

ADDR7

DNC

ADDR8

ADDR9

CLK_CFG0

V_{DD_INT}

CLKIN

XTAL

ADDR10

SDA10

V_{DD_EXT}

V_{DD_INT}

ADDR11

ADDR12

ADDR17

ADDR13

V_{DD_INT}

ADDR18

V_{DD_THD}

V_{DD_INT}

MS1

V_{DD_INT}

WDT_CLKO

WDT_CLKIN

V_{DD_EXT}

ADDR23

ADDR22

ADDR21

V_{DD_INT}

ADDR20

ADDR19

V_{DD_EXT}

ADDR16

ADDR15

V_{DD_INT}

79*

80*

81*

82*

83*

84

85

86

87

88

RESETOUT/RUNRSTIN 36

V_{DD_INT}

37

38

39

40

41

42

43

44

DPI_P01

DPI_P02

DPI_P03

V_{DD_INT}

DPI_P05

DPI_P04

DPI_P06

SDRAS

RESET

TMS

SDCAS

V_{DD_INT}

GND

ADDR14

AMI_WR

AMI_RD

* Do not make any electrical connection to this pin.

**Leadno. 177(exposed pad) is the GND supply (seeFigure 51 and Figure 52) for theprocessor; thispadmustbe robustly connected toGND.

Rev. H

| Page 64 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Figure 51 shows the top view of the 176-lead LQFP_EP lead

configuration. Figure 52 shows the bottom view of the 176-lead

LQFP_EP lead configuration.

LEAD 176

LEAD 133

LEAD 1

LEAD 132

LEAD 1 INDICATOR

ADSP-2148x

176-LEAD LQFP_EP

TOP VIEW

LEAD 44

LEAD 89

LEAD 45

LEAD 88

Figure 51. 176-Lead LQFP_EP Lead Configuration (Top View)

LEAD 133

LEAD 176

LEAD 132

LEAD 1

ADSP-2148x

176-LEAD LQFP_EP

GND PAD

LEAD 1 INDICATOR

(LEAD 177)

BOTTOM VIEW

LEAD 89

LEAD 44

LEAD 88

LEAD 45

Figure 52. 176-Lead LQFP_EP Lead Configuration (Bottom View)

Rev. H

| Page 65 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

OUTLINE DIMENSIONS

The ADSP-2148x processors are available in 88-lead

LFCSP_VQ, 100-lead LQFP_EP, and 176-lead

LQFP_EP RoHS compliant packages.

12.10

12.00 SQ

11.90

0.30

0.23

0.18

0.60 MAX

0.60

MAX

PIN 1

67

66

88

INDICATOR

1

PIN 1

INDICATOR

0.50

BSC

11.85

11.75 SQ

11.65

6.80

6.70 SQ

6.60

EXPOSED

PAD

0.50

0.40

0.30

22

45

44

23

BOTTOM VIEW

TOP VIEW

10.50

REF

0.70

0.65

0.60

12° MAX

*

0.90

0.85

0.75

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.045

0.025

0.005

SECTION OF THIS DATA SHEET.

COPLANARITY

SEATING

PLANE

0.08

0.138~0.194 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-VRRD

EXCEPT FOR MINIMUM THICKNESS AND LEAD COUNT.

Figure 53. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ¹]

(CP-88-5)

Dimensions shown in millimeters

¹For information relating to the exposed pad on the CP-88-5 package, see the table endnote on Page 58.

Rev. H

| Page 66 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

16.20

16.00 SQ

15.80

1.60

14.20

14.00 SQ

13.80

MAX

0.75

0.60

0.45

12.00 REF

100

76

100

1

75

1

1.00 REF

PIN 1

SEATING

PLANE

EXPOSED

PAD

6.00 BSC

SQ

TOP VIEW

BOTTOM VIEW

(PINS UP)

1.45

1.40

1.35

(PINS DOWN)

51

25

51

25

0.20

0.09

26

50

26

50

0.27

0.22

0.17

VIEW A

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

“SURFACE-MOUNT DESIGN” IN

THIS DATA SHEET.

0.50

BSC

LEAD PITCH

0.15

0.05

7°

0°

0.08

COPLANARITY

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD

ROTATED 90° CCW

Figure 54. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]¹

(SW-100-2)

Dimensions shown in millimeters

¹For information relating to the exposed pad on the SW-100-2 package, see the table endnote on Page 60.

26.20

26.00 SQ

25.80

24.10

24.00 SQ

23.90

1.60 MAX

0.75

0.60

0.45

21.50 REF

133

132

133

176

1

132

1

1.00 REF

SEATING

PLANE

PIN 1

EXPOSED

PAD

6.00 BSC

SQ

1.45

1.40

1.35

0.20

0.15

0.09

0.15

0.10

0.05

7°

3.5°

0°

TOP VIEW

BOTTOM VIEW

(PINS UP)

(PINS DOWN)

44

89

0.08

45

88

45

COPLANARITY

0.27

0.22

0.17

VIEW A

0.50

VIEW A

BSC

ROTATED 90° CCW

LEAD PITCH

FOR PROPER CONNECTION

OF THE EXPOSED PAD, REFER

TO “SURFACE-MOUNT DESIGN”

IN THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD

Figure 55. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]¹

(SW-176-2)

Dimensions shown in millimeters

¹For information relating to the exposed pad on the SW-176-2 package, see the table endnote on Page 62.

Rev. H

| Page 67 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SURFACE-MOUNT DESIGN

The exposed pad is required to be electrically and thermally

connected to GND. Implement this by soldering the exposed

pad to a GND PCB land that is the same size as the exposed pad.

The GND PCB land should be robustly connected to the GND

plane in the PCB for best electrical and thermal performance.

No separate GND pins are provided in the package.

Rev. H

| Page 68 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

AUTOMOTIVE PRODUCTS

The following models are available with controlled manufactur-

ing to support the quality and reliability requirements of

automotive applications. Note that these automotive models

may have specifications that differ from the commercial models;

therefore designers should review the Specifications section of

this data sheet carefully. Only the automotive grade products

shown in Table 64 are available for use in automotive applica-

tions. Contact your local Analog Devices account representative

for specific product ordering information and to obtain the spe-

cific Automotive Reliability reports for these models.

Table 64. Automotive Products

Processor

Instruction

Model^{1, 2, 3, 4}

Notes Temperature Range⁵RAM

Rate (Max)

400 MHz

300 MHz

400 MHz

300 MHz

350 MHz

400 MHz

266 MHz

300 MHz

266 MHz

400 MHz

300 MHz

350 MHz

400 MHz

Package Description

100-Lead LQFP_EP

176-Lead LQFP_EP

88-Lead LFCSP_VQ

100-Lead LQFP_EP

176-Lead LQFP_EP

88-Lead LFCSP_VQ

100-Lead LQFP_EP

176-Lead LQFP_EP

Package Option

SW-100-2

SW-176-2

CP-88-5

6

AD21486WBSWZ4Axx

AD21487WBSWZ4Axx

AD21487WBSWZ4Bxx

AD21488WBCPZ2202

AD21488WBCPZ4202

AD21488WBCPZ202

AD21488WBCPZ302

AD21488WBCPZ402

AD21488WBSWZ1Axx

AD21488WBSWZ2Axx

AD21488WBSWZ1Bxx

AD21488WBSWZ2Bxx

AD21488WBSWZ4Bxx

AD21489WBCPZ202

AD21489WBCPZ302

AD21489WBCPZ402

AD21489WBSWZ4xx

AD21489WBSWZ4xxRL

AD21489WBSWZ4Bxx

–40°C to +125°C

5 Mbit

2 Mbit

3 Mbit

2 Mbit

3 Mbit

5 Mbit

6

CP-88-5

SW-100-2

SW-176-2

CP-88-5

SW-100-2

SW-176-2

¹Z =RoHS Compliant Part.

²W = automotive applications.

³xx denotes the current die revision.

⁴RL = Tape and Reel.

⁵Referenced temperature is junction temperature. See Operating Conditions on Page 18 for junction temperature (T_J) specification.

⁶This product contains IP from Dolby, DTS and DTLA. Proper software licenses required. Contact Analog Devices, Inc. for information.

Rev. H

| Page 69 of 71 | February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

ORDERING GUIDE

Processor

Instruction

Model^{1, 2}

Notes Temperature Range³RAM

4

Rate (Max)

300 MHz

350 MHz

400 MHz

300 MHz

350 MHz

400 MHz

300 MHz

350 MHz

400 MHz

450 MHz

350 MHz

400 MHz

Package Description

176-Lead LQFP_EP

100-Lead LQFP_EP

176-Lead LQFP_EP

100-Lead LQFP_EP

176-Lead LQFP_EP

100-Lead LQFP_EP

176-Lead LQFP_EP

100-Lead LQFP_EP

176-Lead LQFP_EP

100-Lead LQFP_EP

176-Lead LQFP_EP

100-Lead LQFP_EP

88-Lead LFCSP_VQ

176-Lead LQFP_EP

100-Lead LQFP_EP

176-Lead LQFP_EP

100-Lead LQFP_EP

176-Lead LQFP_EP

Package Option

SW-176-2

SW-100-2

SW-176-2

SW-100-2

SW-176-2

SW-100-2

SW-176-2

SW-100-2

SW-176-2

SW-100-2

SW-176-2

SW-100-2

CP-88-5

ADSP-21483KSWZ-2B

ADSP-21483KSWZ-3B

ADSP-21483KSWZ-3AB

ADSP-21483KSWZ-4B

ADSP-21483KSWZ-4AB

ADSP-21486KSWZ-2A

ADSP-21486KSWZ-2B

ADSP-21486KSWZ-2AB

ADSP-21486KSWZ-2BB

ADSP-21486KSWZ-3A

ADSP-21486KSWZ-3B

ADSP-21486KSWZ-3AB

ADSP21486KSWZ3ABRL

ADSP-21486KSWZ-3BB

ADSP-21486KSWZ-4A

ADSP-21486KSWZ-4AB

ADSP-21487KCPZ-4

0°C to +110°C

0°C to +115°C

0°C to +110°C

0°C to +115°C

0°C to +115C

–40°C to +125°C

0°C to +110°C

0°C to +110C

–40°C to +125°C

0°C to +110°C

–40°C to +125°C

0°C to +110°C

–40°C to +125°C

0°C to +110°C

3 Mbit

5 Mbit

3 Mbit

4

ADSP-21487KSWZ-2B

ADSP-21487KSWZ-2BB

ADSP-21487KSWZ-3B

ADSP-21487KSWZ-3BB

ADSP-21487KSWZ-4B

ADSP-21487KSWZ-4BB

ADSP-21487KSWZ-5B

ADSP-21487KSWZ-5BB

ADSP21487KSWZ5BBRL

ADSP-21488BSWZ-3A

ADSP-21488KSWZ-3A

ADSP-21488KSWZ-3A1

ADSP-21488KSWZ-3B

ADSP-21488BSWZ-3B

ADSP-21488KSWZ-4A

ADSP-21488BSWZ-4A

ADSP-21488KSWZ-4B

ADSP-21488BSWZ-4B

ADSP-21488KSWZ-4B1

SW-176-2

SW-100-2

SW-176-2

SW-100-2

SW-176-2

4

4, 5

6

Rev. H

|

Page 70 of 71

|

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Processor

Instruction

Model^{1, 2}

Notes Temperature Range³RAM

Rate (Max)

400 MHz

350 MHz

400 MHz

450 MHz

Package Description

88-Lead LFCSP_VQ

100-Lead LQFP_EP

176-Lead LQFP_EP

100-Lead LQFP_EP

176-Lead LQFP_EP

Package Option

CP-88-5

ADSP-21489KCPZ-4

ADSP-21489KSWZ-3A

ADSP-21489BSWZ-3A

ADSP-21489KSWZ-3B

ADSP-21489BSWZ-3B

ADSP-21489KSWZ-4A

ADSP-21489BSWZ-4A

ADSP-21489KSWZ-4B

ADSP-21489BSWZ-4B

ADSP-21489KSWZ-5B

0°C to +115°C

0°C to +110°C

–40°C to +125°C

0°C to +110°C

–40°C to +125°C

0°C to +110°C

–40°C to +125°C

0°C to +110°C

–40°C to +125°C

0°C to +115°C

5 Mbit

SW-100-2

SW-176-2

SW-100-2

SW-176-2

5

¹Z = RoHS compliant part.

²RL = Tape and Reel.

³Referenced temperature is junction temperature. See Operating Conditions on Page 18 for junction temperature (T_J) specification.

⁴The ADSP-21483, ADSP-21486, and ADSP-21487 models are available with factory programmed ROM including the latest multichannel audio decoding and post-processing

algorithms from Dolby Labs and DTS. ROM contents may vary depending on chip version and silicon revision. Visit www.analog.com for complete information.

⁵See Engineer-to-Engineer Note Static Voltage Scaling for ADSP-2148x SHARC Processors (EE-357) for operating ADSP-2148x processors at 450 MHz.

⁶This product contains a –140 dB sample rate converter.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D09018-2/20(H)

Rev. H

| Page 71 of 71 | February 2020


型号：	ADSP-21483
厂家：	ADI
描述：	SHARC Processor
文件：	总71页 (文件大小：1881K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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