ADSP-2178-780244 [ADI]
GSM Baseband Processing Chipset; GSM基带处理芯片组
| 型号： | ADSP-2178-780244 |
| 厂家： | 
ADI |
| 描述： | GSM Baseband Processing Chipset |
| 文件： | 总8页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GSM
a
Baseband Processing Chipset
AD20msp410
SYSTEM ARCH ITECTURE
FEATURES
Passed European GSM Phase I Type Approval
Com plete Baseband Processing Chipset Perform s:
Speech Coding/ Decoding, According to GSM 06.XX
DTMF and Call Progress Tone Generation
Equalization w ith 16-State Viterbi, Soft Decision
Channel Coding/ Decoding According to GSM 05.03
All ADC and DAC Interface Functions
Includes all Radio, Auxiliary and Voice Interfaces
Support for GSM Data Services
ALGORITHM
BASEBAND
SIGNAL
CONVERTER
PROCESSOR
RADIO
SUBSYSTEM
BBC
ASP
PHYSICAL
LAYER
PROCESSOR
PLP
µC
Em bedded 16-Bit Microcontroller
AD20msp410
GSM CHIPSET
Layer 1 Softw are Provided w ith Chipset
Full Phase 2 Protocol Stack Softw are Available
Integrated SIM- and Keyboard Interface
Ultralow Pow er Design
2.7 V Operating Voltage
Intelligent Pow er Managem ent Features
Up to 70 Hours Standby Tim e Achievable
J TAG-Boundary Scan
512K x 16
ROM
128K x 8
RAM
2K x 8
EEPROM
DISPLAY
KEYPAD
SIM
Full Reference Design Available
Three TQFP Devices, Occupying Less than 12 cm 2
APPLICATIONS
GSM/ DCS1800 Mobile Radios and PCMCIA Cards
GENERAL D ESCRIP TIO N
preprogrammed ROM, no user programming is required. T he
ASP implements full rate speech transcoding according to GSM
specifications, including Discontinuous T ransmission (DT X)
and Comfort Noise Insertion (CNI). A high performance soft-
decision Viterbi equalizer is also implemented in software,
embedded in the ROM.
T he Analog Devices GSM baseband processing chipset provides
a competitive solution for GSM based mobile radio systems. It
is designed to be fully integrated, easy to use, and compatible
with a wide range of product solutions. GSM phones using this
chipset and its accompanying Layer 1, 2, 3 software have passed
the European GSM full type approval process.
P hysical Layer P r ocessor (P LP )
T he chipset consists of three highly integrated, sub-micron, low
power CMOS components that form the core baseband signal
processing of the GSM handset. T he system architecture is
designed to be easily integrated into current designs and form
the basis of next generation of designs.
T he PLP combines application specific hardware and an
embedded 16-bit microcontroller (H itachi H 8/300H ) to
perform channel coding and decoding and execute the protocol
stack and user software. T he embedded processor executes the
Layer 1, 2, 3 and user MMI software. T he PLP can control all
powerdown functions of the other chips and memory support
components to achieve maximum power savings.
T he chipset uses an operating voltage of 2.7 V to 3.6 V, which
coupled with the extensive power management features,
significantly reduces the drain on battery power and extends the
handset’s talktime and standby time.
Baseband Conver ter (BBC)
T he BBC performs the voiceband and baseband analog-to-
digital and digital-to-analog conversions, interfacing the digital
sections of the chipset to the microphone, loudspeaker and radio
section. In addition, the BBC contains all the auxiliary convert-
ers for burst-ramping, AFC, AGC, battery and temperature
monitoring. T he chipset interfaces directly with a variety of
industry standard radio architectures and supplies all the
synthesizer and timing control signals.
CH IP SET CO MP O NENTS
Algor ithm Signal P r ocessor (ASP )
T he ASP is an application specific variant of the ADSP-2171
standard DSP from Analog Devices. It has been optimized to
meet the cost, size and power consumption requirements of
GSM mobile applications. All necessary memory to run the
GSM specific programs is provided on-chip and with its
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD20msp410
Softwar e
T he analog voice signal is sampled at 8 kHz, producing 13-bit
linear values corresponding to the magnitude of the input. T he
resulting data is passed to the ASP through a dedicated serial
port.
T he required Layer 1 software is supplied with the chipset. In
addition, an object code license for Layers 2 and 3 of the
protocol stack is available. T his exact package of Layers 1,2,3 of
software, coupled with the AD20msp410 chipset, is today in
phones that have passed European GSM Final T ype Approval.
Speech Encoding (ASP )
T he ASP receives the voice data stream from the BBC and
encodes the data from 104 kb/s to 13 kb/s. T he algorithm used
is Regular Pulse Excitation, with Long T erm Prediction (RPE-
LT P) as specified in the 06-series of GSM recommendations.
T he algorithm is tested and proven to be bit-exact against the
GSM test vectors including all VAD/DT X functions. After
encoding the data is transferred to the PLP through a parallel
port in discrete blocks of 260 bits at 20 ms intervals.
Ar chitectur e O ver view
A standard GSM Handset can be divided into five functional
areas:
• Analog and Digital Baseband Processing Subsystem
• (Voice to Radio)
• Layer 1 Software (Physical Layer)
• Protocol Stack Software (Layers 2 and 3)
• Radio Subsystem
Channel Coding (P LP )
T he information received from the ASP contains data values
and filter coefficients that have different levels of priority. T hese
are subsequently protected to different levels within the channel
coding. T he encode protection process incorporates block
coding and convolutional encoding. In addition to the normal
speech traffic channels, the channel coding function also
supports data transmission at full rate and half rate. After the
interleave process, if necessary, the data is encrypted using the
required A5/1 or A5/2 encryption algorithm. Data is then
formatted into bursts, with the required timing and training
sequences and sent to the BBC through a dedicated serial port.
• User Interface Software (MMI)
Analog Devices and T he T echnology Partnership (T T P)
provide a cost effective and proven method of attaining the
baseband processing subsystem and protocol stack software.
T his data sheet includes functional descriptions of the baseband
processing subsystem and the Layer 1 software. T he T echnol-
ogy Partnership can provide licenses to software and reference
designs in all the other areas of a GSM hand-portable terminal.
For detailed information about the individual chipset compo-
nents, please refer to the ADSP-2178 (ASP), AD7015 (BBC)
and ADPLP01 (PLP) data sheets for electrical characteristics
and timing information.
GMSK Modulation and D /A Conver sion (BBC)
T he BBC receives data at 270 kb/s. T he on-chip lookup-table
ROM modulates and spectrally shapes the data being sent. A
pair of 10-bit matched differential DACs convert the modulated
data from the digital domain to the analog domain and pass I
and Q data to the transmit section of the radio subsystem.
FUNCTIO NAL D ESCRIP TIO N
Figure 1 is a functional block diagram of the GSM baseband
processing chipset. T he chipset can be viewed as a functional
block that contains a number of discrete functional units. T he
electrical and functional interfaces to the rest of the system are
briefly described at the end of this section and described in
detail in the individual data sheets for each component.
D O WNLINK
T he downlink baseband processing functions include the
following operations:
Analog-to-D igital Conver sion (BBC)
T he receiver I and Q signals are sampled by a pair of ADCs at
270 kHz. T he resulting digital words are transferred to the ASP
through a dedicated receive path serial link and DMA control.
BBC
ASP
Equalization (ASP )
BASE-
T he equalizer recovers and demodulates the received signal and
establishes local timing and frequency references for the mobile
unit. T he equalization algorithm is a version of the Maximum
Likelihood Sequence Estimation (MLSE) using the Viterbi
algorithm. T wo confidence bits per symbol provide additional
information about the accuracy of each decision to the channel
codec’s convolutional decoder. T he equalizer outputs a
sequence of bits including the confidence bits. T his data is
transferred to the PLP through a dedicated parallel port on the
ASP. At this point, the training sequence and trailing bits,
contained within the burst, are discarded.
VOICE
ADC
SPEECH
ENCODE
CHANNEL
ENCODE
INTER-
LEAVE
ENCRYPT
DECRYPT
BAND
DAC
BASE-
BAND
ADC
VOICE
DAC
SPEECH
E
ENCODE
CHANNEL DEINTER-
DECODE
EQUALIZER
LEAVE
PLP
CONTROL + MMI + I/O
Figure 1. Functional Description
UP LINK
Channel D ecoding (P LP )
T he uplink baseband processing functions include the following
operations:
T he A5/1 or A5/2 decryption algorithm is used, as required, to
recover the data that is ready for the deinterleave process. T he
deinterleave process is an exact inversion of the interleave
process used by the transmit section. Data can pass directly to
this function, without the A5/1 or the A5/2 decryption, con-
trolled by the Layer 1 processing. T he decode function then
performs convolutional decoding and parity decoding. T he
convolutional decoder uses a Viterbi algorithm, with two soft
Analog-to-D igital Voice Conver sion (BBC)
A conventional microphone, connected directly to the BBC,
provides an analog input signal to the ADC. T he voice ADC
function uses a sigma-delta converter to convert and noise shape
the input signal, achieving a Signal-to-Noise Ratio plus T otal
Harmonic Distortion (SNR+T HD) of greater than 62.5 dB.
REV. 0
–2–
AD20msp410
decision confidence bits supplied by the equalizer. Once these
decoding functions are complete, digitized voice data is trans-
ferred to the ASP through a parallel port. Error control mecha-
nisms are used to ensure adequate bad frame indication.
BBC and upconverted to 900 MHz for GSM applications and
1800 MHz for PCN applications.
A dedicated power amplifier increases the RF-signal to the
required level. T he receiver amplifies the antenna signal, down-
converts it to an intermediate frequency (IF) and amplifies it
there again. After second conversion to baseband, the I and Q
components of the signal are fed into the BBC.
Speech D ecoding (ASP )
Encoded speech data is transferred at 20 ms intervals from the
PLP to the ASP in blocks of 260 bits plus the Bad Frame
Indicator (BFI). T he speech decoder supports a Comfort Noise
Insertion (CNI) function that inserts a predefined silence
descriptor into the decoding process. T he ASP also implements
control of talker side-tone and short term echo cancellation.
T he resulting data, at 104 kb/s, is transferred to the BBC
through a dedicated serial path.
T he BBC, ASP and PLP provide three auxiliary functions for
interfacing to the radio subsystem. T hese auxiliary functions
include AGC, AFC and Power Ramping.
P ower Ram p Envelope (BBC)
T o meet the spectral and time-domain specifications of the
transmitted output signal, the burst has to follow a specified
power envelope. T he envelope for the power profile originates in
the PLP as a set of coefficients, down-loaded and stored in the
BBC. T his envelope profile is sent to one of the auxiliary DACs
on the BBC with each burst. T he analog output is fed into the
RF power amplifier, controlling the power profile and absolute
level of the transmitted data.
Voice D igital-to-Analog Conver sion
T he Voice DAC function of the BBC uses a sigma-delta con-
verter to convert and noise shape the signal. T he 13-bit linear
values are converted to the analog domain and filtered to avoid
any images. T he resulting differential signals can be controlled
in volume and drive directly a small earpiece as well as a
separate auxiliary output.
Autom atic Gain Contr ol (AGC)
T he mobile radio has to cope with a wide range of input signal
levels. T he major part of the overall gain is provided in the IF
amplifier. T he incoming signal level is analyzed in the ASP and
the PLP and a digital gain control signal is sent to the BBC. A
10-bit auxiliary DAC generates the appropriate analog control
signal for the IF amplifier. Additionally gain control can be
implemented by using two output flags of the ASP.
AUXILIARY SYSTEM FUNCTIO NS
T he ASP, the PLP and the BBC perform a number of auxiliary
functions which are essential to build a complete mobile radio.
A general radio section constitutes the three functions of
transmitter, receiver and synthesizer. Figure 2 shows how the
baseband chipset interfaces to a typical radio architecture. T he
transmitter is fed with baseband analog I and Q signals from the
BASEBAND/AUXILIARY SECTION OF AD7015
I
T
T
DAC
DAC
X
X
GSMSK
MODULATOR
BURST
STORE
PA
Q
BASEBAND
SERIAL
INTERFACE
I
R
R
DAC
DAC
DIGITALFIRFILTER
X
IF
Q
DIGITALFIRFILTER
X
AGC
10-BIT DAC
8-BIT DAC
AUXILIARY
SERIAL
AFC
10-BIT DAC
13 MHz VCTCXO
INTERFACE
10-BIT DAC
FLAGS
RAMP CONTROL
AGC
ASP
PLP
PAERROR
LOCK
SYNTHESIZER
CONTROL SIGNALS
13 MHz VCTCXO
Figure 2. Control of RF Section
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AD20msp410
Autom atic Fr equency Contr ol (AFC)
D ATA SERVICES
T he mobile radio has to track precisely the master clock
provided by the base station. Drift of the crystal oscillator over
time and temperature has to be compensated as well as fre-
quency shifts due to the Doppler effect in the case of a moving
mobile radio. T he received signal is analyzed in the ASP and the
PLP and a digital control signal is generated. T his signal is sent
to the two DACs in the BBC. T he 10-bit DAC operates as
coarse and the 8-bit DAC as fine adjust. T he weighting of the
DACs is such, that both DACs yield a combined resolution of
13 bits. T he combined analog output signal is used to control
the voltage controlled, temperature compensated crystal
oscillator (VCT CXO).
Data Services is considered to be an essential feature for GSM
terminals and the AD20msp410 chipset is designed to provide
flexible and low cost implementation of Data Services supported
via the GSM air interface.
HANDSET
EXTERNAL
DATA TERMINAL
ADAPTER
APPLICATION LAYER
FOREGROUND
COMMAND
INTERPRETER
APPLICATION LAYER
BACKGROUND
V110'
PROTOCOL STACK
LAYERS 2/3
FRAME
ROUTER
FRAMES
DATA TERMINAL
ADAPTER
Synthesizer Contr ol
PROTOCOL STACK
LAYER 1
T he PLP and the respective parts of the Layer 1 software
control the overall timing and frequency generation of the radio
subsystem. T his includes control signals for up to two synthesiz-
ers, powerdown control signals and power amplifier monitor
signals. Detailed information can be found in the ADPLP01
data sheet.
MAN MACHINE INTERFSCE
DATA APPLICATION
LAYER 2 RELAY (L2R)
RADIO LINK PROTOCOL (RLP)
RATE ADAPTION
AD20msp410
CHIPSET
Gener ation of Auxiliar y Audio Signals
Figure 4. Im plem entation of Data Services
Under control of Layer 1 the ASP can generate a variety of fixed
and user-programmable tones. T his includes all standard
DT MF and Call Progress tones as well as user defined tones.
T he tone structure can consist of up to four frequency compo-
nents with individual durations.
T he selected system architecture shown in Figure 4 provides for
minimum terminal Bill of Materials, the lowest possible number
of interconnection points and the lowest power consumption
when running speech traffic only. However, the chipset provides
full channel coding and decoding for all Data Services. Parity
and convolutional encoding and interleaving for T CH/F9.6,
T CH/F4.8 and T CH/F2.4 are implemented in the PLP.
T he ASP also generates T alker Sidetone as specified in the
GSM recommendations. In comparison to traditional hardware
implementations, this software implementation provides manu-
facturing flexibility over a wide range of speaker/microphone
sensitivities.
T he interface to the chipset is a user-configurable, 3-wire serial
interface supplying V110 data packets as defined in GSM 05.03,
combined with protocol information and control to the Applica-
tion Layer. External to the terminal is the Data T erminal
Adapter (DTA) which runs the Data Services Software. Included
in the DT A are the rate adaptation functions and the Data
Services application. T he Command Interpreter resident on the
mobile supports a serial interface protocol with the DT A via
both traffic data and control information are communicated.
T he T echnology Partnership can provide all requisite Data
Services Software.
VOLTAGE
REFERENCE
LOCK
AUDIO/AUXILIARY SECTION
MUX
FILTER
Σ/∆ DAC
PGA
PGA
PGA
VOICEBAND
SERIAL
INTERFACE
CAR
KIT
FILTER
Σ/∆ DAC
SO FTWARE IMP LEMENTATIO NS
A full implementation of the GSM Layer 1 functionality is
supplied as an object code module, for execution on the
controller, embedded in the PLP. Functions performed by this
software include:
U
BAT
AUXILIARY
SERIAL
INTERFACE
TEMP
MUX
10-BIT DAC
OTHER
•
•
•
Initial scan of GSM band and selection of strongest thirty
channels as required by 03.22 and 05.08
Figure 3. Audio-/Auxiliary Section of AD7015
Mobile oscillator adjustment, timing synchronization and
BCCH decoding from serving cell (camping-on)
Figure 3 shows the audio section and the auxiliary ADC of the
BBC. Input signals can come from either a directly connected
microphone or from a remote microphone in a car kit. Input
gain can be set to 0 dB or +26 dB. T he output signal can be
directly connected to a small earpiece and, for further amplifica-
tion, to an external car-kit. T wo output-PGAs can be pro-
grammed for –15 dB or +6 dB.
Base station frequency and timing measurements and BSIC
extraction from neighbor cells under control of Layer 3
•
•
Frequency hopping according to 05.02
Full implementation of discontinuous reception (DRX) and
transmission (DT X)
•
Reporting of received level and signal quality
REV. 0
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AD20msp410
•
•
•
•
Full engineering and test mode support
Support for all phase 1 and phase 2 handover modes
SIM Interface driver
Analog Voice Inter face to BBC
T he analog voice interface to the BBC is specified in the
AD7015 data sheet. Several design examples are given for
single-ended or differential inputs or outputs. A voltage
reference for biasing the microphone signal is provided on the
BBC. T he analog output of the BBC is capable of driving an
earpiece directly with and impedance of 150 Ω. For optional
use of a separate external microphone and power amplifier, a set
of auxiliary inputs/outputs is provided.
Message interfacing to Layer 3 (Radio Resources Manager)
and Layer 2 (data link layer, both signaling and data)
•
External functions for AGC, AFC and synthesizer setting are
called by Layer 1. T hese allow the user to configure the
system for a wide range of radio architectures including the
T T P GSM reference radio.
Radio Inter face to BBC and P LP
T he analog interface between the BBC and the radio subsystem
consists of differential inputs and outputs for the I and Q parts
of the signal and three analog control signals for AFC, AGC and
transmit ramp envelope. Details of these signals are specified in
the AD7015 data sheet. T he digital interface between the PLP
and the radio subsystem consists of a serial port for communi-
cating with the synthesizers and several control signals as
specified in detail in the ADPLP01 data sheet.
•
T he higher layers of the protocol stack also reside on this
embedded processor. A GSM Phase 2 compliant, Layer 2/3
protocol stack is available from T he T echnology Partnership.
P O WER D ISSIP ATIO N CO NSID ERATIO NS
In mobile applications, minimizing the power consumption of
all devices is critical to achieving longer standby and talk times.
In a GSM handset the baseband subsystem dominates the
current consumption of the phone in standby. T he design of the
ASP, PLP and BBC includes extensive features to reduce current
consumption and give standby times of up to 70 hours.
D igital SIM Car d Inter face to P LP
T he PLP is designed to interface directly to the SIM. However
interface logic may be necessary to connect the 3 V chipset to a
5 V SIM.
All three devices were specifically designed to operate from
2.7 V to 3.6 V, so facilitating three or four cell NiCad/NiMH or
single-cell Li Ion batteries.
D igital Inter face to Keypad
Keypad interface logic for up to 40 keys is provided on the PLP.
T his interface provides keyboard scan for 8 Rows and 4
columns. Additionally an extra pin on the PLP is provided for
the power switch.
T he PLP incorporates intelligent power management, permit-
ting automatic control of power consumption in the PLP and
the peripheral circuitry. Data processing modules are switched
on only when they process data, otherwise they are powered
down.
D igital Bus Inter face to Mem or y and D isplay
External RAM and ROM as well as the display controller
interfaces directly to the 21-bit address bus and 16-bit data bus
of the PLP.
Additional control signals are provided that enable the Layer 1
software to control the external subsystems, such as the ASP,
BBC, radio and memory components, so that their power is
intelligently switched by the PLP.
Inter face to FLASH Mem or y
T he large FLASH memory can contain all programs for the
embedded Control Processor of the PLP. T his includes the
complete GSM protocol software as well as the User Interface
Software. A size of 4 Mbit to 8 Mbit is suggested to accommo-
date all Protocol software plus a typical size of User Interface
Software. Enhanced features, requiring larger memories are
supported easily by the large address space of the embedded
Control Processor. T o facilitate production programming and
field upgrades of the FLASH memories, the PLP provides
embedded code to download the software into the FLASH
memory via its standard serial port.
Within the ASP the different powerdown modes range from a
simple “wait for interrupt” state to a complete hardware
powerdown, with only leakage currents dissipating power.
In the BBC, the powerdown functions are split separately
between receive, transmit and auxiliary circuits. T his provides
optimal analog power performance when operating in different
modes.
INTERFACES
Figure 5 shows the chipset’s eight interfaces, which have to be
considered in the design of the complete mobile radio. Some of
these interfaces have to meet GSM specifications, others will be
design specific.
Inter face to SRAM
Beside the FLASH memory, the Control Processor additionally
supports static RAM to store user defined variables, typically
those used by the Protocol Stack or Application Layer. Standard
SRAMs interface directly to the address and data bus of the
PLP.
• Analog Voice Interface to BBC
• Radio Interface to BBC and PLP
Inter face to D isplay Contr oller
• Digital SIM Card Interface to PLP
• Digital Interface to the Keypad
T his interface is achieved through the address and data buses
and associated read and write strobes, as well as a specific
enable signal. An integrated wait state generator helps interface
to a wide range of display controllers. T wo pins with PWM
outputs control the intensity of separate backlights for display
and keypad.
• Digital Bus Interface from PLP to Memory and Display
• Digital Interface from the PLP to the EEPROM
• Digital Audio Interface (DAI)
• Digital Interface to PLP for Data Services
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AD20msp410
D igital Audio Inter face (D AI)
Table I. List of Key Com ponents
As required by the GSM specifications, a digital audio interface
is provided to allow certain tests of the audio section during type
approval. T his interface is provided by the serial bus between
the ASP and the PLP and two additional control signals from
the PLP. A fully functional “DAI Box” needed for the FT A
process may be obtained from Analog Devices upon request.
Quantity
D escription
Specification
1
1
1
1
1
1
1
ASP1
ADSP-2178
ADPLP01
AD7015
256K × 16, 150 ns
128K × 8, 120 ns
2K × 8
PLP1
BBC1
FLASH-PROM2
SRAM
D igital Inter face to the P LP for D ata Ser vices
A conventional H8 serial port combined with a proprietary
protocol is used to interface to an external Data T erminal
Adapter.
EEPROM3
Display Driver
Design Specific
NOT ES
1T hese components comprise the AD20msp410 chipset.
D igital Inter face fr om the P LP to the EEP RO M
2A size of 4 Mbits is recommended to allow storage of all GSM Layer
(1, 2, 3) programs as well as a typical user interface (MMI). Larger
memory can be used to support enhanced user interfaces.
3Can be omitted if parameters are stored in FLASH memory.
T he PLP provides separate pins to interface directly to an
external EEPROM via a serial port. T his EEPROM is typically
used for storage of calibration or user variable parameters like
handset identifier (IMEI), language, keypad lock and radio
calibration parameters. A typical size of the EEPROM is 2K × 8
bits, but this depends on the individual design of the handset.
GSM Baseband P r ocessing Key P ar ts List
T able 1 lists the major hardware components necessary to
complete the GSM baseband processing subsystem. An example
Bill Of Material is available from Analog Devices. A full
reference design is available through Analog Devices/T he
T echnology Partnership.
13MHz
DAI
VCTCXO
INTERFACE
PLP
BBC
CAR KIT
SIM
INTERFACE
AUX DAC 2
(AFC)
VOICEBAND
ANALOG I/O
DAI CONTROL
SERIAL PORT
ADDRESS
DATA
VOICEBAND
SERIAL PORT
SPORT 0
ASP
AUX DAC 1
(AGC)
POWER
AMPLIFIER
ASP
ADDRESS
DATA BUS
INTERFACE
PSRAM
CONTROL
BASEBAND
SERIAL PORT
SPORT 1
RADIO
IF
AUX DAC 3
(AGC)
DISPLAY
CONTROL
AMPLIFIER
CLOCK
MODULATOR
BASEBAND
ANALOG I/O
BACKLIGHT
CONTROL
DEMODULATOR
KEYPAD
INTERFACE
POWER
SUBSYSTEM
POWER
CONTROL
KEYPAD
KEYPAD
AUX ADC
EEPROM
INTERFACE
SYNTHESIZER
AND RADIO
CONTROL
SYNTHESIZER
AND RADIO
CONTROL
DATA
DATA
INTERFACE
INTERFACE
Figure 5. System Interfaces
REV. 0
–6–
AD20msp410
Mechanical Consider ations
O RD ERING GUID E
T he chipset has been specifically designed to meet not only cost
and power consumption requirements but also attention was
paid to the physical dimensions. State-of-the-art package
technology was used to achieve smallest possible geometries. See
T able II for a list of main packaging dimensions and consult
individual data sheets of the three components for further
details.
T o order the parts for the AD20msp410 GSM chipset, please
order one of each of the following components.
P art P art Num ber
ASP ADSP-2178-780244
Supply Voltage Range
+2.7 V to 3.6 V
BBC AD53/009-9 (Special AD7015) +2.7 V to 3.6 V
PLP ADPLP01 +2.7 V to 3.6 V
Table II. P ackage D im ensions
An evaluation and development system may be ordered for this
chipset, under the part number, AD20msp410-EB03.
P aram eter
ASP
P LP
BBC
Unit
Package
Leads
T QFP
100
T QFP
176
T QFP
80
Pitch
Body
T otal Height
Board Area
0.5
14 × 14
1.6
0.5
24 × 24
1.7
0.65
14 × 14
1.6
mm
mm2
mm
16 × 16
26 × 26
16 × 16
mm2
All three components utilize low profile Plastic Quad Flat Packs
with lead pitches of 0.5 mm minimum. Special attention was
paid to the possible use in PCMCIA cards.
REV. 0
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AD20msp410
–8–
REV. 0
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